From: Jagan Teki <jagan@amarulasolutions.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>, Marek Szyprowski <m.szyprowski@samsung.com>, Neil Armstrong <neil.armstrong@linaro.org>, Marek Vasut <marex@denx.de>, Maxime Ripard <mripard@kernel.org> Cc: linux-samsung-soc@vger.kernel.org, Matteo Lisi <matteo.lisi@engicam.com>, linux-amarula <linux-amarula@amarulasolutions.com>, Seung-Woo Kim <sw0312.kim@samsung.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Kyungmin Park <kyungmin.park@samsung.com>, dri-devel@lists.freedesktop.org, Adam Ford <aford173@gmail.com>, Jagan Teki <jagan@amarulasolutions.com> Subject: [PATCH v15 07/16] drm: exynos: dsi: Add atomic check Date: Fri, 3 Mar 2023 20:21:29 +0530 [thread overview] Message-ID: <20230303145138.29233-8-jagan@amarulasolutions.com> (raw) In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> Look like an explicit fixing up of mode_flags is required for DSIM IP present in i.MX8M Mini/Nano SoCs. At least the LCDIF + DSIM needs active low sync polarities in order to correlate the correct sync flags of the surrounding components in the chain to make sure the whole pipeline can work properly. On the other hand the i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 says. "13.6.3.5.2 RGB interface Vsync, Hsync, and VDEN are active high signals." i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 3.6.3.5.2 RGB interface i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 13.6.2.7.2 RGB interface both claim "Vsync, Hsync, and VDEN are active high signals.", the LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. No clear evidence about whether it can be documentation issues or something, so added proper comments on the code. Comments are suggested by Marek Vasut. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - fix commit message Changes for v10, v9: - none Changes for v8: - update the comments about sync signals polarities - added clear commit message by including i.MX8M Nano details Changes for v7: - fix the hw_type checking logic Changes for v6: - none Changes for v5: - rebase based new bridge changes [mszyprow] - remove DSIM_QUIRK_FIXUP_SYNC_POL - add hw_type check for sync polarities change. Changes for v4: - none Changes for v3: - add DSIM_QUIRK_FIXUP_SYNC_POL to handle mode_flasg fixup Changes for v2: - none Changes for v1: - fix mode flags in atomic_check instead of mode_fixup drivers/gpu/drm/exynos/exynos_drm_dsi.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index fe195d76ce76..796480e4a18b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -263,6 +263,7 @@ enum exynos_dsi_type { DSIM_TYPE_EXYNOS5410, DSIM_TYPE_EXYNOS5422, DSIM_TYPE_EXYNOS5433, + DSIM_TYPE_IMX8MM, DSIM_TYPE_COUNT, }; @@ -1465,6 +1466,32 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +static int exynos_dsi_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct exynos_dsi *dsi = bridge_to_dsi(bridge); + struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + + /* + * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM + * inverts HS/VS/DE sync signals polarity, therefore, while + * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 + * 13.6.3.5.2 RGB interface + * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 + * 13.6.2.7.2 RGB interface + * both claim "Vsync, Hsync, and VDEN are active high signals.", the + * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. + */ + if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { + adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + } + + return 0; +} + static void exynos_dsi_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) @@ -1487,6 +1514,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable, .atomic_disable = exynos_dsi_atomic_disable, -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Jagan Teki <jagan@amarulasolutions.com> To: Andrzej Hajda <andrzej.hajda@intel.com>, Inki Dae <inki.dae@samsung.com>, Marek Szyprowski <m.szyprowski@samsung.com>, Neil Armstrong <neil.armstrong@linaro.org>, Marek Vasut <marex@denx.de>, Maxime Ripard <mripard@kernel.org> Cc: Seung-Woo Kim <sw0312.kim@samsung.com>, Kyungmin Park <kyungmin.park@samsung.com>, Frieder Schrempf <frieder.schrempf@kontron.de>, Tim Harvey <tharvey@gateworks.com>, Adam Ford <aford173@gmail.com>, Matteo Lisi <matteo.lisi@engicam.com>, dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-amarula <linux-amarula@amarulasolutions.com>, Jagan Teki <jagan@amarulasolutions.com> Subject: [PATCH v15 07/16] drm: exynos: dsi: Add atomic check Date: Fri, 3 Mar 2023 20:21:29 +0530 [thread overview] Message-ID: <20230303145138.29233-8-jagan@amarulasolutions.com> (raw) In-Reply-To: <20230303145138.29233-1-jagan@amarulasolutions.com> Look like an explicit fixing up of mode_flags is required for DSIM IP present in i.MX8M Mini/Nano SoCs. At least the LCDIF + DSIM needs active low sync polarities in order to correlate the correct sync flags of the surrounding components in the chain to make sure the whole pipeline can work properly. On the other hand the i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020 says. "13.6.3.5.2 RGB interface Vsync, Hsync, and VDEN are active high signals." i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 3.6.3.5.2 RGB interface i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 13.6.2.7.2 RGB interface both claim "Vsync, Hsync, and VDEN are active high signals.", the LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. No clear evidence about whether it can be documentation issues or something, so added proper comments on the code. Comments are suggested by Marek Vasut. Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> --- Changes for v15, v13: - none Changes for v12: - collect RB from Marek Changes for v11: - collect RB from Frieder - fix commit message Changes for v10, v9: - none Changes for v8: - update the comments about sync signals polarities - added clear commit message by including i.MX8M Nano details Changes for v7: - fix the hw_type checking logic Changes for v6: - none Changes for v5: - rebase based new bridge changes [mszyprow] - remove DSIM_QUIRK_FIXUP_SYNC_POL - add hw_type check for sync polarities change. Changes for v4: - none Changes for v3: - add DSIM_QUIRK_FIXUP_SYNC_POL to handle mode_flasg fixup Changes for v2: - none Changes for v1: - fix mode flags in atomic_check instead of mode_fixup drivers/gpu/drm/exynos/exynos_drm_dsi.c | 28 +++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index fe195d76ce76..796480e4a18b 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -263,6 +263,7 @@ enum exynos_dsi_type { DSIM_TYPE_EXYNOS5410, DSIM_TYPE_EXYNOS5422, DSIM_TYPE_EXYNOS5433, + DSIM_TYPE_IMX8MM, DSIM_TYPE_COUNT, }; @@ -1465,6 +1466,32 @@ static void exynos_dsi_atomic_post_disable(struct drm_bridge *bridge, pm_runtime_put_sync(dsi->dev); } +static int exynos_dsi_atomic_check(struct drm_bridge *bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct exynos_dsi *dsi = bridge_to_dsi(bridge); + struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; + + /* + * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM + * inverts HS/VS/DE sync signals polarity, therefore, while + * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 + * 13.6.3.5.2 RGB interface + * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 + * 13.6.2.7.2 RGB interface + * both claim "Vsync, Hsync, and VDEN are active high signals.", the + * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. + */ + if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { + adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); + adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); + } + + return 0; +} + static void exynos_dsi_mode_set(struct drm_bridge *bridge, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) @@ -1487,6 +1514,7 @@ static const struct drm_bridge_funcs exynos_dsi_bridge_funcs = { .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, .atomic_reset = drm_atomic_helper_bridge_reset, + .atomic_check = exynos_dsi_atomic_check, .atomic_pre_enable = exynos_dsi_atomic_pre_enable, .atomic_enable = exynos_dsi_atomic_enable, .atomic_disable = exynos_dsi_atomic_disable, -- 2.25.1
next prev parent reply other threads:[~2023-03-03 14:52 UTC|newest] Thread overview: 75+ messages / expand[flat|nested] mbox.gz Atom feed top [not found] <CGME20230303145219eucas1p218c2e302e41464432627c8ac074302f8@eucas1p2.samsung.com> 2023-03-03 14:51 ` [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 01/16] drm: exynos: dsi: Drop explicit call to bridge detach Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 16:39 ` Marek Vasut 2023-03-03 16:39 ` Marek Vasut 2023-03-03 14:51 ` [PATCH v15 02/16] drm: exynos: dsi: Lookup OF-graph or Child node devices Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 16:41 ` Marek Vasut 2023-03-03 16:41 ` Marek Vasut 2023-03-03 14:51 ` [PATCH v15 03/16] drm: exynos: dsi: Mark PHY as optional Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 04/16] drm: exynos: dsi: Add platform PLL_P (PMS_P) offset Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 05/16] drm: exynos: dsi: Introduce hw_type platform data Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 06/16] drm: exynos: dsi: Handle proper host initialization Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` Jagan Teki [this message] 2023-03-03 14:51 ` [PATCH v15 07/16] drm: exynos: dsi: Add atomic check Jagan Teki 2023-03-03 14:51 ` [PATCH v15 08/16] drm: exynos: dsi: Add input_bus_flags Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 15:00 ` Maxime Ripard 2023-03-03 15:00 ` Maxime Ripard 2023-03-03 15:02 ` Maxime Ripard 2023-03-03 15:02 ` Maxime Ripard 2023-03-03 14:51 ` [PATCH v15 09/16] drm: exynos: dsi: Add atomic_get_input_bus_fmts Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 10/16] drm: exynos: dsi: Consolidate component and bridge Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 11/16] drm: exynos: dsi: Add host helper for te_irq_handler Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 12/16] drm: bridge: Generalize Exynos-DSI driver into a Samsung DSIM bridge Jagan Teki 2023-03-03 15:08 ` Maxime Ripard 2023-03-03 15:08 ` Maxime Ripard 2023-03-03 15:11 ` Jagan Teki 2023-03-03 15:11 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 13/16] dt-bindings: display: exynos: dsim: Add NXP i.MX8M Mini/Nano support Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 14/16] drm: bridge: samsung-dsim: Add " Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 15/16] dt-bindings: display: exynos: dsim: Add NXP i.MX8M Plus support Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 14:51 ` [PATCH v15 16/16] drm: bridge: samsung-dsim: Add " Jagan Teki 2023-03-03 14:51 ` Jagan Teki 2023-03-03 22:26 ` [PATCH v15 00/16] drm: Add Samsung MIPI DSIM bridge Marek Szyprowski 2023-03-03 22:26 ` Marek Szyprowski 2023-03-04 18:59 ` Jagan Teki 2023-03-04 18:59 ` Jagan Teki 2023-03-06 11:02 ` Marek Szyprowski 2023-03-06 11:02 ` Marek Szyprowski 2023-03-06 17:24 ` Jagan Teki 2023-03-06 17:24 ` Jagan Teki 2023-03-06 22:41 ` Marek Szyprowski 2023-03-06 22:41 ` Marek Szyprowski 2023-03-07 7:55 ` Jagan Teki 2023-03-07 7:55 ` Jagan Teki 2023-03-07 9:22 ` Jagan Teki 2023-03-07 9:22 ` Jagan Teki 2023-03-07 10:44 ` Marek Szyprowski 2023-03-07 10:44 ` Marek Szyprowski 2023-03-06 5:24 ` 대인기/Tizen Platform Lab(SR)/삼성전자 2023-03-06 5:24 ` 대인기/Tizen Platform Lab(SR)/삼성전자 2023-03-06 8:48 ` Jagan Teki 2023-03-06 8:48 ` Jagan Teki 2023-03-14 0:31 ` Fabio Estevam 2023-03-14 0:31 ` Fabio Estevam 2023-03-14 0:51 ` Inki Dae 2023-03-23 15:34 ` Fabio Estevam 2023-03-23 15:34 ` Fabio Estevam 2023-03-27 14:08 ` Neil Armstrong 2023-03-27 14:08 ` Neil Armstrong 2023-03-28 0:03 ` Inki Dae 2023-03-28 7:53 ` Neil Armstrong 2023-03-28 7:53 ` Neil Armstrong
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