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From: Sean Anderson <sean.anderson@seco.com>
To: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	linux-phy@lists.infradead.org
Cc: Madalin Bucur <madalin.bucur@nxp.com>,
	linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	Rob Herring <robh+dt@kernel.org>,
	Camelia Alexandra Groza <camelia.groza@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	Bagas Sanjaya <bagasdotme@gmail.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Sean Anderson <sean.anderson@seco.com>,
	Li Yang <leoyang.li@nxp.com>, Shawn Guo <shawnguo@kernel.org>
Subject: [PATCH v10 10/13] arm64: dts: ls1046ardb: Add serdes descriptions
Date: Mon,  6 Mar 2023 14:15:32 -0500	[thread overview]
Message-ID: <20230306191535.1917656-11-sean.anderson@seco.com> (raw)
In-Reply-To: <20230306191535.1917656-1-sean.anderson@seco.com>

This adds appropriate descriptions for the macs which use the SerDes. The
156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
no driver for this device (and as far as I know all you can do with the
100MHz clocks is gate them), so I have chosen to model it as a single
fixed clock.

Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>

---

Changes in v10:
- Move serdes descriptions to SoC dtsi
- Don't use /clocks
- Use "descriptions" instead of "bindings"
- Split off defconfig change into separate patch

Changes in v9:
- Fix name of phy mode node
- phy-type -> fsl,phy

Changes in v8:
- Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
  This should help remind readers that the numbering corresponds to the
  physical layout of the registers, and not the lane (pin) number.

Changes in v6:
- XGI.9 -> XFI.9

Changes in v4:
- Convert to new bindings

 .../boot/dts/freescale/fsl-ls1046a-rdb.dts    | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 07f6cc6e354a..0d6dcfd1630a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -26,6 +26,24 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	clk_100mhz: clock-100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	clk_156mhz: clock-156mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <156250000>;
+	};
+};
+
+&serdes1 {
+	clocks = <&clk_100mhz>, <&clk_156mhz>;
+	clock-names = "ref0", "ref1";
+	status = "okay";
 };
 
 &duart0 {
@@ -140,21 +158,29 @@ ethernet@e6000 {
 	ethernet@e8000 {
 		phy-handle = <&sgmii_phy1>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_B>;
+		phy-names = "serdes";
 	};
 
 	ethernet@ea000 {
 		phy-handle = <&sgmii_phy2>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_A>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f0000 { /* 10GEC1 */
 		phy-handle = <&aqr106_phy>;
 		phy-connection-type = "xgmii";
+		phys = <&serdes1_D>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f2000 { /* 10GEC2 */
 		phy-connection-type = "10gbase-r";
 		managed = "in-band-status";
+		phys = <&serdes1_C>;
+		phy-names = "serdes";
 	};
 
 	mdio@fc000 {
-- 
2.35.1.1320.gc452695387.dirty


WARNING: multiple messages have this Message-ID (diff)
From: Sean Anderson <sean.anderson@seco.com>
To: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	linux-phy@lists.infradead.org
Cc: Madalin Bucur <madalin.bucur@nxp.com>,
	linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	Rob Herring <robh+dt@kernel.org>,
	Camelia Alexandra Groza <camelia.groza@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	Bagas Sanjaya <bagasdotme@gmail.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Sean Anderson <sean.anderson@seco.com>,
	Li Yang <leoyang.li@nxp.com>, Shawn Guo <shawnguo@kernel.org>
Subject: [PATCH v10 10/13] arm64: dts: ls1046ardb: Add serdes descriptions
Date: Mon,  6 Mar 2023 14:15:32 -0500	[thread overview]
Message-ID: <20230306191535.1917656-11-sean.anderson@seco.com> (raw)
In-Reply-To: <20230306191535.1917656-1-sean.anderson@seco.com>

This adds appropriate descriptions for the macs which use the SerDes. The
156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
no driver for this device (and as far as I know all you can do with the
100MHz clocks is gate them), so I have chosen to model it as a single
fixed clock.

Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>

---

Changes in v10:
- Move serdes descriptions to SoC dtsi
- Don't use /clocks
- Use "descriptions" instead of "bindings"
- Split off defconfig change into separate patch

Changes in v9:
- Fix name of phy mode node
- phy-type -> fsl,phy

Changes in v8:
- Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
  This should help remind readers that the numbering corresponds to the
  physical layout of the registers, and not the lane (pin) number.

Changes in v6:
- XGI.9 -> XFI.9

Changes in v4:
- Convert to new bindings

 .../boot/dts/freescale/fsl-ls1046a-rdb.dts    | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 07f6cc6e354a..0d6dcfd1630a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -26,6 +26,24 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	clk_100mhz: clock-100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	clk_156mhz: clock-156mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <156250000>;
+	};
+};
+
+&serdes1 {
+	clocks = <&clk_100mhz>, <&clk_156mhz>;
+	clock-names = "ref0", "ref1";
+	status = "okay";
 };
 
 &duart0 {
@@ -140,21 +158,29 @@ ethernet@e6000 {
 	ethernet@e8000 {
 		phy-handle = <&sgmii_phy1>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_B>;
+		phy-names = "serdes";
 	};
 
 	ethernet@ea000 {
 		phy-handle = <&sgmii_phy2>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_A>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f0000 { /* 10GEC1 */
 		phy-handle = <&aqr106_phy>;
 		phy-connection-type = "xgmii";
+		phys = <&serdes1_D>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f2000 { /* 10GEC2 */
 		phy-connection-type = "10gbase-r";
 		managed = "in-band-status";
+		phys = <&serdes1_C>;
+		phy-names = "serdes";
 	};
 
 	mdio@fc000 {
-- 
2.35.1.1320.gc452695387.dirty


-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Sean Anderson <sean.anderson@seco.com>
To: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	linux-phy@lists.infradead.org
Cc: Madalin Bucur <madalin.bucur@nxp.com>,
	linuxppc-dev@lists.ozlabs.org, devicetree@vger.kernel.org,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	Rob Herring <robh+dt@kernel.org>,
	Camelia Alexandra Groza <camelia.groza@nxp.com>,
	linux-arm-kernel@lists.infradead.org,
	Bagas Sanjaya <bagasdotme@gmail.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Sean Anderson <sean.anderson@seco.com>,
	Li Yang <leoyang.li@nxp.com>, Shawn Guo <shawnguo@kernel.org>
Subject: [PATCH v10 10/13] arm64: dts: ls1046ardb: Add serdes descriptions
Date: Mon,  6 Mar 2023 14:15:32 -0500	[thread overview]
Message-ID: <20230306191535.1917656-11-sean.anderson@seco.com> (raw)
In-Reply-To: <20230306191535.1917656-1-sean.anderson@seco.com>

This adds appropriate descriptions for the macs which use the SerDes. The
156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
no driver for this device (and as far as I know all you can do with the
100MHz clocks is gate them), so I have chosen to model it as a single
fixed clock.

Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>

---

Changes in v10:
- Move serdes descriptions to SoC dtsi
- Don't use /clocks
- Use "descriptions" instead of "bindings"
- Split off defconfig change into separate patch

Changes in v9:
- Fix name of phy mode node
- phy-type -> fsl,phy

Changes in v8:
- Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
  This should help remind readers that the numbering corresponds to the
  physical layout of the registers, and not the lane (pin) number.

Changes in v6:
- XGI.9 -> XFI.9

Changes in v4:
- Convert to new bindings

 .../boot/dts/freescale/fsl-ls1046a-rdb.dts    | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 07f6cc6e354a..0d6dcfd1630a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -26,6 +26,24 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	clk_100mhz: clock-100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	clk_156mhz: clock-156mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <156250000>;
+	};
+};
+
+&serdes1 {
+	clocks = <&clk_100mhz>, <&clk_156mhz>;
+	clock-names = "ref0", "ref1";
+	status = "okay";
 };
 
 &duart0 {
@@ -140,21 +158,29 @@ ethernet@e6000 {
 	ethernet@e8000 {
 		phy-handle = <&sgmii_phy1>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_B>;
+		phy-names = "serdes";
 	};
 
 	ethernet@ea000 {
 		phy-handle = <&sgmii_phy2>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_A>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f0000 { /* 10GEC1 */
 		phy-handle = <&aqr106_phy>;
 		phy-connection-type = "xgmii";
+		phys = <&serdes1_D>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f2000 { /* 10GEC2 */
 		phy-connection-type = "10gbase-r";
 		managed = "in-band-status";
+		phys = <&serdes1_C>;
+		phy-names = "serdes";
 	};
 
 	mdio@fc000 {
-- 
2.35.1.1320.gc452695387.dirty


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Sean Anderson <sean.anderson@seco.com>
To: Vinod Koul <vkoul@kernel.org>,
	Kishon Vijay Abraham I <kishon@kernel.org>,
	linux-phy@lists.infradead.org
Cc: devicetree@vger.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Madalin Bucur <madalin.bucur@nxp.com>,
	Sean Anderson <sean.anderson@seco.com>,
	Shawn Guo <shawnguo@kernel.org>, Li Yang <leoyang.li@nxp.com>,
	Rob Herring <robh+dt@kernel.org>,
	Camelia Alexandra Groza <camelia.groza@nxp.com>,
	Bagas Sanjaya <bagasdotme@gmail.com>,
	Ioana Ciornei <ioana.ciornei@nxp.com>,
	linuxppc-dev@lists.ozlabs.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 10/13] arm64: dts: ls1046ardb: Add serdes descriptions
Date: Mon,  6 Mar 2023 14:15:32 -0500	[thread overview]
Message-ID: <20230306191535.1917656-11-sean.anderson@seco.com> (raw)
In-Reply-To: <20230306191535.1917656-1-sean.anderson@seco.com>

This adds appropriate descriptions for the macs which use the SerDes. The
156.25MHz fixed clock is a crystal. The 100MHz clocks (there are
actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is
no driver for this device (and as far as I know all you can do with the
100MHz clocks is gate them), so I have chosen to model it as a single
fixed clock.

Note: the SerDes1 lane numbering for the LS1046A is *reversed*.
This means that Lane A (what the driver thinks is lane 0) uses pins
SD1_TX3_P/N.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>

---

Changes in v10:
- Move serdes descriptions to SoC dtsi
- Don't use /clocks
- Use "descriptions" instead of "bindings"
- Split off defconfig change into separate patch

Changes in v9:
- Fix name of phy mode node
- phy-type -> fsl,phy

Changes in v8:
- Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc.
  This should help remind readers that the numbering corresponds to the
  physical layout of the registers, and not the lane (pin) number.

Changes in v6:
- XGI.9 -> XFI.9

Changes in v4:
- Convert to new bindings

 .../boot/dts/freescale/fsl-ls1046a-rdb.dts    | 26 +++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
index 07f6cc6e354a..0d6dcfd1630a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
@@ -26,6 +26,24 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	clk_100mhz: clock-100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	clk_156mhz: clock-156mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <156250000>;
+	};
+};
+
+&serdes1 {
+	clocks = <&clk_100mhz>, <&clk_156mhz>;
+	clock-names = "ref0", "ref1";
+	status = "okay";
 };
 
 &duart0 {
@@ -140,21 +158,29 @@ ethernet@e6000 {
 	ethernet@e8000 {
 		phy-handle = <&sgmii_phy1>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_B>;
+		phy-names = "serdes";
 	};
 
 	ethernet@ea000 {
 		phy-handle = <&sgmii_phy2>;
 		phy-connection-type = "sgmii";
+		phys = <&serdes1_A>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f0000 { /* 10GEC1 */
 		phy-handle = <&aqr106_phy>;
 		phy-connection-type = "xgmii";
+		phys = <&serdes1_D>;
+		phy-names = "serdes";
 	};
 
 	ethernet@f2000 { /* 10GEC2 */
 		phy-connection-type = "10gbase-r";
 		managed = "in-band-status";
+		phys = <&serdes1_C>;
+		phy-names = "serdes";
 	};
 
 	mdio@fc000 {
-- 
2.35.1.1320.gc452695387.dirty


  parent reply	other threads:[~2023-03-06 19:16 UTC|newest]

Thread overview: 116+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-06 19:15 [PATCH v10 00/13] phy: Add support for Lynx 10G SerDes Sean Anderson
2023-03-06 19:15 ` Sean Anderson
2023-03-06 19:15 ` Sean Anderson
2023-03-06 19:15 ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 01/13] dt-bindings: phy: Add 2500BASE-X and 10GBASE-R Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 02/13] dt-bindings: phy: Add Lynx 10G phy binding Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-07 19:14   ` Sean Anderson
2023-03-07 19:14     ` Sean Anderson
2023-03-07 19:14     ` Sean Anderson
2023-03-07 19:14     ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 03/13] dt-bindings: Convert gpio-mmio to yaml Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 20:51   ` Jonas Gorski
2023-03-06 20:51     ` Jonas Gorski
2023-03-06 20:51     ` Jonas Gorski
2023-03-06 20:51     ` Jonas Gorski
2023-03-06 21:27     ` Sean Anderson
2023-03-06 21:27       ` Sean Anderson
2023-03-06 21:27       ` Sean Anderson
2023-03-06 21:27       ` Sean Anderson
2023-03-10 10:33       ` Jonas Gorski
2023-03-10 10:33         ` Jonas Gorski
2023-03-10 10:33         ` Jonas Gorski
2023-03-10 10:33         ` Jonas Gorski
2023-03-06 22:04   ` Linus Walleij
2023-03-06 22:04     ` Linus Walleij
2023-03-06 22:04     ` Linus Walleij
2023-03-06 22:04     ` Linus Walleij
2023-03-07  8:42   ` Krzysztof Kozlowski
2023-03-07  8:42     ` Krzysztof Kozlowski
2023-03-07  8:42     ` Krzysztof Kozlowski
2023-03-07  8:42     ` Krzysztof Kozlowski
2023-03-07 15:35     ` Sean Anderson
2023-03-07 15:35       ` Sean Anderson
2023-03-07 15:35       ` Sean Anderson
2023-03-07 15:35       ` Sean Anderson
2023-03-08  8:48       ` Krzysztof Kozlowski
2023-03-08  8:48         ` Krzysztof Kozlowski
2023-03-08  8:48         ` Krzysztof Kozlowski
2023-03-08  8:48         ` Krzysztof Kozlowski
2023-03-09  9:16       ` Linus Walleij
2023-03-09  9:16         ` Linus Walleij
2023-03-09  9:16         ` Linus Walleij
2023-03-09  9:16         ` Linus Walleij
2023-03-13  8:53         ` Leonard, Niall
2023-03-13  8:53           ` Leonard, Niall
2023-03-13  8:53           ` Leonard, Niall
2023-03-13  8:53           ` Leonard, Niall
2023-03-13 15:19           ` Sean Anderson
2023-03-13 15:19             ` Sean Anderson
2023-03-13 15:19             ` Sean Anderson
2023-03-13 15:19             ` Sean Anderson
2023-03-13 22:13           ` Linus Walleij
2023-03-13 22:13             ` Linus Walleij
2023-03-13 22:13             ` Linus Walleij
2023-03-13 22:13             ` Linus Walleij
2023-03-08 23:10   ` Rob Herring
2023-03-08 23:10     ` Rob Herring
2023-03-08 23:10     ` Rob Herring
2023-03-08 23:10     ` Rob Herring
2023-03-09 16:03     ` Sean Anderson
2023-03-09 16:03       ` Sean Anderson
2023-03-09 16:03       ` Sean Anderson
2023-03-09 16:03       ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 04/13] dt-bindings: gpio-mmio: Add compatible for QIXIS Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-08 23:11   ` Rob Herring
2023-03-08 23:11     ` Rob Herring
2023-03-08 23:11     ` Rob Herring
2023-03-08 23:11     ` Rob Herring
2023-03-06 19:15 ` [PATCH v10 05/13] dt-bindings: clock: Add ids for Lynx 10g PLLs Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 06/13] clk: Add Lynx 10G SerDes PLL driver Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 07/13] phy: fsl: Add Lynx 10G SerDes driver Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 08/13] phy: lynx10g: Enable by default on Layerscape Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 09/13] arm64: dts: ls1046a: Add serdes nodes Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` Sean Anderson [this message]
2023-03-06 19:15   ` [PATCH v10 10/13] arm64: dts: ls1046ardb: Add serdes descriptions Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 11/13] arm64: dts: ls1088a: Add serdes nodes Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 12/13] arm64: dts: ls1088a: Prevent PCSs from probing as phys Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15 ` [PATCH v10 13/13] arm64: dts: ls1088ardb: Add serdes descriptions Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson
2023-03-06 19:15   ` Sean Anderson

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