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* [PATCH 0/5] New boards support: Qualcomm RB2 board
@ 2023-03-24  8:04 Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 1/5] dt-bindings: clock: Import qcom,gcc-sm6115.h Bhupesh Sharma
                   ` (4 more replies)
  0 siblings, 5 replies; 7+ messages in thread
From: Bhupesh Sharma @ 2023-03-24  8:04 UTC (permalink / raw)
  To: u-boot
  Cc: jh80.chung, peng.fan, rfried.dev, sjg, trini, dsankouski,
	bhupesh.linux, bhupesh.sharma

Add initial support for Qualcomm RB2 robotics board (see [1]).
It is based on the Robotics version of the Snapdragon SM4250
Soc, i.e. QRB4210.

Currently it supports standard u-boot and booting upstream linux kernel
Subsequent patchset(s) will add more peripherals like USB, uSD card etc.

As with the existing Snapdragon platforms, u-boot is chain-loaded
in 64-bit mode via Android Boot Loader (ABL) which is an EFI application.

For further details on chain-loading refer to platform specific
documentation:
- doc/board/qualcomm/qrb4210-rb2.rst 

[1]. https://www.qualcomm.com/products/internet-of-things/industrial/industrial-automation/qualcomm-robotics-rb2-platform#Overview

Bhupesh Sharma (5):
  dt-bindings: clock: Import qcom,gcc-sm6115.h
  clocks: qcom: Add clock driver for SM6115 SoC
  reset: qcom: Add support for SM6115 SoC reset table
  pinctrl: qcom: Add pinctrl driver for SM6115 SoC
  board: qualcomm: Add support for QRB4210-RB2

 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/qrb4210-rb2-uboot.dtsi           |  24 +++
 arch/arm/dts/qrb4210-rb2.dtsi                 | 120 +++++++++++
 arch/arm/mach-snapdragon/Kconfig              |  11 +
 arch/arm/mach-snapdragon/Makefile             |   3 +
 arch/arm/mach-snapdragon/clock-qrb4210-rb2.c  | 110 ++++++++++
 arch/arm/mach-snapdragon/clock-snapdragon.c   |   1 +
 arch/arm/mach-snapdragon/clock-snapdragon.h   |   2 +
 .../include/mach/sysmap-qrb4210rb2.h          |  46 ++++
 .../arm/mach-snapdragon/pinctrl-qrb4210-rb2.c |  59 +++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |   1 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |   1 +
 arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c |  35 +++
 board/qualcomm/qrb4210-rb2/Kconfig            |  15 ++
 board/qualcomm/qrb4210-rb2/MAINTAINERS        |   6 +
 board/qualcomm/qrb4210-rb2/Makefile           |   6 +
 board/qualcomm/qrb4210-rb2/qrb4210-rb2.c      |  51 +++++
 board/qualcomm/qrb4210-rb2/qrb4210-rb2.its    |  64 ++++++
 configs/qrb4210rb2_defconfig                  |  56 +++++
 doc/board/qualcomm/index.rst                  |   1 +
 doc/board/qualcomm/qrb4210-rb2.rst            |  79 +++++++
 drivers/reset/reset-qcom.c                    |  18 ++
 include/configs/qrb4210-rb2.h                 |  21 ++
 include/dt-bindings/clock/qcom,gcc-sm6115.h   | 201 ++++++++++++++++++
 24 files changed, 932 insertions(+)
 create mode 100644 arch/arm/dts/qrb4210-rb2-uboot.dtsi
 create mode 100644 arch/arm/dts/qrb4210-rb2.dtsi
 create mode 100644 arch/arm/mach-snapdragon/clock-qrb4210-rb2.c
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c
 create mode 100644 arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c
 create mode 100644 board/qualcomm/qrb4210-rb2/Kconfig
 create mode 100644 board/qualcomm/qrb4210-rb2/MAINTAINERS
 create mode 100644 board/qualcomm/qrb4210-rb2/Makefile
 create mode 100644 board/qualcomm/qrb4210-rb2/qrb4210-rb2.c
 create mode 100644 board/qualcomm/qrb4210-rb2/qrb4210-rb2.its
 create mode 100644 configs/qrb4210rb2_defconfig
 create mode 100644 doc/board/qualcomm/qrb4210-rb2.rst
 create mode 100644 include/configs/qrb4210-rb2.h
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm6115.h

-- 
2.38.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH 1/5] dt-bindings: clock: Import qcom,gcc-sm6115.h
  2023-03-24  8:04 [PATCH 0/5] New boards support: Qualcomm RB2 board Bhupesh Sharma
@ 2023-03-24  8:04 ` Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 2/5] clocks: qcom: Add clock driver for SM6115 SoC Bhupesh Sharma
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Bhupesh Sharma @ 2023-03-24  8:04 UTC (permalink / raw)
  To: u-boot
  Cc: jh80.chung, peng.fan, rfried.dev, sjg, trini, dsankouski,
	bhupesh.linux, bhupesh.sharma

Import qcom,gcc-sm6115.h from Linux to allow standard macros to be
used as clock ids.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 include/dt-bindings/clock/qcom,gcc-sm6115.h | 201 ++++++++++++++++++++
 1 file changed, 201 insertions(+)
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm6115.h

diff --git a/include/dt-bindings/clock/qcom,gcc-sm6115.h b/include/dt-bindings/clock/qcom,gcc-sm6115.h
new file mode 100644
index 0000000000..b91a7b4604
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sm6115.h
@@ -0,0 +1,201 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H
+
+/* GCC clocks */
+#define GPLL0							0
+#define GPLL0_OUT_AUX2						1
+#define GPLL0_OUT_MAIN						2
+#define GPLL10							3
+#define GPLL10_OUT_MAIN						4
+#define GPLL11							5
+#define GPLL11_OUT_MAIN						6
+#define GPLL3							7
+#define GPLL4							8
+#define GPLL4_OUT_MAIN						9
+#define GPLL6							10
+#define GPLL6_OUT_MAIN						11
+#define GPLL7							12
+#define GPLL7_OUT_MAIN						13
+#define GPLL8							14
+#define GPLL8_OUT_MAIN						15
+#define GPLL9							16
+#define GPLL9_OUT_MAIN						17
+#define GCC_CAMSS_CSI0PHYTIMER_CLK				18
+#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC				19
+#define GCC_CAMSS_CSI1PHYTIMER_CLK				20
+#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC				21
+#define GCC_CAMSS_CSI2PHYTIMER_CLK				22
+#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC				23
+#define GCC_CAMSS_MCLK0_CLK					24
+#define GCC_CAMSS_MCLK0_CLK_SRC					25
+#define GCC_CAMSS_MCLK1_CLK					26
+#define GCC_CAMSS_MCLK1_CLK_SRC					27
+#define GCC_CAMSS_MCLK2_CLK					28
+#define GCC_CAMSS_MCLK2_CLK_SRC					29
+#define GCC_CAMSS_MCLK3_CLK					30
+#define GCC_CAMSS_MCLK3_CLK_SRC					31
+#define GCC_CAMSS_NRT_AXI_CLK					32
+#define GCC_CAMSS_OPE_AHB_CLK					33
+#define GCC_CAMSS_OPE_AHB_CLK_SRC				34
+#define GCC_CAMSS_OPE_CLK					35
+#define GCC_CAMSS_OPE_CLK_SRC					36
+#define GCC_CAMSS_RT_AXI_CLK					37
+#define GCC_CAMSS_TFE_0_CLK					38
+#define GCC_CAMSS_TFE_0_CLK_SRC					39
+#define GCC_CAMSS_TFE_0_CPHY_RX_CLK				40
+#define GCC_CAMSS_TFE_0_CSID_CLK				41
+#define GCC_CAMSS_TFE_0_CSID_CLK_SRC				42
+#define GCC_CAMSS_TFE_1_CLK					43
+#define GCC_CAMSS_TFE_1_CLK_SRC					44
+#define GCC_CAMSS_TFE_1_CPHY_RX_CLK				45
+#define GCC_CAMSS_TFE_1_CSID_CLK				46
+#define GCC_CAMSS_TFE_1_CSID_CLK_SRC				47
+#define GCC_CAMSS_TFE_2_CLK					48
+#define GCC_CAMSS_TFE_2_CLK_SRC					49
+#define GCC_CAMSS_TFE_2_CPHY_RX_CLK				50
+#define GCC_CAMSS_TFE_2_CSID_CLK				51
+#define GCC_CAMSS_TFE_2_CSID_CLK_SRC				52
+#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC				53
+#define GCC_CAMSS_TOP_AHB_CLK					54
+#define GCC_CAMSS_TOP_AHB_CLK_SRC				55
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				56
+#define GCC_CPUSS_AHB_CLK					57
+#define GCC_CPUSS_GNOC_CLK					60
+#define GCC_DISP_AHB_CLK					61
+#define GCC_DISP_GPLL0_DIV_CLK_SRC				62
+#define GCC_DISP_HF_AXI_CLK					63
+#define GCC_DISP_THROTTLE_CORE_CLK				64
+#define GCC_DISP_XO_CLK						65
+#define GCC_GP1_CLK						66
+#define GCC_GP1_CLK_SRC						67
+#define GCC_GP2_CLK						68
+#define GCC_GP2_CLK_SRC						69
+#define GCC_GP3_CLK						70
+#define GCC_GP3_CLK_SRC						71
+#define GCC_GPU_CFG_AHB_CLK					72
+#define GCC_GPU_GPLL0_CLK_SRC					73
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				74
+#define GCC_GPU_IREF_CLK					75
+#define GCC_GPU_MEMNOC_GFX_CLK					76
+#define GCC_GPU_SNOC_DVM_GFX_CLK				77
+#define GCC_GPU_THROTTLE_CORE_CLK				78
+#define GCC_GPU_THROTTLE_XO_CLK					79
+#define GCC_PDM2_CLK						80
+#define GCC_PDM2_CLK_SRC					81
+#define GCC_PDM_AHB_CLK						82
+#define GCC_PDM_XO4_CLK						83
+#define GCC_PRNG_AHB_CLK					84
+#define GCC_QMIP_CAMERA_NRT_AHB_CLK				85
+#define GCC_QMIP_CAMERA_RT_AHB_CLK				86
+#define GCC_QMIP_DISP_AHB_CLK					87
+#define GCC_QMIP_GPU_CFG_AHB_CLK				88
+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK				89
+#define GCC_QUPV3_WRAP0_CORE_2X_CLK				90
+#define GCC_QUPV3_WRAP0_CORE_CLK				91
+#define GCC_QUPV3_WRAP0_S0_CLK					92
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				93
+#define GCC_QUPV3_WRAP0_S1_CLK					94
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				95
+#define GCC_QUPV3_WRAP0_S2_CLK					96
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				97
+#define GCC_QUPV3_WRAP0_S3_CLK					98
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				99
+#define GCC_QUPV3_WRAP0_S4_CLK					100
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				101
+#define GCC_QUPV3_WRAP0_S5_CLK					102
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				103
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				104
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				105
+#define GCC_SDCC1_AHB_CLK					106
+#define GCC_SDCC1_APPS_CLK					107
+#define GCC_SDCC1_APPS_CLK_SRC					108
+#define GCC_SDCC1_ICE_CORE_CLK					109
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				110
+#define GCC_SDCC2_AHB_CLK					111
+#define GCC_SDCC2_APPS_CLK					112
+#define GCC_SDCC2_APPS_CLK_SRC					113
+#define GCC_SYS_NOC_CPUSS_AHB_CLK				114
+#define GCC_SYS_NOC_UFS_PHY_AXI_CLK				115
+#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK				116
+#define GCC_UFS_PHY_AHB_CLK					117
+#define GCC_UFS_PHY_AXI_CLK					118
+#define GCC_UFS_PHY_AXI_CLK_SRC					119
+#define GCC_UFS_PHY_ICE_CORE_CLK				120
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				121
+#define GCC_UFS_PHY_PHY_AUX_CLK					122
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				123
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				124
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				125
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				126
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				127
+#define GCC_USB30_PRIM_MASTER_CLK				128
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				129
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				130
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			131
+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC		132
+#define GCC_USB30_PRIM_SLEEP_CLK				133
+#define GCC_USB3_PRIM_CLKREF_CLK				134
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				135
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				136
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				137
+#define GCC_VCODEC0_AXI_CLK					138
+#define GCC_VENUS_AHB_CLK					139
+#define GCC_VENUS_CTL_AXI_CLK					140
+#define GCC_VIDEO_AHB_CLK					141
+#define GCC_VIDEO_AXI0_CLK					142
+#define GCC_VIDEO_THROTTLE_CORE_CLK				143
+#define GCC_VIDEO_VCODEC0_SYS_CLK				144
+#define GCC_VIDEO_VENUS_CLK_SRC					145
+#define GCC_VIDEO_VENUS_CTL_CLK					146
+#define GCC_VIDEO_XO_CLK					147
+#define GCC_AHB2PHY_CSI_CLK					148
+#define GCC_AHB2PHY_USB_CLK					149
+#define GCC_BIMC_GPU_AXI_CLK					150
+#define GCC_BOOT_ROM_AHB_CLK					151
+#define GCC_CAM_THROTTLE_NRT_CLK				152
+#define GCC_CAM_THROTTLE_RT_CLK					153
+#define GCC_CAMERA_AHB_CLK					154
+#define GCC_CAMERA_XO_CLK					155
+#define GCC_CAMSS_AXI_CLK					156
+#define GCC_CAMSS_AXI_CLK_SRC					157
+#define GCC_CAMSS_CAMNOC_ATB_CLK				158
+#define GCC_CAMSS_CAMNOC_NTS_XO_CLK				159
+#define GCC_CAMSS_CCI_0_CLK					160
+#define GCC_CAMSS_CCI_CLK_SRC					161
+#define GCC_CAMSS_CPHY_0_CLK					162
+#define GCC_CAMSS_CPHY_1_CLK					163
+#define GCC_CAMSS_CPHY_2_CLK					164
+#define GCC_UFS_CLKREF_CLK					165
+#define GCC_DISP_GPLL0_CLK_SRC					166
+
+/* GCC resets */
+#define GCC_QUSB2PHY_PRIM_BCR					0
+#define GCC_QUSB2PHY_SEC_BCR					1
+#define GCC_SDCC1_BCR						2
+#define GCC_UFS_PHY_BCR						3
+#define GCC_USB30_PRIM_BCR					4
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				5
+#define GCC_VCODEC0_BCR						6
+#define GCC_VENUS_BCR						7
+#define GCC_VIDEO_INTERFACE_BCR					8
+#define GCC_USB3PHY_PHY_PRIM_SP0_BCR				9
+#define GCC_USB3_PHY_PRIM_SP0_BCR				10
+#define GCC_SDCC2_BCR						11
+
+/* Indexes for GDSCs */
+#define GCC_CAMSS_TOP_GDSC			0
+#define GCC_UFS_PHY_GDSC			1
+#define GCC_USB30_PRIM_GDSC			2
+#define GCC_VCODEC0_GDSC			3
+#define GCC_VENUS_GDSC				4
+#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC		5
+#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC		6
+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC	7
+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC	8
+
+#endif
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 2/5] clocks: qcom: Add clock driver for SM6115 SoC
  2023-03-24  8:04 [PATCH 0/5] New boards support: Qualcomm RB2 board Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 1/5] dt-bindings: clock: Import qcom,gcc-sm6115.h Bhupesh Sharma
@ 2023-03-24  8:04 ` Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 3/5] reset: qcom: Add support for SM6115 SoC reset table Bhupesh Sharma
                   ` (2 subsequent siblings)
  4 siblings, 0 replies; 7+ messages in thread
From: Bhupesh Sharma @ 2023-03-24  8:04 UTC (permalink / raw)
  To: u-boot
  Cc: jh80.chung, peng.fan, rfried.dev, sjg, trini, dsankouski,
	bhupesh.linux, bhupesh.sharma

Currently the SM6115 clock driver initializes clocks for debug UART only.
Along with this import "qcom,gcc-sm6115.h" header from Linux mainline to
support DT bindings.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm/mach-snapdragon/Makefile            |   1 +
 arch/arm/mach-snapdragon/clock-qrb4210-rb2.c | 110 +++++++++++++++++++
 arch/arm/mach-snapdragon/clock-snapdragon.c  |   1 +
 arch/arm/mach-snapdragon/clock-snapdragon.h  |   2 +
 4 files changed, 114 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/clock-qrb4210-rb2.c

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index cbaaf23f6b..23aa1a974c 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -19,3 +19,4 @@ obj-y += pinctrl-qcs404.o
 obj-y += pinctrl-sdm845.o
 obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
 obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
+obj-$(CONFIG_TARGET_QRB4210RB2) += clock-qrb4210-rb2.o
diff --git a/arch/arm/mach-snapdragon/clock-qrb4210-rb2.c b/arch/arm/mach-snapdragon/clock-qrb4210-rb2.c
new file mode 100644
index 0000000000..d67c69b320
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-qrb4210-rb2.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm SM6115
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ *
+ * Based on Kernel driver, simplified
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include "clock-snapdragon.h"
+
+#include <dt-bindings/clock/qcom,gcc-sm6115.h>
+
+/* GPLL clock control registers */
+#define GPLL0_STATUS_ACTIVE	BIT(31)
+
+#define GCC_GLOBAL_EN_BASE		(0x84000)
+#define GCC_CLOBAL_PERIPHERALS_EN	BIT(5)
+
+#define GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1	(0x7900C)
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+struct freq_tbl {
+	uint freq;
+	uint src;
+	u8 pre_div;
+	u16 m;
+	u16 n;
+};
+
+static const struct freq_tbl ftbl_gcc_qupv3_wrap0_s0_clk_src[] = {
+	F(7372800, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 384, 15625),
+	F(14745600, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 768, 15625),
+	F(19200000, CFG_CLK_SRC_CXO, 1, 0, 0),
+	F(29491200, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 1536, 15625),
+	F(32000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 8, 75),
+	F(48000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 4, 25),
+	F(64000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 16, 75),
+	F(75000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 4, 0, 0),
+	F(80000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 4, 15),
+	F(96000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 8, 25),
+	F(100000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 3, 0, 0),
+	F(102400000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 128, 375),
+	F(112000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 28, 75),
+	F(117964800, CFG_CLK_SRC_GPLL0_OUT_AUX2, 1, 6144, 15625),
+	F(120000000, CFG_CLK_SRC_GPLL0_OUT_AUX2, 2.5, 0, 0),
+	F(128000000, CFG_CLK_SRC_GPLL6_OUT_MAIN, 3, 0, 0),
+	{ }
+};
+
+static const struct bcr_regs uart4_regs = {
+	.cfg_rcgr = UART4_APPS_CFG_RCGR,
+	.cmd_rcgr = UART4_APPS_CMD_RCGR,
+	.M = UART4_APPS_M,
+	.N = UART4_APPS_N,
+	.D = UART4_APPS_D,
+};
+
+const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, uint rate)
+{
+	if (!f)
+		return NULL;
+
+	if (!f->freq)
+		return f;
+
+	for (; f->freq; f++)
+		if (rate <= f->freq)
+			return f;
+
+	/* Default to our fastest rate */
+	return f - 1;
+}
+
+static int clk_init_uart(struct msm_clk_priv *priv, uint rate)
+{
+	const struct freq_tbl *freq = qcom_find_freq(ftbl_gcc_qupv3_wrap0_s0_clk_src, rate);
+
+	clk_rcg_set_rate_mnd(priv->base, &uart4_regs,
+						freq->pre_div, freq->m, freq->n, freq->src);
+
+	return 0;
+}
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case GCC_QUPV3_WRAP0_S4_CLK: /* UART4 */
+		return clk_init_uart(priv, rate);
+	default:
+		return 0;
+	}
+
+	return 0;
+}
+
+int msm_enable(struct clk *clk)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 0ac45dce9a..f306fd5b20 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -167,6 +167,7 @@ static const struct udevice_id msm_clk_ids[] = {
 	{ .compatible = "qcom,gcc-msm8996" },
 	{ .compatible = "qcom,gcc-apq8096" },
 	{ .compatible = "qcom,gcc-sdm845" },
+	{ .compatible = "qcom,gcc-sm6115" },
 	{ .compatible = "qcom,gcc-qcs404" },
 	{ }
 };
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h
index c90bbefa58..9e520dbbce 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.h
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.h
@@ -10,6 +10,8 @@
 #define CFG_CLK_SRC_CXO   (0 << 8)
 #define CFG_CLK_SRC_GPLL0 (1 << 8)
 #define CFG_CLK_SRC_GPLL0_EVEN (6 << 8)
+#define CFG_CLK_SRC_GPLL0_OUT_AUX2 (2 << 8)
+#define CFG_CLK_SRC_GPLL6_OUT_MAIN (4 << 8)
 #define CFG_CLK_SRC_MASK  (7 << 8)
 
 struct pll_vote_clk {
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 3/5] reset: qcom: Add support for SM6115 SoC reset table
  2023-03-24  8:04 [PATCH 0/5] New boards support: Qualcomm RB2 board Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 1/5] dt-bindings: clock: Import qcom,gcc-sm6115.h Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 2/5] clocks: qcom: Add clock driver for SM6115 SoC Bhupesh Sharma
@ 2023-03-24  8:04 ` Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 4/5] pinctrl: qcom: Add pinctrl driver for SM6115 SoC Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 5/5] board: qualcomm: Add support for QRB4210-RB2 Bhupesh Sharma
  4 siblings, 0 replies; 7+ messages in thread
From: Bhupesh Sharma @ 2023-03-24  8:04 UTC (permalink / raw)
  To: u-boot
  Cc: jh80.chung, peng.fan, rfried.dev, sjg, trini, dsankouski,
	bhupesh.linux, bhupesh.sharma

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 drivers/reset/reset-qcom.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/reset/reset-qcom.c b/drivers/reset/reset-qcom.c
index 94315e76d5..046d2c083b 100644
--- a/drivers/reset/reset-qcom.c
+++ b/drivers/reset/reset-qcom.c
@@ -131,6 +131,24 @@ static const struct qcom_reset_map gcc_qcom_resets[] = {
 };
 #endif
 
+#ifdef CONFIG_TARGET_QRB4210RB2
+#include <dt-bindings/clock/qcom,gcc-sm6115.h>
+static const struct qcom_reset_map gcc_qcom_resets[] = {
+	[GCC_QUSB2PHY_PRIM_BCR] = { 0x1c000 },
+	[GCC_QUSB2PHY_SEC_BCR] = { 0x1c004 },
+	[GCC_SDCC1_BCR] = { 0x38000 },
+	[GCC_SDCC2_BCR] = { 0x1e000 },
+	[GCC_UFS_PHY_BCR] = { 0x45000 },
+	[GCC_USB30_PRIM_BCR] = { 0x1a000 },
+	[GCC_USB_PHY_CFG_AHB2PHY_BCR] = { 0x1d000 },
+	[GCC_USB3PHY_PHY_PRIM_SP0_BCR] = { 0x1b008 },
+	[GCC_USB3_PHY_PRIM_SP0_BCR] = { 0x1b000 },
+	[GCC_VCODEC0_BCR] = { 0x58094 },
+	[GCC_VENUS_BCR] = { 0x58078 },
+	[GCC_VIDEO_INTERFACE_BCR] = { 0x6e000 },
+};
+#endif
+
 static int qcom_reset_assert(struct reset_ctl *rst)
 {
 	struct qcom_reset_priv *priv = dev_get_priv(rst->dev);
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 4/5] pinctrl: qcom: Add pinctrl driver for SM6115 SoC
  2023-03-24  8:04 [PATCH 0/5] New boards support: Qualcomm RB2 board Bhupesh Sharma
                   ` (2 preceding siblings ...)
  2023-03-24  8:04 ` [PATCH 3/5] reset: qcom: Add support for SM6115 SoC reset table Bhupesh Sharma
@ 2023-03-24  8:04 ` Bhupesh Sharma
  2023-03-24  8:04 ` [PATCH 5/5] board: qualcomm: Add support for QRB4210-RB2 Bhupesh Sharma
  4 siblings, 0 replies; 7+ messages in thread
From: Bhupesh Sharma @ 2023-03-24  8:04 UTC (permalink / raw)
  To: u-boot
  Cc: jh80.chung, peng.fan, rfried.dev, sjg, trini, dsankouski,
	bhupesh.linux, bhupesh.sharma

Currently this pinctrl driver only supports debug UART
specific pin configuration.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm/mach-snapdragon/Makefile             |  1 +
 .../arm/mach-snapdragon/pinctrl-qrb4210-rb2.c | 59 +++++++++++++++++++
 arch/arm/mach-snapdragon/pinctrl-snapdragon.c |  1 +
 arch/arm/mach-snapdragon/pinctrl-snapdragon.h |  1 +
 4 files changed, 62 insertions(+)
 create mode 100644 arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c

diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 23aa1a974c..4ee6a3902e 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -16,6 +16,7 @@ obj-y += pinctrl-snapdragon.o
 obj-y += pinctrl-apq8016.o
 obj-y += pinctrl-apq8096.o
 obj-y += pinctrl-qcs404.o
+obj-y += pinctrl-qrb4210-rb2.o
 obj-y += pinctrl-sdm845.o
 obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
 obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c b/arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c
new file mode 100644
index 0000000000..a8ab67f20a
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-qrb4210-rb2.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SM6115 pinctrl
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ *
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+
+static const char * const msm_pinctrl_pins[] = {
+	"UFS_RESET",
+	"SDC1_RCLK",
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"qup4", 1},
+	{"gpio", 0},
+};
+
+static const char *sm6115_get_function_name(struct udevice *dev,
+					     unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *sm6115_get_pin_name(struct udevice *dev,
+					unsigned int selector)
+{
+	if (selector < 113) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 113];
+	}
+}
+
+static unsigned int sm6115_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data sm6115_data = {
+	.pin_count = 120,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = sm6115_get_function_name,
+	.get_function_mux = sm6115_get_function_mux,
+	.get_pin_name = sm6115_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index 826dc51486..e7efb5b29f 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -151,6 +151,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
 	{ .compatible = "qcom,msm8916-pinctrl", .data = (ulong)&apq8016_data },
 	{ .compatible = "qcom,msm8996-pinctrl", .data = (ulong)&apq8096_data },
 	{ .compatible = "qcom,sdm845-pinctrl", .data = (ulong)&sdm845_data },
+	{ .compatible = "qcom,sm6115-pinctrl", .data = (ulong)&sm6115_data },
 	{ .compatible = "qcom,qcs404-pinctrl", .data = (ulong)&qcs404_data },
 	{ }
 };
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index 178ee01a41..7f543b0f5a 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -28,6 +28,7 @@ struct pinctrl_function {
 extern struct msm_pinctrl_data apq8016_data;
 extern struct msm_pinctrl_data apq8096_data;
 extern struct msm_pinctrl_data sdm845_data;
+extern struct msm_pinctrl_data sm6115_data;
 extern struct msm_pinctrl_data qcs404_data;
 
 #endif
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* [PATCH 5/5] board: qualcomm: Add support for QRB4210-RB2
  2023-03-24  8:04 [PATCH 0/5] New boards support: Qualcomm RB2 board Bhupesh Sharma
                   ` (3 preceding siblings ...)
  2023-03-24  8:04 ` [PATCH 4/5] pinctrl: qcom: Add pinctrl driver for SM6115 SoC Bhupesh Sharma
@ 2023-03-24  8:04 ` Bhupesh Sharma
  2023-03-24 15:56   ` Tom Rini
  4 siblings, 1 reply; 7+ messages in thread
From: Bhupesh Sharma @ 2023-03-24  8:04 UTC (permalink / raw)
  To: u-boot
  Cc: jh80.chung, peng.fan, rfried.dev, sjg, trini, dsankouski,
	bhupesh.linux, bhupesh.sharma

Add support for Qualcomm QRB4210-RB2 evaluation board
(based on Qualcomm QRB4210 SoC).

Features:
   - Qualcomm Snapdragon QRB4210 (Robotics version of SM6115 SoC).
   - 2GiB RAM (on-board) [max: 8 GiB].
   - 16GiB eMMC, uSD slot.

U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.

For detailed build and boot instructions, refer to
doc/board/qualcomm/qrb4210-rb2.rst.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
---
 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/qrb4210-rb2-uboot.dtsi           |  24 ++++
 arch/arm/dts/qrb4210-rb2.dtsi                 | 120 ++++++++++++++++++
 arch/arm/mach-snapdragon/Kconfig              |  11 ++
 arch/arm/mach-snapdragon/Makefile             |   1 +
 .../include/mach/sysmap-qrb4210rb2.h          |  46 +++++++
 arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c |  35 +++++
 board/qualcomm/qrb4210-rb2/Kconfig            |  15 +++
 board/qualcomm/qrb4210-rb2/MAINTAINERS        |   6 +
 board/qualcomm/qrb4210-rb2/Makefile           |   6 +
 board/qualcomm/qrb4210-rb2/qrb4210-rb2.c      |  51 ++++++++
 board/qualcomm/qrb4210-rb2/qrb4210-rb2.its    |  64 ++++++++++
 configs/qrb4210rb2_defconfig                  |  56 ++++++++
 doc/board/qualcomm/index.rst                  |   1 +
 doc/board/qualcomm/qrb4210-rb2.rst            |  79 ++++++++++++
 include/configs/qrb4210-rb2.h                 |  21 +++
 16 files changed, 537 insertions(+)
 create mode 100644 arch/arm/dts/qrb4210-rb2-uboot.dtsi
 create mode 100644 arch/arm/dts/qrb4210-rb2.dtsi
 create mode 100644 arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h
 create mode 100644 arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c
 create mode 100644 board/qualcomm/qrb4210-rb2/Kconfig
 create mode 100644 board/qualcomm/qrb4210-rb2/MAINTAINERS
 create mode 100644 board/qualcomm/qrb4210-rb2/Makefile
 create mode 100644 board/qualcomm/qrb4210-rb2/qrb4210-rb2.c
 create mode 100644 board/qualcomm/qrb4210-rb2/qrb4210-rb2.its
 create mode 100644 configs/qrb4210rb2_defconfig
 create mode 100644 doc/board/qualcomm/qrb4210-rb2.rst
 create mode 100644 include/configs/qrb4210-rb2.h

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c160e884bf..b551c904d1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -534,6 +534,7 @@ dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
 dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
 dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
+dtb-$(CONFIG_TARGET_QRB4210RB2) += qrb4210-rb2.dtb
 
 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
 
diff --git a/arch/arm/dts/qrb4210-rb2-uboot.dtsi b/arch/arm/dts/qrb4210-rb2-uboot.dtsi
new file mode 100644
index 0000000000..8588dc2bf6
--- /dev/null
+++ b/arch/arm/dts/qrb4210-rb2-uboot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle QRB4210-RB2 pre-relocation devices
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ */
+
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+
+		pinctrl_west@500000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		clock-controller@1400000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@4a90000 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/qrb4210-rb2.dtsi b/arch/arm/dts/qrb4210-rb2.dtsi
new file mode 100644
index 0000000000..ba07263c4a
--- /dev/null
+++ b/arch/arm/dts/qrb4210-rb2.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QRB4210-RB2 evaluation board device tree source
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/qcom,gcc-sm6115.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. QRB4210 RB2";
+	compatible = "qcom,qrb4210-rb2", "qcom,qrb4210", "qcom,sm4250";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &debug_uart;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x40000000>;
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		tlmm: pinctrl_west@500000 {
+			compatible = "qcom,sm6115-pinctrl";
+			reg = <0x00500000 0x400000>;
+			gpio-count = <114>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm_north 0 0 114>;
+
+			/* DEBUG UART */
+			debug_uart_on: debug_uart-default {
+				pins = "GPIO_12", "GPIO_13";
+				function = "qup4";
+			};
+		};
+
+		gcc: clock-controller@1400000 {
+			compatible = "qcom,gcc-sm6115";
+			reg = <0x01400000 0x1f0000>;
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+			#power-domain-cells = <1>;
+		};
+
+		debug_uart: serial@4a90000 {
+			compatible = "qcom,msm-geni-uart";
+			reg = <0x04a90000 0x4000>;
+			clock-names = "se-clk";
+			clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&debug_uart_on>;
+		};
+
+		sdhc_1: mmc@4744000 {
+			compatible = "qcom,sdhci-msm-v5";
+			reg = <0x04744000 0x1000 0x04745000 0x1000>;
+			clock = <&gcc GCC_SDCC1_APPS_CLK>,
+				<&gcc GCC_SDCC1_AHB_CLK>;
+			bus-width = <8>;
+
+			no-sdio;
+			non-removable;
+		};
+
+		sdhc_2: mmc@4784000 {
+			compatible = "qcom,sdhci-msm-v5";
+			reg = <0x04784000 0x1000>;
+			clock = <&gcc GCC_SDCC2_APPS_CLK>,
+				<&gcc GCC_SDCC2_AHB_CLK>;
+			bus-width = <4>;
+
+			no-sdio;
+		};
+
+		spmi@1c40000 {
+			compatible = "qcom,spmi-pmic-arb";
+			reg = <0x01c0a000 0x26000>,
+			      <0x01c40000 0x1100>,
+			      <0x03e00000 0x100000>;
+			reg-names = "cnfg", "core", "obsrvr";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			pm6125: pm6125@0 {
+				compatible = "qcom,spmi-pmic";
+				reg = <0x0 0x1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				pm6125_gpios: pm6125_gpios@c000 {
+					compatible = "qcom,pm6125-gpio";
+					reg = <0xc000>;
+					gpio-controller;
+					gpio-count = <9>;
+					#gpio-cells = <2>;
+					gpio-bank-name="pmic";
+				};
+			};
+		};
+	};
+};
+
+#include "qrb4210-rb2-uboot.dtsi"
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 914f4d9605..f150192cbb 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -77,6 +77,16 @@ config TARGET_QCS404EVB
 	  - 1GiB RAM
 	  - 8GiB eMMC, uSD slot
 
+config TARGET_QRB4210RB2
+	bool "Qualcomm Technologies, Inc. QRB4210 RB2"
+	select LINUX_KERNEL_IMAGE_HEADER
+	help
+	  Support for Qualcomm Technologies, Inc. QRB4210 RB2 board.
+	  Features:
+	  - Qualcomm Snapdragon SM6115 / SM4250 SoC
+	  - 2GiB RAM
+	  - 16GiB eMMC
+
 endchoice
 
 source "board/qualcomm/dragonboard410c/Kconfig"
@@ -84,5 +94,6 @@ source "board/qualcomm/dragonboard820c/Kconfig"
 source "board/qualcomm/dragonboard845c/Kconfig"
 source "board/samsung/starqltechn/Kconfig"
 source "board/qualcomm/qcs404-evb/Kconfig"
+source "board/qualcomm/qrb4210-rb2/Kconfig"
 
 endif
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 4ee6a3902e..eef584aaed 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -21,3 +21,4 @@ obj-y += pinctrl-sdm845.o
 obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
 obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
 obj-$(CONFIG_TARGET_QRB4210RB2) += clock-qrb4210-rb2.o
+obj-$(CONFIG_TARGET_QRB4210RB2) += sysmap-qrb4210-rb2.o
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h
new file mode 100644
index 0000000000..544e48cf00
--- /dev/null
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qrb4210rb2.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm SM6115 sysmap
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ */
+#ifndef _MACH_SYSMAP_SM6115_H
+#define _MACH_SYSMAP_SM6115_H
+
+/* Clocks: (from CLK_CTL_BASE)  */
+#define GPLL0_STATUS			(0x0)
+#define APCS_GPLL_ENA_VOTE		(0x79000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x79004)
+
+/* Root clock for QUPv3 WRAPPER0 */
+#define QUPV3_WRAPPER_0_BCR	(0x1F000)
+
+/* Uart clock control registers */
+#define UART4_APPS_CBCR		(0x1F604)
+#define UART4_APPS_CMD_RCGR	(0x1F608)
+#define UART4_APPS_CFG_RCGR	(0x1F60c)
+#define UART4_APPS_M		(0x1F610)
+#define UART4_APPS_N		(0x1F614)
+#define UART4_APPS_D		(0x1F618)
+
+/* SDCC1 controller clock control registers */
+#define SDCC1_BCR		(0x38000)
+#define SDCC1_APPS_CBCR		(0x38004)
+#define SDCC1_AHB_CBCR		(0x38008)
+#define SDCC1_CMD_RCGR		(0x38028)
+#define SDCC1_CFG_RCGR		(0x3802c)
+#define SDCC1_M			(0x38030)
+#define SDCC1_N			(0x38034)
+#define SDCC1_D			(0x38038)
+
+/* SDCC2 controller clock control registers */
+#define SDCC2_BCR		(0x1E000)
+#define SDCC2_APPS_CBCR		(0x1E004)
+#define SDCC2_AHB_CBCR		(0x1E008)
+#define SDCC2_CMD_RCGR		(0x1E00C)
+#define SDCC2_CFG_RCGR		(0x1E010)
+#define SDCC2_M			(0x1E014)
+#define SDCC2_N			(0x1E018)
+#define SDCC2_D			(0x1E01c)
+
+#endif
diff --git a/arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c b/arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c
new file mode 100644
index 0000000000..c08a6d7d9f
--- /dev/null
+++ b/arch/arm/mach-snapdragon/sysmap-qrb4210-rb2.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm SM6115 memory map
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region sm6115_mem_map[] = {
+	/* Peripheral block */
+	{
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x40000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN |
+			 PTE_BLOCK_UXN
+	},
+
+	{
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x80000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	},
+
+	/* Terminator */
+	{ 0 }
+};
+
+struct mm_region *mem_map = sm6115_mem_map;
diff --git a/board/qualcomm/qrb4210-rb2/Kconfig b/board/qualcomm/qrb4210-rb2/Kconfig
new file mode 100644
index 0000000000..485757e268
--- /dev/null
+++ b/board/qualcomm/qrb4210-rb2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QRB4210RB2
+
+config SYS_BOARD
+	default "qrb4210-rb2"
+
+config SYS_VENDOR
+	default "qualcomm"
+
+config SYS_SOC
+	default "sm6115"
+
+config SYS_CONFIG_NAME
+	default "qrb4210-rb2"
+
+endif
diff --git a/board/qualcomm/qrb4210-rb2/MAINTAINERS b/board/qualcomm/qrb4210-rb2/MAINTAINERS
new file mode 100644
index 0000000000..2b569bb983
--- /dev/null
+++ b/board/qualcomm/qrb4210-rb2/MAINTAINERS
@@ -0,0 +1,6 @@
+Qualcomm Technologies, Inc. QRB4210-RB2 evaluation board
+M:	Bhupesh Sharma <bhupesh.sharma@linaro.org>
+S:	Maintained
+F:	board/qualcomm/qrb4210-rb2/
+F:	include/configs/qrb4210-rb2.h
+F:	configs/qrb4210rb2_defconfig
diff --git a/board/qualcomm/qrb4210-rb2/Makefile b/board/qualcomm/qrb4210-rb2/Makefile
new file mode 100644
index 0000000000..d3cebdd221
--- /dev/null
+++ b/board/qualcomm/qrb4210-rb2/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+#
+
+obj-y += qrb4210-rb2.o
diff --git a/board/qualcomm/qrb4210-rb2/qrb4210-rb2.c b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.c
new file mode 100644
index 0000000000..38c2c23f78
--- /dev/null
+++ b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for QRB4210-RB2
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <asm/cache.h>
+#include <asm/gpio.h>
+#include <asm/global_data.h>
+#include <fdt_support.h>
+#include <asm/psci.h>
+#include <asm/arch/dram.h>
+
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+static void show_psci_version(void)
+{
+	struct arm_smccc_res res;
+
+	arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+	printf("PSCI:  v%ld.%ld\n",
+	       PSCI_VERSION_MAJOR(res.a0),
+		PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+	show_psci_version();
+
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
diff --git a/board/qualcomm/qrb4210-rb2/qrb4210-rb2.its b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.its
new file mode 100644
index 0000000000..df77874d60
--- /dev/null
+++ b/board/qualcomm/qrb4210-rb2/qrb4210-rb2.its
@@ -0,0 +1,64 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Various kernels, ramdisks and FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel-1 {
+			description = "6.2-rc8";
+			data = /incbin/("./qrb4210rb2_imgs/Image.gz");
+			type = "kernel";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <0x80000000>;
+			entry = <0x80000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		ramdisk-1 {
+			description = "Initial ramdisk";
+			data = /incbin/("./qrb4210rb2_imgs/initramfs-test-image-qemuarm64-20230209073803-1343.rootfs.cpio.gz");
+			type = "ramdisk";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <00000000>;
+			entry = <00000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		fdt-1 {
+			description = "qrb4210-rb2-fdt";
+			data = /incbin/("./qrb4210rb2_imgs/qrb4210-rb2.dtb");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			load = <0x83000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+	};
+
+	configurations {
+		default = "config-1";
+
+		config-1 {
+			description = "qrb4210-rb2 kernel-6.2-rc8 configuration";
+			kernel = "kernel-1";
+			ramdisk = "ramdisk-1";
+			fdt = "fdt-1";
+		};
+	};
+};
diff --git a/configs/qrb4210rb2_defconfig b/configs/qrb4210rb2_defconfig
new file mode 100644
index 0000000000..d04e6af729
--- /dev/null
+++ b/configs/qrb4210rb2_defconfig
@@ -0,0 +1,56 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_DEFAULT_DEVICE_TREE="qrb4210-rb2"
+CONFIG_TARGET_QRB4210RB2=y
+CONFIG_IDENT_STRING="\nQualcomm QRB4210-RB2"
+CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_QCOM_PMIC_GPIO=y
+CONFIG_MISC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PHY=y
+CONFIG_PHY_QCOM_USB_HS_28NM=y
+CONFIG_PHY_QCOM_USB_SS=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_QCOM=y
+CONFIG_DM_RESET=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_REQUIRE_SERIAL_CONSOLE=y
+CONFIG_MSM_GPIO=y
+CONFIG_SPMI_MSM=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_LMB_MAX_REGIONS=64
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 0f9c429956..8b840a0d5a 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -9,3 +9,4 @@ Qualcomm
    dragonboard410c
    sdm845
    qcs404
+   qrb4210-rb2
diff --git a/doc/board/qualcomm/qrb4210-rb2.rst b/doc/board/qualcomm/qrb4210-rb2.rst
new file mode 100644
index 0000000000..65815d2325
--- /dev/null
+++ b/doc/board/qualcomm/qrb4210-rb2.rst
@@ -0,0 +1,79 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Bhupesh Sharma <bhupesh.sharma@linaro.org>
+
+QRB4210 RB2
+===========
+
+About this
+----------
+This document describes the information about Qualcomm QRB4210 RB2 board
+and it's usage steps.
+
+U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
+It is loaded as an Android boot image through ABL.
+
+Installation
+------------
+Build
+^^^^^
+Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
+
+	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
+	$ make qrb4210rb2_defconfig
+	$ make
+
+This will build ``u-boot.bin`` in the configured output directory.
+
+Generate FIT image
+^^^^^^^^^^^^^^^^^^
+A ``qrb4210-rb2.its`` file can be found in ``board/qualcomm/qrb4210-rb2/`` directory.
+It expects a folder as ``qrb4210rb2_imgs/`` in the main directory containing
+pre-built kernel, dts and ramdisk images. See ``qrb4210-rb2.its`` for full path to
+images.
+
+- Build FIT image::
+
+	mkimage -f qrb4210-rb2.its qrb4210-rb2.itb
+
+Pack android boot image
+^^^^^^^^^^^^^^^^^^^^^^^
+We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
+and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
+with appended dtb, so let's mimic linux to satisfy stock bootloader:
+
+- create dump dtb::
+
+	workdir=/tmp/prepare_payload
+	mkdir -p "$workdir"
+	cd "$workdir"
+	mock_dtb="$workdir"/payload_mock.dtb
+
+	dtc -I dts -O dtb -o "$mock_dtb" << EOF
+	/dts-v1/;
+	/ {
+		model = "Qualcomm Technologies, Inc. QRB4210 RB2";
+		compatible = "qcom,qrb4210-rb2", "qcom,sm6115";
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		memory@80000000 {
+			device_type = "memory";
+			/* We expect the bootloader to fill in the size */
+			reg = <0 0x80000000 0 0>;
+		};
+
+		chosen { };
+	};
+	EOF
+
+- gzip u-boot ``gzip u-boot.bin``
+- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
+
+Now we've got everything to build android boot image:::
+
+	mkbootimg --kernel u-boot.bin.gz-dtb \
+	--ramdisk qrb4210-rb2.itb --pagesize 4096 \
+	--base 0x80000000 --output boot.img
+
+Flash image on qrb4210 rb2 using fastboot method.
diff --git a/include/configs/qrb4210-rb2.h b/include/configs/qrb4210-rb2.h
new file mode 100644
index 0000000000..80b9c5e2dd
--- /dev/null
+++ b/include/configs/qrb4210-rb2.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for QRB4210-RB2 board
+ *
+ * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
+ */
+
+#ifndef __CONFIGS_QRB4210RB2_H
+#define __CONFIGS_QRB4210RB2_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-qrb4210rb2.h>
+
+#define CFG_SYS_BAUDRATE_TABLE	{ 115200 }
+
+#define CFG_EXTRA_ENV_SETTINGS \
+	"bootm_size=0x5000000\0"	\
+	"bootm_low=0x80000000\0"	\
+	"bootcmd=bootm $prevbl_initrd_start_addr\0"
+
+#endif
-- 
2.38.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread
* Re: [PATCH 5/5] board: qualcomm: Add support for QRB4210-RB2
  2023-03-24  8:04 ` [PATCH 5/5] board: qualcomm: Add support for QRB4210-RB2 Bhupesh Sharma
@ 2023-03-24 15:56   ` Tom Rini
  0 siblings, 0 replies; 7+ messages in thread
From: Tom Rini @ 2023-03-24 15:56 UTC (permalink / raw)
  To: Bhupesh Sharma
  Cc: u-boot, jh80.chung, peng.fan, rfried.dev, sjg, dsankouski, bhupesh.linux

[-- Attachment #1: Type: text/plain, Size: 2888 bytes --]

On Fri, Mar 24, 2023 at 01:34:18PM +0530, Bhupesh Sharma wrote:

> Add support for Qualcomm QRB4210-RB2 evaluation board
> (based on Qualcomm QRB4210 SoC).
> 
> Features:
>    - Qualcomm Snapdragon QRB4210 (Robotics version of SM6115 SoC).
>    - 2GiB RAM (on-board) [max: 8 GiB].
>    - 16GiB eMMC, uSD slot.
> 
> U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
> 
> For detailed build and boot instructions, refer to
> doc/board/qualcomm/qrb4210-rb2.rst.
> 
> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
[snip]
You don't say where the dtsi file is synced from, and it should be in
linux-next or similar, at least.

[snip]
> diff --git a/arch/arm/dts/qrb4210-rb2-uboot.dtsi b/arch/arm/dts/qrb4210-rb2-uboot.dtsi
> new file mode 100644
> index 0000000000..8588dc2bf6
> --- /dev/null
> +++ b/arch/arm/dts/qrb4210-rb2-uboot.dtsi

"-u-boot.dtsi" is automatically included, but this needs #included,
also:

> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * U-Boot addition to handle QRB4210-RB2 pre-relocation devices
> + *
> + * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
> + */
> +
> +/ {
> +	soc {
> +		u-boot,dm-pre-reloc;

You didn't build-test on -next, where these are all bootph-* now. And,
they go upstream too as the binding exists there.

> diff --git a/board/qualcomm/qrb4210-rb2/MAINTAINERS b/board/qualcomm/qrb4210-rb2/MAINTAINERS
> new file mode 100644
> index 0000000000..2b569bb983
> --- /dev/null
> +++ b/board/qualcomm/qrb4210-rb2/MAINTAINERS
> @@ -0,0 +1,6 @@
> +Qualcomm Technologies, Inc. QRB4210-RB2 evaluation board
> +M:	Bhupesh Sharma <bhupesh.sharma@linaro.org>
> +S:	Maintained
> +F:	board/qualcomm/qrb4210-rb2/
> +F:	include/configs/qrb4210-rb2.h
> +F:	configs/qrb4210rb2_defconfig

Please list the board doc file as well here (which I'm quite glad to see
you wrote!).

> diff --git a/include/configs/qrb4210-rb2.h b/include/configs/qrb4210-rb2.h
> new file mode 100644
> index 0000000000..80b9c5e2dd
> --- /dev/null
> +++ b/include/configs/qrb4210-rb2.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Configuration file for QRB4210-RB2 board
> + *
> + * (C) Copyright 2023 Bhupesh Sharma <bhupesh.sharma@linaro.org>
> + */
> +
> +#ifndef __CONFIGS_QRB4210RB2_H
> +#define __CONFIGS_QRB4210RB2_H
> +
> +#include <linux/sizes.h>
> +#include <asm/arch/sysmap-qrb4210rb2.h>

We should really really not need include files here. You aren't using
either of them directly.

> +#define CFG_SYS_BAUDRATE_TABLE	{ 115200 }
> +
> +#define CFG_EXTRA_ENV_SETTINGS \
> +	"bootm_size=0x5000000\0"	\
> +	"bootm_low=0x80000000\0"	\
> +	"bootcmd=bootm $prevbl_initrd_start_addr\0"

Shouldn't this be using either distro_bootcmd or bootstd (see
doc/develop/bootstd.rst) instead?

-- 
Tom

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^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-03-24 15:56 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-03-24  8:04 [PATCH 0/5] New boards support: Qualcomm RB2 board Bhupesh Sharma
2023-03-24  8:04 ` [PATCH 1/5] dt-bindings: clock: Import qcom,gcc-sm6115.h Bhupesh Sharma
2023-03-24  8:04 ` [PATCH 2/5] clocks: qcom: Add clock driver for SM6115 SoC Bhupesh Sharma
2023-03-24  8:04 ` [PATCH 3/5] reset: qcom: Add support for SM6115 SoC reset table Bhupesh Sharma
2023-03-24  8:04 ` [PATCH 4/5] pinctrl: qcom: Add pinctrl driver for SM6115 SoC Bhupesh Sharma
2023-03-24  8:04 ` [PATCH 5/5] board: qualcomm: Add support for QRB4210-RB2 Bhupesh Sharma
2023-03-24 15:56   ` Tom Rini

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