From: Sascha Hauer <s.hauer@pengutronix.de> To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>, Kyungmin Park <kyungmin.park@samsung.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, kernel@pengutronix.de, Michael Riesch <michael.riesch@wolfvision.net>, Sascha Hauer <s.hauer@pengutronix.de> Subject: [PATCH v4 17/21] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers Date: Fri, 5 May 2023 13:38:52 +0200 [thread overview] Message-ID: <20230505113856.463650-18-s.hauer@pengutronix.de> (raw) In-Reply-To: <20230505113856.463650-1-s.hauer@pengutronix.de> The currently supported RK3399 has a set of registers per channel, but it has only a single DDRMON_CTRL register. With upcoming RK3588 this will be different, the RK3588 has a DDRMON_CTRL register per channel. Instead of expecting a single DDRMON_CTRL register, loop over the channels and write the channel specific DDRMON_CTRL register. Break out early out of the loop when there is only a single DDRMON_CTRL register like on the RK3399. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/devfreq/event/rockchip-dfi.c | 69 ++++++++++++++++++---------- 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 3d76e58c602b2..74d69153e6386 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -101,12 +101,13 @@ struct rockchip_dfi { int burst_len; int buswidth[DMC_MAX_CHANNELS]; int ddrmon_stride; + bool ddrmon_ctrl_single; }; static int rockchip_dfi_enable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; - int ret = 0; + int i, ret = 0; mutex_lock(&dfi->mutex); @@ -120,28 +121,39 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi) goto out; } - /* clear DDRMON_CTRL setting */ - writel_relaxed(HIWORD_UPDATE(0, 0xffff), dfi_regs + DDRMON_CTRL); + for (i = 0; i < DMC_MAX_CHANNELS; i++) { + if (!(dfi->channel_mask & BIT(i))) + continue; - /* set ddr type to dfi */ - switch (dfi->ddr_type) { - case ROCKCHIP_DDRTYPE_LPDDR2: - case ROCKCHIP_DDRTYPE_LPDDR3: - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), - dfi_regs + DDRMON_CTRL); - break; - case ROCKCHIP_DDRTYPE_LPDDR4: - case ROCKCHIP_DDRTYPE_LPDDR4X: - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), - dfi_regs + DDRMON_CTRL); - break; - default: - break; - } + /* clear DDRMON_CTRL setting */ + writel_relaxed(HIWORD_UPDATE(0, 0xffff), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + /* set ddr type to dfi */ + switch (dfi->ddr_type) { + case ROCKCHIP_DDRTYPE_LPDDR2: + case ROCKCHIP_DDRTYPE_LPDDR3: + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, + DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + break; + case ROCKCHIP_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4X: + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, + DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + break; + default: + break; + } + + /* enable count, use software mode */ + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); - /* enable count, use software mode */ - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), - dfi_regs + DDRMON_CTRL); + if (dfi->ddrmon_ctrl_single) + break; + } out: mutex_unlock(&dfi->mutex); @@ -151,6 +163,7 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi) static void rockchip_dfi_disable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; + int i; mutex_lock(&dfi->mutex); @@ -161,8 +174,17 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi) if (dfi->usecount > 0) goto out; - writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), - dfi_regs + DDRMON_CTRL); + for (i = 0; i < DMC_MAX_CHANNELS; i++) { + if (!(dfi->channel_mask & BIT(i))) + continue; + + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + if (dfi->ddrmon_ctrl_single) + break; + } + clk_disable_unprepare(dfi->clk); out: mutex_unlock(&dfi->mutex); @@ -569,6 +591,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2; dfi->ddrmon_stride = 0x14; + dfi->ddrmon_ctrl_single = true; return 0; }; -- 2.39.2 _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip
WARNING: multiple messages have this Message-ID (diff)
From: Sascha Hauer <s.hauer@pengutronix.de> To: linux-rockchip@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, Heiko Stuebner <heiko@sntech.de>, Kyungmin Park <kyungmin.park@samsung.com>, MyungJoo Ham <myungjoo.ham@samsung.com>, Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>, kernel@pengutronix.de, Michael Riesch <michael.riesch@wolfvision.net>, Sascha Hauer <s.hauer@pengutronix.de> Subject: [PATCH v4 17/21] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers Date: Fri, 5 May 2023 13:38:52 +0200 [thread overview] Message-ID: <20230505113856.463650-18-s.hauer@pengutronix.de> (raw) In-Reply-To: <20230505113856.463650-1-s.hauer@pengutronix.de> The currently supported RK3399 has a set of registers per channel, but it has only a single DDRMON_CTRL register. With upcoming RK3588 this will be different, the RK3588 has a DDRMON_CTRL register per channel. Instead of expecting a single DDRMON_CTRL register, loop over the channels and write the channel specific DDRMON_CTRL register. Break out early out of the loop when there is only a single DDRMON_CTRL register like on the RK3399. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> --- drivers/devfreq/event/rockchip-dfi.c | 69 ++++++++++++++++++---------- 1 file changed, 46 insertions(+), 23 deletions(-) diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c index 3d76e58c602b2..74d69153e6386 100644 --- a/drivers/devfreq/event/rockchip-dfi.c +++ b/drivers/devfreq/event/rockchip-dfi.c @@ -101,12 +101,13 @@ struct rockchip_dfi { int burst_len; int buswidth[DMC_MAX_CHANNELS]; int ddrmon_stride; + bool ddrmon_ctrl_single; }; static int rockchip_dfi_enable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; - int ret = 0; + int i, ret = 0; mutex_lock(&dfi->mutex); @@ -120,28 +121,39 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi) goto out; } - /* clear DDRMON_CTRL setting */ - writel_relaxed(HIWORD_UPDATE(0, 0xffff), dfi_regs + DDRMON_CTRL); + for (i = 0; i < DMC_MAX_CHANNELS; i++) { + if (!(dfi->channel_mask & BIT(i))) + continue; - /* set ddr type to dfi */ - switch (dfi->ddr_type) { - case ROCKCHIP_DDRTYPE_LPDDR2: - case ROCKCHIP_DDRTYPE_LPDDR3: - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK), - dfi_regs + DDRMON_CTRL); - break; - case ROCKCHIP_DDRTYPE_LPDDR4: - case ROCKCHIP_DDRTYPE_LPDDR4X: - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK), - dfi_regs + DDRMON_CTRL); - break; - default: - break; - } + /* clear DDRMON_CTRL setting */ + writel_relaxed(HIWORD_UPDATE(0, 0xffff), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + /* set ddr type to dfi */ + switch (dfi->ddr_type) { + case ROCKCHIP_DDRTYPE_LPDDR2: + case ROCKCHIP_DDRTYPE_LPDDR3: + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, + DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + break; + case ROCKCHIP_DDRTYPE_LPDDR4: + case ROCKCHIP_DDRTYPE_LPDDR4X: + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, + DDRMON_CTRL_DDR_TYPE_MASK), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + break; + default: + break; + } + + /* enable count, use software mode */ + writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); - /* enable count, use software mode */ - writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN), - dfi_regs + DDRMON_CTRL); + if (dfi->ddrmon_ctrl_single) + break; + } out: mutex_unlock(&dfi->mutex); @@ -151,6 +163,7 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi) static void rockchip_dfi_disable(struct rockchip_dfi *dfi) { void __iomem *dfi_regs = dfi->regs; + int i; mutex_lock(&dfi->mutex); @@ -161,8 +174,17 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi) if (dfi->usecount > 0) goto out; - writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), - dfi_regs + DDRMON_CTRL); + for (i = 0; i < DMC_MAX_CHANNELS; i++) { + if (!(dfi->channel_mask & BIT(i))) + continue; + + writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN), + dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL); + + if (dfi->ddrmon_ctrl_single) + break; + } + clk_disable_unprepare(dfi->clk); out: mutex_unlock(&dfi->mutex); @@ -569,6 +591,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi) dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2; dfi->ddrmon_stride = 0x14; + dfi->ddrmon_ctrl_single = true; return 0; }; -- 2.39.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2023-05-05 11:39 UTC|newest] Thread overview: 121+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-05-05 11:38 [PATCH v4 00/21] Add perf support to the rockchip-dfi driver Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 01/21] PM / devfreq: rockchip-dfi: Embed desc into private data struct Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-07 10:08 ` Heiko Stübner 2023-05-07 10:08 ` Heiko Stübner 2023-05-16 15:12 ` Jonathan Cameron 2023-05-16 15:12 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 02/21] PM / devfreq: rockchip-dfi: use consistent name for " Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-07 10:22 ` Heiko Stübner 2023-05-07 10:22 ` Heiko Stübner 2023-05-16 15:27 ` Jonathan Cameron 2023-05-16 15:27 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 03/21] PM / devfreq: rockchip-dfi: Make pmu regmap mandatory Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 15:33 ` Jonathan Cameron 2023-05-16 15:33 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 04/21] PM / devfreq: rockchip-dfi: Add SoC specific init function Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 15:40 ` Jonathan Cameron 2023-05-16 15:40 ` Jonathan Cameron 2023-05-17 9:20 ` Sascha Hauer 2023-05-17 9:20 ` Sascha Hauer 2023-05-17 10:19 ` Jonathan Cameron 2023-05-17 10:19 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 05/21] PM / devfreq: rockchip-dfi: dfi store raw values in counter struct Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 15:43 ` Jonathan Cameron 2023-05-16 15:43 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 06/21] PM / devfreq: rockchip-dfi: Use free running counter Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 15:48 ` Jonathan Cameron 2023-05-16 15:48 ` Jonathan Cameron 2023-05-17 9:29 ` Sascha Hauer 2023-05-17 9:29 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 07/21] PM / devfreq: rockchip-dfi: introduce channel mask Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 15:50 ` Jonathan Cameron 2023-05-16 15:50 ` Jonathan Cameron 2023-05-17 9:33 ` Sascha Hauer 2023-05-17 9:33 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 08/21] PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE defines Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 15:54 ` Jonathan Cameron 2023-05-16 15:54 ` Jonathan Cameron 2023-05-17 10:51 ` Sascha Hauer 2023-05-17 10:51 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 09/21] PM / devfreq: rockchip-dfi: Clean up DDR type register defines Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 16:01 ` Jonathan Cameron 2023-05-16 16:01 ` Jonathan Cameron 2023-05-17 11:11 ` Sascha Hauer 2023-05-17 11:11 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 10/21] PM / devfreq: rockchip-dfi: Add RK3568 support Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 16:04 ` Jonathan Cameron 2023-05-16 16:04 ` Jonathan Cameron 2023-05-17 11:38 ` Sascha Hauer 2023-05-17 11:38 ` Sascha Hauer 2023-05-17 14:46 ` Jonathan Cameron 2023-05-17 14:46 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 11/21] PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 16:06 ` Jonathan Cameron 2023-05-16 16:06 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 12/21] PM / devfreq: rockchip-dfi: Handle LPDDR4X Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 16:09 ` Jonathan Cameron 2023-05-16 16:09 ` Jonathan Cameron 2023-05-19 6:14 ` Sascha Hauer 2023-05-19 6:14 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 13/21] PM / devfreq: rockchip-dfi: Pass private data struct to internal functions Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 16:10 ` Jonathan Cameron 2023-05-16 16:10 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 14/21] PM / devfreq: rockchip-dfi: Prepare for multiple users Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 16:16 ` Jonathan Cameron 2023-05-16 16:16 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 15/21] PM / devfreq: rockchip-dfi: Add perf support Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-09 20:04 ` Robin Murphy 2023-05-10 19:56 ` Sascha Hauer 2023-05-16 15:39 ` Sascha Hauer 2023-05-16 15:39 ` Sascha Hauer 2023-05-16 15:27 ` Sascha Hauer 2023-05-16 15:27 ` Sascha Hauer 2023-05-17 10:53 ` Jonathan Cameron 2023-05-17 10:53 ` Jonathan Cameron 2023-05-17 14:26 ` Sascha Hauer 2023-05-17 14:26 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 16/21] PM / devfreq: rockchip-dfi: make register stride SoC specific Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-16 16:18 ` Jonathan Cameron 2023-05-16 16:18 ` Jonathan Cameron 2023-05-19 6:45 ` Sascha Hauer 2023-05-19 6:45 ` Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer [this message] 2023-05-05 11:38 ` [PATCH v4 17/21] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers Sascha Hauer 2023-05-17 10:23 ` Jonathan Cameron 2023-05-17 10:23 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 18/21] PM / devfreq: rockchip-dfi: add support for RK3588 Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-17 10:24 ` Jonathan Cameron 2023-05-17 10:24 ` Jonathan Cameron 2023-05-05 11:38 ` [PATCH v4 19/21] arm64: dts: rockchip: rk3399: Enable DFI Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 20/21] arm64: dts: rockchip: rk356x: Add DFI Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-05 11:38 ` [PATCH v4 21/21] dt-bindings: devfreq: event: convert Rockchip DFI binding to yaml Sascha Hauer 2023-05-05 11:38 ` Sascha Hauer 2023-05-05 16:29 ` Krzysztof Kozlowski 2023-05-05 16:29 ` Krzysztof Kozlowski 2023-05-05 16:31 ` Krzysztof Kozlowski 2023-05-05 16:31 ` Krzysztof Kozlowski 2023-05-09 9:37 ` Sascha Hauer 2023-05-09 9:40 ` Krzysztof Kozlowski 2023-05-09 10:02 ` Sascha Hauer 2023-05-05 16:38 ` [PATCH v4 00/21] Add perf support to the rockchip-dfi driver Vincent Legoll 2023-05-05 16:38 ` Vincent Legoll
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