From: Minda Chen <minda.chen@starfivetech.com> To: "Daire McNamara" <daire.mcnamara@microchip.com>, "Conor Dooley" <conor@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Emil Renner Berthing" <emil.renner.berthing@canonical.com> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-pci@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp Zabel <p.zabel@pengutronix.de>, Mason Huo <mason.huo@starfivetech.com>, Leyfoon Tan <leyfoon.tan@starfivetech.com>, Kevin Xie <kevin.xie@starfivetech.com>, Minda Chen <minda.chen@starfivetech.com> Subject: [PATCH v1 7/9] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Date: Wed, 19 Jul 2023 18:20:55 +0800 [thread overview] Message-ID: <20230719102057.22329-8-minda.chen@starfivetech.com> (raw) In-Reply-To: <20230719102057.22329-1-minda.chen@starfivetech.com> Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA XpressRICH PCIe host controller IP. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> --- .../bindings/pci/starfive,jh7110-pcie.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml new file mode 100644 index 000000000000..467286df557d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PCIe host controller + +maintainers: + - Minda Chen <minda.chen@starfivetech.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: plda,xpressrich-pcie-common.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - $ref: /schemas/gpio/gpio-consumer-common.yaml# + +properties: + compatible: + const: starfive,jh7110-pcie + + clocks: + items: + - description: NOC bus clock + - description: Transport layer clock + - description: AXI MST0 clock + - description: APB clock + + clock-names: + items: + - const: noc + - const: tl + - const: axi_mst0 + - const: apb + + resets: + items: + - description: AXI MST0 reset + - description: AXI SLAVE reset + - description: AXI SLAVE0 reset + - description: PCIE BRIDGE reset + - description: PCIE CORE reset + - description: PCIE APB reset + + reset-names: + items: + - const: mst0 + - const: slv0 + - const: slv + - const: brg + - const: core + - const: apb + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller stg_syscon node. + - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset + for PCIe. + + phys: + description: + Specified PHY is attached to PCIe controller. + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - "#interrupt-cells" + - interrupts + - interrupt-map-mask + - interrupt-map + - clocks + - resets + - starfive,stg-syscon + - msi-controller + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@2b000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x0 0x2b000000 0x0 0x1000000>, + <0x9 0x40000000 0x0 0x10000000>; + reg-names = "host", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; + bus-range = <0x0 0xff>; + interrupt-parent = <&plic>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-parent = <&pcie0>; + msi-controller; + clocks = <&syscrg 86>, + <&stgcrg 10>, + <&stgcrg 8>, + <&stgcrg 9>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg 11>, + <&stgcrg 12>, + <&stgcrg 13>, + <&stgcrg 14>, + <&stgcrg 15>, + <&stgcrg 16>; + reset-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; -- 2.17.1
WARNING: multiple messages have this Message-ID (diff)
From: Minda Chen <minda.chen@starfivetech.com> To: "Daire McNamara" <daire.mcnamara@microchip.com>, "Conor Dooley" <conor@kernel.org>, "Rob Herring" <robh+dt@kernel.org>, "Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>, "Bjorn Helgaas" <bhelgaas@google.com>, "Lorenzo Pieralisi" <lpieralisi@kernel.org>, "Krzysztof Wilczyński" <kw@linux.com>, "Emil Renner Berthing" <emil.renner.berthing@canonical.com> Cc: <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>, <linux-pci@vger.kernel.org>, Paul Walmsley <paul.walmsley@sifive.com>, Palmer Dabbelt <palmer@dabbelt.com>, Albert Ou <aou@eecs.berkeley.edu>, Philipp Zabel <p.zabel@pengutronix.de>, Mason Huo <mason.huo@starfivetech.com>, Leyfoon Tan <leyfoon.tan@starfivetech.com>, Kevin Xie <kevin.xie@starfivetech.com>, Minda Chen <minda.chen@starfivetech.com> Subject: [PATCH v1 7/9] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Date: Wed, 19 Jul 2023 18:20:55 +0800 [thread overview] Message-ID: <20230719102057.22329-8-minda.chen@starfivetech.com> (raw) In-Reply-To: <20230719102057.22329-1-minda.chen@starfivetech.com> Add StarFive JH7110 SoC PCIe controller dt-bindings. JH7110 using PLDA XpressRICH PCIe host controller IP. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> --- .../bindings/pci/starfive,jh7110-pcie.yaml | 138 ++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml new file mode 100644 index 000000000000..467286df557d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml @@ -0,0 +1,138 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/starfive,jh7110-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 PCIe host controller + +maintainers: + - Minda Chen <minda.chen@starfivetech.com> + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + - $ref: plda,xpressrich-pcie-common.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + - $ref: /schemas/gpio/gpio-consumer-common.yaml# + +properties: + compatible: + const: starfive,jh7110-pcie + + clocks: + items: + - description: NOC bus clock + - description: Transport layer clock + - description: AXI MST0 clock + - description: APB clock + + clock-names: + items: + - const: noc + - const: tl + - const: axi_mst0 + - const: apb + + resets: + items: + - description: AXI MST0 reset + - description: AXI SLAVE reset + - description: AXI SLAVE0 reset + - description: PCIE BRIDGE reset + - description: PCIE CORE reset + - description: PCIE APB reset + + reset-names: + items: + - const: mst0 + - const: slv0 + - const: slv + - const: brg + - const: core + - const: apb + + starfive,stg-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to System Register Controller stg_syscon node. + - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for PCIe. + description: + The phandle to System Register Controller syscon node and the offset + of STG_SYSCONSAIF__SYSCFG register for PCIe. Total 4 regsisters offset + for PCIe. + + phys: + description: + Specified PHY is attached to PCIe controller. + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - "#interrupt-cells" + - interrupts + - interrupt-map-mask + - interrupt-map + - clocks + - resets + - starfive,stg-syscon + - msi-controller + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@2b000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x0 0x2b000000 0x0 0x1000000>, + <0x9 0x40000000 0x0 0x10000000>; + reg-names = "host", "cfg"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>; + bus-range = <0x0 0xff>; + interrupt-parent = <&plic>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-parent = <&pcie0>; + msi-controller; + clocks = <&syscrg 86>, + <&stgcrg 10>, + <&stgcrg 8>, + <&stgcrg 9>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg 11>, + <&stgcrg 12>, + <&stgcrg 13>, + <&stgcrg 14>, + <&stgcrg 15>, + <&stgcrg 16>; + reset-gpios = <&gpios 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; -- 2.17.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-07-19 10:21 UTC|newest] Thread overview: 92+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-07-19 10:20 [PATCH v1 0/9] Refactoring Microchip PolarFire PCIe driver Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 10:20 ` [PATCH v1 1/9] dt-bindings: PCI: Add PLDA XpressRICH PCIe host common properties Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 10:52 ` Krzysztof Kozlowski 2023-07-19 10:52 ` Krzysztof Kozlowski 2023-07-20 6:59 ` Minda Chen 2023-07-20 6:59 ` Minda Chen 2023-07-19 22:31 ` Rob Herring 2023-07-19 22:31 ` Rob Herring 2023-07-20 6:47 ` Minda Chen 2023-07-20 6:47 ` Minda Chen 2023-07-19 10:20 ` [PATCH v1 2/9] dt-bindings: PCI: microchip: Remove the PLDA " Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 10:53 ` Krzysztof Kozlowski 2023-07-19 10:53 ` Krzysztof Kozlowski 2023-07-19 10:20 ` [PATCH v1 3/9] PCI: PLDA: Get PLDA common codes from Microchip PolarFire host Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 10:20 ` [PATCH v1 4/9] PCI: microchip: Move PCIe driver to PLDA directory Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-20 11:07 ` Conor Dooley 2023-07-20 11:07 ` Conor Dooley 2023-07-20 12:26 ` Conor Dooley 2023-07-20 12:26 ` Conor Dooley 2023-07-21 1:12 ` Minda Chen 2023-07-21 1:12 ` Minda Chen 2023-07-19 10:20 ` [PATCH v1 5/9] dt-bindings: PLDA: Add PLDA XpressRICH PCIe host controller Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 10:55 ` Krzysztof Kozlowski 2023-07-19 10:55 ` Krzysztof Kozlowski 2023-07-19 22:29 ` Rob Herring 2023-07-19 22:29 ` Rob Herring 2023-07-20 7:02 ` Minda Chen 2023-07-20 7:02 ` Minda Chen 2023-07-19 10:20 ` [PATCH v1 6/9] PCI: PLDA: Add host conroller platform driver Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 10:20 ` Minda Chen [this message] 2023-07-19 10:20 ` [PATCH v1 7/9] dt-bindings: PCI: Add StarFive JH7110 PCIe controller Minda Chen 2023-07-19 10:56 ` Krzysztof Kozlowski 2023-07-19 10:56 ` Krzysztof Kozlowski 2023-07-19 10:20 ` [PATCH v1 8/9] PCI: PLDA: starfive: Add " Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 16:48 ` Bjorn Helgaas 2023-07-19 16:48 ` Bjorn Helgaas 2023-07-20 10:11 ` Kevin Xie 2023-07-20 10:11 ` Kevin Xie 2023-07-20 16:15 ` Bjorn Helgaas 2023-07-20 16:15 ` Bjorn Helgaas 2023-07-24 10:48 ` Kevin Xie 2023-07-24 10:48 ` Kevin Xie 2023-07-25 20:46 ` Bjorn Helgaas 2023-07-25 20:46 ` Bjorn Helgaas 2023-07-27 21:40 ` Bjorn Helgaas 2023-07-27 21:40 ` Bjorn Helgaas 2023-07-31 5:52 ` Kevin Xie 2023-07-31 5:52 ` Kevin Xie 2023-07-31 23:12 ` Bjorn Helgaas 2023-07-31 23:12 ` Bjorn Helgaas 2023-08-01 7:05 ` Pali Rohár 2023-08-01 7:05 ` Pali Rohár 2023-08-01 7:05 ` Kevin Xie 2023-08-01 7:05 ` Kevin Xie 2023-08-01 7:14 ` Pali Rohár 2023-08-01 7:14 ` Pali Rohár 2023-08-02 17:14 ` Bjorn Helgaas 2023-08-02 17:14 ` Bjorn Helgaas 2023-08-02 17:18 ` Bjorn Helgaas 2023-08-02 17:18 ` Bjorn Helgaas 2023-08-03 2:23 ` Kevin Xie 2023-08-03 2:23 ` Kevin Xie 2023-08-03 6:58 ` Pali Rohár 2023-08-03 6:58 ` Pali Rohár 2023-08-03 7:43 ` Kevin Xie 2023-08-03 7:43 ` Kevin Xie 2023-07-20 11:14 ` Conor Dooley 2023-07-20 11:14 ` Conor Dooley 2023-07-21 1:03 ` Minda Chen 2023-07-21 1:03 ` Minda Chen 2023-07-19 10:20 ` [PATCH v1 9/9] riscv: dts: starfive: add PCIe dts configuration for JH7110 Minda Chen 2023-07-19 10:20 ` Minda Chen 2023-07-19 15:26 ` [PATCH v1 0/9] Refactoring Microchip PolarFire PCIe driver Bjorn Helgaas 2023-07-19 15:26 ` Bjorn Helgaas 2023-07-20 2:15 ` Minda Chen 2023-07-20 2:15 ` Minda Chen 2023-07-20 12:12 ` Conor Dooley 2023-07-20 12:12 ` Conor Dooley 2023-07-21 9:34 ` Minda Chen 2023-07-21 9:34 ` Minda Chen 2023-07-21 9:55 ` Minda Chen 2023-07-21 9:55 ` Minda Chen 2023-07-19 16:58 ` Conor Dooley 2023-07-19 16:58 ` Conor Dooley
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