[PATCH v13 00/10] Add multiport support for DWC3 controllers

[Krishna Kurapati <quic_kriskura@quicinc.com>]

Currently the DWC3 driver supports only single port controller which
requires at most two PHYs ie HS and SS PHYs. There are SoCs that has
DWC3 controller with multiple ports that can operate in host mode.
Some of the port supports both SS+HS and other port supports only HS
mode.

This change primarily refactors the Phy logic in core driver to allow
multiport support with Generic Phy's.

Changes have been tested on  QCOM SoC SA8295P which has 4 ports (2
are HS+SS capable and 2 are HS only capable).

Changes in v13:
This series is a subset of patches in v11 as the first 3 patches in v11
have been mereged into usb-next.
Moved dr_mode property from platform specific files to common sc8280xp DT.
Fixed function call wrapping, added comments and replaced #defines with
enum in dwc3-qcom for identifying IRQ index appropriately.
Fixed nitpicks pointed out in v11 for suspend-resume handling.
Added reported-by tag for phy refactoring patch as a compile error was
found by kernel test bot [1].
Removed reviewed-by tag of maintainer for phy refactoring patch as a minor
change of increasing phy-names array size by 2-bytes was done to fix
compilation issue mentioned in [1].

Changes in v12:
Pushed as a subset of acked but no-yet-merged patches of v11 with intent
of making rebase of other patches easy. Active reviewers from community
suggested that it would be better to push the whole series in one go as it
would give good clarity and context for all the patches in the series.
So pushed v13 for the same addressing comments received in v11.

Changes in v11:
Implemented port_count calculation by reading interrupt-names from DT.
Refactored IRQ handling in dwc3-qcom.
Moving of macros to xhci-ext-caps.h made as a separate patch.
Names of interrupts to be displayed on /proc/interrupts set to the ones
present in DT.

Changes in v10:
Refactored phy init/exit/power-on/off functions in dwc3 core
Refactored dwc3-qcom irq registration and handling
Implemented wakeup for multiport irq's
Moved few macros from xhci.h to xhci-ext-caps.h
Fixed nits pointed out in v9
Fixed Co-developed by and SOB tags in patches 5 and 11

Changes in v9:
Added IRQ support for DP/DM/SS MP Irq's of SC8280
Refactored code to read port count by accessing xhci registers

Changes in v8:
Reorganised code in patch-5
Fixed nitpicks in code according to comments received on v7
Fixed indentation in DT patches
Added drive strength for pinctrl nodes in SA8295 DT

Changes in v7:
Added power event irq's for Multiport controller.
Udpated commit text for patch-9 (adding DT changes for enabling first
port of multiport controller on sa8540-ride).
Fixed check-patch warnings for driver code.
Fixed DT binding errors for changes in snps,dwc3.yaml
Reabsed code on top of usb-next

Changes in v6:
Updated comments in code after.
Updated variables names appropriately as per review comments.
Updated commit text in patch-2 and added additional info as per review
comments.
The patch header in v5 doesn't have "PATHCH v5" notation present. Corrected
it in this version.

Changes in v5:
Added DT support for first port of Teritiary USB controller on SA8540-Ride
Added support for reading port info from XHCI Extended Params registers.

Changes in RFC v4:
Added DT support for SA8295p.

Changes in RFC v3:
Incase any PHY init fails, then clear/exit the PHYs that
are already initialized.

Changes in RFC v2:
Changed dwc3_count_phys to return the number of PHY Phandles in the node.
This will be used now in dwc3_extract_num_phys to increment num_usb2_phy 
and num_usb3_phy.

Added new parameter "ss_idx" in dwc3_core_get_phy_ny_node and changed its
structure such that the first half is for HS-PHY and second half is for
SS-PHY.

In dwc3_core_get_phy, for multiport controller, only if SS-PHY phandle is
present, pass proper SS_IDX else pass -1.

Tests done on v13:

1) MP controller enumerting devices on different ports:

/ # lsusb
Bus 001 Device 001: ID 1d6b:0002
Bus 001 Device 003: ID 03f0:0024
Bus 001 Device 002: ID 17ef:6099
Bus 002 Device 001: ID 1d6b:0003

2) Interrupt registration for 3 controllers of sa8295p-adp

/ # cat /proc/interrupts | grep phy
171: 0 0 0 0 0 0 0 0 PDC 127 Level     dp_hs_phy_1
172: 0 0 0 0 0 0 0 0 PDC 126 Level     dm_hs_phy_1
173: 0 0 0 0 0 0 0 0 PDC 129 Level     dp_hs_phy_2
174: 0 0 0 0 0 0 0 0 PDC 128 Level     dm_hs_phy_2
175: 0 0 0 0 0 0 0 0 PDC 131 Level     dp_hs_phy_3
176: 0 0 0 0 0 0 0 0 PDC 130 Level     dm_hs_phy_3
177: 0 0 0 0 0 0 0 0 PDC 133 Level     dp_hs_phy_4
178: 0 0 0 0 0 0 0 0 PDC 132 Level     dm_hs_phy_4
179: 0 0 0 0 0 0 0 0 PDC  16 Level     ss_phy_1
180: 0 0 0 0 0 0 0 0 PDC  17 Level     ss_phy_2
182: 0 0 0 0 0 0 0 0 PDC  14 Level     dp_hs_phy_irq
183: 0 0 0 0 0 0 0 0 PDC  15 Level     dm_hs_phy_irq
184: 0 0 0 0 0 0 0 0 PDC 138 Level     ss_phy_irq
190: 0 0 0 0 0 0 0 0 PDC  12 Level     dp_hs_phy_irq
191: 0 0 0 0 0 0 0 0 PDC  13 Level     dm_hs_phy_irq
192: 0 0 0 0 0 0 0 0 PDC 136 Level     ss_phy_irq

3) Wakeup was tested on all 4 ports of tertiary controller by
a) Connecting peripheral after device is suspended and checking wakeup
b) Removing peripheral after device is suspended and checking wakeup
c) Connecting keyboard and checking if button press wakes up system

4) Testing interrupt registration on single port controller SM8550-MTP

/ # cat /proc/interrupts | grep phy
146:  0 0 0 0 0 0 0 0     GICv3 162 Level     hs_phy_irq
147:  0 0 0 0 0 0 0 0       PDC  17 Level     ss_phy_irq
148:  0 0 0 0 0 0 0 0       PDC  15 Level     dm_hs_phy_irq
149:  0 0 0 0 0 0 0 0       PDC  14 Level     dp_hs_phy_irq

5) ADB enumeration and working on SM8550-MTP has been tested

[1]: https://lore.kernel.org/all/202309200156.CxQ3yaLY-lkp@intel.com/

Links to previous versions:
Link to v12: https://lore.kernel.org/all/20231004165922.25642-1-quic_kriskura@quicinc.com/
Link to v11: https://lore.kernel.org/all/20230828133033.11988-1-quic_kriskura@quicinc.com/
Link to v10: https://lore.kernel.org/all/20230727223307.8096-1-quic_kriskura@quicinc.com/
Link to v9: https://lore.kernel.org/all/20230621043628.21485-1-quic_kriskura@quicinc.com/
Link to v8: https://lore.kernel.org/all/20230514054917.21318-1-quic_kriskura@quicinc.com/
Link to v7: https://lore.kernel.org/all/20230501143445.3851-1-quic_kriskura@quicinc.com/
Link to v6: https://lore.kernel.org/all/20230405125759.4201-1-quic_kriskura@quicinc.com/
Link to v5: https://lore.kernel.org/all/20230310163420.7582-1-quic_kriskura@quicinc.com/
Link to RFC v4: https://lore.kernel.org/all/20230115114146.12628-1-quic_kriskura@quicinc.com/
Link to RFC v3: https://lore.kernel.org/all/1654709787-23686-1-git-send-email-quic_harshq@quicinc.com/#r
Link to RFC v2: https://lore.kernel.org/all/1653560029-6937-1-git-send-email-quic_harshq@quicinc.com/#r

Andrew Halaney (1):
  arm64: dts: qcom: sa8540-ride: Enable first port of tertiary usb
    controller

Harsh Agarwal (1):
  usb: dwc3: core: Refactor PHY logic to support Multiport Controller

Krishna Kurapati (8):
  usb: dwc3: core: Access XHCI address space temporarily to read port
    info
  usb: dwc3: core: Skip setting event buffers for host only controllers
  usb: dwc3: qcom: Add helper function to request threaded IRQ
  usb: dwc3: qcom: Refactor IRQ handling in QCOM Glue driver
  usb: dwc3: qcom: Enable wakeup for applicable ports of multiport
  usb: dwc3: qcom: Add multiport suspend/resume support for wrapper
  arm64: dts: qcom: sc8280xp: Add multiport controller node for SC8280
  arm64: dts: qcom: sa8295p: Enable tertiary controller and its 4 USB
    ports

 arch/arm64/boot/dts/qcom/sa8295p-adp.dts  |  49 ++++
 arch/arm64/boot/dts/qcom/sa8540p-ride.dts |  21 ++
 arch/arm64/boot/dts/qcom/sc8280xp.dtsi    |  84 ++++++
 drivers/usb/dwc3/core.c                   | 324 +++++++++++++++++-----
 drivers/usb/dwc3/core.h                   |  16 +-
 drivers/usb/dwc3/drd.c                    |  15 +-
 drivers/usb/dwc3/dwc3-qcom.c              | 323 ++++++++++++++-------
 7 files changed, 642 insertions(+), 190 deletions(-)

-- 
2.42.0