All of lore.kernel.org
 help / color / mirror / Atom feed
From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
	<Rodrigo.Siqueira@amd.com>, <Aurabindo.Pillai@amd.com>,
	<roman.li@amd.com>, <wayne.lin@amd.com>,
	<agustin.gutierrez@amd.com>, <chiahsuan.chung@amd.com>,
	<hersenxs.wu@amd.com>, <jerry.zuo@amd.com>
Subject: [PATCH 12/43] drm/amd/display: Add missing registers and offset
Date: Tue, 12 Mar 2024 17:20:05 +0800	[thread overview]
Message-ID: <20240312092036.3283319-13-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20240312092036.3283319-1-Wayne.Lin@amd.com>

From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>

[Why & How]
Registers and offset are missing. Add it back

Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../include/asic_reg/dcn/dcn_3_2_1_offset.h   | 37 ++++++++++++++++++-
 .../include/asic_reg/dcn/dcn_3_2_1_sh_mask.h  | 16 ++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
index 3bd8792fd7b3..a04b8c32c564 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_offset.h
@@ -1719,6 +1719,10 @@
 #define regDCHUBBUB_TIMEOUT_INTERRUPT_STATUS_BASE_IDX                                                   2
 #define regFMON_CTRL                                                                                    0x0541
 #define regFMON_CTRL_BASE_IDX                                                                           2
+#define regDCHUBBUB_TEST_DEBUG_INDEX                                                                    0x0542
+#define regDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX                                                           2
+#define regDCHUBBUB_TEST_DEBUG_DATA                                                                     0x0543
+#define regDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX                                                            2
 
 
 // addressBlock: dce_dc_dchubbubl_hubbub_sdpif_dispdec
@@ -3573,6 +3577,10 @@
 #define regCM0_CM_DEALPHA_BASE_IDX                                                                      2
 #define regCM0_CM_COEF_FORMAT                                                                           0x0d8c
 #define regCM0_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM0_CM_TEST_DEBUG_INDEX                                                                      0x0d8d
+#define regCM0_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM0_CM_TEST_DEBUG_DATA                                                                       0x0d8e
+#define regCM0_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
 
 
 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
@@ -3959,6 +3967,10 @@
 #define regCM1_CM_DEALPHA_BASE_IDX                                                                      2
 #define regCM1_CM_COEF_FORMAT                                                                           0x0ef7
 #define regCM1_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM1_CM_TEST_DEBUG_INDEX                                                                      0x0ef8
+#define regCM1_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM1_CM_TEST_DEBUG_DATA                                                                       0x0ef9
+#define regCM1_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
 
 
 // addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec
@@ -4345,6 +4357,10 @@
 #define regCM2_CM_DEALPHA_BASE_IDX                                                                      2
 #define regCM2_CM_COEF_FORMAT                                                                           0x1062
 #define regCM2_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM2_CM_TEST_DEBUG_INDEX                                                                      0x1063
+#define regCM2_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM2_CM_TEST_DEBUG_DATA                                                                       0x1064
+#define regCM2_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
 
 
 // addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec
@@ -4731,6 +4747,10 @@
 #define regCM3_CM_DEALPHA_BASE_IDX                                                                      2
 #define regCM3_CM_COEF_FORMAT                                                                           0x11cd
 #define regCM3_CM_COEF_FORMAT_BASE_IDX                                                                  2
+#define regCM3_CM_TEST_DEBUG_INDEX                                                                      0x11ce
+#define regCM3_CM_TEST_DEBUG_INDEX_BASE_IDX                                                             2
+#define regCM3_CM_TEST_DEBUG_DATA                                                                       0x11cf
+#define regCM3_CM_TEST_DEBUG_DATA_BASE_IDX                                                              2
 
 
 // addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec
@@ -11789,6 +11809,10 @@
 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3035
 #define regDSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x303a
+#define regDSCC0_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+#define regDSCC0_DSCC_TEST_DEBUG_DATA0                                                                  0x303b
+#define regDSCC0_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2
 
 
 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
@@ -11897,6 +11921,10 @@
 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3091
 #define regDSCC1_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x3096
+#define regDSCC1_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+#define regDSCC1_DSCC_TEST_DEBUG_DATA0                                                                  0x3097
+#define regDSCC1_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2
 
 
 // addressBlock: dce_dc_dsc1_dispdec_dsccif_dispdec
@@ -12005,7 +12033,10 @@
 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x30ed
 #define regDSCC2_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
-
+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x30f2
+#define regDSCC2_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+#define regDSCC2_DSCC_TEST_DEBUG_DATA0                                                                  0x30f3
+#define regDSCC2_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2
 
 // addressBlock: dce_dc_dsc2_dispdec_dsccif_dispdec
 // base address: 0x2e0
@@ -12113,6 +12144,10 @@
 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER2_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL                                           0x3149
 #define regDSCC3_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_BASE_IDX                                  2
+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE                                                             0x314e
+#define regDSCC3_DSCC_TEST_DEBUG_BUS_ROTATE_BASE_IDX                                                    2
+#define regDSCC3_DSCC_TEST_DEBUG_DATA0                                                                  0x314f
+#define regDSCC3_DSCC_TEST_DEBUG_DATA0_BASE_IDX                                                         2
 
 
 // addressBlock: dce_dc_dsc3_dispdec_dsccif_dispdec
diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
index e82dffc2b9b0..ce773fca621f 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_2_1_sh_mask.h
@@ -11547,6 +11547,11 @@
 #define CM0_CM_COEF_FORMAT__CM_BIAS_FORMAT_MASK                                                               0x00000001L
 #define CM0_CM_COEF_FORMAT__CM_POST_CSC_COEF_FORMAT_MASK                                                      0x00000010L
 #define CM0_CM_COEF_FORMAT__CM_GAMUT_REMAP_COEF_FORMAT_MASK                                                   0x00000100L
+//CM0_CM_TEST_DEBUG_INDEX
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX__SHIFT                                                   0x0
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN__SHIFT                                                0x8
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_INDEX_MASK                                                     0x000000FFL
+#define CM0_CM_TEST_DEBUG_INDEX__CM_TEST_DEBUG_WRITE_EN_MASK                                                  0x00000100L
 
 
 // addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec
@@ -42315,6 +42320,15 @@
 //DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL
 #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__SHIFT  0x0
 #define DSCC0_DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL__DSCC_RATE_CONTROL_BUFFER3_MAX_FULLNESS_LEVEL_MASK  0x0003FFFFL
+//DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE__SHIFT                                  0x0
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE__SHIFT                                  0x8
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE__SHIFT                                  0x10
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE__SHIFT                                  0x18
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS0_ROTATE_MASK                                    0x0000001FL
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS1_ROTATE_MASK                                    0x00001F00L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS2_ROTATE_MASK                                    0x001F0000L
+#define DSCC0_DSCC_TEST_DEBUG_BUS_ROTATE__DSCC_TEST_DEBUG_BUS3_ROTATE_MASK                                    0x1F000000L
 
 
 // addressBlock: dce_dc_dsc0_dispdec_dsccif_dispdec
@@ -42348,7 +42362,9 @@
 #define DSC_TOP0_DSC_TOP_CONTROL__DSC_DSCCLK_R_GATE_DIS_MASK                                                  0x00000100L
 //DSC_TOP0_DSC_DEBUG_CONTROL
 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN__SHIFT                                                         0x0
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL__SHIFT                                             0x4
 #define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_DBG_EN_MASK                                                           0x00000001L
+#define DSC_TOP0_DSC_DEBUG_CONTROL__DSC_TEST_CLOCK_MUX_SEL_MASK                                               0x00000070L
 
 
 // addressBlock: dce_dc_dsc1_dispdec_dscc_dispdec
-- 
2.37.3


  parent reply	other threads:[~2024-03-12  9:22 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-12  9:19 [PATCH 00/43] DC Patches March 18, 2024 Wayne Lin
2024-03-12  9:19 ` [PATCH 01/43] drm/amd/display: Remove code duplication Wayne Lin
2024-03-12  9:19 ` [PATCH 02/43] drm/amd/display: Remove wrong signal from vrr calculation Wayne Lin
2024-03-12  9:19 ` [PATCH 03/43] drm/amd/display: Enable 2to1 ODM policy for DCN35 Wayne Lin
2024-03-12 10:20   ` Christian König
2024-03-13  6:35     ` Lin, Wayne
2024-03-12  9:19 ` [PATCH 04/43] drm/amd/display: Delete duplicated function prototypes Wayne Lin
2024-03-12  9:19 ` [PATCH 05/43] drm/amd/display: Correct indentations and spaces Wayne Lin
2024-03-12  9:19 ` [PATCH 06/43] drm/amd/display: Add the MALL size in the fallback function Wayne Lin
2024-03-12  9:20 ` [PATCH 07/43] drm/amd/display: Move define to the proper header Wayne Lin
2024-03-12  9:20 ` [PATCH 08/43] drm/amd/display: Enable fast update for DCN314 Wayne Lin
2024-03-12  9:20 ` [PATCH 09/43] drm/amd/display: Remove legacy code Wayne Lin
2024-03-12  9:20 ` [PATCH 10/43] drm/amd/display: correct hostvm flag Wayne Lin
2024-03-12  9:20 ` [PATCH 11/43] drm/amd/display: Comments adjustments Wayne Lin
2024-03-12  9:20 ` Wayne Lin [this message]
2024-03-12  9:20 ` [PATCH 13/43] drm/amd/display: Fix noise issue on HDMI AV mute Wayne Lin
2024-03-12  9:20 ` [PATCH 14/43] drm/amd/display: skip forcing odm in minimal transition Wayne Lin
2024-03-12  9:20 ` [PATCH 15/43] drm/amd/display: revert Exit idle optimizations before HDCP execution Wayne Lin
2024-03-12  9:20 ` [PATCH 16/43] drm/amd/display: Add debug option for idle reg checks Wayne Lin
2024-03-12  9:20 ` [PATCH 17/43] drm/amd/display: Revert Add left edge pixel + ODM pipe split Wayne Lin
2024-03-12  9:20 ` [PATCH 18/43] drm/amd/display: To adjust dprefclk by down spread percentage Wayne Lin
2024-03-12  9:20 ` [PATCH 19/43] drm/amd/display: Enabling urgent latency adjustment for DCN35 Wayne Lin
2024-03-12  9:20 ` [PATCH 20/43] drm/amd/display: Revert "Set the power_down_on_boot function pointer to null" Wayne Lin
2024-03-12  9:20 ` [PATCH 21/43] drm/amd/display: add stream clock source to DP DTO params Wayne Lin
2024-03-12  9:20 ` [PATCH 22/43] drm/amd/display: Program pixclk according to dcn revision Wayne Lin
2024-03-12  9:20 ` [PATCH 23/43] drm/amd/display: clear mpc_tree in init_pipes Wayne Lin
2024-03-12  9:20 ` [PATCH 24/43] drm/amd/display: [FW Promotion] Release 0.0.208.0 Wayne Lin
2024-03-12  9:20 ` [PATCH 25/43] drm/amd/display: 3.2.276 Wayne Lin
2024-03-12  9:20 ` [PATCH 26/43] drm/amd/display: Workaround register access in idle race with cursor Wayne Lin
2024-03-12  9:20 ` [PATCH 27/43] drm/amd/display: Revert Remove pixle rate limit for subvp Wayne Lin
2024-03-12  9:20 ` [PATCH 28/43] drm/amd/display: fix debug key not working on dml2 Wayne Lin
2024-03-12  9:20 ` [PATCH 29/43] drm/amd/display: Power on VPG memory unconditionally if off Wayne Lin
2024-03-12  9:20 ` [PATCH 30/43] drm/amd/display: Added debug prints for zstate_support and StutterPeriod Wayne Lin
2024-03-12  9:20 ` [PATCH 31/43] drm/amd/display: change aux_init to apu version Wayne Lin
2024-03-12  9:20 ` [PATCH 32/43] drm/amd/display: Increase Z8 watermark times Wayne Lin
2024-03-12  9:20 ` [PATCH 33/43] drm/amd/display: Prevent crash on bring-up Wayne Lin
2024-03-13 14:40   ` Pillai, Aurabindo
2024-03-12  9:20 ` [PATCH 34/43] drm/amd/display: increase bb clock for DCN351 Wayne Lin
2024-03-12  9:20 ` [PATCH 35/43] drm/amd/display: Detect and disallow idle reallow during reentrancy Wayne Lin
2024-03-12  9:20 ` [PATCH 36/43] drm/amd/display: Add optional optimization for IPS handshake Wayne Lin
2024-03-12  9:20 ` [PATCH 37/43] drm/amd/display: Enable optimized handshake for DCN35 Wayne Lin
2024-03-12  9:20 ` [PATCH 38/43] drm/amd/display: Remove unnecessary hard coded DPM states Wayne Lin
2024-03-12  9:20 ` [PATCH 39/43] drm/amd/display: Enable new interface design for alternate scrambling Wayne Lin
2024-03-12  9:20 ` [PATCH 40/43] drm/amd/display: Enable reallow for idle on DCN35 Wayne Lin
2024-03-12  9:20 ` [PATCH 41/43] drm/amd/display: fix a bug to dereference already freed old current state memory Wayne Lin
2024-03-12  9:20 ` [PATCH 42/43] drm/amd/display: Add TB_BORROWED_MAX definition Wayne Lin
2024-03-12  9:20 ` [PATCH 43/43] drm/amd/display: 3.2.277 Wayne Lin
2024-03-18 13:54 ` [PATCH 00/43] DC Patches March 18, 2024 Wheeler, Daniel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240312092036.3283319-13-Wayne.Lin@amd.com \
    --to=wayne.lin@amd.com \
    --cc=Aurabindo.Pillai@amd.com \
    --cc=Harry.Wentland@amd.com \
    --cc=Rodrigo.Siqueira@amd.com \
    --cc=Sunpeng.Li@amd.com \
    --cc=agustin.gutierrez@amd.com \
    --cc=amd-gfx@lists.freedesktop.org \
    --cc=chiahsuan.chung@amd.com \
    --cc=hersenxs.wu@amd.com \
    --cc=jerry.zuo@amd.com \
    --cc=roman.li@amd.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.