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From: Wayne Lin <Wayne.Lin@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: <Harry.Wentland@amd.com>, <Sunpeng.Li@amd.com>,
	<Rodrigo.Siqueira@amd.com>, <Aurabindo.Pillai@amd.com>,
	<roman.li@amd.com>, <wayne.lin@amd.com>,
	<agustin.gutierrez@amd.com>, <chiahsuan.chung@amd.com>,
	<hersenxs.wu@amd.com>, <jerry.zuo@amd.com>,
	Zhongwei <zhongwei.zhang@amd.com>,
	Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Subject: [PATCH 18/43] drm/amd/display: To adjust dprefclk by down spread percentage
Date: Tue, 12 Mar 2024 17:20:11 +0800	[thread overview]
Message-ID: <20240312092036.3283319-19-Wayne.Lin@amd.com> (raw)
In-Reply-To: <20240312092036.3283319-1-Wayne.Lin@amd.com>

From: Zhongwei <zhongwei.zhang@amd.com>

[Why]
OLED panels show no display for large vtotal timings.

[How]
Check if spread spectrum is enabled and read from lut for spread spectrum
percentage. Adjust dprefclk as required.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Zhongwei <zhongwei.zhang@amd.com>
---
 .../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c  | 50 +++++++++++++++++++
 1 file changed, 50 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index c6030bed95a0..96c3562276f4 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -73,6 +73,12 @@
 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_SEL_MASK		0x00000007L
 #define CLK1_CLK2_BYPASS_CNTL__CLK2_BYPASS_DIV_MASK		0x000F0000L
 
+#define regCLK5_0_CLK5_spll_field_8				0x464b
+#define regCLK5_0_CLK5_spll_field_8_BASE_IDX	0
+
+#define CLK5_0_CLK5_spll_field_8__spll_ssc_en__SHIFT	0xd
+#define CLK5_0_CLK5_spll_field_8__spll_ssc_en_MASK		0x00002000L
+
 #define REG(reg_name) \
 	(ctx->clk_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
 
@@ -410,6 +416,17 @@ static void dcn35_dump_clk_registers(struct clk_state_registers_and_bypass *regs
 {
 }
 
+static bool dcn35_is_spll_ssc_enabled(struct clk_mgr *clk_mgr_base)
+{
+	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
+	struct dc_context *ctx = clk_mgr->base.ctx;
+	uint32_t ssc_enable;
+
+	REG_GET(CLK5_0_CLK5_spll_field_8, spll_ssc_en, &ssc_enable);
+
+	return ssc_enable == 1;
+}
+
 static void init_clk_states(struct clk_mgr *clk_mgr)
 {
 	uint32_t ref_dtbclk = clk_mgr->clks.ref_dtbclk_khz;
@@ -424,7 +441,16 @@ static void init_clk_states(struct clk_mgr *clk_mgr)
 
 void dcn35_init_clocks(struct clk_mgr *clk_mgr)
 {
+	struct clk_mgr_internal *clk_mgr_int = TO_CLK_MGR_INTERNAL(clk_mgr);
 	init_clk_states(clk_mgr);
+
+	// to adjust dp_dto reference clock if ssc is enable otherwise to apply dprefclk
+	if (dcn35_is_spll_ssc_enabled(clk_mgr))
+		clk_mgr->dp_dto_source_clock_in_khz =
+			dce_adjust_dp_ref_freq_for_ss(clk_mgr_int, clk_mgr->dprefclk_khz);
+	else
+		clk_mgr->dp_dto_source_clock_in_khz = clk_mgr->dprefclk_khz;
+
 }
 static struct clk_bw_params dcn35_bw_params = {
 	.vram_type = Ddr4MemType,
@@ -513,6 +539,28 @@ static DpmClocks_t_dcn35 dummy_clocks;
 
 static struct dcn35_watermarks dummy_wms = { 0 };
 
+static struct dcn35_ss_info_table ss_info_table = {
+	.ss_divider = 1000,
+	.ss_percentage = {0, 0, 375, 375, 375}
+};
+
+static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
+{
+	struct dc_context *ctx = clk_mgr->base.ctx;
+	uint32_t clock_source;
+
+	REG_GET(CLK1_CLK2_BYPASS_CNTL, CLK2_BYPASS_SEL, &clock_source);
+
+	if (dcn35_is_spll_ssc_enabled(&clk_mgr->base) && (clock_source < ARRAY_SIZE(ss_info_table.ss_percentage))) {
+		clk_mgr->dprefclk_ss_percentage = ss_info_table.ss_percentage[clock_source];
+
+		if (clk_mgr->dprefclk_ss_percentage != 0) {
+			clk_mgr->ss_on_dprefclk = true;
+			clk_mgr->dprefclk_ss_divider = ss_info_table.ss_divider;
+		}
+	}
+}
+
 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
 {
 	int i, num_valid_sets;
@@ -1057,6 +1105,8 @@ void dcn35_clk_mgr_construct(
 	dce_clock_read_ss_info(&clk_mgr->base);
 	/*when clk src is from FCH, it could have ss, same clock src as DPREF clk*/
 
+	dcn35_read_ss_info_from_lut(&clk_mgr->base);
+
 	clk_mgr->base.base.bw_params = &dcn35_bw_params;
 
 	if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
-- 
2.37.3


  parent reply	other threads:[~2024-03-12  9:22 UTC|newest]

Thread overview: 48+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-03-12  9:19 [PATCH 00/43] DC Patches March 18, 2024 Wayne Lin
2024-03-12  9:19 ` [PATCH 01/43] drm/amd/display: Remove code duplication Wayne Lin
2024-03-12  9:19 ` [PATCH 02/43] drm/amd/display: Remove wrong signal from vrr calculation Wayne Lin
2024-03-12  9:19 ` [PATCH 03/43] drm/amd/display: Enable 2to1 ODM policy for DCN35 Wayne Lin
2024-03-12 10:20   ` Christian König
2024-03-13  6:35     ` Lin, Wayne
2024-03-12  9:19 ` [PATCH 04/43] drm/amd/display: Delete duplicated function prototypes Wayne Lin
2024-03-12  9:19 ` [PATCH 05/43] drm/amd/display: Correct indentations and spaces Wayne Lin
2024-03-12  9:19 ` [PATCH 06/43] drm/amd/display: Add the MALL size in the fallback function Wayne Lin
2024-03-12  9:20 ` [PATCH 07/43] drm/amd/display: Move define to the proper header Wayne Lin
2024-03-12  9:20 ` [PATCH 08/43] drm/amd/display: Enable fast update for DCN314 Wayne Lin
2024-03-12  9:20 ` [PATCH 09/43] drm/amd/display: Remove legacy code Wayne Lin
2024-03-12  9:20 ` [PATCH 10/43] drm/amd/display: correct hostvm flag Wayne Lin
2024-03-12  9:20 ` [PATCH 11/43] drm/amd/display: Comments adjustments Wayne Lin
2024-03-12  9:20 ` [PATCH 12/43] drm/amd/display: Add missing registers and offset Wayne Lin
2024-03-12  9:20 ` [PATCH 13/43] drm/amd/display: Fix noise issue on HDMI AV mute Wayne Lin
2024-03-12  9:20 ` [PATCH 14/43] drm/amd/display: skip forcing odm in minimal transition Wayne Lin
2024-03-12  9:20 ` [PATCH 15/43] drm/amd/display: revert Exit idle optimizations before HDCP execution Wayne Lin
2024-03-12  9:20 ` [PATCH 16/43] drm/amd/display: Add debug option for idle reg checks Wayne Lin
2024-03-12  9:20 ` [PATCH 17/43] drm/amd/display: Revert Add left edge pixel + ODM pipe split Wayne Lin
2024-03-12  9:20 ` Wayne Lin [this message]
2024-03-12  9:20 ` [PATCH 19/43] drm/amd/display: Enabling urgent latency adjustment for DCN35 Wayne Lin
2024-03-12  9:20 ` [PATCH 20/43] drm/amd/display: Revert "Set the power_down_on_boot function pointer to null" Wayne Lin
2024-03-12  9:20 ` [PATCH 21/43] drm/amd/display: add stream clock source to DP DTO params Wayne Lin
2024-03-12  9:20 ` [PATCH 22/43] drm/amd/display: Program pixclk according to dcn revision Wayne Lin
2024-03-12  9:20 ` [PATCH 23/43] drm/amd/display: clear mpc_tree in init_pipes Wayne Lin
2024-03-12  9:20 ` [PATCH 24/43] drm/amd/display: [FW Promotion] Release 0.0.208.0 Wayne Lin
2024-03-12  9:20 ` [PATCH 25/43] drm/amd/display: 3.2.276 Wayne Lin
2024-03-12  9:20 ` [PATCH 26/43] drm/amd/display: Workaround register access in idle race with cursor Wayne Lin
2024-03-12  9:20 ` [PATCH 27/43] drm/amd/display: Revert Remove pixle rate limit for subvp Wayne Lin
2024-03-12  9:20 ` [PATCH 28/43] drm/amd/display: fix debug key not working on dml2 Wayne Lin
2024-03-12  9:20 ` [PATCH 29/43] drm/amd/display: Power on VPG memory unconditionally if off Wayne Lin
2024-03-12  9:20 ` [PATCH 30/43] drm/amd/display: Added debug prints for zstate_support and StutterPeriod Wayne Lin
2024-03-12  9:20 ` [PATCH 31/43] drm/amd/display: change aux_init to apu version Wayne Lin
2024-03-12  9:20 ` [PATCH 32/43] drm/amd/display: Increase Z8 watermark times Wayne Lin
2024-03-12  9:20 ` [PATCH 33/43] drm/amd/display: Prevent crash on bring-up Wayne Lin
2024-03-13 14:40   ` Pillai, Aurabindo
2024-03-12  9:20 ` [PATCH 34/43] drm/amd/display: increase bb clock for DCN351 Wayne Lin
2024-03-12  9:20 ` [PATCH 35/43] drm/amd/display: Detect and disallow idle reallow during reentrancy Wayne Lin
2024-03-12  9:20 ` [PATCH 36/43] drm/amd/display: Add optional optimization for IPS handshake Wayne Lin
2024-03-12  9:20 ` [PATCH 37/43] drm/amd/display: Enable optimized handshake for DCN35 Wayne Lin
2024-03-12  9:20 ` [PATCH 38/43] drm/amd/display: Remove unnecessary hard coded DPM states Wayne Lin
2024-03-12  9:20 ` [PATCH 39/43] drm/amd/display: Enable new interface design for alternate scrambling Wayne Lin
2024-03-12  9:20 ` [PATCH 40/43] drm/amd/display: Enable reallow for idle on DCN35 Wayne Lin
2024-03-12  9:20 ` [PATCH 41/43] drm/amd/display: fix a bug to dereference already freed old current state memory Wayne Lin
2024-03-12  9:20 ` [PATCH 42/43] drm/amd/display: Add TB_BORROWED_MAX definition Wayne Lin
2024-03-12  9:20 ` [PATCH 43/43] drm/amd/display: 3.2.277 Wayne Lin
2024-03-18 13:54 ` [PATCH 00/43] DC Patches March 18, 2024 Wheeler, Daniel

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