* [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
@ 2021-07-06 3:50 Kito Cheng
2021-07-06 4:42 ` Richard Henderson
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Kito Cheng @ 2021-07-06 3:50 UTC (permalink / raw)
To: alistair.francis, palmer, frank.chang, qemu-devel, qemu-riscv,
richard.henderson
Cc: Kito Cheng
Set I, M, A, F, D and C bit for hwcap if misa is set.
V3 Changes:
- Simplify logic of getting hwcap.
V2 Changes:
- Only set imafdc bits, sync with upstream linux kernel.
Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
---
linux-user/elfload.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 598ab8aa13..42ef2a1148 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
#define ELF_CLASS ELFCLASS64
#endif
+#define ELF_HWCAP get_elf_hwcap()
+
+static uint32_t get_elf_hwcap(void)
+{
+#define MISA_BIT(EXT) (1 << (EXT - 'A'))
+ RISCVCPU *cpu = RISCV_CPU(thread_cpu);
+ uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
+ | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
+
+ return cpu->env.misa & mask;
+#undef MISA_BIT
+}
+
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
--
2.31.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
2021-07-06 3:50 [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Kito Cheng
@ 2021-07-06 4:42 ` Richard Henderson
2021-07-06 5:51 ` Bin Meng
2021-07-07 19:15 ` Laurent Vivier
2 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2021-07-06 4:42 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv
On 7/5/21 8:50 PM, Kito Cheng wrote:
> Set I, M, A, F, D and C bit for hwcap if misa is set.
>
> V3 Changes:
> - Simplify logic of getting hwcap.
>
> V2 Changes:
> - Only set imafdc bits, sync with upstream linux kernel.
>
> Signed-off-by: Kito Cheng<kito.cheng@sifive.com>
> ---
> linux-user/elfload.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
2021-07-06 3:50 [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Kito Cheng
@ 2021-07-06 5:51 ` Bin Meng
2021-07-06 5:51 ` Bin Meng
2021-07-07 19:15 ` Laurent Vivier
2 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2021-07-06 5:51 UTC (permalink / raw)
To: Kito Cheng
Cc: open list:RISC-V, frank.chang, Richard Henderson,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis
On Tue, Jul 6, 2021 at 11:50 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> Set I, M, A, F, D and C bit for hwcap if misa is set.
>
> V3 Changes:
> - Simplify logic of getting hwcap.
>
> V2 Changes:
> - Only set imafdc bits, sync with upstream linux kernel.
These changelogs should not be in the commit message, but should be
put below ---
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> linux-user/elfload.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 598ab8aa13..42ef2a1148 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
> #define ELF_CLASS ELFCLASS64
> #endif
>
> +#define ELF_HWCAP get_elf_hwcap()
> +
> +static uint32_t get_elf_hwcap(void)
> +{
> +#define MISA_BIT(EXT) (1 << (EXT - 'A'))
> + RISCVCPU *cpu = RISCV_CPU(thread_cpu);
> + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
> +
> + return cpu->env.misa & mask;
> +#undef MISA_BIT
> +}
> +
> static inline void init_thread(struct target_pt_regs *regs,
> struct image_info *infop)
> {
Regards,
Bin
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
@ 2021-07-06 5:51 ` Bin Meng
0 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2021-07-06 5:51 UTC (permalink / raw)
To: Kito Cheng
Cc: Alistair Francis, Palmer Dabbelt, frank.chang,
qemu-devel@nongnu.org Developers, open list:RISC-V,
Richard Henderson
On Tue, Jul 6, 2021 at 11:50 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> Set I, M, A, F, D and C bit for hwcap if misa is set.
>
> V3 Changes:
> - Simplify logic of getting hwcap.
>
> V2 Changes:
> - Only set imafdc bits, sync with upstream linux kernel.
These changelogs should not be in the commit message, but should be
put below ---
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> linux-user/elfload.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 598ab8aa13..42ef2a1148 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
> #define ELF_CLASS ELFCLASS64
> #endif
>
> +#define ELF_HWCAP get_elf_hwcap()
> +
> +static uint32_t get_elf_hwcap(void)
> +{
> +#define MISA_BIT(EXT) (1 << (EXT - 'A'))
> + RISCVCPU *cpu = RISCV_CPU(thread_cpu);
> + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
> +
> + return cpu->env.misa & mask;
> +#undef MISA_BIT
> +}
> +
> static inline void init_thread(struct target_pt_regs *regs,
> struct image_info *infop)
> {
Regards,
Bin
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V
2021-07-06 3:50 [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Kito Cheng
2021-07-06 4:42 ` Richard Henderson
2021-07-06 5:51 ` Bin Meng
@ 2021-07-07 19:15 ` Laurent Vivier
2 siblings, 0 replies; 5+ messages in thread
From: Laurent Vivier @ 2021-07-07 19:15 UTC (permalink / raw)
To: Kito Cheng, alistair.francis, palmer, frank.chang, qemu-devel,
qemu-riscv, richard.henderson
Le 06/07/2021 à 05:50, Kito Cheng a écrit :
> Set I, M, A, F, D and C bit for hwcap if misa is set.
>
> V3 Changes:
> - Simplify logic of getting hwcap.
>
> V2 Changes:
> - Only set imafdc bits, sync with upstream linux kernel.
>
> Signed-off-by: Kito Cheng <kito.cheng@sifive.com>
> ---
> linux-user/elfload.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 598ab8aa13..42ef2a1148 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -1434,6 +1434,19 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs,
> #define ELF_CLASS ELFCLASS64
> #endif
>
> +#define ELF_HWCAP get_elf_hwcap()
> +
> +static uint32_t get_elf_hwcap(void)
> +{
> +#define MISA_BIT(EXT) (1 << (EXT - 'A'))
> + RISCVCPU *cpu = RISCV_CPU(thread_cpu);
> + uint32_t mask = MISA_BIT('I') | MISA_BIT('M') | MISA_BIT('A')
> + | MISA_BIT('F') | MISA_BIT('D') | MISA_BIT('C');
> +
> + return cpu->env.misa & mask;
> +#undef MISA_BIT
> +}
> +
> static inline void init_thread(struct target_pt_regs *regs,
> struct image_info *infop)
> {
>
Applied to my linux-user-for-6.1 branch.
(I have removed the history from the commit message)
Thanks,
Laurent
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2021-07-07 19:16 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-07-06 3:50 [PATCH v3] linux-user/elfload: Implement ELF_HWCAP for RISC-V Kito Cheng
2021-07-06 4:42 ` Richard Henderson
2021-07-06 5:51 ` Bin Meng
2021-07-06 5:51 ` Bin Meng
2021-07-07 19:15 ` Laurent Vivier
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.