From: Alistair Francis <Alistair.Francis@wdc.com> To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, "alistair23@gmail.com" <alistair23@gmail.com> Subject: [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Date: Thu, 15 Nov 2018 22:35:14 +0000 [thread overview] Message-ID: <2d6d038f9949b5b39feb48e322be881f31a7f4e1.1542321076.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1542321076.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> --- tcg/riscv/tcg-target.inc.c | 81 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index e585740870..5319f7ade5 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -258,6 +258,87 @@ typedef enum { OPC_FENCE_RW_W = 0x0310000f, } RISCVInsn; +/* + * RISC-V immediate and instruction encoders (excludes 16-bit RVC) + */ + +/* Type-R */ + +static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; +} + +/* Type-I */ + +static int32_t encode_imm12(uint32_t imm) +{ + return (imm & 0xfff) << 20; +} + +static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); +} + +/* Type-S */ + +static int32_t encode_simm12(uint32_t imm) +{ + return ((imm << 20) >> 25) << 25 | ((imm << 27) >> 27) << 7; +} + +static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); +} + +/* Type-SB */ + +static int32_t encode_sbimm12(uint32_t imm) +{ + return ((imm << 19) >> 31) << 31 | ((imm << 21) >> 26) << 25 | + ((imm << 27) >> 28) << 8 | ((imm << 20) >> 31) << 7; +} + +static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); +} + +/* Type-U */ + +static int32_t encode_uimm20(uint32_t imm) +{ + return (imm >> 12) << 12; +} + +static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); +} + +/* Type-UJ */ + +static int32_t encode_ujimm12(uint32_t imm) +{ + return ((imm << 11) >> 31) << 31 | ((imm << 21) >> 22) << 21 | + ((imm << 20) >> 31) << 20 | ((imm << 12) >> 24) << 12; +} + +static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_ujimm12(imm); +} + +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) +{ + /* Note: jump target patching should be atomic */ + reloc_call((tcg_insn_unit *)jmp_addr, (tcg_insn_unit*)addr); + flush_icache_range(jmp_addr, jmp_addr + 8); +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; -- 2.19.1
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <Alistair.Francis@wdc.com> To: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org> Cc: Alistair Francis <Alistair.Francis@wdc.com>, "alistair23@gmail.com" <alistair23@gmail.com> Subject: [Qemu-riscv] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Date: Thu, 15 Nov 2018 22:35:14 +0000 [thread overview] Message-ID: <2d6d038f9949b5b39feb48e322be881f31a7f4e1.1542321076.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1542321076.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> --- tcg/riscv/tcg-target.inc.c | 81 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c index e585740870..5319f7ade5 100644 --- a/tcg/riscv/tcg-target.inc.c +++ b/tcg/riscv/tcg-target.inc.c @@ -258,6 +258,87 @@ typedef enum { OPC_FENCE_RW_W = 0x0310000f, } RISCVInsn; +/* + * RISC-V immediate and instruction encoders (excludes 16-bit RVC) + */ + +/* Type-R */ + +static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; +} + +/* Type-I */ + +static int32_t encode_imm12(uint32_t imm) +{ + return (imm & 0xfff) << 20; +} + +static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); +} + +/* Type-S */ + +static int32_t encode_simm12(uint32_t imm) +{ + return ((imm << 20) >> 25) << 25 | ((imm << 27) >> 27) << 7; +} + +static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); +} + +/* Type-SB */ + +static int32_t encode_sbimm12(uint32_t imm) +{ + return ((imm << 19) >> 31) << 31 | ((imm << 21) >> 26) << 25 | + ((imm << 27) >> 28) << 8 | ((imm << 20) >> 31) << 7; +} + +static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); +} + +/* Type-U */ + +static int32_t encode_uimm20(uint32_t imm) +{ + return (imm >> 12) << 12; +} + +static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); +} + +/* Type-UJ */ + +static int32_t encode_ujimm12(uint32_t imm) +{ + return ((imm << 11) >> 31) << 31 | ((imm << 21) >> 22) << 21 | + ((imm << 20) >> 31) << 20 | ((imm << 12) >> 24) << 12; +} + +static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_ujimm12(imm); +} + +void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, + uintptr_t addr) +{ + /* Note: jump target patching should be atomic */ + reloc_call((tcg_insn_unit *)jmp_addr, (tcg_insn_unit*)addr); + flush_icache_range(jmp_addr, jmp_addr + 8); +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4]; -- 2.19.1
next prev parent reply other threads:[~2018-11-15 22:35 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-15 22:33 [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support Alistair Francis 2018-11-15 22:33 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson 2018-11-16 7:47 ` Richard Henderson 2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:47 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson 2018-11-16 17:20 ` Richard Henderson 2018-11-16 17:20 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:58 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:58 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:59 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:59 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:13 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:13 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` Alistair Francis [this message] 2018-11-15 22:35 ` [Qemu-riscv] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Alistair Francis 2018-11-16 8:26 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:26 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:27 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:27 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:33 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:33 ` [Qemu-riscv] " Richard Henderson 2018-11-21 1:15 ` Alistair Francis 2018-11-21 1:15 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:25 ` Richard Henderson 2018-11-21 7:25 ` [Qemu-riscv] " Richard Henderson 2018-11-21 15:53 ` Palmer Dabbelt 2018-11-21 15:53 ` [Qemu-riscv] " Palmer Dabbelt 2018-11-21 17:01 ` Richard Henderson 2018-11-21 17:01 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:55 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:55 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:56 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:56 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:59 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:59 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 9:14 ` [Qemu-devel] " Richard Henderson 2018-11-16 9:14 ` [Qemu-riscv] " Richard Henderson 2018-11-20 23:49 ` Alistair Francis 2018-11-20 23:49 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:40 ` Richard Henderson 2018-11-21 7:40 ` [Qemu-riscv] " Richard Henderson 2018-11-26 22:58 ` Alistair Francis 2018-11-26 22:58 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 9:24 ` [Qemu-devel] " Richard Henderson 2018-11-16 9:24 ` [Qemu-riscv] " Richard Henderson 2018-11-21 0:18 ` Alistair Francis 2018-11-21 0:18 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:43 ` Richard Henderson 2018-11-21 7:43 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct " Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:10 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:10 ` [Qemu-riscv] " Richard Henderson 2018-11-19 23:06 ` Alistair Francis 2018-11-19 23:06 ` [Qemu-riscv] " Alistair Francis 2018-11-20 6:57 ` Richard Henderson 2018-11-20 6:57 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:22 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:22 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:25 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:25 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:26 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:26 ` [Qemu-riscv] " Richard Henderson 2018-11-19 23:04 ` Alistair Francis 2018-11-19 23:04 ` [Qemu-riscv] " Alistair Francis 2018-11-20 6:55 ` Richard Henderson 2018-11-20 6:55 ` [Qemu-riscv] " Richard Henderson 2018-11-20 23:22 ` Alistair Francis 2018-11-20 23:22 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:27 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:27 ` [Qemu-riscv] " Richard Henderson 2018-11-16 17:29 ` Richard Henderson 2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:29 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:30 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:30 ` [Qemu-riscv] " Richard Henderson 2018-11-16 8:31 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support no-reply 2018-11-16 8:31 ` [Qemu-riscv] " no-reply
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