From: Richard Henderson <richard.henderson@linaro.org> To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org> Cc: "alistair23@gmail.com" <alistair23@gmail.com> Subject: Re: [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Date: Fri, 16 Nov 2018 09:55:42 +0100 [thread overview] Message-ID: <a9f58e8f-0cba-57fa-59ed-415b58ae2f2c@linaro.org> (raw) In-Reply-To: <51aa21df48c5d80484bf396b82d9e3943daf1e0c.1542321076.git.alistair.francis@wdc.com> On 11/15/18 11:35 PM, Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > Signed-off-by: Michael Clark <mjc@sifive.com> > --- > tcg/riscv/tcg-target.inc.c | 62 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c > index 475feca906..0e891e24c9 100644 > --- a/tcg/riscv/tcg-target.inc.c > +++ b/tcg/riscv/tcg-target.inc.c > @@ -422,6 +422,68 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, > } > } > > +/* > + * TCG intrinsics > + */ > + > +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) > +{ > + if (ret == arg) { > + return; > + } > + switch (type) { > + case TCG_TYPE_I32: > + case TCG_TYPE_I64: > + tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); > + break; > + default: > + g_assert_not_reached(); > + } > +} > + > +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, > + tcg_target_long val) > +{ > + tcg_target_long lo = sextract32(val, 0, 12); sextract64, otherwise you'll make wrong decisions for rv64. (Although it might be worthwhile to add a local alias so that rv32 doesn't do more work than necessary.) > + tcg_target_long hi = val - lo; > + > + RISCVInsn add32_op = TCG_TARGET_REG_BITS == 64 ? OPC_ADDIW : OPC_ADDI; > + > +#if TCG_TARGET_REG_BITS == 64 > + ptrdiff_t offset = tcg_pcrel_diff(s, (void *)val); > +#endif > + > + if (val == lo) { > + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, val); return; } Should match if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) { tcg_out_opc_upper(s, OPC_LUI, rd, hi); if (lo != 0) { tcg_out_opc_imm(s, add32_op, rd, rd, lo); } return; } here. (1) Almost all values requested are 32-bit constants, so check the most common cases first. (2) You know hi != 0 because you just eliminated val == lo. (3) This handles the cases where LUI alone can load the constant, e.g. 0x1000, which would otherwise have been matched by your power-of-two test. > + } else if (val && !(val & (val - 1))) { > + /* power of 2 */ > + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, 1); > + tcg_out_opc_imm(s, OPC_SLLI, rd, rd, ctz64(val)); There's no reason to restrict this to powers of 2 and a shift of the constant 1: shift = ctz64(val); tmp = val >> shift; if (tmp == sextract64(tmp, 0, 12)) > + } else if (TCG_TARGET_REG_BITS == 64 && > + !(val >> 31 == 0 || val >> 31 == -1)) { > + int shift = 12 + ctz64(hi >> 12); This is just ctz64(hi), since you've already cleared the lo 12 bits. > + hi >>= shift; > + tcg_out_movi(s, type, rd, hi); > + tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift); > + if (lo != 0) { > + tcg_out_opc_imm(s, OPC_ADDI, rd, rd, lo); > + } > +#if TCG_TARGET_REG_BITS == 64 > + } else if (offset == sextract32(offset, 1, 31) << 1) { sextract64. > + tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); > + tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); > + reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); > +#endif Move this pc-rel case above the fully general case and then you can make the fully general case unconditional. Also, that preserves an invariant of increasing order of complexity of the cases. No need for the ifdef, since this code should be removed as dead for rv32 (which saw the lui+addi case as unconditional). r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org> To: Alistair Francis <Alistair.Francis@wdc.com>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>, "qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org> Cc: "alistair23@gmail.com" <alistair23@gmail.com> Subject: Re: [Qemu-riscv] [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Date: Fri, 16 Nov 2018 09:55:42 +0100 [thread overview] Message-ID: <a9f58e8f-0cba-57fa-59ed-415b58ae2f2c@linaro.org> (raw) In-Reply-To: <51aa21df48c5d80484bf396b82d9e3943daf1e0c.1542321076.git.alistair.francis@wdc.com> On 11/15/18 11:35 PM, Alistair Francis wrote: > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > Signed-off-by: Michael Clark <mjc@sifive.com> > --- > tcg/riscv/tcg-target.inc.c | 62 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 62 insertions(+) > > diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c > index 475feca906..0e891e24c9 100644 > --- a/tcg/riscv/tcg-target.inc.c > +++ b/tcg/riscv/tcg-target.inc.c > @@ -422,6 +422,68 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, > } > } > > +/* > + * TCG intrinsics > + */ > + > +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) > +{ > + if (ret == arg) { > + return; > + } > + switch (type) { > + case TCG_TYPE_I32: > + case TCG_TYPE_I64: > + tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); > + break; > + default: > + g_assert_not_reached(); > + } > +} > + > +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, > + tcg_target_long val) > +{ > + tcg_target_long lo = sextract32(val, 0, 12); sextract64, otherwise you'll make wrong decisions for rv64. (Although it might be worthwhile to add a local alias so that rv32 doesn't do more work than necessary.) > + tcg_target_long hi = val - lo; > + > + RISCVInsn add32_op = TCG_TARGET_REG_BITS == 64 ? OPC_ADDIW : OPC_ADDI; > + > +#if TCG_TARGET_REG_BITS == 64 > + ptrdiff_t offset = tcg_pcrel_diff(s, (void *)val); > +#endif > + > + if (val == lo) { > + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, val); return; } Should match if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) { tcg_out_opc_upper(s, OPC_LUI, rd, hi); if (lo != 0) { tcg_out_opc_imm(s, add32_op, rd, rd, lo); } return; } here. (1) Almost all values requested are 32-bit constants, so check the most common cases first. (2) You know hi != 0 because you just eliminated val == lo. (3) This handles the cases where LUI alone can load the constant, e.g. 0x1000, which would otherwise have been matched by your power-of-two test. > + } else if (val && !(val & (val - 1))) { > + /* power of 2 */ > + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, 1); > + tcg_out_opc_imm(s, OPC_SLLI, rd, rd, ctz64(val)); There's no reason to restrict this to powers of 2 and a shift of the constant 1: shift = ctz64(val); tmp = val >> shift; if (tmp == sextract64(tmp, 0, 12)) > + } else if (TCG_TARGET_REG_BITS == 64 && > + !(val >> 31 == 0 || val >> 31 == -1)) { > + int shift = 12 + ctz64(hi >> 12); This is just ctz64(hi), since you've already cleared the lo 12 bits. > + hi >>= shift; > + tcg_out_movi(s, type, rd, hi); > + tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift); > + if (lo != 0) { > + tcg_out_opc_imm(s, OPC_ADDI, rd, rd, lo); > + } > +#if TCG_TARGET_REG_BITS == 64 > + } else if (offset == sextract32(offset, 1, 31) << 1) { sextract64. > + tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); > + tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); > + reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); > +#endif Move this pc-rel case above the fully general case and then you can make the fully general case unconditional. Also, that preserves an invariant of increasing order of complexity of the cases. No need for the ifdef, since this code should be removed as dead for rv32 (which saw the lui+addi case as unconditional). r~
next prev parent reply other threads:[~2018-11-16 8:55 UTC|newest] Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-11-15 22:33 [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support Alistair Francis 2018-11-15 22:33 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson 2018-11-16 7:47 ` Richard Henderson 2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:47 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson 2018-11-16 17:20 ` Richard Henderson 2018-11-16 17:20 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:58 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:58 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:34 ` [Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT Alistair Francis 2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis 2018-11-16 7:59 ` [Qemu-devel] " Richard Henderson 2018-11-16 7:59 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:13 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:13 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:26 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:26 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:27 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:27 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:33 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:33 ` [Qemu-riscv] " Richard Henderson 2018-11-21 1:15 ` Alistair Francis 2018-11-21 1:15 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:25 ` Richard Henderson 2018-11-21 7:25 ` [Qemu-riscv] " Richard Henderson 2018-11-21 15:53 ` Palmer Dabbelt 2018-11-21 15:53 ` [Qemu-riscv] " Palmer Dabbelt 2018-11-21 17:01 ` Richard Henderson 2018-11-21 17:01 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:55 ` Richard Henderson [this message] 2018-11-16 8:55 ` [Qemu-riscv] [Qemu-devel] " Richard Henderson 2018-11-15 22:35 ` [Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions Alistair Francis 2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:56 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:56 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 8:59 ` [Qemu-devel] " Richard Henderson 2018-11-16 8:59 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 9:14 ` [Qemu-devel] " Richard Henderson 2018-11-16 9:14 ` [Qemu-riscv] " Richard Henderson 2018-11-20 23:49 ` Alistair Francis 2018-11-20 23:49 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:40 ` Richard Henderson 2018-11-21 7:40 ` [Qemu-riscv] " Richard Henderson 2018-11-26 22:58 ` Alistair Francis 2018-11-26 22:58 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 9:24 ` [Qemu-devel] " Richard Henderson 2018-11-16 9:24 ` [Qemu-riscv] " Richard Henderson 2018-11-21 0:18 ` Alistair Francis 2018-11-21 0:18 ` [Qemu-riscv] " Alistair Francis 2018-11-21 7:43 ` Richard Henderson 2018-11-21 7:43 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct " Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:10 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:10 ` [Qemu-riscv] " Richard Henderson 2018-11-19 23:06 ` Alistair Francis 2018-11-19 23:06 ` [Qemu-riscv] " Alistair Francis 2018-11-20 6:57 ` Richard Henderson 2018-11-20 6:57 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:22 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:22 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:25 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:25 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:36 ` [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code Alistair Francis 2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:26 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:26 ` [Qemu-riscv] " Richard Henderson 2018-11-19 23:04 ` Alistair Francis 2018-11-19 23:04 ` [Qemu-riscv] " Alistair Francis 2018-11-20 6:55 ` Richard Henderson 2018-11-20 6:55 ` [Qemu-riscv] " Richard Henderson 2018-11-20 23:22 ` Alistair Francis 2018-11-20 23:22 ` [Qemu-riscv] " Alistair Francis 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:27 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:27 ` [Qemu-riscv] " Richard Henderson 2018-11-16 17:29 ` Richard Henderson 2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:29 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson 2018-11-15 22:37 ` [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host Alistair Francis 2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis 2018-11-16 17:30 ` [Qemu-devel] " Richard Henderson 2018-11-16 17:30 ` [Qemu-riscv] " Richard Henderson 2018-11-16 8:31 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support no-reply 2018-11-16 8:31 ` [Qemu-riscv] " no-reply
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