From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: Re: [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions
Date: Fri, 16 Nov 2018 09:59:04 +0100 [thread overview]
Message-ID: <d11e2ddb-978e-1359-16ff-4b640cd74e6d@linaro.org> (raw)
In-Reply-To: <7961f2bc55e109ff10543c4665c5cbc3c75a5bf7.1542321076.git.alistair.francis@wdc.com>
On 11/15/18 11:36 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> tcg/riscv/tcg-target.inc.c | 56 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
> index 646a4d3ebd..bc433170c4 100644
> --- a/tcg/riscv/tcg-target.inc.c
> +++ b/tcg/riscv/tcg-target.inc.c
> @@ -518,6 +518,62 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
> tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
> }
>
> +static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
> + TCGReg addr, intptr_t offset)
> +{
> + int32_t imm12 = sextract32(offset, 0, 12);
sextract64 for rv64.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
WARNING: multiple messages have this Message-ID (diff)
From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <Alistair.Francis@wdc.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"qemu-riscv@nongnu.org" <qemu-riscv@nongnu.org>
Cc: "alistair23@gmail.com" <alistair23@gmail.com>
Subject: Re: [Qemu-riscv] [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions
Date: Fri, 16 Nov 2018 09:59:04 +0100 [thread overview]
Message-ID: <d11e2ddb-978e-1359-16ff-4b640cd74e6d@linaro.org> (raw)
In-Reply-To: <7961f2bc55e109ff10543c4665c5cbc3c75a5bf7.1542321076.git.alistair.francis@wdc.com>
On 11/15/18 11:36 PM, Alistair Francis wrote:
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>
> ---
> tcg/riscv/tcg-target.inc.c | 56 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
> index 646a4d3ebd..bc433170c4 100644
> --- a/tcg/riscv/tcg-target.inc.c
> +++ b/tcg/riscv/tcg-target.inc.c
> @@ -518,6 +518,62 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
> tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0);
> }
>
> +static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data,
> + TCGReg addr, intptr_t offset)
> +{
> + int32_t imm12 = sextract32(offset, 0, 12);
sextract64 for rv64.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2018-11-16 8:59 UTC|newest]
Thread overview: 130+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-15 22:33 [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support Alistair Francis
2018-11-15 22:33 ` [Qemu-riscv] " Alistair Francis
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 01/23] elf.h: Add the RISCV ELF magic numbers Alistair Francis
2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis
2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson
2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 02/23] linux-user: Add host dependency for RISC-V 32-bit Alistair Francis
2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis
2018-11-16 7:46 ` [Qemu-devel] " Richard Henderson
2018-11-16 7:46 ` [Qemu-riscv] " Richard Henderson
2018-11-16 7:47 ` Richard Henderson
2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 03/23] linux-user: Add host dependency for RISC-V 64-bit Alistair Francis
2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis
2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson
2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 04/23] exec: Add RISC-V GCC poison macro Alistair Francis
2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis
2018-11-16 7:47 ` [Qemu-devel] " Richard Henderson
2018-11-16 7:47 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 05/23] riscv: Add the tcg-target header file Alistair Francis
2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis
2018-11-16 7:57 ` [Qemu-devel] " Richard Henderson
2018-11-16 7:57 ` [Qemu-riscv] " Richard Henderson
2018-11-16 17:20 ` Richard Henderson
2018-11-16 17:20 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 06/23] riscv: Add the tcg target registers Alistair Francis
2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis
2018-11-16 7:58 ` [Qemu-devel] " Richard Henderson
2018-11-16 7:58 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:34 ` [Qemu-devel] [RFC v1 07/23] riscv: tcg-target: Regiser the JIT Alistair Francis
2018-11-15 22:34 ` [Qemu-riscv] " Alistair Francis
2018-11-16 7:59 ` [Qemu-devel] " Richard Henderson
2018-11-16 7:59 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 08/23] riscv: tcg-target: Add support for the constraints Alistair Francis
2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis
2018-11-16 8:13 ` [Qemu-devel] " Richard Henderson
2018-11-16 8:13 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 09/23] riscv: tcg-target: Add the immediate encoders Alistair Francis
2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis
2018-11-16 8:26 ` [Qemu-devel] " Richard Henderson
2018-11-16 8:26 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 10/23] riscv: tcg-target: Add the instruction emitters Alistair Francis
2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis
2018-11-16 8:27 ` [Qemu-devel] " Richard Henderson
2018-11-16 8:27 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 11/23] riscv: tcg-target: Add the relocation functions Alistair Francis
2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis
2018-11-16 8:33 ` [Qemu-devel] " Richard Henderson
2018-11-16 8:33 ` [Qemu-riscv] " Richard Henderson
2018-11-21 1:15 ` Alistair Francis
2018-11-21 1:15 ` [Qemu-riscv] " Alistair Francis
2018-11-21 7:25 ` Richard Henderson
2018-11-21 7:25 ` [Qemu-riscv] " Richard Henderson
2018-11-21 15:53 ` Palmer Dabbelt
2018-11-21 15:53 ` [Qemu-riscv] " Palmer Dabbelt
2018-11-21 17:01 ` Richard Henderson
2018-11-21 17:01 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 12/23] riscv: tcg-target: Add the mov and movi instruction Alistair Francis
2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis
2018-11-16 8:55 ` [Qemu-devel] " Richard Henderson
2018-11-16 8:55 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:35 ` [Qemu-devel] [RFC v1 13/23] riscv: tcg-target: Add the extract instructions Alistair Francis
2018-11-15 22:35 ` [Qemu-riscv] " Alistair Francis
2018-11-16 8:56 ` [Qemu-devel] " Richard Henderson
2018-11-16 8:56 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 14/23] riscv: tcg-target: Add the out load and store instructions Alistair Francis
2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis
2018-11-16 8:59 ` Richard Henderson [this message]
2018-11-16 8:59 ` [Qemu-riscv] [Qemu-devel] " Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 15/23] riscv: tcg-target: Add branch and jump instructions Alistair Francis
2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis
2018-11-16 9:14 ` [Qemu-devel] " Richard Henderson
2018-11-16 9:14 ` [Qemu-riscv] " Richard Henderson
2018-11-20 23:49 ` Alistair Francis
2018-11-20 23:49 ` [Qemu-riscv] " Alistair Francis
2018-11-21 7:40 ` Richard Henderson
2018-11-21 7:40 ` [Qemu-riscv] " Richard Henderson
2018-11-26 22:58 ` Alistair Francis
2018-11-26 22:58 ` [Qemu-riscv] " Alistair Francis
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 16/23] riscv: tcg-target: Add slowpath load and store instructions Alistair Francis
2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis
2018-11-16 9:24 ` [Qemu-devel] " Richard Henderson
2018-11-16 9:24 ` [Qemu-riscv] " Richard Henderson
2018-11-21 0:18 ` Alistair Francis
2018-11-21 0:18 ` [Qemu-riscv] " Alistair Francis
2018-11-21 7:43 ` Richard Henderson
2018-11-21 7:43 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 17/23] riscv: tcg-target: Add direct " Alistair Francis
2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis
2018-11-16 17:10 ` [Qemu-devel] " Richard Henderson
2018-11-16 17:10 ` [Qemu-riscv] " Richard Henderson
2018-11-19 23:06 ` Alistair Francis
2018-11-19 23:06 ` [Qemu-riscv] " Alistair Francis
2018-11-20 6:57 ` Richard Henderson
2018-11-20 6:57 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 18/23] riscv: tcg-target: Add the out op decoder Alistair Francis
2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis
2018-11-16 17:22 ` [Qemu-devel] " Richard Henderson
2018-11-16 17:22 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 19/23] riscv: tcg-target: Add the prologue generation Alistair Francis
2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis
2018-11-16 17:25 ` [Qemu-devel] " Richard Henderson
2018-11-16 17:25 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:36 ` [Qemu-devel] [RFC v1 20/23] riscv: tcg-target: Add the target init code Alistair Francis
2018-11-15 22:36 ` [Qemu-riscv] " Alistair Francis
2018-11-16 17:26 ` [Qemu-devel] " Richard Henderson
2018-11-16 17:26 ` [Qemu-riscv] " Richard Henderson
2018-11-19 23:04 ` Alistair Francis
2018-11-19 23:04 ` [Qemu-riscv] " Alistair Francis
2018-11-20 6:55 ` Richard Henderson
2018-11-20 6:55 ` [Qemu-riscv] " Richard Henderson
2018-11-20 23:22 ` Alistair Francis
2018-11-20 23:22 ` [Qemu-riscv] " Alistair Francis
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 21/23] tcg: Add RISC-V cpu signal handler Alistair Francis
2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis
2018-11-16 17:27 ` [Qemu-devel] " Richard Henderson
2018-11-16 17:27 ` [Qemu-riscv] " Richard Henderson
2018-11-16 17:29 ` Richard Henderson
2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 22/23] dias: Add RISC-V support Alistair Francis
2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis
2018-11-16 17:29 ` [Qemu-devel] " Richard Henderson
2018-11-16 17:29 ` [Qemu-riscv] " Richard Henderson
2018-11-15 22:37 ` [Qemu-devel] [RFC v1 23/23] configure: Add support for building RISC-V host Alistair Francis
2018-11-15 22:37 ` [Qemu-riscv] " Alistair Francis
2018-11-16 17:30 ` [Qemu-devel] " Richard Henderson
2018-11-16 17:30 ` [Qemu-riscv] " Richard Henderson
2018-11-16 8:31 ` [Qemu-devel] [RFC v1 00/23] Add RISC-V TCG backend support no-reply
2018-11-16 8:31 ` [Qemu-riscv] " no-reply
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