From: Samuel Holland <samuel@sholland.org> To: Icenowy Zheng <icenowy@sipeed.com>, Rob Herring <robh+dt@kernel.org>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Ulf Hansson <ulf.hansson@linaro.org>, Linus Walleij <linus.walleij@linaro.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Andre Przywara <andre.przywara@arm.com> Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 07/17] pinctrl: sunxi: add support for R329 CPUX pin controller Date: Wed, 18 Aug 2021 22:09:56 -0500 [thread overview] Message-ID: <2f6de069-7983-efc2-3c4a-7c1355c4cbc5@sholland.org> (raw) In-Reply-To: <20210802062212.73220-8-icenowy@sipeed.com> On 8/2/21 1:22 AM, Icenowy Zheng wrote: > Allwinner R329 SoC has two pin controllers similar to ones on previous > SoCs, one in CPUX power domain and another in CPUS. > > This patch adds support for the CPUX domain pin controller. > > Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> > --- > drivers/pinctrl/sunxi/Kconfig | 5 + > drivers/pinctrl/sunxi/Makefile | 1 + > drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c | 410 ++++++++++++++++++++ > 3 files changed, 416 insertions(+) > create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c > > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig > index 33751a6a0757..c662e8b1b351 100644 > --- a/drivers/pinctrl/sunxi/Kconfig > +++ b/drivers/pinctrl/sunxi/Kconfig > @@ -129,4 +129,9 @@ config PINCTRL_SUN50I_H616_R > default ARM64 && ARCH_SUNXI > select PINCTRL_SUNXI > > +config PINCTRL_SUN50I_R329 > + bool "Support for the Allwinner R329 PIO" > + default ARM64 && ARCH_SUNXI > + select PINCTRL_SUNXI > + > endif > diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile > index d3440c42b9d6..e33f7c5f1ff9 100644 > --- a/drivers/pinctrl/sunxi/Makefile > +++ b/drivers/pinctrl/sunxi/Makefile > @@ -25,5 +25,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o > obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o > obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o > obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o > +obj-$(CONFIG_PINCTRL_SUN50I_R329) += pinctrl-sun50i-r329.o > obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o > obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c > new file mode 100644 > index 000000000000..742f437ec0b6 > --- /dev/null > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c > @@ -0,0 +1,410 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Allwinner R329 SoC pinctrl driver. > + * > + * Copyright (C) 2021 Sipeed > + * based on the H616 pinctrl driver > + * Copyright (C) 2020 Arm Ltd. > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/pinctrl/pinctrl.h> > + > +#include "pinctrl-sunxi.h" > + > +static const struct sunxi_desc_pin r329_pins[] = { > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM0 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ > + SUNXI_FUNCTION(0x5, "ledc"), /* DO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ > + SUNXI_FUNCTION(0x5, "i2s0"), /* MCLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM2 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ > + SUNXI_FUNCTION(0x5, "i2s0"), /* LRCK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM3 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ > + SUNXI_FUNCTION(0x5, "i2s0"), /* BCLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM4 */ > + SUNXI_FUNCTION(0x4, "i2s0_dout0"), > + SUNXI_FUNCTION(0x5, "i2s0_din1"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM5 */ > + SUNXI_FUNCTION(0x4, "i2s0_dout1"), > + SUNXI_FUNCTION(0x5, "i2s0_din0"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "ir"), /* RX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM6 */ > + SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT2 */ > + SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "ir"), /* TX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM7 */ > + SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT3 */ > + SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "ir_tx"), > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM8 */ > + SUNXI_FUNCTION(0x4, "ir_rx"), > + SUNXI_FUNCTION(0x5, "ledc"), /* DO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* CLK */ > + SUNXI_FUNCTION(0x4, "spi0")), /* CS */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* CMD */ > + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D2 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* WP */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D1 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D0 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* CLK */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D3 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ > + SUNXI_FUNCTION(0x3, "mmc0")), /* RST */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ > + SUNXI_FUNCTION(0x5, "boot_sel")), > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ Please be consistent between "nand" and "nand0". "nand0" looks like it is much more common. > + SUNXI_FUNCTION(0x3, "sim0"), /* VPPEN */ > + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* D1 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* VPPPP */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* D0 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ5 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* PWREN */ > + SUNXI_FUNCTION(0x4, "uart"), /* TX */ Should be "uart0". > + SUNXI_FUNCTION(0x5, "mmc0"), /* CLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ4 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* CLK */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* CMD */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ > + SUNXI_FUNCTION(0x3, "sim0"), /* DATA */ > + SUNXI_FUNCTION(0x4, "uart"), /* RX */ "uart0" here as well. > + SUNXI_FUNCTION(0x5, "mmc0"), /* D3 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ2 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* RST */ > + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* D2 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ1 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* DET */ > + SUNXI_FUNCTION(0x4, "spdif_in"), > + SUNXI_FUNCTION(0x5, "spdif_out"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_clk"), > + SUNXI_FUNCTION(0x3, "mmc1_d2"), > + /* 0x4 is also mmc1_d2 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_cmd"), > + SUNXI_FUNCTION(0x3, "mmc1_d3"), > + SUNXI_FUNCTION(0x4, "mmc1_clk"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d0"), > + SUNXI_FUNCTION(0x3, "mmc1_cmd"), > + SUNXI_FUNCTION(0x4, "mmc1_d3"), Missing function 5 "pll". > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d1"), > + SUNXI_FUNCTION(0x3, "mmc1_clk"), > + /* 0x4 is also mmc1_d1 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d2"), > + SUNXI_FUNCTION(0x3, "mmc1_d0"), > + /* 0x4 is also mmc1_d0 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d3"), > + SUNXI_FUNCTION(0x3, "mmc1_d1"), > + SUNXI_FUNCTION(0x4, "mmc1_cmd"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ > + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ > + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ > + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ > + SUNXI_FUNCTION(0x5, "spi1"), /* HOLD/DBI-DCX/DBI-WRX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ > + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ > + SUNXI_FUNCTION(0x5, "spi1"), /* WP/DBI-TE */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ > + SUNXI_FUNCTION(0x3, "ledc"), /* DO */ Should be function 4. > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ > + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ > + SUNXI_FUNCTION(0x5, "spi1"), /* CS/DBI-CSX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ > + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ > + SUNXI_FUNCTION(0x5, "spi1"), /* CLK/DBI-SCLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ > + SUNXI_FUNCTION(0x3, "i2s1_dout0"), > + SUNXI_FUNCTION(0x4, "i2s1_din1"), > + SUNXI_FUNCTION(0x5, "spi1"), /* MOSI/DBI-SDO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ > + SUNXI_FUNCTION(0x3, "i2s1_dout1"), > + SUNXI_FUNCTION(0x4, "i2s1_din0"), > + SUNXI_FUNCTION(0x5, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */ > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ > + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ > + SUNXI_FUNCTION(0x4, "spi1"), /* CS/DBI-CSX */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM0 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ > + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ > + SUNXI_FUNCTION(0x4, "spi1"), /* CLK/DBI-SCLK */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM1 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ > + SUNXI_FUNCTION(0x3, "ledc"), /* DO */ > + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI/DBI-SDO */ > + SUNXI_FUNCTION(0x5, "ir"), /* RX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ > + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ > + SUNXI_FUNCTION(0x4, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ > + SUNXI_FUNCTION(0x5, "ir"), /* TX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ > + SUNXI_FUNCTION(0x3, "spi1_cs"), /* CS/DBI-CSX */ > + SUNXI_FUNCTION(0x4, "spi1_hold"), /* HOLD/DBI-DCX/DBI-WRX */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM2 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ > + SUNXI_FUNCTION(0x3, "spi1_clk"), /* CLK/DBI-SCLK */ > + SUNXI_FUNCTION(0x4, "spi1_wp"), /* WP/DBI-TE */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM3 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ > + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI/SPI-DBO */ > + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM4 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ > + SUNXI_FUNCTION(0x3, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ > + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM5 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ > + SUNXI_FUNCTION(0x3, "spi1"), /* WP/DBI-TE */ > + SUNXI_FUNCTION(0x4, "ledc"), /* DO */ > + SUNXI_FUNCTION(0x5, "ir"), /* TX */ You have PH8 and PH9 functions 2 through 5 swapped. And I won't be surprised if I missed something too :) Regards, Samuel > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ > + SUNXI_FUNCTION(0x3, "spi1"), /* HOLD/DBI-DCX/DBI-WRX */ > + SUNXI_FUNCTION(0x4, "spdif"), /* IN */ > + SUNXI_FUNCTION(0x5, "ir"), /* RX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */ > +}; > +static const unsigned int r329_irq_bank_map[] = { 1, 5, 6, 7 }; > + > +static const struct sunxi_pinctrl_desc r329_pinctrl_data = { > + .pins = r329_pins, > + .npins = ARRAY_SIZE(r329_pins), > + .irq_banks = ARRAY_SIZE(r329_irq_bank_map), > + .irq_bank_map = r329_irq_bank_map, > + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, > +}; > + > +static int r329_pinctrl_probe(struct platform_device *pdev) > +{ > + return sunxi_pinctrl_init(pdev, &r329_pinctrl_data); > +} > + > +static const struct of_device_id r329_pinctrl_match[] = { > + { .compatible = "allwinner,sun50i-r329-pinctrl", }, > + {} > +}; > + > +static struct platform_driver r329_pinctrl_driver = { > + .probe = r329_pinctrl_probe, > + .driver = { > + .name = "sun50i-r329-pinctrl", > + .of_match_table = r329_pinctrl_match, > + }, > +}; > +builtin_platform_driver(r329_pinctrl_driver); >
WARNING: multiple messages have this Message-ID (diff)
From: Samuel Holland <samuel@sholland.org> To: Icenowy Zheng <icenowy@sipeed.com>, Rob Herring <robh+dt@kernel.org>, Maxime Ripard <mripard@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Ulf Hansson <ulf.hansson@linaro.org>, Linus Walleij <linus.walleij@linaro.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Andre Przywara <andre.przywara@arm.com> Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 07/17] pinctrl: sunxi: add support for R329 CPUX pin controller Date: Wed, 18 Aug 2021 22:09:56 -0500 [thread overview] Message-ID: <2f6de069-7983-efc2-3c4a-7c1355c4cbc5@sholland.org> (raw) In-Reply-To: <20210802062212.73220-8-icenowy@sipeed.com> On 8/2/21 1:22 AM, Icenowy Zheng wrote: > Allwinner R329 SoC has two pin controllers similar to ones on previous > SoCs, one in CPUX power domain and another in CPUS. > > This patch adds support for the CPUX domain pin controller. > > Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> > --- > drivers/pinctrl/sunxi/Kconfig | 5 + > drivers/pinctrl/sunxi/Makefile | 1 + > drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c | 410 ++++++++++++++++++++ > 3 files changed, 416 insertions(+) > create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c > > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig > index 33751a6a0757..c662e8b1b351 100644 > --- a/drivers/pinctrl/sunxi/Kconfig > +++ b/drivers/pinctrl/sunxi/Kconfig > @@ -129,4 +129,9 @@ config PINCTRL_SUN50I_H616_R > default ARM64 && ARCH_SUNXI > select PINCTRL_SUNXI > > +config PINCTRL_SUN50I_R329 > + bool "Support for the Allwinner R329 PIO" > + default ARM64 && ARCH_SUNXI > + select PINCTRL_SUNXI > + > endif > diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile > index d3440c42b9d6..e33f7c5f1ff9 100644 > --- a/drivers/pinctrl/sunxi/Makefile > +++ b/drivers/pinctrl/sunxi/Makefile > @@ -25,5 +25,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o > obj-$(CONFIG_PINCTRL_SUN50I_H6_R) += pinctrl-sun50i-h6-r.o > obj-$(CONFIG_PINCTRL_SUN50I_H616) += pinctrl-sun50i-h616.o > obj-$(CONFIG_PINCTRL_SUN50I_H616_R) += pinctrl-sun50i-h616-r.o > +obj-$(CONFIG_PINCTRL_SUN50I_R329) += pinctrl-sun50i-r329.o > obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o > obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c > new file mode 100644 > index 000000000000..742f437ec0b6 > --- /dev/null > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-r329.c > @@ -0,0 +1,410 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Allwinner R329 SoC pinctrl driver. > + * > + * Copyright (C) 2021 Sipeed > + * based on the H616 pinctrl driver > + * Copyright (C) 2020 Arm Ltd. > + */ > + > +#include <linux/module.h> > +#include <linux/platform_device.h> > +#include <linux/of.h> > +#include <linux/of_device.h> > +#include <linux/pinctrl/pinctrl.h> > + > +#include "pinctrl-sunxi.h" > + > +static const struct sunxi_desc_pin r329_pins[] = { > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* TX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM0 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ > + SUNXI_FUNCTION(0x5, "ledc"), /* DO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PB_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* RX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM1 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ > + SUNXI_FUNCTION(0x5, "i2s0"), /* MCLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PB_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM2 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ > + SUNXI_FUNCTION(0x5, "i2s0"), /* LRCK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PB_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM3 */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ > + SUNXI_FUNCTION(0x5, "i2s0"), /* BCLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PB_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart0"), /* TX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM4 */ > + SUNXI_FUNCTION(0x4, "i2s0_dout0"), > + SUNXI_FUNCTION(0x5, "i2s0_din1"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PB_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart0"), /* RX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM5 */ > + SUNXI_FUNCTION(0x4, "i2s0_dout1"), > + SUNXI_FUNCTION(0x5, "i2s0_din0"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PB_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "ir"), /* RX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM6 */ > + SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT2 */ > + SUNXI_FUNCTION(0x5, "i2c0"), /* SCK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PB_EINT6 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "ir"), /* TX */ > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM7 */ > + SUNXI_FUNCTION(0x4, "i2s0"), /* DOUT3 */ > + SUNXI_FUNCTION(0x5, "i2c0"), /* SDA */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PB_EINT7 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "ir_tx"), > + SUNXI_FUNCTION(0x3, "pwm"), /* PWM8 */ > + SUNXI_FUNCTION(0x4, "ir_rx"), > + SUNXI_FUNCTION(0x5, "ledc"), /* DO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PB_EINT8 */ > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* CLK */ > + SUNXI_FUNCTION(0x4, "spi0")), /* CS */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* RE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* CMD */ > + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D2 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* WP */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D1 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* MOSI */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D0 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* CLK */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* WE */ > + SUNXI_FUNCTION(0x3, "mmc0"), /* D3 */ > + SUNXI_FUNCTION(0x4, "spi0")), /* HOLD */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */ > + SUNXI_FUNCTION(0x3, "mmc0")), /* RST */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */ > + SUNXI_FUNCTION(0x5, "boot_sel")), > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ7 */ Please be consistent between "nand" and "nand0". "nand0" looks like it is much more common. > + SUNXI_FUNCTION(0x3, "sim0"), /* VPPEN */ > + SUNXI_FUNCTION(0x4, "jtag"), /* MS */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* D1 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ6 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* VPPPP */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DI */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* D0 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ5 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* PWREN */ > + SUNXI_FUNCTION(0x4, "uart"), /* TX */ Should be "uart0". > + SUNXI_FUNCTION(0x5, "mmc0"), /* CLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ4 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* CLK */ > + SUNXI_FUNCTION(0x4, "jtag"), /* DO */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* CMD */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQS */ > + SUNXI_FUNCTION(0x3, "sim0"), /* DATA */ > + SUNXI_FUNCTION(0x4, "uart"), /* RX */ "uart0" here as well. > + SUNXI_FUNCTION(0x5, "mmc0"), /* D3 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ2 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* RST */ > + SUNXI_FUNCTION(0x4, "jtag"), /* CK */ > + SUNXI_FUNCTION(0x5, "mmc0"), /* D2 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "nand"), /* DQ1 */ > + SUNXI_FUNCTION(0x3, "sim0"), /* DET */ > + SUNXI_FUNCTION(0x4, "spdif_in"), > + SUNXI_FUNCTION(0x5, "spdif_out"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */ > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_clk"), > + SUNXI_FUNCTION(0x3, "mmc1_d2"), > + /* 0x4 is also mmc1_d2 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_cmd"), > + SUNXI_FUNCTION(0x3, "mmc1_d3"), > + SUNXI_FUNCTION(0x4, "mmc1_clk"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d0"), > + SUNXI_FUNCTION(0x3, "mmc1_cmd"), > + SUNXI_FUNCTION(0x4, "mmc1_d3"), Missing function 5 "pll". > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d1"), > + SUNXI_FUNCTION(0x3, "mmc1_clk"), > + /* 0x4 is also mmc1_d1 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d2"), > + SUNXI_FUNCTION(0x3, "mmc1_d0"), > + /* 0x4 is also mmc1_d0 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "mmc1_d3"), > + SUNXI_FUNCTION(0x3, "mmc1_d1"), > + SUNXI_FUNCTION(0x4, "mmc1_cmd"), > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* TX */ > + SUNXI_FUNCTION(0x3, "i2c0"), /* SCK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* RX */ > + SUNXI_FUNCTION(0x3, "i2c0"), /* SDA */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */ > + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */ > + SUNXI_FUNCTION(0x5, "spi1"), /* HOLD/DBI-DCX/DBI-WRX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */ > + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */ > + SUNXI_FUNCTION(0x5, "spi1"), /* WP/DBI-TE */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x3, "i2s1"), /* MCLK */ > + SUNXI_FUNCTION(0x3, "ledc"), /* DO */ Should be function 4. > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ > + SUNXI_FUNCTION(0x3, "i2s1"), /* LRCK */ > + SUNXI_FUNCTION(0x5, "spi1"), /* CS/DBI-CSX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ > + SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */ > + SUNXI_FUNCTION(0x5, "spi1"), /* CLK/DBI-SCLK */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ > + SUNXI_FUNCTION(0x3, "i2s1_dout0"), > + SUNXI_FUNCTION(0x4, "i2s1_din1"), > + SUNXI_FUNCTION(0x5, "spi1"), /* MOSI/DBI-SDO */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 14), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ > + SUNXI_FUNCTION(0x3, "i2s1_dout1"), > + SUNXI_FUNCTION(0x4, "i2s1_din0"), > + SUNXI_FUNCTION(0x5, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 14)), /* PG_EINT14 */ > + /* Hole */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 0), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */ > + SUNXI_FUNCTION(0x3, "uart0"), /* TX */ > + SUNXI_FUNCTION(0x4, "spi1"), /* CS/DBI-CSX */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM0 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 0)), /* PH_EINT0 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 1), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */ > + SUNXI_FUNCTION(0x3, "uart0"), /* RX */ > + SUNXI_FUNCTION(0x4, "spi1"), /* CLK/DBI-SCLK */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM1 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 1)), /* PH_EINT1 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 2), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ > + SUNXI_FUNCTION(0x3, "ledc"), /* DO */ > + SUNXI_FUNCTION(0x4, "spi1"), /* MOSI/DBI-SDO */ > + SUNXI_FUNCTION(0x5, "ir"), /* RX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 2)), /* PH_EINT2 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 3), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ > + SUNXI_FUNCTION(0x3, "spdif"), /* OUT */ > + SUNXI_FUNCTION(0x4, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ > + SUNXI_FUNCTION(0x5, "ir"), /* TX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 3)), /* PH_EINT3 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 4), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* TX */ > + SUNXI_FUNCTION(0x3, "spi1_cs"), /* CS/DBI-CSX */ > + SUNXI_FUNCTION(0x4, "spi1_hold"), /* HOLD/DBI-DCX/DBI-WRX */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM2 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 4)), /* PH_EINT4 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 5), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RX */ > + SUNXI_FUNCTION(0x3, "spi1_clk"), /* CLK/DBI-SCLK */ > + SUNXI_FUNCTION(0x4, "spi1_wp"), /* WP/DBI-TE */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM3 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 5)), /* PH_EINT5 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 6), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* RTS */ > + SUNXI_FUNCTION(0x3, "spi1"), /* MOSI/SPI-DBO */ > + SUNXI_FUNCTION(0x4, "i2c0"), /* SCK */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM4 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 6)), /* PH_EINT6 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 7), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "uart3"), /* CTS */ > + SUNXI_FUNCTION(0x3, "spi1"), /* MISO/DBI-SDI/DBI-TE/DBI-DCX */ > + SUNXI_FUNCTION(0x4, "i2c0"), /* SDA */ > + SUNXI_FUNCTION(0x5, "pwm"), /* PWM5 */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 7)), /* PH_EINT7 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 8), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SDA */ > + SUNXI_FUNCTION(0x3, "spi1"), /* WP/DBI-TE */ > + SUNXI_FUNCTION(0x4, "ledc"), /* DO */ > + SUNXI_FUNCTION(0x5, "ir"), /* TX */ You have PH8 and PH9 functions 2 through 5 swapped. And I won't be surprised if I missed something too :) Regards, Samuel > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 8)), /* PH_EINT8 */ > + SUNXI_PIN(SUNXI_PINCTRL_PIN(H, 9), > + SUNXI_FUNCTION(0x0, "gpio_in"), > + SUNXI_FUNCTION(0x1, "gpio_out"), > + SUNXI_FUNCTION(0x2, "i2c1"), /* SCK */ > + SUNXI_FUNCTION(0x3, "spi1"), /* HOLD/DBI-DCX/DBI-WRX */ > + SUNXI_FUNCTION(0x4, "spdif"), /* IN */ > + SUNXI_FUNCTION(0x5, "ir"), /* RX */ > + SUNXI_FUNCTION_IRQ_BANK(0x6, 3, 9)), /* PH_EINT9 */ > +}; > +static const unsigned int r329_irq_bank_map[] = { 1, 5, 6, 7 }; > + > +static const struct sunxi_pinctrl_desc r329_pinctrl_data = { > + .pins = r329_pins, > + .npins = ARRAY_SIZE(r329_pins), > + .irq_banks = ARRAY_SIZE(r329_irq_bank_map), > + .irq_bank_map = r329_irq_bank_map, > + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL, > +}; > + > +static int r329_pinctrl_probe(struct platform_device *pdev) > +{ > + return sunxi_pinctrl_init(pdev, &r329_pinctrl_data); > +} > + > +static const struct of_device_id r329_pinctrl_match[] = { > + { .compatible = "allwinner,sun50i-r329-pinctrl", }, > + {} > +}; > + > +static struct platform_driver r329_pinctrl_driver = { > + .probe = r329_pinctrl_probe, > + .driver = { > + .name = "sun50i-r329-pinctrl", > + .of_match_table = r329_pinctrl_match, > + }, > +}; > +builtin_platform_driver(r329_pinctrl_driver); > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-19 3:10 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-02 6:21 [PATCH 00/17] Basical Allwinner R329 support Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 01/17] rtc: sun6i: Fix time overflow handling Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 02/17] rtc: sun6i: Add support for linear day storage Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 03/17] rtc: sun6i: Add support for broken-down alarm registers Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 04/17] dt-bindings: rtc: sun6i: add compatible string for R329 RTC Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-06 21:39 ` Rob Herring 2021-08-06 21:39 ` Rob Herring 2021-08-02 6:22 ` [PATCH 05/17] rtc: sun6i: add support " Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 6:22 ` [PATCH 06/17] dt-bindings: pinctrl: document Allwinner R329 PIO and R-PIO Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:40 ` Rob Herring 2021-08-06 21:40 ` Rob Herring 2021-08-18 8:48 ` Maxime Ripard 2021-08-18 8:48 ` Maxime Ripard 2021-08-19 2:40 ` Samuel Holland 2021-08-19 2:40 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 07/17] pinctrl: sunxi: add support for R329 CPUX pin controller Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-11 9:23 ` Linus Walleij 2021-08-11 9:23 ` Linus Walleij 2021-08-11 9:23 ` Linus Walleij 2021-08-18 8:48 ` Maxime Ripard 2021-08-18 8:48 ` Maxime Ripard 2021-08-19 3:09 ` Samuel Holland [this message] 2021-08-19 3:09 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 08/17] pinctrl: sunxi: add support for R329 R-PIO " Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 8:52 ` Maxime Ripard 2021-08-18 8:52 ` Maxime Ripard 2021-08-19 3:22 ` Samuel Holland 2021-08-19 3:22 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 09/17] dt-bindings: clock: sunxi-ng: add compatibles for R329 CCUs Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:41 ` Rob Herring 2021-08-06 21:41 ` Rob Herring 2021-08-02 6:22 ` [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 9:03 ` Icenowy Zheng 2021-08-02 9:03 ` Icenowy Zheng 2021-08-02 9:52 ` Icenowy Zheng 2021-08-02 9:52 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-18 8:50 ` Maxime Ripard 2021-08-18 8:50 ` Maxime Ripard 2021-08-20 0:55 ` Samuel Holland 2021-08-20 0:55 ` Samuel Holland 2021-08-20 4:34 ` Jernej Škrabec 2021-08-20 4:34 ` Jernej Škrabec 2021-08-25 14:50 ` Maxime Ripard 2021-08-25 14:50 ` Maxime Ripard 2021-08-25 15:03 ` Jernej Škrabec 2021-08-25 15:03 ` Jernej Škrabec 2021-08-25 15:37 ` Maxime Ripard 2021-08-25 15:37 ` Maxime Ripard 2021-08-26 0:20 ` Samuel Holland 2021-08-26 0:20 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 11/17] clk: sunxi-ng: add support for Allwinner R329 CCU Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-20 2:41 ` Samuel Holland 2021-08-20 2:41 ` Samuel Holland 2021-08-20 3:52 ` Icenowy Zheng 2021-08-20 3:52 ` Icenowy Zheng 2021-08-25 14:54 ` Maxime Ripard 2021-08-25 14:54 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 12/17] dt-bindings: mmc: sunxi-mmc: add R329 MMC compatible string Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-18 8:47 ` Maxime Ripard 2021-08-18 8:47 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 13/17] mmc: sunxi: add support for R329 MMC controllers Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 8:47 ` Maxime Ripard 2021-08-18 8:47 ` Maxime Ripard 2021-08-20 2:43 ` Samuel Holland 2021-08-20 2:43 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 14/17] dt-bindings: arm: sunxi: add compatible strings for Sipeed MaixSense Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:43 ` Rob Herring 2021-08-06 21:43 ` Rob Herring 2021-08-18 9:03 ` Maxime Ripard 2021-08-18 9:03 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 9:01 ` Maxime Ripard 2021-08-18 9:01 ` Maxime Ripard 2021-08-18 9:15 ` Icenowy Zheng 2021-08-18 9:15 ` Icenowy Zheng 2021-08-19 2:32 ` Samuel Holland 2021-08-19 2:32 ` Samuel Holland 2021-08-20 3:06 ` Samuel Holland 2021-08-20 3:06 ` Samuel Holland 2021-08-25 15:00 ` Maxime Ripard 2021-08-25 15:00 ` Maxime Ripard 2021-08-20 2:59 ` Samuel Holland 2021-08-20 2:59 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 16/17] arm64: allwinner: dts: r329: add DTSI file for Sipeed Maix IIA Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 6:22 ` [PATCH 17/17] arm64: allwinner: dts: r329: add support for Sipeed MaixSense Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-10 11:04 ` [PATCH 00/17] Basical Allwinner R329 support Ulf Hansson 2021-08-10 11:04 ` Ulf Hansson 2021-08-10 11:04 ` Ulf Hansson
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