From: Icenowy Zheng <icenowy@sipeed.com> To: Maxime Ripard <maxime@cerno.tech> Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Ulf Hansson <ulf.hansson@linaro.org>, Linus Walleij <linus.walleij@linaro.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Andre Przywara <andre.przywara@arm.com>, Samuel Holland <samuel@sholland.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Date: Wed, 18 Aug 2021 17:15:05 +0800 [thread overview] Message-ID: <74F51516-2470-4A49-972B-E19D8EDD9A3D@sipeed.com> (raw) In-Reply-To: <20210818090139.rllz4fvvq3pzdkls@gilmour> 于 2021年8月18日 GMT+08:00 下午5:01:39, Maxime Ripard <maxime@cerno.tech> 写到: >On Mon, Aug 02, 2021 at 02:22:10PM +0800, Icenowy Zheng wrote: >> Allwinner R329 is a new SoC focused on smart audio devices. >> >> Add a DTSI file for it. >> >> Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> >> --- >> .../arm64/boot/dts/allwinner/sun50i-r329.dtsi | 244 ++++++++++++++++++ >> 1 file changed, 244 insertions(+) >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi >> new file mode 100644 >> index 000000000000..bfefa2b734b0 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi >> @@ -0,0 +1,244 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +// Copyright (c) 2021 Sipeed >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/sun50i-r329-ccu.h> >> +#include <dt-bindings/reset/sun50i-r329-ccu.h> >> +#include <dt-bindings/clock/sun50i-r329-r-ccu.h> >> +#include <dt-bindings/reset/sun50i-r329-r-ccu.h> >> + >> +/ { >> + interrupt-parent = <&gic>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a53"; >> + device_type = "cpu"; >> + reg = <0>; >> + enable-method = "psci"; >> + }; >> + >> + cpu1: cpu@1 { >> + compatible = "arm,cortex-a53"; >> + device_type = "cpu"; >> + reg = <1>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + osc24M: osc24M_clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "osc24M"; >> + }; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + arm,no-tick-in-suspend; >> + interrupts = <GIC_PPI 13 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 14 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + >> + soc { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + pio: pinctrl@2000400 { >> + compatible = "allwinner,sun50i-r329-pinctrl"; >> + reg = <0x02000400 0x400>; >> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; >> + clock-names = "apb", "hosc", "losc"; >> + gpio-controller; >> + #gpio-cells = <3>; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + >> + uart0_pb_pins: uart0-pb-pins { >> + pins = "PB4", "PB5"; >> + function = "uart0"; >> + }; >> + >> + mmc0_pf_pins: mmc0-pf-pins { >> + pins = "PF0", "PF1", "PF2", >> + "PF3", "PF4", "PF5"; >> + function = "mmc0"; >> + }; >> + >> + mmc1_clk_pg0: mmc1-clk-pg0 { >> + pins = "PG0"; >> + function = "mmc1_clk"; >> + }; > >Argh, of course it was bound to happen :) > >Make sure your DT pass validation though, all your mmc1 node names will report errors. > >> + >> + mmc1_cmd_pg1: mmc1-clk-pg1 { > >s/clk/cmd/ ? > >> + pins = "PG1"; >> + function = "mmc1_cmd"; >> + }; >> + >> + mmc1_d0_pg2: mmc1-clk-pg2 { > >s/clk/d0/ > >> + pins = "PG2"; >> + function = "mmc1_d0"; >> + }; >> + >> + mmc1_d1_pg3: mmc1-clk-pg3 { > >s/clk/d1/ > >> + pins = "PG3"; >> + function = "mmc1_d1"; >> + }; >> + >> + mmc1_d2_pg4: mmc1-clk-pg4 { > >s/clk/d2/ > >> + pins = "PG4"; >> + function = "mmc1_d2"; >> + }; >> + >> + mmc1_d3_pg5: mmc1-clk-pg5 { > >s/clk/d3/ > >> + pins = "PG5"; >> + function = "mmc1_d3"; >> + }; >> + }; >> + >> + ccu: clock@2001000 { >> + compatible = "allwinner,sun50i-r329-ccu"; >> + reg = <0x02001000 0x1000>; >> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; >> + clock-names = "hosc", "losc", "iosc"; > >Do we have a clock tree for the RTC? Is it the same than the H616? Nope, it's the same with H6 because of external LOSC crystal is possible. (Although production M2A SoMs has it NC for cost control.) What's the same between H616 and R329 is linear day storage of the timekeeping part, not the clock part. > >Maxime -- 使用 K-9 Mail 发送自我的Android设备。 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Icenowy Zheng <icenowy@sipeed.com> To: Maxime Ripard <maxime@cerno.tech> Cc: Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>, Ulf Hansson <ulf.hansson@linaro.org>, Linus Walleij <linus.walleij@linaro.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Andre Przywara <andre.przywara@arm.com>, Samuel Holland <samuel@sholland.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Date: Wed, 18 Aug 2021 17:15:05 +0800 [thread overview] Message-ID: <74F51516-2470-4A49-972B-E19D8EDD9A3D@sipeed.com> (raw) In-Reply-To: <20210818090139.rllz4fvvq3pzdkls@gilmour> 于 2021年8月18日 GMT+08:00 下午5:01:39, Maxime Ripard <maxime@cerno.tech> 写到: >On Mon, Aug 02, 2021 at 02:22:10PM +0800, Icenowy Zheng wrote: >> Allwinner R329 is a new SoC focused on smart audio devices. >> >> Add a DTSI file for it. >> >> Signed-off-by: Icenowy Zheng <icenowy@sipeed.com> >> --- >> .../arm64/boot/dts/allwinner/sun50i-r329.dtsi | 244 ++++++++++++++++++ >> 1 file changed, 244 insertions(+) >> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi >> new file mode 100644 >> index 000000000000..bfefa2b734b0 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-r329.dtsi >> @@ -0,0 +1,244 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +// Copyright (c) 2021 Sipeed >> + >> +#include <dt-bindings/interrupt-controller/arm-gic.h> >> +#include <dt-bindings/clock/sun50i-r329-ccu.h> >> +#include <dt-bindings/reset/sun50i-r329-ccu.h> >> +#include <dt-bindings/clock/sun50i-r329-r-ccu.h> >> +#include <dt-bindings/reset/sun50i-r329-r-ccu.h> >> + >> +/ { >> + interrupt-parent = <&gic>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a53"; >> + device_type = "cpu"; >> + reg = <0>; >> + enable-method = "psci"; >> + }; >> + >> + cpu1: cpu@1 { >> + compatible = "arm,cortex-a53"; >> + device_type = "cpu"; >> + reg = <1>; >> + enable-method = "psci"; >> + }; >> + }; >> + >> + osc24M: osc24M_clk { >> + #clock-cells = <0>; >> + compatible = "fixed-clock"; >> + clock-frequency = <24000000>; >> + clock-output-names = "osc24M"; >> + }; >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + arm,no-tick-in-suspend; >> + interrupts = <GIC_PPI 13 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 14 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 11 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, >> + <GIC_PPI 10 >> + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; >> + }; >> + >> + soc { >> + compatible = "simple-bus"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + ranges; >> + >> + pio: pinctrl@2000400 { >> + compatible = "allwinner,sun50i-r329-pinctrl"; >> + reg = <0x02000400 0x400>; >> + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; >> + clock-names = "apb", "hosc", "losc"; >> + gpio-controller; >> + #gpio-cells = <3>; >> + interrupt-controller; >> + #interrupt-cells = <3>; >> + >> + uart0_pb_pins: uart0-pb-pins { >> + pins = "PB4", "PB5"; >> + function = "uart0"; >> + }; >> + >> + mmc0_pf_pins: mmc0-pf-pins { >> + pins = "PF0", "PF1", "PF2", >> + "PF3", "PF4", "PF5"; >> + function = "mmc0"; >> + }; >> + >> + mmc1_clk_pg0: mmc1-clk-pg0 { >> + pins = "PG0"; >> + function = "mmc1_clk"; >> + }; > >Argh, of course it was bound to happen :) > >Make sure your DT pass validation though, all your mmc1 node names will report errors. > >> + >> + mmc1_cmd_pg1: mmc1-clk-pg1 { > >s/clk/cmd/ ? > >> + pins = "PG1"; >> + function = "mmc1_cmd"; >> + }; >> + >> + mmc1_d0_pg2: mmc1-clk-pg2 { > >s/clk/d0/ > >> + pins = "PG2"; >> + function = "mmc1_d0"; >> + }; >> + >> + mmc1_d1_pg3: mmc1-clk-pg3 { > >s/clk/d1/ > >> + pins = "PG3"; >> + function = "mmc1_d1"; >> + }; >> + >> + mmc1_d2_pg4: mmc1-clk-pg4 { > >s/clk/d2/ > >> + pins = "PG4"; >> + function = "mmc1_d2"; >> + }; >> + >> + mmc1_d3_pg5: mmc1-clk-pg5 { > >s/clk/d3/ > >> + pins = "PG5"; >> + function = "mmc1_d3"; >> + }; >> + }; >> + >> + ccu: clock@2001000 { >> + compatible = "allwinner,sun50i-r329-ccu"; >> + reg = <0x02001000 0x1000>; >> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; >> + clock-names = "hosc", "losc", "iosc"; > >Do we have a clock tree for the RTC? Is it the same than the H616? Nope, it's the same with H6 because of external LOSC crystal is possible. (Although production M2A SoMs has it NC for cost control.) What's the same between H616 and R329 is linear day storage of the timekeeping part, not the clock part. > >Maxime -- 使用 K-9 Mail 发送自我的Android设备。
next prev parent reply other threads:[~2021-08-18 9:19 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-02 6:21 [PATCH 00/17] Basical Allwinner R329 support Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 01/17] rtc: sun6i: Fix time overflow handling Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 02/17] rtc: sun6i: Add support for linear day storage Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 03/17] rtc: sun6i: Add support for broken-down alarm registers Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 04/17] dt-bindings: rtc: sun6i: add compatible string for R329 RTC Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-06 21:39 ` Rob Herring 2021-08-06 21:39 ` Rob Herring 2021-08-02 6:22 ` [PATCH 05/17] rtc: sun6i: add support " Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 6:22 ` [PATCH 06/17] dt-bindings: pinctrl: document Allwinner R329 PIO and R-PIO Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:40 ` Rob Herring 2021-08-06 21:40 ` Rob Herring 2021-08-18 8:48 ` Maxime Ripard 2021-08-18 8:48 ` Maxime Ripard 2021-08-19 2:40 ` Samuel Holland 2021-08-19 2:40 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 07/17] pinctrl: sunxi: add support for R329 CPUX pin controller Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-11 9:23 ` Linus Walleij 2021-08-11 9:23 ` Linus Walleij 2021-08-11 9:23 ` Linus Walleij 2021-08-18 8:48 ` Maxime Ripard 2021-08-18 8:48 ` Maxime Ripard 2021-08-19 3:09 ` Samuel Holland 2021-08-19 3:09 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 08/17] pinctrl: sunxi: add support for R329 R-PIO " Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 8:52 ` Maxime Ripard 2021-08-18 8:52 ` Maxime Ripard 2021-08-19 3:22 ` Samuel Holland 2021-08-19 3:22 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 09/17] dt-bindings: clock: sunxi-ng: add compatibles for R329 CCUs Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:41 ` Rob Herring 2021-08-06 21:41 ` Rob Herring 2021-08-02 6:22 ` [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 9:03 ` Icenowy Zheng 2021-08-02 9:03 ` Icenowy Zheng 2021-08-02 9:52 ` Icenowy Zheng 2021-08-02 9:52 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-18 8:50 ` Maxime Ripard 2021-08-18 8:50 ` Maxime Ripard 2021-08-20 0:55 ` Samuel Holland 2021-08-20 0:55 ` Samuel Holland 2021-08-20 4:34 ` Jernej Škrabec 2021-08-20 4:34 ` Jernej Škrabec 2021-08-25 14:50 ` Maxime Ripard 2021-08-25 14:50 ` Maxime Ripard 2021-08-25 15:03 ` Jernej Škrabec 2021-08-25 15:03 ` Jernej Škrabec 2021-08-25 15:37 ` Maxime Ripard 2021-08-25 15:37 ` Maxime Ripard 2021-08-26 0:20 ` Samuel Holland 2021-08-26 0:20 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 11/17] clk: sunxi-ng: add support for Allwinner R329 CCU Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-20 2:41 ` Samuel Holland 2021-08-20 2:41 ` Samuel Holland 2021-08-20 3:52 ` Icenowy Zheng 2021-08-20 3:52 ` Icenowy Zheng 2021-08-25 14:54 ` Maxime Ripard 2021-08-25 14:54 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 12/17] dt-bindings: mmc: sunxi-mmc: add R329 MMC compatible string Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-18 8:47 ` Maxime Ripard 2021-08-18 8:47 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 13/17] mmc: sunxi: add support for R329 MMC controllers Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 8:47 ` Maxime Ripard 2021-08-18 8:47 ` Maxime Ripard 2021-08-20 2:43 ` Samuel Holland 2021-08-20 2:43 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 14/17] dt-bindings: arm: sunxi: add compatible strings for Sipeed MaixSense Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:43 ` Rob Herring 2021-08-06 21:43 ` Rob Herring 2021-08-18 9:03 ` Maxime Ripard 2021-08-18 9:03 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 9:01 ` Maxime Ripard 2021-08-18 9:01 ` Maxime Ripard 2021-08-18 9:15 ` Icenowy Zheng [this message] 2021-08-18 9:15 ` Icenowy Zheng 2021-08-19 2:32 ` Samuel Holland 2021-08-19 2:32 ` Samuel Holland 2021-08-20 3:06 ` Samuel Holland 2021-08-20 3:06 ` Samuel Holland 2021-08-25 15:00 ` Maxime Ripard 2021-08-25 15:00 ` Maxime Ripard 2021-08-20 2:59 ` Samuel Holland 2021-08-20 2:59 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 16/17] arm64: allwinner: dts: r329: add DTSI file for Sipeed Maix IIA Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 6:22 ` [PATCH 17/17] arm64: allwinner: dts: r329: add support for Sipeed MaixSense Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-10 11:04 ` [PATCH 00/17] Basical Allwinner R329 support Ulf Hansson 2021-08-10 11:04 ` Ulf Hansson 2021-08-10 11:04 ` Ulf Hansson
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