From: "Jernej Škrabec" <jernej.skrabec@gmail.com> To: Maxime Ripard <maxime@cerno.tech> Cc: Icenowy Zheng <icenowy@sipeed.com>, Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Ulf Hansson <ulf.hansson@linaro.org>, Linus Walleij <linus.walleij@linaro.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Andre Przywara <andre.przywara@arm.com>, Samuel Holland <samuel@sholland.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Date: Wed, 25 Aug 2021 17:03:30 +0200 [thread overview] Message-ID: <3221818.pD4rYpbbZ1@jernej-laptop> (raw) In-Reply-To: <20210825145027.ixc7wnh3x5w6wzny@gilmour> Dne sreda, 25. avgust 2021 ob 16:50:27 CEST je Maxime Ripard napisal(a): > Hi, > > On Fri, Aug 20, 2021 at 06:34:38AM +0200, Jernej Škrabec wrote: > > > > +static void __init sun50i_r329_r_ccu_setup(struct device_node *node) > > > > +{ > > > > + void __iomem *reg; > > > > + u32 val; > > > > + int i; > > > > + > > > > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > > > > + if (IS_ERR(reg)) { > > > > + pr_err("%pOF: Could not map clock registers\n", node); > > > > + return; > > > > + } > > > > + > > > > + /* Enable the lock bits and the output enable bits on all PLLs */ > > > > + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { > > > > + val = readl(reg + pll_regs[i]); > > > > + val |= BIT(29) | BIT(27); > > > > + writel(val, reg + pll_regs[i]); > > > > + } > > > > + > > > > + /* > > > > + * Force the I/O dividers of PLL-AUDIO1 to reset default value > > > > + * > > > > + * See the comment before pll-audio1 definition for the reason. > > > > + */ > > > > + > > > > + val = readl(reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > + val &= ~BIT(1); > > > > + val |= BIT(0); > > > > + writel(val, reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > + > > > > + i = sunxi_ccu_probe(node, reg, &sun50i_r329_r_ccu_desc); > > > > + if (i) > > > > + pr_err("%pOF: probing clocks fails: %d\n", node, i); > > > > +} > > > > + > > > > +CLK_OF_DECLARE(sun50i_r329_r_ccu, "allwinner,sun50i-r329-r-ccu", > > > > + sun50i_r329_r_ccu_setup); > > > > > > Please make this a platform driver. There is no particular reason why it > > > needs to be an early OF clock provider. > > > > Why? It's good to have it as early clock provider. It has no dependencies > > and other drivers that depends on it, like IR, can be deferred, if this > > is loaded later. > > No, Samuel is right, we should make them regular drivers as much as we > can. > > The reason we had CLK_OF_DECLARE in the first place is that timers > usually have a parent clock, and you need the timers before the device > model is set up. > > Fortunately for us, since the A20, the architected timers don't require > a parent clock from us, and we can thus boot up fine. There are other timers. A lot of SoCs, newer than A20 (like H6), have High Speed Timer, which requires parent clock to be enabled. We just choose not to add node for it to DT, even if it's there and driver already exists. Best regards, Jernej > > Since the dependencies are minimal, it should probe fairly early and > with the on-demand probing from the device links you might not even tell > the difference for most consumers. > > Maxime
WARNING: multiple messages have this Message-ID (diff)
From: "Jernej Škrabec" <jernej.skrabec@gmail.com> To: Maxime Ripard <maxime@cerno.tech> Cc: Icenowy Zheng <icenowy@sipeed.com>, Rob Herring <robh+dt@kernel.org>, Chen-Yu Tsai <wens@csie.org>, Ulf Hansson <ulf.hansson@linaro.org>, Linus Walleij <linus.walleij@linaro.org>, Alexandre Belloni <alexandre.belloni@bootlin.com>, Andre Przywara <andre.przywara@arm.com>, Samuel Holland <samuel@sholland.org>, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Date: Wed, 25 Aug 2021 17:03:30 +0200 [thread overview] Message-ID: <3221818.pD4rYpbbZ1@jernej-laptop> (raw) In-Reply-To: <20210825145027.ixc7wnh3x5w6wzny@gilmour> Dne sreda, 25. avgust 2021 ob 16:50:27 CEST je Maxime Ripard napisal(a): > Hi, > > On Fri, Aug 20, 2021 at 06:34:38AM +0200, Jernej Škrabec wrote: > > > > +static void __init sun50i_r329_r_ccu_setup(struct device_node *node) > > > > +{ > > > > + void __iomem *reg; > > > > + u32 val; > > > > + int i; > > > > + > > > > + reg = of_io_request_and_map(node, 0, of_node_full_name(node)); > > > > + if (IS_ERR(reg)) { > > > > + pr_err("%pOF: Could not map clock registers\n", node); > > > > + return; > > > > + } > > > > + > > > > + /* Enable the lock bits and the output enable bits on all PLLs */ > > > > + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { > > > > + val = readl(reg + pll_regs[i]); > > > > + val |= BIT(29) | BIT(27); > > > > + writel(val, reg + pll_regs[i]); > > > > + } > > > > + > > > > + /* > > > > + * Force the I/O dividers of PLL-AUDIO1 to reset default value > > > > + * > > > > + * See the comment before pll-audio1 definition for the reason. > > > > + */ > > > > + > > > > + val = readl(reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > + val &= ~BIT(1); > > > > + val |= BIT(0); > > > > + writel(val, reg + SUN50I_R329_PLL_AUDIO1_REG); > > > > + > > > > + i = sunxi_ccu_probe(node, reg, &sun50i_r329_r_ccu_desc); > > > > + if (i) > > > > + pr_err("%pOF: probing clocks fails: %d\n", node, i); > > > > +} > > > > + > > > > +CLK_OF_DECLARE(sun50i_r329_r_ccu, "allwinner,sun50i-r329-r-ccu", > > > > + sun50i_r329_r_ccu_setup); > > > > > > Please make this a platform driver. There is no particular reason why it > > > needs to be an early OF clock provider. > > > > Why? It's good to have it as early clock provider. It has no dependencies > > and other drivers that depends on it, like IR, can be deferred, if this > > is loaded later. > > No, Samuel is right, we should make them regular drivers as much as we > can. > > The reason we had CLK_OF_DECLARE in the first place is that timers > usually have a parent clock, and you need the timers before the device > model is set up. > > Fortunately for us, since the A20, the architected timers don't require > a parent clock from us, and we can thus boot up fine. There are other timers. A lot of SoCs, newer than A20 (like H6), have High Speed Timer, which requires parent clock to be enabled. We just choose not to add node for it to DT, even if it's there and driver already exists. Best regards, Jernej > > Since the dependencies are minimal, it should probe fairly early and > with the on-demand probing from the device links you might not even tell > the difference for most consumers. > > Maxime _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2021-08-25 15:03 UTC|newest] Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-08-02 6:21 [PATCH 00/17] Basical Allwinner R329 support Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 01/17] rtc: sun6i: Fix time overflow handling Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 02/17] rtc: sun6i: Add support for linear day storage Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 03/17] rtc: sun6i: Add support for broken-down alarm registers Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-02 6:21 ` [PATCH 04/17] dt-bindings: rtc: sun6i: add compatible string for R329 RTC Icenowy Zheng 2021-08-02 6:21 ` Icenowy Zheng 2021-08-06 21:39 ` Rob Herring 2021-08-06 21:39 ` Rob Herring 2021-08-02 6:22 ` [PATCH 05/17] rtc: sun6i: add support " Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 6:22 ` [PATCH 06/17] dt-bindings: pinctrl: document Allwinner R329 PIO and R-PIO Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:40 ` Rob Herring 2021-08-06 21:40 ` Rob Herring 2021-08-18 8:48 ` Maxime Ripard 2021-08-18 8:48 ` Maxime Ripard 2021-08-19 2:40 ` Samuel Holland 2021-08-19 2:40 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 07/17] pinctrl: sunxi: add support for R329 CPUX pin controller Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-11 9:23 ` Linus Walleij 2021-08-11 9:23 ` Linus Walleij 2021-08-11 9:23 ` Linus Walleij 2021-08-18 8:48 ` Maxime Ripard 2021-08-18 8:48 ` Maxime Ripard 2021-08-19 3:09 ` Samuel Holland 2021-08-19 3:09 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 08/17] pinctrl: sunxi: add support for R329 R-PIO " Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 8:52 ` Maxime Ripard 2021-08-18 8:52 ` Maxime Ripard 2021-08-19 3:22 ` Samuel Holland 2021-08-19 3:22 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 09/17] dt-bindings: clock: sunxi-ng: add compatibles for R329 CCUs Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:41 ` Rob Herring 2021-08-06 21:41 ` Rob Herring 2021-08-02 6:22 ` [PATCH 10/17] clk: sunxi=ng: add support for R329 R-CCU Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 9:03 ` Icenowy Zheng 2021-08-02 9:03 ` Icenowy Zheng 2021-08-02 9:52 ` Icenowy Zheng 2021-08-02 9:52 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-18 8:50 ` Maxime Ripard 2021-08-18 8:50 ` Maxime Ripard 2021-08-20 0:55 ` Samuel Holland 2021-08-20 0:55 ` Samuel Holland 2021-08-20 4:34 ` Jernej Škrabec 2021-08-20 4:34 ` Jernej Škrabec 2021-08-25 14:50 ` Maxime Ripard 2021-08-25 14:50 ` Maxime Ripard 2021-08-25 15:03 ` Jernej Škrabec [this message] 2021-08-25 15:03 ` Jernej Škrabec 2021-08-25 15:37 ` Maxime Ripard 2021-08-25 15:37 ` Maxime Ripard 2021-08-26 0:20 ` Samuel Holland 2021-08-26 0:20 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 11/17] clk: sunxi-ng: add support for Allwinner R329 CCU Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-20 2:41 ` Samuel Holland 2021-08-20 2:41 ` Samuel Holland 2021-08-20 3:52 ` Icenowy Zheng 2021-08-20 3:52 ` Icenowy Zheng 2021-08-25 14:54 ` Maxime Ripard 2021-08-25 14:54 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 12/17] dt-bindings: mmc: sunxi-mmc: add R329 MMC compatible string Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:42 ` Rob Herring 2021-08-06 21:42 ` Rob Herring 2021-08-18 8:47 ` Maxime Ripard 2021-08-18 8:47 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 13/17] mmc: sunxi: add support for R329 MMC controllers Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 8:47 ` Maxime Ripard 2021-08-18 8:47 ` Maxime Ripard 2021-08-20 2:43 ` Samuel Holland 2021-08-20 2:43 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 14/17] dt-bindings: arm: sunxi: add compatible strings for Sipeed MaixSense Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-06 21:43 ` Rob Herring 2021-08-06 21:43 ` Rob Herring 2021-08-18 9:03 ` Maxime Ripard 2021-08-18 9:03 ` Maxime Ripard 2021-08-02 6:22 ` [PATCH 15/17] arm64: allwinner: dts: add DTSI file for R329 SoC Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-18 9:01 ` Maxime Ripard 2021-08-18 9:01 ` Maxime Ripard 2021-08-18 9:15 ` Icenowy Zheng 2021-08-18 9:15 ` Icenowy Zheng 2021-08-19 2:32 ` Samuel Holland 2021-08-19 2:32 ` Samuel Holland 2021-08-20 3:06 ` Samuel Holland 2021-08-20 3:06 ` Samuel Holland 2021-08-25 15:00 ` Maxime Ripard 2021-08-25 15:00 ` Maxime Ripard 2021-08-20 2:59 ` Samuel Holland 2021-08-20 2:59 ` Samuel Holland 2021-08-02 6:22 ` [PATCH 16/17] arm64: allwinner: dts: r329: add DTSI file for Sipeed Maix IIA Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-02 6:22 ` [PATCH 17/17] arm64: allwinner: dts: r329: add support for Sipeed MaixSense Icenowy Zheng 2021-08-02 6:22 ` Icenowy Zheng 2021-08-10 11:04 ` [PATCH 00/17] Basical Allwinner R329 support Ulf Hansson 2021-08-10 11:04 ` Ulf Hansson 2021-08-10 11:04 ` Ulf Hansson
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