[PATCH 0/7] Add minimal boot support for IPQ9574

[PATCH 0/7] Add minimal boot support for IPQ9574

[devi priya]

The IPQ9574 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.

This series adds minimal board boot support for ipq9574-al02-c7 board

POOVENDHAN SELVARAJ (1):
  arm64: dts: Add ipq9574 SoC and AL02 board support

devi priya (6):
  dt-bindings: arm64: ipq9574: Add binding descriptions for clock and
    reset
  clk: qcom: Add Global Clock Controller driver for IPQ9574
  dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings
  pinctrl: qcom: Add IPQ9574 pinctrl driver
  dt-bindings: qcom: Add ipq9574 bindings
  arm64: defconfig: Enable IPQ9574 SoC base configs

 .../devicetree/bindings/arm/qcom.yaml         |    7 +
 .../bindings/clock/qcom,gcc-other.yaml        |    4 +
 .../devicetree/bindings/clock/qcom,gcc.yaml   |    9 +-
 .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   |  129 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts  |   69 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         |  318 ++
 arch/arm64/configs/defconfig                  |    2 +
 drivers/clk/qcom/Kconfig                      |    8 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/gcc-ipq9574.c                | 4706 +++++++++++++++++
 drivers/pinctrl/qcom/Kconfig                  |   10 +
 drivers/pinctrl/qcom/Makefile                 |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq9574.c        | 1003 ++++
 include/dt-bindings/clock/qcom,gcc-ipq9574.h  |  226 +
 include/dt-bindings/reset/qcom,gcc-ipq9574.h  |  164 +
 16 files changed, 6657 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h


base-commit: 1fe4fd6f5cad346e598593af36caeadc4f5d4fa9
-- 
2.17.1


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 0/7] Add minimal boot support for IPQ9574

[devi priya]

The IPQ9574 is Qualcomm's 802.11ax SoC for Routers,
Gateways and Access Points.

This series adds minimal board boot support for ipq9574-al02-c7 board

POOVENDHAN SELVARAJ (1):
  arm64: dts: Add ipq9574 SoC and AL02 board support

devi priya (6):
  dt-bindings: arm64: ipq9574: Add binding descriptions for clock and
    reset
  clk: qcom: Add Global Clock Controller driver for IPQ9574
  dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings
  pinctrl: qcom: Add IPQ9574 pinctrl driver
  dt-bindings: qcom: Add ipq9574 bindings
  arm64: defconfig: Enable IPQ9574 SoC base configs

 .../devicetree/bindings/arm/qcom.yaml         |    7 +
 .../bindings/clock/qcom,gcc-other.yaml        |    4 +
 .../devicetree/bindings/clock/qcom,gcc.yaml   |    9 +-
 .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   |  129 +
 arch/arm64/boot/dts/qcom/Makefile             |    1 +
 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts  |   69 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         |  318 ++
 arch/arm64/configs/defconfig                  |    2 +
 drivers/clk/qcom/Kconfig                      |    8 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/gcc-ipq9574.c                | 4706 +++++++++++++++++
 drivers/pinctrl/qcom/Kconfig                  |   10 +
 drivers/pinctrl/qcom/Makefile                 |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq9574.c        | 1003 ++++
 include/dt-bindings/clock/qcom,gcc-ipq9574.h  |  226 +
 include/dt-bindings/reset/qcom,gcc-ipq9574.h  |  164 +
 16 files changed, 6657 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
 create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h


base-commit: 1fe4fd6f5cad346e598593af36caeadc4f5d4fa9
-- 
2.17.1

[PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[devi priya]

Adding support for the global clock controller found on
IPQ9574 based devices

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 .../bindings/clock/qcom,gcc-other.yaml        |   4 +
 .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
 include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
 include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
 4 files changed, 402 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index 2e8acca64af1..cc563d640336 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -18,6 +18,8 @@ description: |
     include/dt-bindings/clock/qcom,gcc-ipq4019.h
     include/dt-bindings/clock/qcom,gcc-ipq6018.h
     include/dt-bindings/reset/qcom,gcc-ipq6018.h
+    include/dt-bindings/clock/qcom,gcc-ipq9574.h
+    include/dt-bindings/reset/qcom,gcc-ipq9574.h
     include/dt-bindings/clock/qcom,gcc-msm8953.h
     include/dt-bindings/clock/qcom,gcc-mdm9607.h
     include/dt-bindings/clock/qcom,gcc-mdm9615.h
@@ -34,6 +36,8 @@ properties:
       - qcom,gcc-mdm9607
       - qcom,gcc-msm8953
       - qcom,gcc-mdm9615
+      - qcom,gcc-ipq9574
+
 
 required:
   - compatible
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index 7129fbcf2b6c..5a71268538e6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -24,6 +24,14 @@ properties:
   '#power-domain-cells':
     const: 1
 
+  clocks:
+    minItems: 1
+    maxItems: 8
+
+  clock-names:
+    minItems: 1
+    maxItems: 8
+
   reg:
     maxItems: 1
 
@@ -35,7 +43,6 @@ required:
   - reg
   - '#clock-cells'
   - '#reset-cells'
-  - '#power-domain-cells'
 
 additionalProperties: true
 
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq9574.h b/include/dt-bindings/clock/qcom,gcc-ipq9574.h
new file mode 100644
index 000000000000..312d513305ec
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq9574.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018-2022 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9048_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_9048_H
+
+#define GPLL0_MAIN					0
+#define GPLL0						1
+#define GPLL2_MAIN					2
+#define GPLL2						3
+#define GPLL4_MAIN					4
+#define GPLL4						5
+#define GCC_SLEEP_CLK_SRC				6
+#define APSS_AHB_CLK_SRC				7
+#define APSS_AXI_CLK_SRC				8
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			9
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			10
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			11
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			12
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC			13
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC			14
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC			15
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC			16
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC			17
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC			18
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC			19
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC			20
+#define BLSP1_UART1_APPS_CLK_SRC			21
+#define BLSP1_UART2_APPS_CLK_SRC			22
+#define BLSP1_UART3_APPS_CLK_SRC			23
+#define BLSP1_UART4_APPS_CLK_SRC			24
+#define BLSP1_UART5_APPS_CLK_SRC			25
+#define BLSP1_UART6_APPS_CLK_SRC			26
+#define GCC_APSS_AHB_CLK				27
+#define GCC_APSS_AXI_CLK				28
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			29
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			30
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			31
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			32
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK			33
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK			34
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK			35
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK			36
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK			37
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK			38
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK			39
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK			40
+#define GCC_BLSP1_UART1_APPS_CLK			41
+#define GCC_BLSP1_UART2_APPS_CLK			42
+#define GCC_BLSP1_UART3_APPS_CLK			43
+#define GCC_BLSP1_UART4_APPS_CLK			44
+#define GCC_BLSP1_UART5_APPS_CLK			45
+#define GCC_BLSP1_UART6_APPS_CLK			46
+#define PCIE0_AXI_M_CLK_SRC				47
+#define GCC_PCIE0_AXI_M_CLK				48
+#define PCIE1_AXI_M_CLK_SRC				49
+#define GCC_PCIE1_AXI_M_CLK				50
+#define PCIE2_AXI_M_CLK_SRC				51
+#define GCC_PCIE2_AXI_M_CLK				52
+#define PCIE3_AXI_M_CLK_SRC				53
+#define GCC_PCIE3_AXI_M_CLK				54
+#define PCIE0_AXI_S_CLK_SRC				55
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK			56
+#define GCC_PCIE0_AXI_S_CLK				57
+#define PCIE1_AXI_S_CLK_SRC				58
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK			59
+#define GCC_PCIE1_AXI_S_CLK				60
+#define PCIE2_AXI_S_CLK_SRC				61
+#define GCC_PCIE2_AXI_S_BRIDGE_CLK			62
+#define GCC_PCIE2_AXI_S_CLK				63
+#define PCIE3_AXI_S_CLK_SRC				64
+#define GCC_PCIE3_AXI_S_BRIDGE_CLK			65
+#define GCC_PCIE3_AXI_S_CLK				66
+#define PCIE0_PIPE_CLK_SRC				67
+#define PCIE1_PIPE_CLK_SRC				68
+#define PCIE2_PIPE_CLK_SRC				69
+#define PCIE3_PIPE_CLK_SRC				70
+#define PCIE_AUX_CLK_SRC				71
+#define GCC_PCIE0_AUX_CLK				72
+#define GCC_PCIE1_AUX_CLK				73
+#define GCC_PCIE2_AUX_CLK				74
+#define GCC_PCIE3_AUX_CLK				75
+#define PCIE0_RCHNG_CLK_SRC				76
+#define GCC_PCIE0_RCHNG_CLK				77
+#define PCIE1_RCHNG_CLK_SRC				78
+#define GCC_PCIE1_RCHNG_CLK				79
+#define PCIE2_RCHNG_CLK_SRC				80
+#define GCC_PCIE2_RCHNG_CLK				81
+#define PCIE3_RCHNG_CLK_SRC				82
+#define GCC_PCIE3_RCHNG_CLK				83
+#define GCC_PCIE0_AHB_CLK				84
+#define GCC_PCIE1_AHB_CLK				85
+#define GCC_PCIE2_AHB_CLK				86
+#define GCC_PCIE3_AHB_CLK				87
+#define USB0_AUX_CLK_SRC				88
+#define GCC_USB0_AUX_CLK				89
+#define USB0_MASTER_CLK_SRC				90
+#define GCC_USB0_MASTER_CLK				91
+#define GCC_SNOC_USB_CLK				92
+#define GCC_ANOC_USB_AXI_CLK				93
+#define USB0_MOCK_UTMI_CLK_SRC				94
+#define USB0_MOCK_UTMI_DIV_CLK_SRC			95
+#define GCC_USB0_MOCK_UTMI_CLK				96
+#define USB0_PIPE_CLK_SRC				97
+#define GCC_USB0_PHY_CFG_AHB_CLK			98
+#define SDCC1_APPS_CLK_SRC				99
+#define GCC_SDCC1_APPS_CLK				100
+#define SDCC1_ICE_CORE_CLK_SRC				101
+#define GCC_SDCC1_ICE_CORE_CLK				102
+#define GCC_SDCC1_AHB_CLK				103
+#define PCNOC_BFDCD_CLK_SRC				104
+#define GCC_NSSCFG_CLK					105
+#define GCC_NSSNOC_NSSCC_CLK				106
+#define GCC_NSSCC_CLK					107
+#define GCC_NSSNOC_PCNOC_1_CLK				108
+#define GCC_QDSS_DAP_AHB_CLK				109
+#define GCC_QDSS_CFG_AHB_CLK				110
+#define GCC_SNOC_PCNOC_AHB_CLK				111
+#define GCC_ANOC_PCNOC_AHB_CLK				112
+#define GCC_QPIC_AHB_CLK				113
+#define GCC_QPIC_CLK					114
+#define GCC_BLSP1_AHB_CLK				115
+#define GCC_MDIO_AHB_CLK				116
+#define GCC_PRNG_AHB_CLK				117
+#define GCC_UNIPHY0_AHB_CLK				118
+#define GCC_UNIPHY1_AHB_CLK				119
+#define GCC_UNIPHY2_AHB_CLK				120
+#define GCC_CMN_12GPLL_AHB_CLK				121
+#define GCC_CMN_12GPLL_APU_CLK				122
+#define SYSTEM_NOC_BFDCD_CLK_SRC			123
+#define GCC_NSSNOC_SNOC_CLK				124
+#define GCC_NSSNOC_SNOC_1_CLK				125
+#define GCC_QDSS_ETR_USB_CLK				126
+#define GCC_SYS_NOC_AXI_CLK				127
+#define GCC_ANOC0_AXI_CLK				128
+#define GCC_ANOC1_AXI_CLK				129
+#define GCC_ANOC0_TBU_CLK				130
+#define GCC_ANOC1_TBU_CLK				131
+#define GCC_MEM_NOC_SNOC_AXI_CLK			132
+#define GCC_IMEM_AXI_CLK				133
+#define WCSS_AHB_CLK_SRC				134
+#define GCC_Q6_AHB_CLK					135
+#define GCC_Q6_AHB_S_CLK				136
+#define GCC_WCSS_ECAHB_CLK				137
+#define GCC_WCSS_ACMT_CLK				138
+#define GCC_SYS_NOC_WCSS_AHB_CLK			139
+#define WCSS_AXI_M_CLK_SRC				140
+#define GCC_ANOC_WCSS_AXI_M_CLK				141
+#define QDSS_AT_CLK_SRC					142
+#define GCC_Q6SS_ATBM_CLK				143
+#define GCC_WCSS_DBG_IFC_ATB_CLK			144
+#define GCC_NSSNOC_ATB_CLK				145
+#define GCC_QDSS_AT_CLK					146
+#define GCC_SYS_NOC_AT_CLK				147
+#define GCC_PCNOC_AT_CLK				148
+#define GCC_USB0_EUD_AT_CLK				149
+#define GCC_QDSS_EUD_AT_CLK				150
+#define QDSS_STM_CLK_SRC				151
+#define GCC_QDSS_STM_CLK				152
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK			153
+#define QDSS_TRACECLKIN_CLK_SRC				154
+#define GCC_QDSS_TRACECLKIN_CLK				155
+#define QDSS_TSCTR_CLK_SRC				156
+#define GCC_Q6_TSCTR_1TO2_CLK				157
+#define GCC_WCSS_DBG_IFC_NTS_CLK			158
+#define GCC_QDSS_TSCTR_DIV2_CLK				159
+#define GCC_QDSS_TS_CLK					160
+#define GCC_SNOC_TS_CLK					161
+#define GCC_MEM_NOC_TS_CLK				162
+#define GCC_QDSS_TSCTR_DIV4_CLK				163
+#define GCC_NSS_TS_CLK					164
+#define GCC_QDSS_TSCTR_DIV8_CLK				165
+#define GCC_PCNOC_TS_CLK				166
+#define GCC_QDSS_TSCTR_DIV16_CLK			167
+#define GCC_Q6SS_PCLKDBG_CLK				168
+#define GCC_Q6SS_TRIG_CLK				169
+#define GCC_WCSS_DBG_IFC_APB_CLK			170
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK			171
+#define GCC_QDSS_DAP_CLK				172
+#define GCC_QDSS_APB2JTAG_CLK				173
+#define GCC_QDSS_TSCTR_DIV3_CLK				174
+#define QPIC_IO_MACRO_CLK_SRC				175
+#define GCC_QPIC_IO_MACRO_CLK				176
+#define Q6_AXI_CLK_SRC					177
+#define GCC_Q6_AXIM_CLK					178
+#define GCC_WCSS_Q6_TBU_CLK				179
+#define GCC_MEM_NOC_Q6_AXI_CLK				180
+#define Q6_AXIM2_CLK_SRC				181
+#define NSSNOC_MEMNOC_BFDCD_CLK_SRC			182
+#define GCC_NSSNOC_MEMNOC_CLK				183
+#define GCC_NSSNOC_MEM_NOC_1_CLK			184
+#define GCC_NSS_TBU_CLK					185
+#define GCC_MEM_NOC_NSSNOC_CLK				186
+#define LPASS_AXIM_CLK_SRC				187
+#define LPASS_SWAY_CLK_SRC				188
+#define ADSS_PWM_CLK_SRC				189
+#define GCC_ADSS_PWM_CLK				190
+#define GP1_CLK_SRC					191
+#define GP2_CLK_SRC					192
+#define GP3_CLK_SRC					193
+#define DDRSS_SMS_SLOW_CLK_SRC				194
+#define GCC_XO_CLK_SRC					195
+#define GCC_XO_CLK					196
+#define GCC_NSSNOC_QOSGEN_REF_CLK			197
+#define GCC_NSSNOC_TIMEOUT_REF_CLK			198
+#define GCC_XO_DIV4_CLK					199
+#define GCC_UNIPHY0_SYS_CLK				200
+#define GCC_UNIPHY1_SYS_CLK				201
+#define GCC_UNIPHY2_SYS_CLK				202
+#define GCC_CMN_12GPLL_SYS_CLK				203
+#define GCC_NSSNOC_XO_DCD_CLK				204
+#define GCC_Q6SS_BOOT_CLK				205
+#define UNIPHY_SYS_CLK_SRC				206
+#define NSS_TS_CLK_SRC					207
+#define GCC_ANOC_PCIE0_1LANE_M_CLK			208
+#define GCC_ANOC_PCIE1_1LANE_M_CLK			209
+#define GCC_ANOC_PCIE2_2LANE_M_CLK			210
+#define GCC_ANOC_PCIE3_2LANE_M_CLK			211
+#define GCC_SNOC_PCIE0_1LANE_S_CLK			212
+#define GCC_SNOC_PCIE1_1LANE_S_CLK			213
+#define GCC_SNOC_PCIE2_2LANE_S_CLK			214
+#define GCC_SNOC_PCIE3_2LANE_S_CLK			215
+#define GCC_PCNOC_DCC_CLK				216
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq9574.h b/include/dt-bindings/reset/qcom,gcc-ipq9574.h
new file mode 100644
index 000000000000..18207b577b99
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-ipq9574.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018-2022, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9048_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_9048_H
+
+#define GCC_ADSS_BCR						0
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			1
+#define GCC_BLSP1_BCR						2
+#define GCC_BLSP1_QUP1_BCR					3
+#define GCC_BLSP1_QUP2_BCR					4
+#define GCC_BLSP1_QUP3_BCR					5
+#define GCC_BLSP1_QUP4_BCR					6
+#define GCC_BLSP1_QUP5_BCR					7
+#define GCC_BLSP1_QUP6_BCR					8
+#define GCC_BLSP1_UART1_BCR					9
+#define GCC_BLSP1_UART2_BCR					10
+#define GCC_BLSP1_UART3_BCR					11
+#define GCC_BLSP1_UART4_BCR					12
+#define GCC_BLSP1_UART5_BCR					13
+#define GCC_BLSP1_UART6_BCR					14
+#define GCC_BOOT_ROM_BCR					15
+#define GCC_MDIO_BCR						16
+#define GCC_NSS_BCR						17
+#define GCC_NSS_TBU_BCR						18
+#define GCC_PCIE0_BCR						19
+#define GCC_PCIE0_LINK_DOWN_BCR					20
+#define GCC_PCIE0_PHY_BCR					21
+#define GCC_PCIE0PHY_PHY_BCR					22
+#define GCC_PCIE1_BCR						23
+#define GCC_PCIE1_LINK_DOWN_BCR					24
+#define GCC_PCIE1_PHY_BCR					25
+#define GCC_PCIE1PHY_PHY_BCR					26
+#define GCC_PCIE2_BCR						27
+#define GCC_PCIE2_LINK_DOWN_BCR					28
+#define GCC_PCIE2_PHY_BCR					29
+#define GCC_PCIE2PHY_PHY_BCR					30
+#define GCC_PCIE3_BCR						31
+#define GCC_PCIE3_LINK_DOWN_BCR					32
+#define GCC_PCIE3_PHY_BCR					33
+#define GCC_PCIE3PHY_PHY_BCR					34
+#define GCC_PRNG_BCR						35
+#define GCC_QUSB2_0_PHY_BCR					36
+#define GCC_SDCC_BCR						37
+#define GCC_TLMM_BCR						38
+#define GCC_UNIPHY0_BCR						39
+#define GCC_UNIPHY1_BCR						40
+#define GCC_UNIPHY2_BCR						41
+#define GCC_USB0_PHY_BCR					42
+#define GCC_USB3PHY_0_PHY_BCR					43
+#define GCC_USB_BCR						44
+#define GCC_ANOC0_TBU_BCR					45
+#define GCC_ANOC1_TBU_BCR					46
+#define GCC_ANOC_BCR						47
+#define GCC_APSS_TCU_BCR					48
+#define GCC_CMN_BLK_BCR						49
+#define GCC_CMN_BLK_AHB_ARES					50
+#define GCC_CMN_BLK_SYS_ARES					51
+#define GCC_CMN_BLK_APU_ARES					52
+#define GCC_DCC_BCR						53
+#define GCC_DDRSS_BCR						54
+#define GCC_IMEM_BCR						55
+#define GCC_LPASS_BCR						56
+#define GCC_MPM_BCR						57
+#define GCC_MSG_RAM_BCR						58
+#define GCC_NSSNOC_MEMNOC_1_ARES				59
+#define GCC_NSSNOC_PCNOC_1_ARES					60
+#define GCC_NSSNOC_SNOC_1_ARES					61
+#define GCC_NSSNOC_XO_DCD_ARES					62
+#define GCC_NSSNOC_TS_ARES					63
+#define GCC_NSSCC_ARES						64
+#define GCC_NSSNOC_NSSCC_ARES					65
+#define GCC_NSSNOC_ATB_ARES					66
+#define GCC_NSSNOC_MEMNOC_ARES					67
+#define GCC_NSSNOC_QOSGEN_REF_ARES				68
+#define GCC_NSSNOC_SNOC_ARES					69
+#define GCC_NSSNOC_TIMEOUT_REF_ARES				70
+#define GCC_NSS_CFG_ARES					71
+#define GCC_UBI0_DBG_ARES					72
+#define GCC_PCIE0_AHB_ARES					73
+#define GCC_PCIE0_AUX_ARES					74
+#define GCC_PCIE0_AXI_M_ARES					75
+#define GCC_PCIE0_AXI_M_STICKY_ARES				76
+#define GCC_PCIE0_AXI_S_ARES					77
+#define GCC_PCIE0_AXI_S_STICKY_ARES				78
+#define GCC_PCIE0_CORE_STICKY_ARES				79
+#define GCC_PCIE0_PIPE_ARES					80
+#define GCC_PCIE1_AHB_ARES					81
+#define GCC_PCIE1_AUX_ARES					82
+#define GCC_PCIE1_AXI_M_ARES					83
+#define GCC_PCIE1_AXI_M_STICKY_ARES				84
+#define GCC_PCIE1_AXI_S_ARES					85
+#define GCC_PCIE1_AXI_S_STICKY_ARES				86
+#define GCC_PCIE1_CORE_STICKY_ARES				87
+#define GCC_PCIE1_PIPE_ARES					88
+#define GCC_PCIE2_AHB_ARES					89
+#define GCC_PCIE2_AUX_ARES					90
+#define GCC_PCIE2_AXI_M_ARES					91
+#define GCC_PCIE2_AXI_M_STICKY_ARES				92
+#define GCC_PCIE2_AXI_S_ARES					93
+#define GCC_PCIE2_AXI_S_STICKY_ARES				94
+#define GCC_PCIE2_CORE_STICKY_ARES				95
+#define GCC_PCIE2_PIPE_ARES					96
+#define GCC_PCIE3_AHB_ARES					97
+#define GCC_PCIE3_AUX_ARES					98
+#define GCC_PCIE3_AXI_M_ARES					99
+#define GCC_PCIE3_AXI_M_STICKY_ARES				100
+#define GCC_PCIE3_AXI_S_ARES					101
+#define GCC_PCIE3_AXI_S_STICKY_ARES				102
+#define GCC_PCIE3_CORE_STICKY_ARES				103
+#define GCC_PCIE3_PIPE_ARES					104
+#define GCC_PCNOC_BCR						105
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR				106
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR				107
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR				108
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR				109
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR				110
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR				111
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR				112
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR				113
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR				114
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR				115
+#define GCC_PCNOC_TBU_BCR					116
+#define GCC_Q6SS_DBG_ARES					117
+#define GCC_Q6_AHB_ARES						118
+#define GCC_Q6_AHB_S_ARES					119
+#define GCC_Q6_AXIM2_ARES					120
+#define GCC_Q6_AXIM_ARES					121
+#define GCC_QDSS_BCR						122
+#define GCC_QPIC_BCR						123
+#define GCC_QPIC_AHB_ARES					124
+#define GCC_QPIC_ARES						125
+#define GCC_RBCPR_BCR						126
+#define GCC_RBCPR_MX_BCR					127
+#define GCC_SEC_CTRL_BCR					128
+#define GCC_SMMU_CFG_BCR					129
+#define GCC_SNOC_BCR						130
+#define GCC_SPDM_BCR						131
+#define GCC_TME_BCR						132
+#define GCC_UNIPHY0_SYS_RESET					133
+#define GCC_UNIPHY0_AHB_RESET					134
+#define GCC_UNIPHY0_XPCS_RESET					135
+#define GCC_UNIPHY1_SYS_RESET					136
+#define GCC_UNIPHY1_AHB_RESET					137
+#define GCC_UNIPHY1_XPCS_RESET					138
+#define GCC_UNIPHY2_SYS_RESET					139
+#define GCC_UNIPHY2_AHB_RESET					140
+#define GCC_UNIPHY2_XPCS_RESET					141
+#define GCC_USB_MISC_RESET					142
+#define GCC_WCSSAON_RESET					143
+#define GCC_WCSS_ACMT_ARES					144
+#define GCC_WCSS_AHB_S_ARES					145
+#define GCC_WCSS_AXI_M_ARES					146
+#define GCC_WCSS_BCR						147
+#define GCC_WCSS_DBG_ARES					148
+#define GCC_WCSS_DBG_BDG_ARES					149
+#define GCC_WCSS_ECAHB_ARES					150
+#define GCC_WCSS_Q6_BCR						151
+#define GCC_WCSS_Q6_TBU_BCR					152
+#define GCC_TCSR_BCR						153
+
+#endif
-- 
2.17.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[devi priya]

Adding support for the global clock controller found on
IPQ9574 based devices

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 .../bindings/clock/qcom,gcc-other.yaml        |   4 +
 .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
 include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
 include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
 4 files changed, 402 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
 create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
index 2e8acca64af1..cc563d640336 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
@@ -18,6 +18,8 @@ description: |
     include/dt-bindings/clock/qcom,gcc-ipq4019.h
     include/dt-bindings/clock/qcom,gcc-ipq6018.h
     include/dt-bindings/reset/qcom,gcc-ipq6018.h
+    include/dt-bindings/clock/qcom,gcc-ipq9574.h
+    include/dt-bindings/reset/qcom,gcc-ipq9574.h
     include/dt-bindings/clock/qcom,gcc-msm8953.h
     include/dt-bindings/clock/qcom,gcc-mdm9607.h
     include/dt-bindings/clock/qcom,gcc-mdm9615.h
@@ -34,6 +36,8 @@ properties:
       - qcom,gcc-mdm9607
       - qcom,gcc-msm8953
       - qcom,gcc-mdm9615
+      - qcom,gcc-ipq9574
+
 
 required:
   - compatible
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
index 7129fbcf2b6c..5a71268538e6 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
@@ -24,6 +24,14 @@ properties:
   '#power-domain-cells':
     const: 1
 
+  clocks:
+    minItems: 1
+    maxItems: 8
+
+  clock-names:
+    minItems: 1
+    maxItems: 8
+
   reg:
     maxItems: 1
 
@@ -35,7 +43,6 @@ required:
   - reg
   - '#clock-cells'
   - '#reset-cells'
-  - '#power-domain-cells'
 
 additionalProperties: true
 
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq9574.h b/include/dt-bindings/clock/qcom,gcc-ipq9574.h
new file mode 100644
index 000000000000..312d513305ec
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-ipq9574.h
@@ -0,0 +1,226 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018-2022 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9048_H
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_9048_H
+
+#define GPLL0_MAIN					0
+#define GPLL0						1
+#define GPLL2_MAIN					2
+#define GPLL2						3
+#define GPLL4_MAIN					4
+#define GPLL4						5
+#define GCC_SLEEP_CLK_SRC				6
+#define APSS_AHB_CLK_SRC				7
+#define APSS_AXI_CLK_SRC				8
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC			9
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC			10
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC			11
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC			12
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC			13
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC			14
+#define BLSP1_QUP4_I2C_APPS_CLK_SRC			15
+#define BLSP1_QUP4_SPI_APPS_CLK_SRC			16
+#define BLSP1_QUP5_I2C_APPS_CLK_SRC			17
+#define BLSP1_QUP5_SPI_APPS_CLK_SRC			18
+#define BLSP1_QUP6_I2C_APPS_CLK_SRC			19
+#define BLSP1_QUP6_SPI_APPS_CLK_SRC			20
+#define BLSP1_UART1_APPS_CLK_SRC			21
+#define BLSP1_UART2_APPS_CLK_SRC			22
+#define BLSP1_UART3_APPS_CLK_SRC			23
+#define BLSP1_UART4_APPS_CLK_SRC			24
+#define BLSP1_UART5_APPS_CLK_SRC			25
+#define BLSP1_UART6_APPS_CLK_SRC			26
+#define GCC_APSS_AHB_CLK				27
+#define GCC_APSS_AXI_CLK				28
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			29
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			30
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			31
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			32
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK			33
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK			34
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK			35
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK			36
+#define GCC_BLSP1_QUP5_I2C_APPS_CLK			37
+#define GCC_BLSP1_QUP5_SPI_APPS_CLK			38
+#define GCC_BLSP1_QUP6_I2C_APPS_CLK			39
+#define GCC_BLSP1_QUP6_SPI_APPS_CLK			40
+#define GCC_BLSP1_UART1_APPS_CLK			41
+#define GCC_BLSP1_UART2_APPS_CLK			42
+#define GCC_BLSP1_UART3_APPS_CLK			43
+#define GCC_BLSP1_UART4_APPS_CLK			44
+#define GCC_BLSP1_UART5_APPS_CLK			45
+#define GCC_BLSP1_UART6_APPS_CLK			46
+#define PCIE0_AXI_M_CLK_SRC				47
+#define GCC_PCIE0_AXI_M_CLK				48
+#define PCIE1_AXI_M_CLK_SRC				49
+#define GCC_PCIE1_AXI_M_CLK				50
+#define PCIE2_AXI_M_CLK_SRC				51
+#define GCC_PCIE2_AXI_M_CLK				52
+#define PCIE3_AXI_M_CLK_SRC				53
+#define GCC_PCIE3_AXI_M_CLK				54
+#define PCIE0_AXI_S_CLK_SRC				55
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK			56
+#define GCC_PCIE0_AXI_S_CLK				57
+#define PCIE1_AXI_S_CLK_SRC				58
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK			59
+#define GCC_PCIE1_AXI_S_CLK				60
+#define PCIE2_AXI_S_CLK_SRC				61
+#define GCC_PCIE2_AXI_S_BRIDGE_CLK			62
+#define GCC_PCIE2_AXI_S_CLK				63
+#define PCIE3_AXI_S_CLK_SRC				64
+#define GCC_PCIE3_AXI_S_BRIDGE_CLK			65
+#define GCC_PCIE3_AXI_S_CLK				66
+#define PCIE0_PIPE_CLK_SRC				67
+#define PCIE1_PIPE_CLK_SRC				68
+#define PCIE2_PIPE_CLK_SRC				69
+#define PCIE3_PIPE_CLK_SRC				70
+#define PCIE_AUX_CLK_SRC				71
+#define GCC_PCIE0_AUX_CLK				72
+#define GCC_PCIE1_AUX_CLK				73
+#define GCC_PCIE2_AUX_CLK				74
+#define GCC_PCIE3_AUX_CLK				75
+#define PCIE0_RCHNG_CLK_SRC				76
+#define GCC_PCIE0_RCHNG_CLK				77
+#define PCIE1_RCHNG_CLK_SRC				78
+#define GCC_PCIE1_RCHNG_CLK				79
+#define PCIE2_RCHNG_CLK_SRC				80
+#define GCC_PCIE2_RCHNG_CLK				81
+#define PCIE3_RCHNG_CLK_SRC				82
+#define GCC_PCIE3_RCHNG_CLK				83
+#define GCC_PCIE0_AHB_CLK				84
+#define GCC_PCIE1_AHB_CLK				85
+#define GCC_PCIE2_AHB_CLK				86
+#define GCC_PCIE3_AHB_CLK				87
+#define USB0_AUX_CLK_SRC				88
+#define GCC_USB0_AUX_CLK				89
+#define USB0_MASTER_CLK_SRC				90
+#define GCC_USB0_MASTER_CLK				91
+#define GCC_SNOC_USB_CLK				92
+#define GCC_ANOC_USB_AXI_CLK				93
+#define USB0_MOCK_UTMI_CLK_SRC				94
+#define USB0_MOCK_UTMI_DIV_CLK_SRC			95
+#define GCC_USB0_MOCK_UTMI_CLK				96
+#define USB0_PIPE_CLK_SRC				97
+#define GCC_USB0_PHY_CFG_AHB_CLK			98
+#define SDCC1_APPS_CLK_SRC				99
+#define GCC_SDCC1_APPS_CLK				100
+#define SDCC1_ICE_CORE_CLK_SRC				101
+#define GCC_SDCC1_ICE_CORE_CLK				102
+#define GCC_SDCC1_AHB_CLK				103
+#define PCNOC_BFDCD_CLK_SRC				104
+#define GCC_NSSCFG_CLK					105
+#define GCC_NSSNOC_NSSCC_CLK				106
+#define GCC_NSSCC_CLK					107
+#define GCC_NSSNOC_PCNOC_1_CLK				108
+#define GCC_QDSS_DAP_AHB_CLK				109
+#define GCC_QDSS_CFG_AHB_CLK				110
+#define GCC_SNOC_PCNOC_AHB_CLK				111
+#define GCC_ANOC_PCNOC_AHB_CLK				112
+#define GCC_QPIC_AHB_CLK				113
+#define GCC_QPIC_CLK					114
+#define GCC_BLSP1_AHB_CLK				115
+#define GCC_MDIO_AHB_CLK				116
+#define GCC_PRNG_AHB_CLK				117
+#define GCC_UNIPHY0_AHB_CLK				118
+#define GCC_UNIPHY1_AHB_CLK				119
+#define GCC_UNIPHY2_AHB_CLK				120
+#define GCC_CMN_12GPLL_AHB_CLK				121
+#define GCC_CMN_12GPLL_APU_CLK				122
+#define SYSTEM_NOC_BFDCD_CLK_SRC			123
+#define GCC_NSSNOC_SNOC_CLK				124
+#define GCC_NSSNOC_SNOC_1_CLK				125
+#define GCC_QDSS_ETR_USB_CLK				126
+#define GCC_SYS_NOC_AXI_CLK				127
+#define GCC_ANOC0_AXI_CLK				128
+#define GCC_ANOC1_AXI_CLK				129
+#define GCC_ANOC0_TBU_CLK				130
+#define GCC_ANOC1_TBU_CLK				131
+#define GCC_MEM_NOC_SNOC_AXI_CLK			132
+#define GCC_IMEM_AXI_CLK				133
+#define WCSS_AHB_CLK_SRC				134
+#define GCC_Q6_AHB_CLK					135
+#define GCC_Q6_AHB_S_CLK				136
+#define GCC_WCSS_ECAHB_CLK				137
+#define GCC_WCSS_ACMT_CLK				138
+#define GCC_SYS_NOC_WCSS_AHB_CLK			139
+#define WCSS_AXI_M_CLK_SRC				140
+#define GCC_ANOC_WCSS_AXI_M_CLK				141
+#define QDSS_AT_CLK_SRC					142
+#define GCC_Q6SS_ATBM_CLK				143
+#define GCC_WCSS_DBG_IFC_ATB_CLK			144
+#define GCC_NSSNOC_ATB_CLK				145
+#define GCC_QDSS_AT_CLK					146
+#define GCC_SYS_NOC_AT_CLK				147
+#define GCC_PCNOC_AT_CLK				148
+#define GCC_USB0_EUD_AT_CLK				149
+#define GCC_QDSS_EUD_AT_CLK				150
+#define QDSS_STM_CLK_SRC				151
+#define GCC_QDSS_STM_CLK				152
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK			153
+#define QDSS_TRACECLKIN_CLK_SRC				154
+#define GCC_QDSS_TRACECLKIN_CLK				155
+#define QDSS_TSCTR_CLK_SRC				156
+#define GCC_Q6_TSCTR_1TO2_CLK				157
+#define GCC_WCSS_DBG_IFC_NTS_CLK			158
+#define GCC_QDSS_TSCTR_DIV2_CLK				159
+#define GCC_QDSS_TS_CLK					160
+#define GCC_SNOC_TS_CLK					161
+#define GCC_MEM_NOC_TS_CLK				162
+#define GCC_QDSS_TSCTR_DIV4_CLK				163
+#define GCC_NSS_TS_CLK					164
+#define GCC_QDSS_TSCTR_DIV8_CLK				165
+#define GCC_PCNOC_TS_CLK				166
+#define GCC_QDSS_TSCTR_DIV16_CLK			167
+#define GCC_Q6SS_PCLKDBG_CLK				168
+#define GCC_Q6SS_TRIG_CLK				169
+#define GCC_WCSS_DBG_IFC_APB_CLK			170
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK			171
+#define GCC_QDSS_DAP_CLK				172
+#define GCC_QDSS_APB2JTAG_CLK				173
+#define GCC_QDSS_TSCTR_DIV3_CLK				174
+#define QPIC_IO_MACRO_CLK_SRC				175
+#define GCC_QPIC_IO_MACRO_CLK				176
+#define Q6_AXI_CLK_SRC					177
+#define GCC_Q6_AXIM_CLK					178
+#define GCC_WCSS_Q6_TBU_CLK				179
+#define GCC_MEM_NOC_Q6_AXI_CLK				180
+#define Q6_AXIM2_CLK_SRC				181
+#define NSSNOC_MEMNOC_BFDCD_CLK_SRC			182
+#define GCC_NSSNOC_MEMNOC_CLK				183
+#define GCC_NSSNOC_MEM_NOC_1_CLK			184
+#define GCC_NSS_TBU_CLK					185
+#define GCC_MEM_NOC_NSSNOC_CLK				186
+#define LPASS_AXIM_CLK_SRC				187
+#define LPASS_SWAY_CLK_SRC				188
+#define ADSS_PWM_CLK_SRC				189
+#define GCC_ADSS_PWM_CLK				190
+#define GP1_CLK_SRC					191
+#define GP2_CLK_SRC					192
+#define GP3_CLK_SRC					193
+#define DDRSS_SMS_SLOW_CLK_SRC				194
+#define GCC_XO_CLK_SRC					195
+#define GCC_XO_CLK					196
+#define GCC_NSSNOC_QOSGEN_REF_CLK			197
+#define GCC_NSSNOC_TIMEOUT_REF_CLK			198
+#define GCC_XO_DIV4_CLK					199
+#define GCC_UNIPHY0_SYS_CLK				200
+#define GCC_UNIPHY1_SYS_CLK				201
+#define GCC_UNIPHY2_SYS_CLK				202
+#define GCC_CMN_12GPLL_SYS_CLK				203
+#define GCC_NSSNOC_XO_DCD_CLK				204
+#define GCC_Q6SS_BOOT_CLK				205
+#define UNIPHY_SYS_CLK_SRC				206
+#define NSS_TS_CLK_SRC					207
+#define GCC_ANOC_PCIE0_1LANE_M_CLK			208
+#define GCC_ANOC_PCIE1_1LANE_M_CLK			209
+#define GCC_ANOC_PCIE2_2LANE_M_CLK			210
+#define GCC_ANOC_PCIE3_2LANE_M_CLK			211
+#define GCC_SNOC_PCIE0_1LANE_S_CLK			212
+#define GCC_SNOC_PCIE1_1LANE_S_CLK			213
+#define GCC_SNOC_PCIE2_2LANE_S_CLK			214
+#define GCC_SNOC_PCIE3_2LANE_S_CLK			215
+#define GCC_PCNOC_DCC_CLK				216
+#endif
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq9574.h b/include/dt-bindings/reset/qcom,gcc-ipq9574.h
new file mode 100644
index 000000000000..18207b577b99
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,gcc-ipq9574.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2018-2022, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9048_H
+#define _DT_BINDINGS_RESET_IPQ_GCC_9048_H
+
+#define GCC_ADSS_BCR						0
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR			1
+#define GCC_BLSP1_BCR						2
+#define GCC_BLSP1_QUP1_BCR					3
+#define GCC_BLSP1_QUP2_BCR					4
+#define GCC_BLSP1_QUP3_BCR					5
+#define GCC_BLSP1_QUP4_BCR					6
+#define GCC_BLSP1_QUP5_BCR					7
+#define GCC_BLSP1_QUP6_BCR					8
+#define GCC_BLSP1_UART1_BCR					9
+#define GCC_BLSP1_UART2_BCR					10
+#define GCC_BLSP1_UART3_BCR					11
+#define GCC_BLSP1_UART4_BCR					12
+#define GCC_BLSP1_UART5_BCR					13
+#define GCC_BLSP1_UART6_BCR					14
+#define GCC_BOOT_ROM_BCR					15
+#define GCC_MDIO_BCR						16
+#define GCC_NSS_BCR						17
+#define GCC_NSS_TBU_BCR						18
+#define GCC_PCIE0_BCR						19
+#define GCC_PCIE0_LINK_DOWN_BCR					20
+#define GCC_PCIE0_PHY_BCR					21
+#define GCC_PCIE0PHY_PHY_BCR					22
+#define GCC_PCIE1_BCR						23
+#define GCC_PCIE1_LINK_DOWN_BCR					24
+#define GCC_PCIE1_PHY_BCR					25
+#define GCC_PCIE1PHY_PHY_BCR					26
+#define GCC_PCIE2_BCR						27
+#define GCC_PCIE2_LINK_DOWN_BCR					28
+#define GCC_PCIE2_PHY_BCR					29
+#define GCC_PCIE2PHY_PHY_BCR					30
+#define GCC_PCIE3_BCR						31
+#define GCC_PCIE3_LINK_DOWN_BCR					32
+#define GCC_PCIE3_PHY_BCR					33
+#define GCC_PCIE3PHY_PHY_BCR					34
+#define GCC_PRNG_BCR						35
+#define GCC_QUSB2_0_PHY_BCR					36
+#define GCC_SDCC_BCR						37
+#define GCC_TLMM_BCR						38
+#define GCC_UNIPHY0_BCR						39
+#define GCC_UNIPHY1_BCR						40
+#define GCC_UNIPHY2_BCR						41
+#define GCC_USB0_PHY_BCR					42
+#define GCC_USB3PHY_0_PHY_BCR					43
+#define GCC_USB_BCR						44
+#define GCC_ANOC0_TBU_BCR					45
+#define GCC_ANOC1_TBU_BCR					46
+#define GCC_ANOC_BCR						47
+#define GCC_APSS_TCU_BCR					48
+#define GCC_CMN_BLK_BCR						49
+#define GCC_CMN_BLK_AHB_ARES					50
+#define GCC_CMN_BLK_SYS_ARES					51
+#define GCC_CMN_BLK_APU_ARES					52
+#define GCC_DCC_BCR						53
+#define GCC_DDRSS_BCR						54
+#define GCC_IMEM_BCR						55
+#define GCC_LPASS_BCR						56
+#define GCC_MPM_BCR						57
+#define GCC_MSG_RAM_BCR						58
+#define GCC_NSSNOC_MEMNOC_1_ARES				59
+#define GCC_NSSNOC_PCNOC_1_ARES					60
+#define GCC_NSSNOC_SNOC_1_ARES					61
+#define GCC_NSSNOC_XO_DCD_ARES					62
+#define GCC_NSSNOC_TS_ARES					63
+#define GCC_NSSCC_ARES						64
+#define GCC_NSSNOC_NSSCC_ARES					65
+#define GCC_NSSNOC_ATB_ARES					66
+#define GCC_NSSNOC_MEMNOC_ARES					67
+#define GCC_NSSNOC_QOSGEN_REF_ARES				68
+#define GCC_NSSNOC_SNOC_ARES					69
+#define GCC_NSSNOC_TIMEOUT_REF_ARES				70
+#define GCC_NSS_CFG_ARES					71
+#define GCC_UBI0_DBG_ARES					72
+#define GCC_PCIE0_AHB_ARES					73
+#define GCC_PCIE0_AUX_ARES					74
+#define GCC_PCIE0_AXI_M_ARES					75
+#define GCC_PCIE0_AXI_M_STICKY_ARES				76
+#define GCC_PCIE0_AXI_S_ARES					77
+#define GCC_PCIE0_AXI_S_STICKY_ARES				78
+#define GCC_PCIE0_CORE_STICKY_ARES				79
+#define GCC_PCIE0_PIPE_ARES					80
+#define GCC_PCIE1_AHB_ARES					81
+#define GCC_PCIE1_AUX_ARES					82
+#define GCC_PCIE1_AXI_M_ARES					83
+#define GCC_PCIE1_AXI_M_STICKY_ARES				84
+#define GCC_PCIE1_AXI_S_ARES					85
+#define GCC_PCIE1_AXI_S_STICKY_ARES				86
+#define GCC_PCIE1_CORE_STICKY_ARES				87
+#define GCC_PCIE1_PIPE_ARES					88
+#define GCC_PCIE2_AHB_ARES					89
+#define GCC_PCIE2_AUX_ARES					90
+#define GCC_PCIE2_AXI_M_ARES					91
+#define GCC_PCIE2_AXI_M_STICKY_ARES				92
+#define GCC_PCIE2_AXI_S_ARES					93
+#define GCC_PCIE2_AXI_S_STICKY_ARES				94
+#define GCC_PCIE2_CORE_STICKY_ARES				95
+#define GCC_PCIE2_PIPE_ARES					96
+#define GCC_PCIE3_AHB_ARES					97
+#define GCC_PCIE3_AUX_ARES					98
+#define GCC_PCIE3_AXI_M_ARES					99
+#define GCC_PCIE3_AXI_M_STICKY_ARES				100
+#define GCC_PCIE3_AXI_S_ARES					101
+#define GCC_PCIE3_AXI_S_STICKY_ARES				102
+#define GCC_PCIE3_CORE_STICKY_ARES				103
+#define GCC_PCIE3_PIPE_ARES					104
+#define GCC_PCNOC_BCR						105
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR				106
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR				107
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR				108
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR				109
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR				110
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR				111
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR				112
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR				113
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR				114
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR				115
+#define GCC_PCNOC_TBU_BCR					116
+#define GCC_Q6SS_DBG_ARES					117
+#define GCC_Q6_AHB_ARES						118
+#define GCC_Q6_AHB_S_ARES					119
+#define GCC_Q6_AXIM2_ARES					120
+#define GCC_Q6_AXIM_ARES					121
+#define GCC_QDSS_BCR						122
+#define GCC_QPIC_BCR						123
+#define GCC_QPIC_AHB_ARES					124
+#define GCC_QPIC_ARES						125
+#define GCC_RBCPR_BCR						126
+#define GCC_RBCPR_MX_BCR					127
+#define GCC_SEC_CTRL_BCR					128
+#define GCC_SMMU_CFG_BCR					129
+#define GCC_SNOC_BCR						130
+#define GCC_SPDM_BCR						131
+#define GCC_TME_BCR						132
+#define GCC_UNIPHY0_SYS_RESET					133
+#define GCC_UNIPHY0_AHB_RESET					134
+#define GCC_UNIPHY0_XPCS_RESET					135
+#define GCC_UNIPHY1_SYS_RESET					136
+#define GCC_UNIPHY1_AHB_RESET					137
+#define GCC_UNIPHY1_XPCS_RESET					138
+#define GCC_UNIPHY2_SYS_RESET					139
+#define GCC_UNIPHY2_AHB_RESET					140
+#define GCC_UNIPHY2_XPCS_RESET					141
+#define GCC_USB_MISC_RESET					142
+#define GCC_WCSSAON_RESET					143
+#define GCC_WCSS_ACMT_ARES					144
+#define GCC_WCSS_AHB_S_ARES					145
+#define GCC_WCSS_AXI_M_ARES					146
+#define GCC_WCSS_BCR						147
+#define GCC_WCSS_DBG_ARES					148
+#define GCC_WCSS_DBG_BDG_ARES					149
+#define GCC_WCSS_ECAHB_ARES					150
+#define GCC_WCSS_Q6_BCR						151
+#define GCC_WCSS_Q6_TBU_BCR					152
+#define GCC_TCSR_BCR						153
+
+#endif
-- 
2.17.1

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Rob Herring]

On Tue, 10 Jan 2023 17:43:10 +0530, devi priya wrote:
> Adding support for the global clock controller found on
> IPQ9574 based devices
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>  .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>  include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>  include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>  4 files changed, 402 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>  create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295, 0], [4294967295, 1], [4294967295, 2], [4294967295]] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295, 1], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk', 'pcie_0_pipe_clk', 'pcie_1_pipe_clk', 'ufs_phy_rx_symbol_0_clk', 'ufs_phy_rx_symbol_1_clk', 'ufs_phy_tx_symbol_0_clk', 'usb3_phy_wrapper_gcc_usb30_pipe_clk'] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230110121316.24892-2-quic_devipriy@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Rob Herring]

On Tue, 10 Jan 2023 17:43:10 +0530, devi priya wrote:
> Adding support for the global clock controller found on
> IPQ9574 based devices
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>  .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>  include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>  include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>  4 files changed, 402 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>  create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295, 0], [4294967295, 1], [4294967295, 2], [4294967295]] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295, 1], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk', 'pcie_0_pipe_clk', 'pcie_1_pipe_clk', 'ufs_phy_rx_symbol_0_clk', 'ufs_phy_rx_symbol_1_clk', 'ufs_phy_tx_symbol_0_clk', 'usb3_phy_wrapper_gcc_usb30_pipe_clk'] is too long
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230110121316.24892-2-quic_devipriy@quicinc.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Devi Priya]

On 1/10/2023 6:59 PM, Rob Herring wrote:
> 
> On Tue, 10 Jan 2023 17:43:10 +0530, devi priya wrote:
>> Adding support for the global clock controller found on
>> IPQ9574 based devices
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>>   .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>>   include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>>   include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>>   4 files changed, 402 insertions(+), 1 deletion(-)
>>   create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>>   create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
>>
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295, 0], [4294967295, 1], [4294967295, 2], [4294967295]] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295, 1], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk', 'pcie_0_pipe_clk', 'pcie_1_pipe_clk', 'ufs_phy_rx_symbol_0_clk', 'ufs_phy_rx_symbol_1_clk', 'ufs_phy_tx_symbol_0_clk', 'usb3_phy_wrapper_gcc_usb30_pipe_clk'] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> 
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230110121316.24892-2-quic_devipriy@quicinc.com
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
> 
Sure, will check

Best Regards,
Devi Priya

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Devi Priya]

On 1/10/2023 6:59 PM, Rob Herring wrote:
> 
> On Tue, 10 Jan 2023 17:43:10 +0530, devi priya wrote:
>> Adding support for the global clock controller found on
>> IPQ9574 based devices
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>>   .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>>   include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>>   include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>>   4 files changed, 402 insertions(+), 1 deletion(-)
>>   create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>>   create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
>>
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295, 0], [4294967295, 1], [4294967295, 2], [4294967295]] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,sm8550-gcc.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc8280xp.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clocks: [[4294967295, 0], [4294967295, 1], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295], [4294967295]] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: clock-names: ['bi_tcxo', 'bi_tcxo_ao', 'sleep_clk', 'pcie_0_pipe_clk', 'pcie_1_pipe_clk', 'ufs_phy_rx_symbol_0_clk', 'ufs_phy_rx_symbol_1_clk', 'ufs_phy_tx_symbol_0_clk', 'usb3_phy_wrapper_gcc_usb30_pipe_clk'] is too long
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.example.dtb: clock-controller@100000: Unevaluated properties are not allowed ('#clock-cells', '#power-domain-cells', '#reset-cells', 'reg' were unexpected)
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/qcom,gcc-sc7280.yaml
> 
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230110121316.24892-2-quic_devipriy@quicinc.com
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
> 
Sure, will check

Best Regards,
Devi Priya

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Adding support for the global clock controller found on
> IPQ9574 based devices

Subject: drop second/last, redundant "bindings descriptions for". The
"dt-bindings" prefix is already stating that these are bindings.

> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>  .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>  include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>  include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>  4 files changed, 402 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>  create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> index 2e8acca64af1..cc563d640336 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> @@ -18,6 +18,8 @@ description: |
>      include/dt-bindings/clock/qcom,gcc-ipq4019.h
>      include/dt-bindings/clock/qcom,gcc-ipq6018.h
>      include/dt-bindings/reset/qcom,gcc-ipq6018.h
> +    include/dt-bindings/clock/qcom,gcc-ipq9574.h
> +    include/dt-bindings/reset/qcom,gcc-ipq9574.h
>      include/dt-bindings/clock/qcom,gcc-msm8953.h
>      include/dt-bindings/clock/qcom,gcc-mdm9607.h
>      include/dt-bindings/clock/qcom,gcc-mdm9615.h
> @@ -34,6 +36,8 @@ properties:
>        - qcom,gcc-mdm9607
>        - qcom,gcc-msm8953
>        - qcom,gcc-mdm9615
> +      - qcom,gcc-ipq9574

Incorrect order but anyway let's switch to new naming style just like
SM8550 and SA8775p.

> +

Not related change.

>  
>  required:
>    - compatible
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> index 7129fbcf2b6c..5a71268538e6 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> @@ -24,6 +24,14 @@ properties:
>    '#power-domain-cells':
>      const: 1
>  
> +  clocks:
> +    minItems: 1
> +    maxItems: 8
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 8

This does not look correct, neither related.
> +
>    reg:
>      maxItems: 1
>  
> @@ -35,7 +43,6 @@ required:
>    - reg
>    - '#clock-cells'
>    - '#reset-cells'
> -  - '#power-domain-cells'

Eee? Why? What's this?




Best regards,
Krzysztof


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Adding support for the global clock controller found on
> IPQ9574 based devices

Subject: drop second/last, redundant "bindings descriptions for". The
"dt-bindings" prefix is already stating that these are bindings.

> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>  .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>  include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>  include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>  4 files changed, 402 insertions(+), 1 deletion(-)
>  create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>  create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> index 2e8acca64af1..cc563d640336 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
> @@ -18,6 +18,8 @@ description: |
>      include/dt-bindings/clock/qcom,gcc-ipq4019.h
>      include/dt-bindings/clock/qcom,gcc-ipq6018.h
>      include/dt-bindings/reset/qcom,gcc-ipq6018.h
> +    include/dt-bindings/clock/qcom,gcc-ipq9574.h
> +    include/dt-bindings/reset/qcom,gcc-ipq9574.h
>      include/dt-bindings/clock/qcom,gcc-msm8953.h
>      include/dt-bindings/clock/qcom,gcc-mdm9607.h
>      include/dt-bindings/clock/qcom,gcc-mdm9615.h
> @@ -34,6 +36,8 @@ properties:
>        - qcom,gcc-mdm9607
>        - qcom,gcc-msm8953
>        - qcom,gcc-mdm9615
> +      - qcom,gcc-ipq9574

Incorrect order but anyway let's switch to new naming style just like
SM8550 and SA8775p.

> +

Not related change.

>  
>  required:
>    - compatible
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> index 7129fbcf2b6c..5a71268538e6 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
> @@ -24,6 +24,14 @@ properties:
>    '#power-domain-cells':
>      const: 1
>  
> +  clocks:
> +    minItems: 1
> +    maxItems: 8
> +
> +  clock-names:
> +    minItems: 1
> +    maxItems: 8

This does not look correct, neither related.
> +
>    reg:
>      maxItems: 1
>  
> @@ -35,7 +43,6 @@ required:
>    - reg
>    - '#clock-cells'
>    - '#reset-cells'
> -  - '#power-domain-cells'

Eee? Why? What's this?




Best regards,
Krzysztof

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Devi Priya]

On 1/11/2023 3:06 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Adding support for the global clock controller found on
>> IPQ9574 based devices
> 
> Subject: drop second/last, redundant "bindings descriptions for". The
> "dt-bindings" prefix is already stating that these are bindings.
Sure, will do
> 
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>>   .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>>   include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>>   include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>>   4 files changed, 402 insertions(+), 1 deletion(-)
>>   create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>>   create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>> index 2e8acca64af1..cc563d640336 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>> @@ -18,6 +18,8 @@ description: |
>>       include/dt-bindings/clock/qcom,gcc-ipq4019.h
>>       include/dt-bindings/clock/qcom,gcc-ipq6018.h
>>       include/dt-bindings/reset/qcom,gcc-ipq6018.h
>> +    include/dt-bindings/clock/qcom,gcc-ipq9574.h
>> +    include/dt-bindings/reset/qcom,gcc-ipq9574.h
>>       include/dt-bindings/clock/qcom,gcc-msm8953.h
>>       include/dt-bindings/clock/qcom,gcc-mdm9607.h
>>       include/dt-bindings/clock/qcom,gcc-mdm9615.h
>> @@ -34,6 +36,8 @@ properties:
>>         - qcom,gcc-mdm9607
>>         - qcom,gcc-msm8953
>>         - qcom,gcc-mdm9615
>> +      - qcom,gcc-ipq9574
> 
> Incorrect order but anyway let's switch to new naming style just like
> SM8550 and SA8775p.
okay
> 
>> +
> 
> Not related change.
> 
Understood, will remove
>>   
>>   required:
>>     - compatible
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> index 7129fbcf2b6c..5a71268538e6 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> @@ -24,6 +24,14 @@ properties:
>>     '#power-domain-cells':
>>       const: 1
>>   
>> +  clocks:
>> +    minItems: 1
>> +    maxItems: 8
>> +
>> +  clock-names:
>> +    minItems: 1
>> +    maxItems: 8
> 
> This does not look correct, neither related.
Okay
>> +
>>     reg:
>>       maxItems: 1
>>   
>> @@ -35,7 +43,6 @@ required:
>>     - reg
>>     - '#clock-cells'
>>     - '#reset-cells'
>> -  - '#power-domain-cells'
> 
> Eee? Why? What's this?
Sure, will address it accordingly
> 
> 
> 
> 
> Best regards,
> Krzysztof
> 

Best regards,
Devi Priya

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Devi Priya]

On 1/11/2023 3:06 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Adding support for the global clock controller found on
>> IPQ9574 based devices
> 
> Subject: drop second/last, redundant "bindings descriptions for". The
> "dt-bindings" prefix is already stating that these are bindings.
Sure, will do
> 
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   .../bindings/clock/qcom,gcc-other.yaml        |   4 +
>>   .../devicetree/bindings/clock/qcom,gcc.yaml   |   9 +-
>>   include/dt-bindings/clock/qcom,gcc-ipq9574.h  | 226 ++++++++++++++++++
>>   include/dt-bindings/reset/qcom,gcc-ipq9574.h  | 164 +++++++++++++
>>   4 files changed, 402 insertions(+), 1 deletion(-)
>>   create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq9574.h
>>   create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq9574.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>> index 2e8acca64af1..cc563d640336 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml
>> @@ -18,6 +18,8 @@ description: |
>>       include/dt-bindings/clock/qcom,gcc-ipq4019.h
>>       include/dt-bindings/clock/qcom,gcc-ipq6018.h
>>       include/dt-bindings/reset/qcom,gcc-ipq6018.h
>> +    include/dt-bindings/clock/qcom,gcc-ipq9574.h
>> +    include/dt-bindings/reset/qcom,gcc-ipq9574.h
>>       include/dt-bindings/clock/qcom,gcc-msm8953.h
>>       include/dt-bindings/clock/qcom,gcc-mdm9607.h
>>       include/dt-bindings/clock/qcom,gcc-mdm9615.h
>> @@ -34,6 +36,8 @@ properties:
>>         - qcom,gcc-mdm9607
>>         - qcom,gcc-msm8953
>>         - qcom,gcc-mdm9615
>> +      - qcom,gcc-ipq9574
> 
> Incorrect order but anyway let's switch to new naming style just like
> SM8550 and SA8775p.
okay
> 
>> +
> 
> Not related change.
> 
Understood, will remove
>>   
>>   required:
>>     - compatible
>> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> index 7129fbcf2b6c..5a71268538e6 100644
>> --- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
>> @@ -24,6 +24,14 @@ properties:
>>     '#power-domain-cells':
>>       const: 1
>>   
>> +  clocks:
>> +    minItems: 1
>> +    maxItems: 8
>> +
>> +  clock-names:
>> +    minItems: 1
>> +    maxItems: 8
> 
> This does not look correct, neither related.
Okay
>> +
>>     reg:
>>       maxItems: 1
>>   
>> @@ -35,7 +43,6 @@ required:
>>     - reg
>>     - '#clock-cells'
>>     - '#reset-cells'
>> -  - '#power-domain-cells'
> 
> Eee? Why? What's this?
Sure, will address it accordingly
> 
> 
> 
> 
> Best regards,
> Krzysztof
> 

Best regards,
Devi Priya

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Adding support for the global clock controller found on
> IPQ9574 based devices
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---

Use subject prefixes matching the subsystem (which you can get for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching).

Best regards,
Krzysztof


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Adding support for the global clock controller found on
> IPQ9574 based devices
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---

Use subject prefixes matching the subsystem (which you can get for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching).

Best regards,
Krzysztof

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Devi Priya]

On 1/11/2023 3:16 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Adding support for the global clock controller found on
>> IPQ9574 based devices
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
> 
> Use subject prefixes matching the subsystem (which you can get for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching).
> 
> Best regards,
> Krzysztof
> 
Sure, will do

Best Regards,
Devi Priya

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 1/7] dt-bindings: arm64: ipq9574: Add binding descriptions for clock and reset

[Devi Priya]

On 1/11/2023 3:16 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Adding support for the global clock controller found on
>> IPQ9574 based devices
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
> 
> Use subject prefixes matching the subsystem (which you can get for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching).
> 
> Best regards,
> Krzysztof
> 
Sure, will do

Best Regards,
Devi Priya

[PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[devi priya]

Add Global Clock Controller (GCC) driver for ipq9574 based devices

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 drivers/clk/qcom/Kconfig       |    8 +
 drivers/clk/qcom/Makefile      |    1 +
 drivers/clk/qcom/gcc-ipq9574.c | 4706 ++++++++++++++++++++++++++++++++
 3 files changed, 4715 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq9574.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 70d43f0a8919..97517d1e3ba4 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -173,6 +173,14 @@ config IPQ_GCC_8074
 	  i2c, USB, SD/eMMC, etc. Select this for the root clock
 	  of ipq8074.
 
+config IPQ_GCC_9574
+	tristate "IPQ9574 Global Clock Controller"
+	help
+	  Support for global clock controller on ipq9574 devices.
+	  Say Y if you want to use peripheral devices such as UART, SPI,
+	  i2c, USB, SD/eMMC, etc. Select this for the root clock
+	  of ipq9574.
+
 config MSM_GCC_8660
 	tristate "MSM8660 Global Clock Controller"
 	help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index f18c446a97ea..55c6ada326e0 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
 obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
 obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
+obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
 obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
 obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
 obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
new file mode 100644
index 000000000000..f44a19c5f9a1
--- /dev/null
+++ b/drivers/clk/qcom/gcc-ipq9574.c
@@ -0,0 +1,4706 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2022 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk-provider.h>
+#include <linux/regmap.h>
+
+#include <linux/reset-controller.h>
+#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
+#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
+
+#include "common.h"
+#include "clk-regmap.h"
+#include "clk-pll.h"
+#include "clk-rcg.h"
+#include "clk-branch.h"
+#include "clk-alpha-pll.h"
+#include "clk-regmap-divider.h"
+#include "clk-regmap-mux.h"
+#include "reset.h"
+
+#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
+
+/* Need to match the order of clocks in DT binding */
+enum {
+	DT_XO,
+	DT_SLEEP_CLK,
+	DT_BIAS_PLL_UBI_NC_CLK,
+	DT_PCIE30_PHY0_PIPE_CLK,
+	DT_PCIE30_PHY1_PIPE_CLK,
+	DT_PCIE30_PHY2_PIPE_CLK,
+	DT_PCIE30_PHY3_PIPE_CLK,
+	DT_USB3PHY_0_CC_PIPE_CLK,
+};
+
+enum {
+	P_XO,
+	P_PCIE30_PHY0_PIPE,
+	P_PCIE30_PHY1_PIPE,
+	P_PCIE30_PHY2_PIPE,
+	P_PCIE30_PHY3_PIPE,
+	P_USB3PHY_0_PIPE,
+	P_GPLL0,
+	P_GPLL0_DIV2,
+	P_GPLL0_OUT_AUX,
+	P_GPLL2,
+	P_GPLL4,
+	P_PI_SLEEP,
+	P_BIAS_PLL_UBI_NC_CLK,
+};
+
+static const struct parent_map gcc_xo_map[] = {
+	{ P_XO, 0 },
+};
+
+static const struct clk_parent_data gcc_xo_data[] = {
+	{ .index = DT_XO },
+};
+
+static const struct clk_parent_data gcc_sleep_clk_data[] = {
+	{ .index = DT_SLEEP_CLK },
+};
+
+static struct clk_alpha_pll gpll0_main = {
+	.offset = 0x20000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.clkr = {
+		.enable_reg = 0x0b000,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gpll0_main",
+			.parent_data = gcc_xo_data,
+			.num_parents = ARRAY_SIZE(gcc_xo_data),
+			.ops = &clk_alpha_pll_ops,
+			.flags = CLK_IS_CRITICAL,
+		},
+	},
+};
+
+static struct clk_fixed_factor gpll0_out_main_div2 = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data) {
+		.name = "gpll0_out_main_div2",
+		.parent_hws = (const struct clk_hw *[]) {
+				&gpll0_main.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_alpha_pll_postdiv gpll0 = {
+	.offset = 0x20000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.width = 4,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "gpll0",
+		.parent_hws = (const struct clk_hw *[]) {
+				&gpll0_main.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_alpha_pll gpll4_main = {
+	.offset = 0x22000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.clkr = {
+		.enable_reg = 0x0b000,
+		.enable_mask = BIT(2),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gpll4_main",
+			.parent_data = gcc_xo_data,
+			.num_parents = ARRAY_SIZE(gcc_xo_data),
+			.ops = &clk_alpha_pll_ops,
+			.flags = CLK_IS_CRITICAL,
+		},
+	},
+};
+
+static struct clk_alpha_pll_postdiv gpll4 = {
+	.offset = 0x22000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.width = 4,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "gpll4",
+		.parent_hws = (const struct clk_hw *[]) {
+				&gpll4_main.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_alpha_pll gpll2_main = {
+	.offset = 0x21000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.clkr = {
+		.enable_reg = 0x0b000,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gpll2_main",
+			.parent_data = gcc_xo_data,
+			.num_parents = ARRAY_SIZE(gcc_xo_data),
+			.ops = &clk_alpha_pll_ops,
+			.flags = CLK_IS_CRITICAL,
+		},
+	},
+};
+
+static struct clk_alpha_pll_postdiv gpll2 = {
+	.offset = 0x21000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
+	.width = 4,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "gpll2",
+		.parent_hws = (const struct clk_hw *[]) {
+				&gpll2_main.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_alpha_pll_postdiv_ro_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_branch gcc_sleep_clk_src = {
+	.halt_reg = 0x3400c,
+	.clkr = {
+		.enable_reg = 0x3400c,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sleep_clk_src",
+			.parent_data = gcc_sleep_clk_data,
+			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
+			.ops = &clk_branch2_ops,
+			.flags = CLK_IS_CRITICAL,
+		},
+	},
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw},
+	{ .hw = &gpll0_out_main_div2.hw},
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll4.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL4, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0_out_main_div2.hw },
+	{ .hw = &gpll0.clkr.hw },
+};
+
+static const struct parent_map
+gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL0_DIV2, 4 },
+	{ P_GPLL0, 5 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0_out_main_div2.hw },
+	{ .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL0_DIV2, 4 },
+	{ P_PI_SLEEP, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 2 },
+	{ P_PI_SLEEP, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll4.clkr.hw },
+	{ .index = DT_BIAS_PLL_UBI_NC_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL4, 2 },
+	{ P_BIAS_PLL_UBI_NC_CLK, 3 },
+};
+
+static const struct clk_parent_data gcc_pcie30_phy0_pipe_clk_xo[] = {
+	{ .index = DT_PCIE30_PHY0_PIPE_CLK },
+	{ .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie30_phy0_pipe_clk_xo_map[] = {
+	{ P_PCIE30_PHY0_PIPE, 0 },
+	{ P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_pcie30_phy1_pipe_clk_xo[] = {
+	{ .index = DT_PCIE30_PHY1_PIPE_CLK },
+	{ .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie30_phy1_pipe_clk_xo_map[] = {
+	{ P_PCIE30_PHY1_PIPE, 0 },
+	{ P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_pcie30_phy2_pipe_clk_xo[] = {
+	{ .index = DT_PCIE30_PHY2_PIPE_CLK },
+	{ .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie30_phy2_pipe_clk_xo_map[] = {
+	{ P_PCIE30_PHY2_PIPE, 0 },
+	{ P_XO, 2 },
+};
+
+static const struct clk_parent_data gcc_pcie30_phy3_pipe_clk_xo[] = {
+	{ .index = DT_PCIE30_PHY3_PIPE_CLK },
+	{ .index = DT_XO },
+};
+
+static const struct parent_map gcc_pcie30_phy3_pipe_clk_xo_map[] = {
+	{ P_PCIE30_PHY3_PIPE, 0 },
+	{ P_XO, 2 },
+};
+
+static const struct clk_parent_data
+			gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map
+			gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL0_OUT_AUX, 2 },
+	{ P_PI_SLEEP, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data
+			gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll4.clkr.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL4, 1 },
+	{ P_GPLL0, 3 },
+	{ P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {
+	{ .index = DT_USB3PHY_0_CC_PIPE_CLK },
+	{ .index = DT_XO },
+};
+
+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {
+	{ P_USB3PHY_0_PIPE, 0 },
+	{ P_XO, 2 },
+};
+
+static const struct clk_parent_data
+			gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll2.clkr.hw },
+	{ .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL2, 2 },
+	{ P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {
+	{ .index = DT_XO},
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll4.clkr.hw },
+	{ .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL4, 2 },
+	{ P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll4.clkr.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0_out_main_div2.hw },
+};
+
+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL4, 1 },
+	{ P_GPLL0, 2 },
+	{ P_GPLL0_DIV2, 4 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll2.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL2, 2 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll2.clkr.hw },
+	{ .hw = &gpll4.clkr.hw },
+	{ .index = DT_SLEEP_CLK },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL2, 2 },
+	{ P_GPLL4, 3 },
+	{ P_PI_SLEEP, 6 },
+};
+
+static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {
+	{ .index = DT_XO },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll0.clkr.hw },
+	{ .hw = &gpll2.clkr.hw },
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL0_OUT_AUX, 2 },
+	{ P_GPLL2, 3 },
+};
+
+static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(50000000, P_GPLL0, 16, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 apss_ahb_clk_src = {
+	.cmd_rcgr = 0x2400c,
+	.freq_tbl = ftbl_apss_ahb_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "apss_ahb_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_apss_axi_clk_src[] = {
+	F(533000000, P_GPLL0, 1.5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 apss_axi_clk_src = {
+	.cmd_rcgr = 0x24004,
+	.freq_tbl = ftbl_apss_axi_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "apss_axi_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {
+	F(9600000, P_XO, 2.5, 0, 0),
+	F(24000000, P_XO, 1, 0, 0),
+	F(50000000, P_GPLL0, 16, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
+	.cmd_rcgr = 0x02018,
+	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup1_i2c_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {
+	F(960000, P_XO, 10, 2, 5),
+	F(4800000, P_XO, 5, 0, 0),
+	F(9600000, P_XO, 2, 4, 5),
+	F(16000000, P_GPLL0, 10, 1, 5),
+	F(24000000, P_XO, 1, 0, 0),
+	F(25000000, P_GPLL0, 16, 1, 2),
+	F(50000000, P_GPLL0, 16, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
+	.cmd_rcgr = 0x02004,
+	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup1_spi_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
+	.cmd_rcgr = 0x03018,
+	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup2_i2c_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
+	.cmd_rcgr = 0x03004,
+	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup2_spi_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
+	.cmd_rcgr = 0x04018,
+	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup3_i2c_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
+	.cmd_rcgr = 0x04004,
+	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup3_spi_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
+	.cmd_rcgr = 0x05018,
+	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup4_i2c_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
+	.cmd_rcgr = 0x05004,
+	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup4_spi_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
+	.cmd_rcgr = 0x06018,
+	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup5_i2c_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
+	.cmd_rcgr = 0x06004,
+	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup5_spi_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
+	.cmd_rcgr = 0x07018,
+	.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup6_i2c_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
+	.cmd_rcgr = 0x07004,
+	.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_qup6_spi_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {
+	F(3686400, P_GPLL0_DIV2, 1, 144, 15625),
+	F(7372800, P_GPLL0_DIV2, 1, 288, 15625),
+	F(14745600, P_GPLL0_DIV2, 1, 576, 15625),
+	F(24000000, P_XO, 1, 0, 0),
+	F(25000000, P_GPLL0, 16, 1, 2),
+	F(32000000, P_GPLL0, 1, 1, 25),
+	F(40000000, P_GPLL0, 1, 1, 20),
+	F(46400000, P_GPLL0, 1, 29, 500),
+	F(48000000, P_GPLL0, 1, 3, 50),
+	F(51200000, P_GPLL0, 1, 8, 125),
+	F(56000000, P_GPLL0, 1, 7, 100),
+	F(58982400, P_GPLL0, 1, 1152, 15625),
+	F(60000000, P_GPLL0, 1, 3, 40),
+	F(64000000, P_GPLL0, 12.5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
+	.cmd_rcgr = 0x0202c,
+	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_uart1_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
+	.cmd_rcgr = 0x0302c,
+	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_uart2_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
+	.cmd_rcgr = 0x0402c,
+	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_uart3_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
+	.cmd_rcgr = 0x0502c,
+	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_uart4_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
+	.cmd_rcgr = 0x0602c,
+	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_uart5_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
+	.cmd_rcgr = 0x0702c,
+	.freq_tbl = ftbl_blsp1_uart_apps_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "blsp1_uart6_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_apss_ahb_clk = {
+	.halt_reg = 0x24018,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x0b004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_apss_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&apss_ahb_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_apss_axi_clk = {
+	.halt_reg = 0x2401c,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x0b004,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_apss_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&apss_axi_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
+	.halt_reg = 0x2024,
+	.clkr = {
+		.enable_reg = 0x2024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup1_i2c_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup1_i2c_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
+	.halt_reg = 0x02020,
+	.clkr = {
+		.enable_reg = 0x02020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup1_spi_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup1_spi_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
+	.halt_reg = 0x03024,
+	.clkr = {
+		.enable_reg = 0x03024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup2_i2c_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup2_i2c_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
+	.halt_reg = 0x03020,
+	.clkr = {
+		.enable_reg = 0x03020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup2_spi_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup2_spi_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
+	.halt_reg = 0x04024,
+	.clkr = {
+		.enable_reg = 0x04024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup3_i2c_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup3_i2c_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
+	.halt_reg = 0x04020,
+	.clkr = {
+		.enable_reg = 0x04020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup3_spi_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup3_spi_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
+	.halt_reg = 0x05024,
+	.clkr = {
+		.enable_reg = 0x05024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup4_i2c_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup4_i2c_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
+	.halt_reg = 0x05020,
+	.clkr = {
+		.enable_reg = 0x05020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup4_spi_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup4_spi_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
+	.halt_reg = 0x06024,
+	.clkr = {
+		.enable_reg = 0x06024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup5_i2c_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup5_i2c_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
+	.halt_reg = 0x06020,
+	.clkr = {
+		.enable_reg = 0x06020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup5_spi_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup5_spi_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
+	.halt_reg = 0x07024,
+	.clkr = {
+		.enable_reg = 0x07024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup6_i2c_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
+	.halt_reg = 0x07020,
+	.clkr = {
+		.enable_reg = 0x07020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_qup6_spi_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_qup6_spi_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_uart1_apps_clk = {
+	.halt_reg = 0x02040,
+	.clkr = {
+		.enable_reg = 0x02040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_uart1_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_uart1_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_uart2_apps_clk = {
+	.halt_reg = 0x03040,
+	.clkr = {
+		.enable_reg = 0x03040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_uart2_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_uart2_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_uart3_apps_clk = {
+	.halt_reg = 0x04054,
+	.clkr = {
+		.enable_reg = 0x04054,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_uart3_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_uart3_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_uart4_apps_clk = {
+	.halt_reg = 0x05040,
+	.clkr = {
+		.enable_reg = 0x05040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_uart4_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_uart4_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_uart5_apps_clk = {
+	.halt_reg = 0x06040,
+	.clkr = {
+		.enable_reg = 0x06040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_uart5_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_uart5_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_uart6_apps_clk = {
+	.halt_reg = 0x07040,
+	.clkr = {
+		.enable_reg = 0x07040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_uart6_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&blsp1_uart6_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {
+	F(240000000, P_GPLL4, 5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 pcie0_axi_m_clk_src = {
+	.cmd_rcgr = 0x28018,
+	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie0_axi_m_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie0_axi_m_clk = {
+	.halt_reg = 0x28038,
+	.clkr = {
+		.enable_reg = 0x28038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie0_axi_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie0_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {
+	.halt_reg = 0x2E07C,
+	.clkr = {
+		.enable_reg = 0x2E07C,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc_pcie0_1lane_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie0_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie1_axi_m_clk_src = {
+	.cmd_rcgr = 0x29018,
+	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie1_axi_m_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie1_axi_m_clk = {
+	.halt_reg = 0x29038,
+	.clkr = {
+		.enable_reg = 0x29038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie1_axi_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie1_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {
+	.halt_reg = 0x2E08C,
+	.clkr = {
+		.enable_reg = 0x2E08C,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc_pcie1_1lane_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie1_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {
+	F(342857143, P_GPLL4, 3.5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 pcie2_axi_m_clk_src = {
+	.cmd_rcgr = 0x2a018,
+	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie2_axi_m_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie2_axi_m_clk = {
+	.halt_reg = 0x2a038,
+	.clkr = {
+		.enable_reg = 0x2a038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie2_axi_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie2_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {
+	.halt_reg = 0x2E080,
+	.clkr = {
+		.enable_reg = 0x2E080,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc_pcie2_2lane_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie2_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie3_axi_m_clk_src = {
+	.cmd_rcgr = 0x2b018,
+	.freq_tbl = ftbl_pcie2_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie3_axi_m_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie3_axi_m_clk = {
+	.halt_reg = 0x2b038,
+	.clkr = {
+		.enable_reg = 0x2b038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie3_axi_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie3_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {
+	.halt_reg = 0x2E090,
+	.clkr = {
+		.enable_reg = 0x2E090,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc_pcie3_2lane_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie3_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie0_axi_s_clk_src = {
+	.cmd_rcgr = 0x28020,
+	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie0_axi_s_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie0_axi_s_clk = {
+	.halt_reg = 0x2803c,
+	.clkr = {
+		.enable_reg = 0x2803c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie0_axi_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie0_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {
+	.halt_reg = 0x28040,
+	.clkr = {
+		.enable_reg = 0x28040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie0_axi_s_bridge_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie0_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {
+	.halt_reg = 0x2E048,
+	.clkr = {
+		.enable_reg = 0x2E048,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_snoc_pcie0_1lane_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie0_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie1_axi_s_clk_src = {
+	.cmd_rcgr = 0x29020,
+	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie1_axi_s_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie1_axi_s_clk = {
+	.halt_reg = 0x2903c,
+	.clkr = {
+		.enable_reg = 0x2903c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie1_axi_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie1_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {
+	.halt_reg = 0x29040,
+	.clkr = {
+		.enable_reg = 0x29040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie1_axi_s_bridge_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie1_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {
+	.halt_reg = 0x2E04C,
+	.clkr = {
+		.enable_reg = 0x2E04C,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_snoc_pcie1_1lane_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie1_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie2_axi_s_clk_src = {
+	.cmd_rcgr = 0x2a020,
+	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie2_axi_s_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie2_axi_s_clk = {
+	.halt_reg = 0x2a03c,
+	.clkr = {
+		.enable_reg = 0x2a03c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie2_axi_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie2_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {
+	.halt_reg = 0x2a040,
+	.clkr = {
+		.enable_reg = 0x2a040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie2_axi_s_bridge_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie2_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {
+	.halt_reg = 0x2E050,
+	.clkr = {
+		.enable_reg = 0x2E050,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_snoc_pcie2_2lane_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie2_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie3_axi_s_clk_src = {
+	.cmd_rcgr = 0x2b020,
+	.freq_tbl = ftbl_pcie0_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie3_axi_s_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie3_axi_s_clk = {
+	.halt_reg = 0x2b03c,
+	.clkr = {
+		.enable_reg = 0x2b03c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie3_axi_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie3_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {
+	.halt_reg = 0x2b040,
+	.clkr = {
+		.enable_reg = 0x2b040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie3_axi_s_bridge_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie3_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {
+	.halt_reg = 0x2E054,
+	.clkr = {
+		.enable_reg = 0x2E054,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_snoc_pcie3_2lane_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie3_axi_s_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_regmap_mux pcie0_pipe_clk_src = {
+	.reg = 0x28064,
+	.shift = 8,
+	.width = 2,
+	.parent_map = gcc_pcie30_phy0_pipe_clk_xo_map,
+	.clkr = {
+		.hw.init = &(struct clk_init_data) {
+			.name = "pcie0_pipe_clk_src",
+			.parent_data = gcc_pcie30_phy0_pipe_clk_xo,
+			.num_parents = ARRAY_SIZE(gcc_pcie30_phy0_pipe_clk_xo),
+			.ops = &clk_regmap_mux_closest_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
+static struct clk_regmap_mux pcie1_pipe_clk_src = {
+	.reg = 0x29064,
+	.shift = 8,
+	.width = 2,
+	.parent_map = gcc_pcie30_phy1_pipe_clk_xo_map,
+	.clkr = {
+		.hw.init = &(struct clk_init_data) {
+			.name = "pcie1_pipe_clk_src",
+			.parent_data = gcc_pcie30_phy1_pipe_clk_xo,
+			.num_parents = ARRAY_SIZE(gcc_pcie30_phy1_pipe_clk_xo),
+			.ops = &clk_regmap_mux_closest_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
+static struct clk_regmap_mux pcie2_pipe_clk_src = {
+	.reg = 0x2a064,
+	.shift = 8,
+	.width = 2,
+	.parent_map = gcc_pcie30_phy2_pipe_clk_xo_map,
+	.clkr = {
+		.hw.init = &(struct clk_init_data) {
+			.name = "pcie2_pipe_clk_src",
+			.parent_data = gcc_pcie30_phy2_pipe_clk_xo,
+			.num_parents = ARRAY_SIZE(gcc_pcie30_phy2_pipe_clk_xo),
+			.ops = &clk_regmap_mux_closest_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
+static struct clk_regmap_mux pcie3_pipe_clk_src = {
+	.reg = 0x2b064,
+	.shift = 8,
+	.width = 2,
+	.parent_map = gcc_pcie30_phy3_pipe_clk_xo_map,
+	.clkr = {
+		.hw.init = &(struct clk_init_data) {
+			.name = "pcie3_pipe_clk_src",
+			.parent_data = gcc_pcie30_phy3_pipe_clk_xo,
+			.num_parents = ARRAY_SIZE(gcc_pcie30_phy3_pipe_clk_xo),
+			.ops = &clk_regmap_mux_closest_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 pcie0_rchng_clk_src = {
+	.cmd_rcgr = 0x28028,
+	.freq_tbl = ftbl_pcie_rchng_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie0_rchng_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie0_rchng_clk = {
+	.halt_reg = 0x28028,
+	.clkr = {
+		.enable_reg = 0x28028,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie0_rchng_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie0_rchng_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie1_rchng_clk_src = {
+	.cmd_rcgr = 0x29028,
+	.freq_tbl = ftbl_pcie_rchng_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie1_rchng_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie1_rchng_clk = {
+	.halt_reg = 0x29028,
+	.clkr = {
+		.enable_reg = 0x29028,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie1_rchng_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie1_rchng_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie2_rchng_clk_src = {
+	.cmd_rcgr = 0x2a028,
+	.freq_tbl = ftbl_pcie_rchng_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie2_rchng_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie2_rchng_clk = {
+	.halt_reg = 0x2a028,
+	.clkr = {
+		.enable_reg = 0x2a028,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie2_rchng_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie2_rchng_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_rcg2 pcie3_rchng_clk_src = {
+	.cmd_rcgr = 0x2b028,
+	.freq_tbl = ftbl_pcie_rchng_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie3_rchng_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie3_rchng_clk = {
+	.halt_reg = 0x2b028,
+	.clkr = {
+		.enable_reg = 0x2b028,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie3_rchng_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie3_rchng_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {
+	F(20000000, P_GPLL0, 10, 1, 4),
+	{ }
+};
+
+static struct clk_rcg2 pcie_aux_clk_src = {
+	.cmd_rcgr = 0x28004,
+	.freq_tbl = ftbl_pcie_aux_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcie_aux_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_pcie0_aux_clk = {
+	.halt_reg = 0x28034,
+	.clkr = {
+		.enable_reg = 0x28034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie0_aux_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie_aux_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie1_aux_clk = {
+	.halt_reg = 0x29034,
+	.clkr = {
+		.enable_reg = 0x29034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie1_aux_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie_aux_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie2_aux_clk = {
+	.halt_reg = 0x2a034,
+	.clkr = {
+		.enable_reg = 0x2a034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie2_aux_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie_aux_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie3_aux_clk = {
+	.halt_reg = 0x2b034,
+	.clkr = {
+		.enable_reg = 0x2b034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie3_aux_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcie_aux_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_usb_aux_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 usb0_aux_clk_src = {
+	.cmd_rcgr = 0x2c018,
+	.freq_tbl = ftbl_usb_aux_clk_src,
+	.mnd_width = 16,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "usb0_aux_clk_src",
+		.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_usb0_aux_clk = {
+	.halt_reg = 0x2c048,
+	.clkr = {
+		.enable_reg = 0x2c048,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_usb0_aux_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&usb0_aux_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_usb0_master_clk_src[] = {
+	F(100000000, P_GPLL0, 8, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 usb0_master_clk_src = {
+	.cmd_rcgr = 0x2c004,
+	.freq_tbl = ftbl_usb0_master_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "usb0_master_clk_src",
+		.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_usb0_master_clk = {
+	.halt_reg = 0x2c044,
+	.clkr = {
+		.enable_reg = 0x2c044,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_usb0_master_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&usb0_master_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_snoc_usb_clk = {
+	.halt_reg = 0x2E058,
+	.clkr = {
+		.enable_reg = 0x2E058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_snoc_usb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&usb0_master_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc_usb_axi_clk = {
+	.halt_reg = 0x2E084,
+	.clkr = {
+		.enable_reg = 0x2E084,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc_usb_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&usb0_master_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(60000000, P_GPLL4, 10, 1, 2),
+	{ }
+};
+
+static struct clk_rcg2 usb0_mock_utmi_clk_src = {
+	.cmd_rcgr = 0x2c02c,
+	.freq_tbl = ftbl_usb0_mock_utmi_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "usb0_mock_utmi_clk_src",
+		.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {
+	.reg = 0x2c040,
+	.shift = 0,
+	.width = 2,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "usb0_mock_utmi_div_clk_src",
+		.parent_data = &(const struct clk_parent_data) {
+			.hw = &usb0_mock_utmi_clk_src.clkr.hw,
+		},
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_regmap_div_ro_ops,
+	},
+};
+
+static struct clk_branch gcc_usb0_mock_utmi_clk = {
+	.halt_reg = 0x2c04c,
+	.clkr = {
+		.enable_reg = 0x2c04c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_usb0_mock_utmi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&usb0_mock_utmi_div_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_regmap_mux usb0_pipe_clk_src = {
+	.reg = 0x2C074,
+	.shift = 8,
+	.width = 2,
+	.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,
+	.clkr = {
+		.hw.init = &(struct clk_init_data) {
+			.name = "usb0_pipe_clk_src",
+			.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,
+			.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),
+			.ops = &clk_regmap_mux_closest_ops,
+			.flags = CLK_SET_RATE_PARENT,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {
+	F(144000, P_XO, 16, 12, 125),
+	F(400000, P_XO, 12, 1, 5),
+	F(24000000, P_GPLL2, 12, 1, 4),
+	F(48000000, P_GPLL2, 12, 1, 2),
+	F(96000000, P_GPLL2, 12, 0, 0),
+	F(177777778, P_GPLL0, 4.5, 0, 0),
+	F(192000000, P_GPLL2, 6, 0, 0),
+	F(384000000, P_GPLL2, 3, 0, 0),
+	F(400000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 sdcc1_apps_clk_src = {
+	.cmd_rcgr = 0x33004,
+	.freq_tbl = ftbl_sdcc_apps_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "sdcc1_apps_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_sdcc1_apps_clk = {
+	.halt_reg = 0x3302c,
+	.clkr = {
+		.enable_reg = 0x3302c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sdcc1_apps_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&sdcc1_apps_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {
+	F(150000000, P_GPLL4, 8, 0, 0),
+	F(300000000, P_GPLL4, 4, 0, 0),
+};
+
+static struct clk_rcg2 sdcc1_ice_core_clk_src = {
+	.cmd_rcgr = 0x33018,
+	.freq_tbl = ftbl_sdcc_ice_core_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "sdcc1_ice_core_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_sdcc1_ice_core_clk = {
+	.halt_reg = 0x33030,
+	.clkr = {
+		.enable_reg = 0x33030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sdcc1_ice_core_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&sdcc1_ice_core_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(50000000, P_GPLL0, 16, 0, 0),
+	F(80000000, P_GPLL0, 10, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
+	.cmd_rcgr = 0x31004,
+	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "pcnoc_bfdcd_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+		.flags = CLK_IS_CRITICAL,
+	},
+};
+
+static struct clk_fixed_factor pcnoc_clk_src = {
+	.mult = 1,
+	.div = 1,
+	.hw.init = &(struct clk_init_data) {
+		.name = "pcnoc_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&pcnoc_bfdcd_clk_src.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_branch gcc_nsscfg_clk = {
+	.halt_reg = 0x1702c,
+	.clkr = {
+		.enable_reg = 0x1702c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nsscfg_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_nsscc_clk = {
+	.halt_reg = 0x17030,
+	.clkr = {
+		.enable_reg = 0x17030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_nsscc_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nsscc_clk = {
+	.halt_reg = 0x17034,
+	.clkr = {
+		.enable_reg = 0x17034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nsscc_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {
+	.halt_reg = 0x17080,
+	.clkr = {
+		.enable_reg = 0x17080,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_pcnoc_1_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_dap_ahb_clk = {
+	.halt_reg = 0x2D064,
+	.clkr = {
+		.enable_reg = 0x2D064,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_dap_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_cfg_ahb_clk = {
+	.halt_reg = 0x2D068,
+	.clkr = {
+		.enable_reg = 0x2D068,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_cfg_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_snoc_pcnoc_ahb_clk = {
+	.halt_reg = 0x2E03C,
+	.clkr = {
+		.enable_reg = 0x2E03C,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_snoc_pcnoc_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc_pcnoc_ahb_clk = {
+	.halt_reg = 0x2E094,
+	.clkr = {
+		.enable_reg = 0x2E094,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc_pcnoc_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qpic_ahb_clk = {
+	.halt_reg = 0x32010,
+	.clkr = {
+		.enable_reg = 0x32010,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qpic_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qpic_clk = {
+	.halt_reg = 0x32014,
+	.clkr = {
+		.enable_reg = 0x32014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qpic_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_blsp1_ahb_clk = {
+	.halt_reg = 0x01004,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x0b004,
+		.enable_mask = BIT(4),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_blsp1_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mdio_ahb_clk = {
+	.halt_reg = 0x17040,
+	.clkr = {
+		.enable_reg = 0x17040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_mdio_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_prng_ahb_clk = {
+	.halt_reg = 0x13024,
+	.halt_check = BRANCH_HALT_VOTED,
+	.clkr = {
+		.enable_reg = 0x0b004,
+		.enable_mask = BIT(10),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_prng_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_uniphy0_ahb_clk = {
+	.halt_reg = 0x1704c,
+	.clkr = {
+		.enable_reg = 0x1704c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_uniphy0_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_uniphy1_ahb_clk = {
+	.halt_reg = 0x1705c,
+	.clkr = {
+		.enable_reg = 0x1705c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_uniphy1_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_uniphy2_ahb_clk = {
+	.halt_reg = 0x1706c,
+	.clkr = {
+		.enable_reg = 0x1706c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_uniphy2_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {
+	.halt_reg = 0x3a004,
+	.clkr = {
+		.enable_reg = 0x3a004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_cmn_12gpll_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_cmn_12gpll_apu_clk = {
+	.halt_reg = 0x3a00c,
+	.clkr = {
+		.enable_reg = 0x3a00c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_cmn_12gpll_apu_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie0_ahb_clk = {
+	.halt_reg = 0x28030,
+	.clkr = {
+		.enable_reg = 0x28030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie0_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie1_ahb_clk = {
+	.halt_reg = 0x29030,
+	.clkr = {
+		.enable_reg = 0x29030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie1_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie2_ahb_clk = {
+	.halt_reg = 0x2a030,
+	.clkr = {
+		.enable_reg = 0x2a030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie2_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcie3_ahb_clk = {
+	.halt_reg = 0x2b030,
+	.clkr = {
+		.enable_reg = 0x2b030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcie3_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {
+	.halt_reg = 0x2c05c,
+	.clkr = {
+		.enable_reg = 0x2c05c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_usb0_phy_cfg_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_sdcc1_ahb_clk = {
+	.halt_reg = 0x33034,
+	.clkr = {
+		.enable_reg = 0x33034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sdcc1_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&pcnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(133333333, P_GPLL0, 6, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	F(342850000, P_GPLL4, 3.5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 system_noc_bfdcd_clk_src = {
+	.cmd_rcgr = 0x2e004,
+	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "system_noc_bfdcd_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
+		.ops = &clk_rcg2_ops,
+		.flags = CLK_IS_CRITICAL,
+	},
+};
+
+static struct clk_branch gcc_q6ss_boot_clk = {
+	.halt_reg = 0x25080,
+	.halt_check = BRANCH_HALT_SKIP,
+	.clkr = {
+		.enable_reg = 0x25080,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6ss_boot_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_snoc_clk = {
+	.halt_reg = 0x17028,
+	.clkr = {
+		.enable_reg = 0x17028,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_snoc_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_snoc_1_clk = {
+	.halt_reg = 0x1707c,
+	.clkr = {
+		.enable_reg = 0x1707c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_snoc_1_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_etr_usb_clk = {
+	.halt_reg = 0x2D060,
+	.clkr = {
+		.enable_reg = 0x2D060,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_etr_usb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(133333333, P_GPLL0, 6, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 wcss_ahb_clk_src = {
+	.cmd_rcgr = 0x25030,
+	.freq_tbl = ftbl_wcss_ahb_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "wcss_ahb_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_q6_ahb_clk = {
+	.halt_reg = 0x25014,
+	.clkr = {
+		.enable_reg = 0x25014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&wcss_ahb_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_q6_ahb_s_clk = {
+	.halt_reg = 0x25018,
+	.clkr = {
+		.enable_reg = 0x25018,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6_ahb_s_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&wcss_ahb_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wcss_ecahb_clk = {
+	.halt_reg = 0x25058,
+	.clkr = {
+		.enable_reg = 0x25058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_wcss_ecahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&wcss_ahb_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wcss_acmt_clk = {
+	.halt_reg = 0x2505c,
+	.clkr = {
+		.enable_reg = 0x2505c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_wcss_acmt_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&wcss_ahb_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_sys_noc_axi_clk = {
+	.halt_reg = 0x2e01c,
+	.clkr = {
+		.enable_reg = 0x2e01c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sys_noc_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc0_axi_clk = {
+	.halt_reg = 0x2e078,
+	.clkr = {
+		.enable_reg = 0x2e078,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc0_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc1_axi_clk = {
+	.halt_reg = 0x2e088,
+	.clkr = {
+		.enable_reg = 0x2e088,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc1_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc0_tbu_clk = {
+	.halt_reg = 0x12038,
+	.clkr = {
+		.enable_reg = 0xb00c,
+		.enable_mask = BIT(3),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc0_tbu_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_anoc1_tbu_clk = {
+	.halt_reg = 0x12048,
+	.clkr = {
+		.enable_reg = 0xb00c,
+		.enable_mask = BIT(5),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc1_tbu_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mem_noc_snoc_axi_clk = {
+	.halt_reg = 0x19018,
+	.clkr = {
+		.enable_reg = 0x19018,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_mem_noc_snoc_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_imem_axi_clk = {
+	.halt_reg = 0xe004,
+	.clkr = {
+		.enable_reg = 0xb004,
+		.enable_mask = BIT(12),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_imem_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&system_noc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
+	.halt_reg = 0x2e030,
+	.clkr = {
+		.enable_reg = 0x2e030,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sys_noc_wcss_ahb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&wcss_ahb_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(133333333, P_GPLL0, 6, 0, 0),
+	F(266666667, P_GPLL0, 3, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 wcss_axi_m_clk_src = {
+	.cmd_rcgr = 0x25078,
+	.freq_tbl = ftbl_wcss_axi_m_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "wcss_axi_m_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
+	.halt_reg = 0x2e0a8,
+	.clkr = {
+		.enable_reg = 0x2e0a8,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_anoc_wcss_axi_m_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&wcss_axi_m_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
+	F(240000000, P_GPLL4, 5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 qdss_at_clk_src = {
+	.cmd_rcgr = 0x2d004,
+	.freq_tbl = ftbl_qdss_at_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "qdss_at_clk_src",
+		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_q6ss_atbm_clk = {
+	.halt_reg = 0x2501c,
+	.clkr = {
+		.enable_reg = 0x2501c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6ss_atbm_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_at_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
+	.halt_reg = 0x2503c,
+	.clkr = {
+		.enable_reg = 0x2503c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_wcss_dbg_ifc_atb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_at_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_atb_clk = {
+	.halt_reg = 0x17014,
+	.clkr = {
+		.enable_reg = 0x17014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_atb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_at_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_at_clk = {
+	.halt_reg = 0x2D038,
+	.clkr = {
+		.enable_reg = 0x2D038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_at_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_at_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_sys_noc_at_clk = {
+	.halt_reg = 0x2e038,
+	.clkr = {
+		.enable_reg = 0x2e038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sys_noc_at_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_at_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcnoc_at_clk = {
+	.halt_reg = 0x31024,
+	.clkr = {
+		.enable_reg = 0x31024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcnoc_at_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_at_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
+	.mult = 1,
+	.div = 6,
+	.hw.init = &(struct clk_init_data) {
+		.name = "gcc_eud_at_div_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&qdss_at_clk_src.clkr.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
+static struct clk_branch gcc_usb0_eud_at_clk = {
+	.halt_reg = 0x30004,
+	.clkr = {
+		.enable_reg = 0x30004,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_usb0_eud_at_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&gcc_eud_at_div_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_eud_at_clk = {
+	.halt_reg = 0x2D06C,
+	.clkr = {
+		.enable_reg = 0x2D06C,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_eud_at_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&gcc_eud_at_div_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 qdss_stm_clk_src = {
+	.cmd_rcgr = 0x2D00C,
+	.freq_tbl = ftbl_qdss_stm_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "qdss_stm_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_qdss_stm_clk = {
+	.halt_reg = 0x2D03C,
+	.clkr = {
+		.enable_reg = 0x2D03C,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_stm_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_stm_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
+	.halt_reg = 0x2E034,
+	.clkr = {
+		.enable_reg = 0x2E034,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_sys_noc_qdss_stm_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_stm_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
+	F(300000000, P_GPLL4, 4, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 qdss_traceclkin_clk_src = {
+	.cmd_rcgr = 0x2d014,
+	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "qdss_traceclkin_clk_src",
+		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_qdss_traceclkin_clk = {
+	.halt_reg = 0x2D040,
+	.clkr = {
+		.enable_reg = 0x2D040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_traceclkin_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_traceclkin_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
+	F(600000000, P_GPLL4, 2, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 qdss_tsctr_clk_src = {
+	.cmd_rcgr = 0x2d01c,
+	.freq_tbl = ftbl_qdss_tsctr_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "qdss_tsctr_clk_src",
+		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
+	.mult = 1,
+	.div = 2,
+	.hw.init = &(struct clk_init_data) {
+		.name = "qdss_tsctr_div2_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&qdss_tsctr_clk_src.clkr.hw },
+		.num_parents = 1,
+		.flags = CLK_SET_RATE_PARENT,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
+static struct clk_branch gcc_q6_tsctr_1to2_clk = {
+	.halt_reg = 0x25020,
+	.clkr = {
+		.enable_reg = 0x25020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6_tsctr_1to2_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div2_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
+	.halt_reg = 0x25040,
+	.clkr = {
+		.enable_reg = 0x25040,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_wcss_dbg_ifc_nts_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div2_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_tsctr_div2_clk = {
+	.halt_reg = 0x2d044,
+	.clkr = {
+		.enable_reg = 0x2d044,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_tsctr_div2_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div2_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 uniphy_sys_clk_src = {
+	.cmd_rcgr = 0x17090,
+	.freq_tbl = ftbl_uniphy_sys_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "uniphy_sys_clk_src",
+		.parent_data = gcc_xo_data,
+		.num_parents = ARRAY_SIZE(gcc_xo_data),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 nss_ts_clk_src = {
+	.cmd_rcgr = 0x17088,
+	.freq_tbl = ftbl_uniphy_sys_clk_src,
+	.mnd_width = 8,
+	.hid_width = 5,
+	.parent_map = gcc_xo_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "nss_ts_clk_src",
+		.parent_data = gcc_xo_data,
+		.num_parents = ARRAY_SIZE(gcc_xo_data),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_qdss_ts_clk = {
+	.halt_reg = 0x2D078,
+	.clkr = {
+		.enable_reg = 0x2D078,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_ts_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&nss_ts_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_snoc_ts_clk = {
+	.halt_reg = 0x2e068,
+	.clkr = {
+		.enable_reg = 0x2e068,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_snoc_ts_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div2_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mem_noc_ts_clk = {
+	.halt_reg = 0x19028,
+	.clkr = {
+		.enable_reg = 0x19028,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_mem_noc_ts_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div2_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_fixed_factor qdss_dap_sync_clk_src = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data) {
+		.name = "qdss_dap_sync_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&qdss_tsctr_clk_src.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
+static struct clk_branch gcc_qdss_tsctr_div4_clk = {
+	.halt_reg = 0x2d04c,
+	.clkr = {
+		.enable_reg = 0x2d04c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_tsctr_div4_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
+	.mult = 1,
+	.div = 8,
+	.hw.init = &(struct clk_init_data) {
+		.name = "qdss_tsctr_div8_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&qdss_tsctr_clk_src.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
+static struct clk_branch gcc_nss_ts_clk = {
+	.halt_reg = 0x17018,
+	.clkr = {
+		.enable_reg = 0x17018,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nss_ts_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&nss_ts_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_tsctr_div8_clk = {
+	.halt_reg = 0x2d050,
+	.clkr = {
+		.enable_reg = 0x2d050,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_tsctr_div8_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div8_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcnoc_ts_clk = {
+	.halt_reg = 0x3102c,
+	.clkr = {
+		.enable_reg = 0x3102c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcnoc_ts_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div8_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
+	.mult = 1,
+	.div = 16,
+	.hw.init = &(struct clk_init_data) {
+		.name = "qdss_tsctr_div16_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&qdss_tsctr_clk_src.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
+static struct clk_branch gcc_qdss_tsctr_div16_clk = {
+	.halt_reg = 0x2d054,
+	.clkr = {
+		.enable_reg = 0x2d054,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_tsctr_div16_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div16_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_q6ss_pclkdbg_clk = {
+	.halt_reg = 0x25024,
+	.clkr = {
+		.enable_reg = 0x25024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6ss_pclkdbg_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_q6ss_trig_clk = {
+	.halt_reg = 0x25068,
+	.clkr = {
+		.enable_reg = 0x25068,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6ss_trig_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
+	.halt_reg = 0x25038,
+	.clkr = {
+		.enable_reg = 0x25038,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_wcss_dbg_ifc_apb_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
+	.halt_reg = 0x25044,
+	.clkr = {
+		.enable_reg = 0x25044,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_dap_clk = {
+	.halt_reg = 0x2d058,
+	.clkr = {
+		.enable_reg = 0x2d058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_dap_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_qdss_apb2jtag_clk = {
+	.halt_reg = 0x2d05c,
+	.clkr = {
+		.enable_reg = 0x2d05c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_apb2jtag_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_pcnoc_dcc_clk = {
+	.halt_reg = 0x31080,
+	.clkr = {
+		.enable_reg = 0x31080,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_pcnoc_dcc_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_dap_sync_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
+	.mult = 1,
+	.div = 3,
+	.hw.init = &(struct clk_init_data) {
+		.name = "qdss_tsctr_div3_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&qdss_tsctr_clk_src.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+	},
+};
+
+static struct clk_branch gcc_qdss_tsctr_div3_clk = {
+	.halt_reg = 0x2d048,
+	.clkr = {
+		.enable_reg = 0x2d048,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qdss_tsctr_div3_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qdss_tsctr_div3_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	F(320000000, P_GPLL0, 2.5, 0, 0),
+	F(400000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 qpic_io_macro_clk_src = {
+	.cmd_rcgr = 0x32004,
+	.freq_tbl = ftbl_qpic_io_macro_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "qpic_io_macro_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_qpic_io_macro_clk = {
+	.halt_reg = 0x3200c,
+	.clkr = {
+		.enable_reg = 0x3200c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_qpic_io_macro_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&qpic_io_macro_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
+	F(533333333, P_GPLL0, 1.5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 q6_axi_clk_src = {
+	.cmd_rcgr = 0x25004,
+	.freq_tbl = ftbl_q6_axi_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "q6_axi_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_q6_axim_clk = {
+	.halt_reg = 0x2500c,
+	.clkr = {
+		.enable_reg = 0x2500c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_q6_axim_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&q6_axi_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_wcss_q6_tbu_clk = {
+	.halt_reg = 0x12050,
+	.halt_check = BRANCH_HALT_DELAY,
+	.clkr = {
+		.enable_reg = 0xb00c,
+		.enable_mask = BIT(6),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_wcss_q6_tbu_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&q6_axi_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mem_noc_q6_axi_clk = {
+	.halt_reg = 0x19010,
+	.clkr = {
+		.enable_reg = 0x19010,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_mem_noc_q6_axi_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&q6_axi_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
+	F(342857143, P_GPLL4, 3.5, 0, 0),
+	{ }
+};
+
+static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
+	{ P_XO, 0 },
+	{ P_GPLL0, 1 },
+	{ P_GPLL4, 2 },
+	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
+};
+
+static struct clk_rcg2 q6_axim2_clk_src = {
+	.cmd_rcgr = 0x25028,
+	.freq_tbl = ftbl_q6_axim2_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "q6_axim2_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
+	F(533333333, P_GPLL0, 1.5, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
+	.cmd_rcgr = 0x17004,
+	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "nssnoc_memnoc_bfdcd_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_nssnoc_memnoc_clk = {
+	.halt_reg = 0x17024,
+	.clkr = {
+		.enable_reg = 0x17024,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_memnoc_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
+	.halt_reg = 0x17084,
+	.clkr = {
+		.enable_reg = 0x17084,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_mem_noc_1_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nss_tbu_clk = {
+	.halt_reg = 0x12040,
+	.clkr = {
+		.enable_reg = 0xb00c,
+		.enable_mask = BIT(4),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nss_tbu_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_mem_noc_nssnoc_clk = {
+	.halt_reg = 0x19014,
+	.clkr = {
+		.enable_reg = 0x19014,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_mem_noc_nssnoc_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
+	F(133333333, P_GPLL0, 6, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 lpass_axim_clk_src = {
+	.cmd_rcgr = 0x2700c,
+	.freq_tbl = ftbl_lpass_axim_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "lpass_axim_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 lpass_sway_clk_src = {
+	.cmd_rcgr = 0x27004,
+	.freq_tbl = ftbl_lpass_axim_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "lpass_sway_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(100000000, P_GPLL0, 8, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 adss_pwm_clk_src = {
+	.cmd_rcgr = 0x1c004,
+	.freq_tbl = ftbl_adss_pwm_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "adss_pwm_clk_src",
+		.parent_data = gcc_xo_gpll0,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_adss_pwm_clk = {
+	.halt_reg = 0x1c00c,
+	.clkr = {
+		.enable_reg = 0x1c00c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_adss_pwm_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&adss_pwm_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static const struct freq_tbl ftbl_gp1_clk_src[] = {
+	F(24000000, P_XO, 1, 0, 0),
+	F(200000000, P_GPLL0, 4, 0, 0),
+	{ }
+};
+
+static struct clk_rcg2 gp1_clk_src = {
+	.cmd_rcgr = 0x8004,
+	.freq_tbl = ftbl_gp1_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "gp1_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 gp2_clk_src = {
+	.cmd_rcgr = 0x9004,
+	.freq_tbl = ftbl_gp1_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "gp2_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_rcg2 gp3_clk_src = {
+	.cmd_rcgr = 0xa004,
+	.freq_tbl = ftbl_gp1_clk_src,
+	.hid_width = 5,
+	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
+	.clkr.hw.init = &(struct clk_init_data) {
+		.name = "gp3_clk_src",
+		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
+		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
+		.ops = &clk_rcg2_ops,
+	},
+};
+
+static struct clk_branch gcc_xo_clk_src = {
+	.halt_reg = 0x34004,
+	.clkr = {
+		.enable_reg = 0x34004,
+		.enable_mask = BIT(1),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_xo_clk_src",
+			.parent_data = gcc_xo_data,
+			.num_parents = ARRAY_SIZE(gcc_xo_data),
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
+	.halt_reg = 0x17074,
+	.clkr = {
+		.enable_reg = 0x17074,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_xo_dcd_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&gcc_xo_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_xo_clk = {
+	.halt_reg = 0x34018,
+	.clkr = {
+		.enable_reg = 0x34018,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_xo_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&gcc_xo_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_uniphy0_sys_clk = {
+	.halt_reg = 0x17048,
+	.clkr = {
+		.enable_reg = 0x17048,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_uniphy0_sys_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&uniphy_sys_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_uniphy1_sys_clk = {
+	.halt_reg = 0x17058,
+	.clkr = {
+		.enable_reg = 0x17058,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_uniphy1_sys_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&uniphy_sys_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_uniphy2_sys_clk = {
+	.halt_reg = 0x17068,
+	.clkr = {
+		.enable_reg = 0x17068,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_uniphy2_sys_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&uniphy_sys_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_cmn_12gpll_sys_clk = {
+	.halt_reg = 0x3a008,
+	.clkr = {
+		.enable_reg = 0x3a008,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_cmn_12gpll_sys_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&uniphy_sys_clk_src.clkr.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_fixed_factor gcc_xo_div4_clk_src = {
+	.mult = 1,
+	.div = 4,
+	.hw.init = &(struct clk_init_data) {
+		.name = "gcc_xo_div4_clk_src",
+		.parent_hws = (const struct clk_hw *[]) {
+				&gcc_xo_clk_src.clkr.hw },
+		.num_parents = 1,
+		.ops = &clk_fixed_factor_ops,
+		.flags = CLK_SET_RATE_PARENT,
+	},
+};
+
+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
+	.halt_reg = 0x1701c,
+	.clkr = {
+		.enable_reg = 0x1701c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_qosgen_ref_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&gcc_xo_div4_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
+	.halt_reg = 0x17020,
+	.clkr = {
+		.enable_reg = 0x17020,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_nssnoc_timeout_ref_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&gcc_xo_div4_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_branch gcc_xo_div4_clk = {
+	.halt_reg = 0x3401c,
+	.clkr = {
+		.enable_reg = 0x3401c,
+		.enable_mask = BIT(0),
+		.hw.init = &(struct clk_init_data) {
+			.name = "gcc_xo_div4_clk",
+			.parent_hws = (const struct clk_hw *[]) {
+					&gcc_xo_div4_clk_src.hw },
+			.num_parents = 1,
+			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
+			.ops = &clk_branch2_ops,
+		},
+	},
+};
+
+static struct clk_hw *gcc_ipq9574_hws[] = {
+	&gpll0_out_main_div2.hw,
+	&gcc_xo_div4_clk_src.hw,
+	&qdss_dap_sync_clk_src.hw,
+	&qdss_tsctr_div2_clk_src.hw,
+	&qdss_tsctr_div8_clk_src.hw,
+	&qdss_tsctr_div16_clk_src.hw,
+	&qdss_tsctr_div3_clk_src.hw,
+	&gcc_eud_at_div_clk_src.hw,
+	&pcnoc_clk_src.hw,
+};
+
+static int clk_dummy_is_enabled(struct clk_hw *hw)
+{
+	return 1;
+};
+
+static int clk_dummy_enable(struct clk_hw *hw)
+{
+	return 0;
+};
+
+static void clk_dummy_disable(struct clk_hw *hw)
+{
+	return;
+};
+
+static u8 clk_dummy_get_parent(struct clk_hw *hw)
+{
+	return 0;
+};
+
+static int clk_dummy_set_parent(struct clk_hw *hw, u8 index)
+{
+	return 0;
+};
+
+static int clk_dummy_set_rate(struct clk_hw *hw, unsigned long rate,
+			      unsigned long parent_rate)
+{
+	return 0;
+};
+
+static int clk_dummy_determine_rate(struct clk_hw *hw,
+				    struct clk_rate_request *req)
+{
+	return 0;
+};
+
+static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw,
+					   unsigned long parent_rate)
+{
+	return parent_rate;
+};
+
+static const struct clk_ops clk_dummy_ops = {
+	.is_enabled = clk_dummy_is_enabled,
+	.enable = clk_dummy_enable,
+	.disable = clk_dummy_disable,
+	.get_parent = clk_dummy_get_parent,
+	.set_parent = clk_dummy_set_parent,
+	.set_rate = clk_dummy_set_rate,
+	.recalc_rate = clk_dummy_recalc_rate,
+	.determine_rate = clk_dummy_determine_rate,
+};
+
+#define DEFINE_DUMMY_CLK(clk_name)				\
+(&(struct clk_regmap) {						\
+	.hw.init = &(struct clk_init_data) {			\
+		.name = #clk_name,				\
+		.parent_names = (const char *[]) { "xo"},	\
+		.num_parents = 1,				\
+		.ops = &clk_dummy_ops,				\
+	},							\
+})
+
+static struct clk_regmap *gcc_ipq9574_clks[] = {
+	[GPLL0_MAIN] = &gpll0_main.clkr,
+	[GPLL0] = &gpll0.clkr,
+	[GPLL4_MAIN] = &gpll4_main.clkr,
+	[GPLL4] = &gpll4.clkr,
+	[GPLL2_MAIN] = &gpll2_main.clkr,
+	[GPLL2] = &gpll2.clkr,
+	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
+	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
+	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
+	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
+	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
+	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
+	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
+	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
+	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
+	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
+	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
+	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
+	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
+	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
+	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
+	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
+	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
+	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
+	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
+	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
+	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
+	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
+	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
+	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
+	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
+	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
+	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
+	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
+	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
+	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
+	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
+	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
+	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
+	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
+	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
+	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
+	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
+	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
+	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
+	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
+	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
+	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
+	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
+	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
+	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
+	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
+	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
+	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
+	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
+	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
+	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
+	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
+	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
+	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
+	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
+	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
+	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
+	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
+	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
+	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
+	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
+	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
+	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
+	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
+	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
+	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
+	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
+	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
+	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
+	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
+	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
+	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
+	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
+	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
+	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
+	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
+	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
+	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
+	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
+	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
+	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
+	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
+	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
+	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
+	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
+	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
+	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
+	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
+	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
+	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
+	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
+	[GCC_SNOC_PCNOC_AHB_CLK] = &gcc_snoc_pcnoc_ahb_clk.clkr,
+	[GCC_ANOC_PCNOC_AHB_CLK] = &gcc_anoc_pcnoc_ahb_clk.clkr,
+	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
+	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
+	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
+	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
+	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
+	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
+	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
+	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
+	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
+	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
+	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
+	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
+	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
+	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
+	[GCC_SYS_NOC_AXI_CLK] = &gcc_sys_noc_axi_clk.clkr,
+	[GCC_ANOC0_AXI_CLK] = &gcc_anoc0_axi_clk.clkr,
+	[GCC_ANOC1_AXI_CLK] = &gcc_anoc1_axi_clk.clkr,
+	[GCC_ANOC0_TBU_CLK] = &gcc_anoc0_tbu_clk.clkr,
+	[GCC_ANOC1_TBU_CLK] = &gcc_anoc1_tbu_clk.clkr,
+	[GCC_MEM_NOC_SNOC_AXI_CLK] = &gcc_mem_noc_snoc_axi_clk.clkr,
+	[GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
+	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
+	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
+	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
+	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
+	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
+	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
+	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
+	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
+	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
+	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
+	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
+	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
+	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
+	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
+	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
+	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
+	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
+	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
+	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
+	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
+	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
+	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
+	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
+	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
+	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
+	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
+	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
+	[GCC_SNOC_TS_CLK] = &gcc_snoc_ts_clk.clkr,
+	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
+	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
+	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
+	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
+	[GCC_PCNOC_TS_CLK] = &gcc_pcnoc_ts_clk.clkr,
+	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
+	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
+	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
+	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
+	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
+	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
+	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
+	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
+	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
+	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
+	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
+	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
+	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
+	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
+	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
+	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
+	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
+	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
+	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
+	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
+	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
+	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
+	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
+	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
+	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
+	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
+	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
+	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
+	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
+	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
+	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
+	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
+	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
+	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
+	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
+	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
+	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
+	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
+	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
+	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
+	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
+	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
+	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
+	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
+	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
+	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
+	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
+	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
+	[GCC_PCNOC_DCC_CLK] = &gcc_pcnoc_dcc_clk.clkr,
+};
+
+static struct clk_regmap *gcc_ipq9574_dummy_clks[] = {
+	[GPLL0_MAIN] = DEFINE_DUMMY_CLK(gpll0_main),
+	[GPLL0] = DEFINE_DUMMY_CLK(gpll0),
+	[GPLL4_MAIN] = DEFINE_DUMMY_CLK(gpll4_main),
+	[GPLL4] = DEFINE_DUMMY_CLK(gpll4),
+	[GPLL2_MAIN] = DEFINE_DUMMY_CLK(gpll2_main),
+	[GPLL2] = DEFINE_DUMMY_CLK(gpll2),
+	[GCC_SLEEP_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_sleep_clk_src),
+	[APSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(apss_ahb_clk_src),
+	[APSS_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(apss_axi_clk_src),
+	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_i2c_apps_clk_src),
+	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_spi_apps_clk_src),
+	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_i2c_apps_clk_src),
+	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_spi_apps_clk_src),
+	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_i2c_apps_clk_src),
+	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_spi_apps_clk_src),
+	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_i2c_apps_clk_src),
+	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_spi_apps_clk_src),
+	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_i2c_apps_clk_src),
+	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_spi_apps_clk_src),
+	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_i2c_apps_clk_src),
+	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_spi_apps_clk_src),
+	[BLSP1_UART1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart1_apps_clk_src),
+	[BLSP1_UART2_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart2_apps_clk_src),
+	[BLSP1_UART3_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart3_apps_clk_src),
+	[BLSP1_UART4_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart4_apps_clk_src),
+	[BLSP1_UART5_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart5_apps_clk_src),
+	[BLSP1_UART6_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart6_apps_clk_src),
+	[GCC_APSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_apss_ahb_clk),
+	[GCC_APSS_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_apss_axi_clk),
+	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_i2c_apps_clk),
+	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_spi_apps_clk),
+	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_i2c_apps_clk),
+	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_spi_apps_clk),
+	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_i2c_apps_clk),
+	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_spi_apps_clk),
+	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_i2c_apps_clk),
+	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_spi_apps_clk),
+	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_i2c_apps_clk),
+	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_spi_apps_clk),
+	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_i2c_apps_clk),
+	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_spi_apps_clk),
+	[GCC_BLSP1_UART1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart1_apps_clk),
+	[GCC_BLSP1_UART2_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart2_apps_clk),
+	[GCC_BLSP1_UART3_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart3_apps_clk),
+	[GCC_BLSP1_UART4_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart4_apps_clk),
+	[GCC_BLSP1_UART5_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart5_apps_clk),
+	[GCC_BLSP1_UART6_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart6_apps_clk),
+	[PCIE0_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_m_clk_src),
+	[GCC_PCIE0_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_m_clk),
+	[PCIE1_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_m_clk_src),
+	[GCC_PCIE1_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_m_clk),
+	[PCIE2_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_m_clk_src),
+	[GCC_PCIE2_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_m_clk),
+	[PCIE3_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_m_clk_src),
+	[GCC_PCIE3_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_m_clk),
+	[PCIE0_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_s_clk_src),
+	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_bridge_clk),
+	[GCC_PCIE0_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_clk),
+	[PCIE1_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_s_clk_src),
+	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_bridge_clk),
+	[GCC_PCIE1_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_clk),
+	[PCIE2_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_s_clk_src),
+	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_bridge_clk),
+	[GCC_PCIE2_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_clk),
+	[PCIE3_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_s_clk_src),
+	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_bridge_clk),
+	[GCC_PCIE3_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_clk),
+	[PCIE0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_pipe_clk_src),
+	[PCIE1_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_pipe_clk_src),
+	[PCIE2_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_pipe_clk_src),
+	[PCIE3_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_pipe_clk_src),
+	[PCIE_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(pcie_aux_clk_src),
+	[GCC_PCIE0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_aux_clk),
+	[GCC_PCIE1_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_aux_clk),
+	[GCC_PCIE2_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_aux_clk),
+	[GCC_PCIE3_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_aux_clk),
+	[PCIE0_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_rchng_clk_src),
+	[GCC_PCIE0_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_rchng_clk),
+	[PCIE1_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_rchng_clk_src),
+	[GCC_PCIE1_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_rchng_clk),
+	[PCIE2_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_rchng_clk_src),
+	[GCC_PCIE2_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_rchng_clk),
+	[PCIE3_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_rchng_clk_src),
+	[GCC_PCIE3_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_rchng_clk),
+	[GCC_PCIE0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_ahb_clk),
+	[GCC_PCIE1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_ahb_clk),
+	[GCC_PCIE2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_ahb_clk),
+	[GCC_PCIE3_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_ahb_clk),
+	[USB0_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_aux_clk_src),
+	[GCC_USB0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_aux_clk),
+	[USB0_MASTER_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_master_clk_src),
+	[GCC_USB0_MASTER_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_master_clk),
+	[GCC_SNOC_USB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_usb_clk),
+	[GCC_ANOC_USB_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_usb_axi_clk),
+	[USB0_MOCK_UTMI_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_clk_src),
+	[USB0_MOCK_UTMI_DIV_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_div_clk_src),
+	[GCC_USB0_MOCK_UTMI_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_mock_utmi_clk),
+	[USB0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_pipe_clk_src),
+	[GCC_USB0_PHY_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_phy_cfg_ahb_clk),
+	[SDCC1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_apps_clk_src),
+	[GCC_SDCC1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_apps_clk),
+	[SDCC1_ICE_CORE_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_ice_core_clk_src),
+	[GCC_SDCC1_ICE_CORE_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ice_core_clk),
+	[GCC_SDCC1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ahb_clk),
+	[PCNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(pcnoc_bfdcd_clk_src),
+	[GCC_NSSCFG_CLK] = DEFINE_DUMMY_CLK(gcc_nsscfg_clk),
+	[GCC_NSSNOC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_nsscc_clk),
+	[GCC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nsscc_clk),
+	[GCC_NSSNOC_PCNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_pcnoc_1_clk),
+	[GCC_QDSS_DAP_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_ahb_clk),
+	[GCC_QDSS_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_cfg_ahb_clk),
+	[GCC_SNOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcnoc_ahb_clk),
+	[GCC_ANOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcnoc_ahb_clk),
+	[GCC_QPIC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_ahb_clk),
+	[GCC_QPIC_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_clk),
+	[GCC_BLSP1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_ahb_clk),
+	[GCC_MDIO_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_mdio_ahb_clk),
+	[GCC_PRNG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_prng_ahb_clk),
+	[GCC_UNIPHY0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_ahb_clk),
+	[GCC_UNIPHY1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_ahb_clk),
+	[GCC_UNIPHY2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_ahb_clk),
+	[GCC_CMN_12GPLL_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_ahb_clk),
+	[GCC_CMN_12GPLL_APU_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_apu_clk),
+	[SYSTEM_NOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(system_noc_bfdcd_clk_src),
+	[GCC_NSSNOC_SNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_clk),
+	[GCC_NSSNOC_SNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_1_clk),
+	[GCC_QDSS_ETR_USB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_etr_usb_clk),
+	[GCC_SYS_NOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_axi_clk),
+	[GCC_ANOC0_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_axi_clk),
+	[GCC_ANOC1_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_axi_clk),
+	[GCC_ANOC0_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_tbu_clk),
+	[GCC_ANOC1_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_tbu_clk),
+	[GCC_MEM_NOC_SNOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_snoc_axi_clk),
+	[GCC_IMEM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_imem_axi_clk),
+	[WCSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_ahb_clk_src),
+	[GCC_Q6_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_clk),
+	[GCC_Q6_AHB_S_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_s_clk),
+	[GCC_WCSS_ECAHB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_ecahb_clk),
+	[GCC_WCSS_ACMT_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_acmt_clk),
+	[GCC_SYS_NOC_WCSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_wcss_ahb_clk),
+	[WCSS_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_axi_m_clk_src),
+	[GCC_ANOC_WCSS_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_wcss_axi_m_clk),
+	[QDSS_AT_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_at_clk_src),
+	[GCC_Q6SS_ATBM_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_atbm_clk),
+	[GCC_WCSS_DBG_IFC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_atb_clk),
+	[GCC_NSSNOC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_atb_clk),
+	[GCC_QDSS_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_at_clk),
+	[GCC_SYS_NOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_at_clk),
+	[GCC_PCNOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_at_clk),
+	[GCC_USB0_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_eud_at_clk),
+	[GCC_QDSS_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_eud_at_clk),
+	[QDSS_STM_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_stm_clk_src),
+	[GCC_QDSS_STM_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_stm_clk),
+	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_qdss_stm_axi_clk),
+	[QDSS_TRACECLKIN_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_traceclkin_clk_src),
+	[GCC_QDSS_TRACECLKIN_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_traceclkin_clk),
+	[QDSS_TSCTR_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_tsctr_clk_src),
+	[GCC_Q6_TSCTR_1TO2_CLK] = DEFINE_DUMMY_CLK(gcc_q6_tsctr_1to2_clk),
+	[GCC_WCSS_DBG_IFC_NTS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_nts_clk),
+	[GCC_QDSS_TSCTR_DIV2_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div2_clk),
+	[GCC_QDSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_ts_clk),
+	[GCC_SNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_ts_clk),
+	[GCC_MEM_NOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_ts_clk),
+	[GCC_QDSS_TSCTR_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div4_clk),
+	[GCC_NSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_nss_ts_clk),
+	[GCC_QDSS_TSCTR_DIV8_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div8_clk),
+	[GCC_PCNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_ts_clk),
+	[GCC_QDSS_TSCTR_DIV16_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div16_clk),
+	[GCC_Q6SS_PCLKDBG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_pclkdbg_clk),
+	[GCC_Q6SS_TRIG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_trig_clk),
+	[GCC_WCSS_DBG_IFC_APB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_apb_clk),
+	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_dapbus_clk),
+	[GCC_QDSS_DAP_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_clk),
+	[GCC_QDSS_APB2JTAG_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_apb2jtag_clk),
+	[GCC_QDSS_TSCTR_DIV3_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div3_clk),
+	[QPIC_IO_MACRO_CLK_SRC] = DEFINE_DUMMY_CLK(qpic_io_macro_clk_src),
+	[GCC_QPIC_IO_MACRO_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_io_macro_clk),
+	[Q6_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axi_clk_src),
+	[GCC_Q6_AXIM_CLK] = DEFINE_DUMMY_CLK(gcc_q6_axim_clk),
+	[GCC_WCSS_Q6_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_q6_tbu_clk),
+	[GCC_MEM_NOC_Q6_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_q6_axi_clk),
+	[Q6_AXIM2_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axim2_clk_src),
+	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(nssnoc_memnoc_bfdcd_clk_src),
+	[GCC_NSSNOC_MEMNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_memnoc_clk),
+	[GCC_NSSNOC_MEM_NOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_mem_noc_1_clk),
+	[GCC_NSS_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_nss_tbu_clk),
+	[GCC_MEM_NOC_NSSNOC_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_nssnoc_clk),
+	[LPASS_AXIM_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_axim_clk_src),
+	[LPASS_SWAY_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_sway_clk_src),
+	[ADSS_PWM_CLK_SRC] = DEFINE_DUMMY_CLK(adss_pwm_clk_src),
+	[GCC_ADSS_PWM_CLK] = DEFINE_DUMMY_CLK(gcc_adss_pwm_clk),
+	[GP1_CLK_SRC] = DEFINE_DUMMY_CLK(gp1_clk_src),
+	[GP2_CLK_SRC] = DEFINE_DUMMY_CLK(gp2_clk_src),
+	[GP3_CLK_SRC] = DEFINE_DUMMY_CLK(gp3_clk_src),
+	[DDRSS_SMS_SLOW_CLK_SRC] = DEFINE_DUMMY_CLK(ddrss_sms_slow_clk_src),
+	[GCC_XO_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_xo_clk_src),
+	[GCC_NSSNOC_XO_DCD_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_xo_dcd_clk),
+	[GCC_XO_CLK] = DEFINE_DUMMY_CLK(gcc_xo_clk),
+	[GCC_NSSNOC_QOSGEN_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_qosgen_ref_clk),
+	[GCC_NSSNOC_TIMEOUT_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_timeout_ref_clk),
+	[GCC_XO_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_xo_div4_clk),
+	[GCC_UNIPHY0_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_sys_clk),
+	[GCC_UNIPHY1_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_sys_clk),
+	[GCC_UNIPHY2_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_sys_clk),
+	[GCC_CMN_12GPLL_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_sys_clk),
+	[GCC_Q6SS_BOOT_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_boot_clk),
+	[UNIPHY_SYS_CLK_SRC] = DEFINE_DUMMY_CLK(uniphy_sys_clk_src),
+	[NSS_TS_CLK_SRC] = DEFINE_DUMMY_CLK(nss_ts_clk_src),
+	[GCC_ANOC_PCIE0_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie0_1lane_m_clk),
+	[GCC_ANOC_PCIE1_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie1_1lane_m_clk),
+	[GCC_ANOC_PCIE2_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie2_2lane_m_clk),
+	[GCC_ANOC_PCIE3_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie3_2lane_m_clk),
+	[GCC_SNOC_PCIE0_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie0_1lane_s_clk),
+	[GCC_SNOC_PCIE1_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie1_1lane_s_clk),
+	[GCC_SNOC_PCIE2_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie2_2lane_s_clk),
+	[GCC_SNOC_PCIE3_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie3_2lane_s_clk),
+	[GCC_PCNOC_DCC_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_dcc_clk),
+};
+
+static const struct qcom_reset_map gcc_ipq9574_resets[] = {
+	[GCC_ADSS_BCR] = { 0x1c000, 0 },
+	[GCC_ANOC0_TBU_BCR] = { 0x1203C, 0 },
+	[GCC_ANOC1_TBU_BCR] = { 0x1204C, 0 },
+	[GCC_ANOC_BCR] = { 0x2E074, 0 },
+	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
+	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
+	[GCC_BLSP1_BCR] = { 0x01000, 0 },
+	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
+	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
+	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
+	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
+	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
+	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
+	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
+	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
+	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
+	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
+	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
+	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
+	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
+	[GCC_CMN_BLK_BCR] = { 0x3A000, 0 },
+	[GCC_CMN_BLK_AHB_ARES] = { 0x3A010, 0 },
+	[GCC_CMN_BLK_SYS_ARES] = { 0x3A010, 1 },
+	[GCC_CMN_BLK_APU_ARES] = { 0x3A010, 2 },
+	[GCC_DCC_BCR] = { 0x35000, 0 },
+	[GCC_DDRSS_BCR] = { 0x11000, 0 },
+	[GCC_IMEM_BCR] = { 0x0e000, 0 },
+	[GCC_LPASS_BCR] = { 0x27000, 0 },
+	[GCC_MDIO_BCR] = { 0x1703c, 0 },
+	[GCC_MPM_BCR] = { 0x37000, 0 },
+	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
+	[GCC_NSS_BCR] = { 0x17000, 0 },
+	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
+	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
+	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
+	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
+	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
+	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
+	[GCC_NSSCC_ARES] = { 0x17038, 8 },
+	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
+	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
+	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
+	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
+	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
+	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
+	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
+	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
+	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
+	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
+	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
+	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
+	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
+	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
+	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
+	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
+	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
+	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
+	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
+	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
+	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
+	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
+	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
+	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
+	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
+	[GCC_PCIE2_AHB_ARES] = { 0x2A058, 7 },
+	[GCC_PCIE2_AUX_ARES] = { 0x2A058, 6 },
+	[GCC_PCIE2_AXI_M_ARES] = { 0x2A058, 5 },
+	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2A058, 4 },
+	[GCC_PCIE2_AXI_S_ARES] = { 0x2A058, 3 },
+	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2A058, 2 },
+	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2A058, 1 },
+	[GCC_PCIE2_PIPE_ARES] = { 0x2A058, 0 },
+	[GCC_PCIE3_AHB_ARES] = { 0x2B058, 7 },
+	[GCC_PCIE3_AUX_ARES] = { 0x2B058, 6 },
+	[GCC_PCIE3_AXI_M_ARES] = { 0x2B058, 5 },
+	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2B058, 4 },
+	[GCC_PCIE3_AXI_S_ARES] = { 0x2B058, 3 },
+	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2B058, 2 },
+	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2B058, 1 },
+	[GCC_PCIE3_PIPE_ARES] = { 0x2B058, 0 },
+	[GCC_PCIE0_BCR] = { 0x28000, 0 },
+	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
+	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
+	[GCC_PCIE1_BCR] = { 0x29000, 0 },
+	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
+	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
+	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
+	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
+	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
+	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
+	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
+	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
+	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
+	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
+	[GCC_PCIE3_PHY_BCR] = { 0x2B060, 0 },
+	[GCC_PCNOC_BCR] = { 0x31000, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
+	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
+	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
+	[GCC_PRNG_BCR] = { 0x13020, 0 },
+	[GCC_Q6SS_DBG_ARES] = { 0x2506C, 4 },
+	[GCC_Q6_AHB_ARES] = { 0x2506C, 3 },
+	[GCC_Q6_AHB_S_ARES] = { 0x2506C, 2 },
+	[GCC_Q6_AXIM2_ARES] = { 0x2506C, 1 },
+	[GCC_Q6_AXIM_ARES] = { 0x2506C, 0 },
+	[GCC_QDSS_BCR] = { 0x2d000, 0 },
+	[GCC_QPIC_BCR] = { 0x32000, 0 },
+	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
+	[GCC_QPIC_ARES] = { 0x3201c, 0 },
+	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
+	[GCC_RBCPR_BCR] = { 0x39000, 0 },
+	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
+	[GCC_SDCC_BCR] = { 0x33000, 0 },
+	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
+	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
+	[GCC_SNOC_BCR] = { 0x2E000, 0 },
+	[GCC_SPDM_BCR] = { 0x36000, 0 },
+	[GCC_TCSR_BCR] = { 0x3d000, 0 },
+	[GCC_TLMM_BCR] = { 0x3e000, 0 },
+	[GCC_TME_BCR] = { 0x10000, 0 },
+	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
+	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
+	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
+	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
+	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
+	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
+	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
+	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
+	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
+	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
+	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
+	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
+	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
+	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
+	[GCC_USB_BCR] = { 0x2c000, 0 },
+	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
+	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
+	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
+	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
+	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
+	[GCC_WCSS_BCR] = { 0x18004, 0 },
+	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
+	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
+	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
+	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
+	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
+};
+
+static const struct of_device_id gcc_ipq9574_match_table[] = {
+	{ .compatible = "qcom,gcc-ipq9574" },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
+
+static const struct regmap_config gcc_ipq9574_regmap_config = {
+	.reg_bits       = 32,
+	.reg_stride     = 4,
+	.val_bits       = 32,
+	.max_register   = 0x7fffc,
+	.fast_io	= true,
+};
+
+static const struct qcom_cc_desc gcc_ipq9574_desc = {
+	.config = &gcc_ipq9574_regmap_config,
+	.clks = gcc_ipq9574_clks,
+	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
+	.resets = gcc_ipq9574_resets,
+	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
+	.clk_hws = gcc_ipq9574_hws,
+	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
+};
+
+static const struct qcom_cc_desc gcc_ipq9574_dummy_desc = {
+	.config = &gcc_ipq9574_regmap_config,
+	.clks = gcc_ipq9574_dummy_clks,
+	.num_clks = ARRAY_SIZE(gcc_ipq9574_dummy_clks),
+	.resets = gcc_ipq9574_resets,
+	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
+};
+
+static int gcc_ipq9574_probe(struct platform_device *pdev)
+{
+	struct regmap *regmap;
+	struct qcom_cc_desc ipq9574_desc = gcc_ipq9574_desc;
+	struct device_node *np = (&pdev->dev)->of_node;
+
+	if (of_property_read_bool(np, "gcc-use-dummy"))
+		ipq9574_desc = gcc_ipq9574_dummy_desc;
+
+	regmap = qcom_cc_map(pdev, &ipq9574_desc);
+	if (IS_ERR(regmap))
+		return PTR_ERR(regmap);
+
+	return qcom_cc_really_probe(pdev, &ipq9574_desc, regmap);
+}
+
+static int gcc_ipq9574_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+static struct platform_driver gcc_ipq9574_driver = {
+	.probe = gcc_ipq9574_probe,
+	.remove = gcc_ipq9574_remove,
+	.driver = {
+		.name   = "qcom,gcc-ipq9574",
+		.of_match_table = gcc_ipq9574_match_table,
+	},
+};
+
+static int __init gcc_ipq9574_init(void)
+{
+	return platform_driver_register(&gcc_ipq9574_driver);
+}
+core_initcall(gcc_ipq9574_init);
+
+static void __exit gcc_ipq9574_exit(void)
+{
+	platform_driver_unregister(&gcc_ipq9574_driver);
+}
+module_exit(gcc_ipq9574_exit);
+
+MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
+MODULE_LICENSE("GPL");
-- 
2.17.1

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Konrad Dybcio]

On 10.01.2023 13:13, devi priya wrote:
> Add Global Clock Controller (GCC) driver for ipq9574 based devices
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  drivers/clk/qcom/Kconfig       |    8 +
>  drivers/clk/qcom/Makefile      |    1 +
>  drivers/clk/qcom/gcc-ipq9574.c | 4706 ++++++++++++++++++++++++++++++++
>  3 files changed, 4715 insertions(+)
>  create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 70d43f0a8919..97517d1e3ba4 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -173,6 +173,14 @@ config IPQ_GCC_8074
>  	  i2c, USB, SD/eMMC, etc. Select this for the root clock
>  	  of ipq8074.
>  
> +config IPQ_GCC_9574
> +	tristate "IPQ9574 Global Clock Controller"
> +	help
> +	  Support for global clock controller on ipq9574 devices.
> +	  Say Y if you want to use peripheral devices such as UART, SPI,
> +	  i2c, USB, SD/eMMC, etc. Select this for the root clock
> +	  of ipq9574.
> +
>  config MSM_GCC_8660
>  	tristate "MSM8660 Global Clock Controller"
>  	help
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index f18c446a97ea..55c6ada326e0 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>  obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>  obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>  obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> +obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>  obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>  obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>  obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> new file mode 100644
> index 000000000000..f44a19c5f9a1
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -0,0 +1,4706 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Hm, interesting choice for a C driver..

> +/*
> + * Copyright (c) 2022 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +
> +#include <linux/reset-controller.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "reset.h"
Many of these includes seem unnecessary..


> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
Drop.

> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> +	DT_XO,
> +	DT_SLEEP_CLK,
> +	DT_BIAS_PLL_UBI_NC_CLK,
> +	DT_PCIE30_PHY0_PIPE_CLK,
> +	DT_PCIE30_PHY1_PIPE_CLK,
> +	DT_PCIE30_PHY2_PIPE_CLK,
> +	DT_PCIE30_PHY3_PIPE_CLK,
> +	DT_USB3PHY_0_CC_PIPE_CLK,
> +};
> +
> +enum {
> +	P_XO,
> +	P_PCIE30_PHY0_PIPE,
> +	P_PCIE30_PHY1_PIPE,
> +	P_PCIE30_PHY2_PIPE,
> +	P_PCIE30_PHY3_PIPE,
> +	P_USB3PHY_0_PIPE,
> +	P_GPLL0,
> +	P_GPLL0_DIV2,
> +	P_GPLL0_OUT_AUX,
> +	P_GPLL2,
> +	P_GPLL4,
> +	P_PI_SLEEP,
> +	P_BIAS_PLL_UBI_NC_CLK,
> +};
> +
> +static const struct parent_map gcc_xo_map[] = {
> +	{ P_XO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_data[] = {
> +	{ .index = DT_XO },
> +};
> +
> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
> +	{ .index = DT_SLEEP_CLK },
> +};
> +
> +static struct clk_alpha_pll gpll0_main = {
> +	.offset = 0x20000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.clkr = {
> +		.enable_reg = 0x0b000,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gpll0_main",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.ops = &clk_alpha_pll_ops,
> +			.flags = CLK_IS_CRITICAL,
Is it? Does it act as a CPU PLL source that's not managed by the
firmware?

> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor gpll0_out_main_div2 = {
> +	.mult = 1,
> +	.div = 2,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "gpll0_out_main_div2",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll0_main.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> +	.offset = 0x20000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.width = 4,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gpll0",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll0_main.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_alpha_pll gpll4_main = {
> +	.offset = 0x22000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.clkr = {
> +		.enable_reg = 0x0b000,
> +		.enable_mask = BIT(2),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gpll4_main",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.ops = &clk_alpha_pll_ops,
> +			.flags = CLK_IS_CRITICAL,
Again, is it?

> +		},
> +	},
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll4 = {
> +	.offset = 0x22000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.width = 4,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gpll4",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll4_main.clkr.hw },
Please put the }, in a new line.

> +		.num_parents = 1,
> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_alpha_pll gpll2_main = {
> +	.offset = 0x21000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.clkr = {
> +		.enable_reg = 0x0b000,
> +		.enable_mask = BIT(1),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gpll2_main",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.ops = &clk_alpha_pll_ops,
> +			.flags = CLK_IS_CRITICAL,
> +		},
> +	},
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll2 = {
> +	.offset = 0x21000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.width = 4,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gpll2",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll2_main.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_branch gcc_sleep_clk_src = {
> +	.halt_reg = 0x3400c,
> +	.clkr = {
> +		.enable_reg = 0x3400c,
> +		.enable_mask = BIT(1),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sleep_clk_src",
> +			.parent_data = gcc_sleep_clk_data,
> +			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
> +			.ops = &clk_branch2_ops,
> +			.flags = CLK_IS_CRITICAL,
> +		},
> +	},
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw},
Please consistently add a space before },

> +	{ .hw = &gpll0_out_main_div2.hw},
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL0_DIV2, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .hw = &gpll4.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL4, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .hw = &gpll0_out_main_div2.hw },
> +	{ .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map
> +gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
Pretty sure you can unwrap that line


> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL0_DIV2, 4 },
> +	{ P_GPLL0, 5 },
> +};
> +

[...]

> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> +	.halt_reg = 0x07024,
> +	.clkr = {
> +		.enable_reg = 0x07024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_blsp1_qup6_i2c_apps_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Sounds very much like a hack..

[...]


> +static struct clk_branch gcc_snoc_usb_clk = {
> +	.halt_reg = 0x2E058,
Please lowercase hex all throughout the file.

> +	.clkr = {
> +		.enable_reg = 0x2E058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_snoc_usb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&usb0_master_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
[...]

> +
> +static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> +	.cmd_rcgr = 0x31004,
> +	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "pcnoc_bfdcd_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> +		.ops = &clk_rcg2_ops,
> +		.flags = CLK_IS_CRITICAL,
> +	},
> +};
> +
> +static struct clk_fixed_factor pcnoc_clk_src = {
> +	.mult = 1,
> +	.div = 1,
Is there any benefit in keeping it instead of providing
the real rcg as a parent?

> +	.hw.init = &(struct clk_init_data) {
> +		.name = "pcnoc_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&pcnoc_bfdcd_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +

[...]
> +static struct clk_branch gcc_snoc_pcnoc_ahb_clk = {
> +	.halt_reg = 0x2E03C,
> +	.clkr = {
> +		.enable_reg = 0x2E03C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_snoc_pcnoc_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&pcnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Can it be turned off? Perhaps CLK_IS_CRITICAL would be more fitting,
with a comment explaining why.


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc_pcnoc_ahb_clk = {
> +	.halt_reg = 0x2E094,
> +	.clkr = {
> +		.enable_reg = 0x2E094,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc_pcnoc_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&pcnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Same thing

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +

> +
> +static struct clk_rcg2 system_noc_bfdcd_clk_src = {
> +	.cmd_rcgr = 0x2e004,
> +	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll4_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "system_noc_bfdcd_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
> +		.ops = &clk_rcg2_ops,
> +		.flags = CLK_IS_CRITICAL,
.flags goes before .ops in all other nodes, please be consistent.

> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_boot_clk = {
> +	.halt_reg = 0x25080,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x25080,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_boot_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_snoc_clk = {
> +	.halt_reg = 0x17028,
> +	.clkr = {
> +		.enable_reg = 0x17028,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_snoc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Same story as with PCNoC
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_snoc_1_clk = {
> +	.halt_reg = 0x1707c,
> +	.clkr = {
> +		.enable_reg = 0x1707c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_snoc_1_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
And here

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_etr_usb_clk = {
> +	.halt_reg = 0x2D060,
> +	.clkr = {
> +		.enable_reg = 0x2D060,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_etr_usb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(133333333, P_GPLL0, 6, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 wcss_ahb_clk_src = {
> +	.cmd_rcgr = 0x25030,
> +	.freq_tbl = ftbl_wcss_ahb_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "wcss_ahb_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_ahb_clk = {
> +	.halt_reg = 0x25014,
> +	.clkr = {
> +		.enable_reg = 0x25014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
This sounds like a hack, perhaps it should be fed to a remoteproc node?


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_ahb_s_clk = {
> +	.halt_reg = 0x25018,
> +	.clkr = {
> +		.enable_reg = 0x25018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_ahb_s_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
And this one too

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_ecahb_clk = {
> +	.halt_reg = 0x25058,
> +	.clkr = {
> +		.enable_reg = 0x25058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_ecahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Similarly, this one should probably be fed to the wcss node and
properly managed with a driver, not left dangling

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_acmt_clk = {
> +	.halt_reg = 0x2505c,
> +	.clkr = {
> +		.enable_reg = 0x2505c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_acmt_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_axi_clk = {
> +	.halt_reg = 0x2e01c,
> +	.clkr = {
> +		.enable_reg = 0x2e01c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
CLK_IS_CRITICAL?

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc0_axi_clk = {
> +	.halt_reg = 0x2e078,
> +	.clkr = {
> +		.enable_reg = 0x2e078,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc0_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
If this it the same kind of ANoC(n) as on 8996/8998, this should
definitely be either CLK_IS_CRITICAL or managed through a driver..
Probably the second one..


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc1_axi_clk = {
> +	.halt_reg = 0x2e088,
> +	.clkr = {
> +		.enable_reg = 0x2e088,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc1_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc0_tbu_clk = {
> +	.halt_reg = 0x12038,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(3),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc0_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc1_tbu_clk = {
> +	.halt_reg = 0x12048,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(5),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc1_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_snoc_axi_clk = {
> +	.halt_reg = 0x19018,
> +	.clkr = {
> +		.enable_reg = 0x19018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_snoc_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
This one also smells of an interconnect clock more than anything else..


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_imem_axi_clk = {
> +	.halt_reg = 0xe004,
> +	.clkr = {
> +		.enable_reg = 0xb004,
> +		.enable_mask = BIT(12),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_imem_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
You could pass this one to the imem node

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
> +	.halt_reg = 0x2e030,
> +	.clkr = {
> +		.enable_reg = 0x2e030,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_wcss_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Definitely handled through a driver..

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(133333333, P_GPLL0, 6, 0, 0),
> +	F(266666667, P_GPLL0, 3, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 wcss_axi_m_clk_src = {
> +	.cmd_rcgr = 0x25078,
> +	.freq_tbl = ftbl_wcss_axi_m_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "wcss_axi_m_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
> +	.halt_reg = 0x2e0a8,
> +	.clkr = {
> +		.enable_reg = 0x2e0a8,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc_wcss_axi_m_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_axi_m_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
> +	F(240000000, P_GPLL4, 5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_at_clk_src = {
> +	.cmd_rcgr = 0x2d004,
> +	.freq_tbl = ftbl_qdss_at_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_at_clk_src",
> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_atbm_clk = {
> +	.halt_reg = 0x2501c,
> +	.clkr = {
> +		.enable_reg = 0x2501c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_atbm_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
> +	.halt_reg = 0x2503c,
> +	.clkr = {
> +		.enable_reg = 0x2503c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_atb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Not gonna point out every similar occurence, you probably get me now

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_atb_clk = {
> +	.halt_reg = 0x17014,
> +	.clkr = {
> +		.enable_reg = 0x17014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_atb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_at_clk = {
> +	.halt_reg = 0x2D038,
> +	.clkr = {
> +		.enable_reg = 0x2D038,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Probably not critical, you don't need debug 24/7.


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_at_clk = {
> +	.halt_reg = 0x2e038,
> +	.clkr = {
> +		.enable_reg = 0x2e038,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcnoc_at_clk = {
> +	.halt_reg = 0x31024,
> +	.clkr = {
> +		.enable_reg = 0x31024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_pcnoc_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
> +	.mult = 1,
> +	.div = 6,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "gcc_eud_at_div_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_at_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_usb0_eud_at_clk = {
> +	.halt_reg = 0x30004,
> +	.clkr = {
> +		.enable_reg = 0x30004,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_usb0_eud_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_eud_at_div_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Definitely not critical.

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_eud_at_clk = {
> +	.halt_reg = 0x2D06C,
> +	.clkr = {
> +		.enable_reg = 0x2D06C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_eud_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_eud_at_div_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Ditto.

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_stm_clk_src = {
> +	.cmd_rcgr = 0x2D00C,
> +	.freq_tbl = ftbl_qdss_stm_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_stm_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_stm_clk = {
> +	.halt_reg = 0x2D03C,
> +	.clkr = {
> +		.enable_reg = 0x2D03C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_stm_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_stm_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
> +	.halt_reg = 0x2E034,
> +	.clkr = {
> +		.enable_reg = 0x2E034,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_qdss_stm_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_stm_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
> +	F(300000000, P_GPLL4, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_traceclkin_clk_src = {
> +	.cmd_rcgr = 0x2d014,
> +	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_traceclkin_clk_src",
> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_traceclkin_clk = {
> +	.halt_reg = 0x2D040,
> +	.clkr = {
> +		.enable_reg = 0x2D040,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_traceclkin_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_traceclkin_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
> +	F(600000000, P_GPLL4, 2, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_tsctr_clk_src = {
> +	.cmd_rcgr = 0x2d01c,
> +	.freq_tbl = ftbl_qdss_tsctr_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_clk_src",
> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
> +	.mult = 1,
> +	.div = 2,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div2_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_tsctr_1to2_clk = {
> +	.halt_reg = 0x25020,
> +	.clkr = {
> +		.enable_reg = 0x25020,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_tsctr_1to2_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
> +	.halt_reg = 0x25040,
> +	.clkr = {
> +		.enable_reg = 0x25040,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_nts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div2_clk = {
> +	.halt_reg = 0x2d044,
> +	.clkr = {
> +		.enable_reg = 0x2d044,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div2_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 uniphy_sys_clk_src = {
> +	.cmd_rcgr = 0x17090,
> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "uniphy_sys_clk_src",
> +		.parent_data = gcc_xo_data,
> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 nss_ts_clk_src = {
> +	.cmd_rcgr = 0x17088,
> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "nss_ts_clk_src",
> +		.parent_data = gcc_xo_data,
> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_ts_clk = {
> +	.halt_reg = 0x2D078,
> +	.clkr = {
> +		.enable_reg = 0x2D078,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nss_ts_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_snoc_ts_clk = {
> +	.halt_reg = 0x2e068,
> +	.clkr = {
> +		.enable_reg = 0x2e068,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_snoc_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_ts_clk = {
> +	.halt_reg = 0x19028,
> +	.clkr = {
> +		.enable_reg = 0x19028,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_dap_sync_clk_src = {
> +	.mult = 1,
> +	.div = 4,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_dap_sync_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div4_clk = {
> +	.halt_reg = 0x2d04c,
> +	.clkr = {
> +		.enable_reg = 0x2d04c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div4_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
> +	.mult = 1,
> +	.div = 8,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div8_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_nss_ts_clk = {
> +	.halt_reg = 0x17018,
> +	.clkr = {
> +		.enable_reg = 0x17018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nss_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nss_ts_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div8_clk = {
> +	.halt_reg = 0x2d050,
> +	.clkr = {
> +		.enable_reg = 0x2d050,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div8_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div8_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcnoc_ts_clk = {
> +	.halt_reg = 0x3102c,
> +	.clkr = {
> +		.enable_reg = 0x3102c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_pcnoc_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div8_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
> +	.mult = 1,
> +	.div = 16,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div16_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div16_clk = {
> +	.halt_reg = 0x2d054,
> +	.clkr = {
> +		.enable_reg = 0x2d054,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div16_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div16_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_pclkdbg_clk = {
> +	.halt_reg = 0x25024,
> +	.clkr = {
> +		.enable_reg = 0x25024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_pclkdbg_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_trig_clk = {
> +	.halt_reg = 0x25068,
> +	.clkr = {
> +		.enable_reg = 0x25068,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_trig_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
> +	.halt_reg = 0x25038,
> +	.clkr = {
> +		.enable_reg = 0x25038,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_apb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
> +	.halt_reg = 0x25044,
> +	.clkr = {
> +		.enable_reg = 0x25044,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_dap_clk = {
> +	.halt_reg = 0x2d058,
> +	.clkr = {
> +		.enable_reg = 0x2d058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_dap_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Probably not critical.

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_apb2jtag_clk = {
> +	.halt_reg = 0x2d05c,
> +	.clkr = {
> +		.enable_reg = 0x2d05c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_apb2jtag_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcnoc_dcc_clk = {
> +	.halt_reg = 0x31080,
> +	.clkr = {
> +		.enable_reg = 0x31080,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_pcnoc_dcc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
> +	.mult = 1,
> +	.div = 3,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div3_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div3_clk = {
> +	.halt_reg = 0x2d048,
> +	.clkr = {
> +		.enable_reg = 0x2d048,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div3_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div3_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(100000000, P_GPLL0, 8, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	F(320000000, P_GPLL0, 2.5, 0, 0),
> +	F(400000000, P_GPLL0, 2, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qpic_io_macro_clk_src = {
> +	.cmd_rcgr = 0x32004,
> +	.freq_tbl = ftbl_qpic_io_macro_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qpic_io_macro_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qpic_io_macro_clk = {
> +	.halt_reg = 0x3200c,
> +	.clkr = {
> +		.enable_reg = 0x3200c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qpic_io_macro_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qpic_io_macro_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
> +	F(533333333, P_GPLL0, 1.5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 q6_axi_clk_src = {
> +	.cmd_rcgr = 0x25004,
> +	.freq_tbl = ftbl_q6_axi_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "q6_axi_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_axim_clk = {
> +	.halt_reg = 0x2500c,
> +	.clkr = {
> +		.enable_reg = 0x2500c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_axim_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&q6_axi_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_q6_tbu_clk = {
> +	.halt_reg = 0x12050,
> +	.halt_check = BRANCH_HALT_DELAY,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(6),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_q6_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&q6_axi_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_q6_axi_clk = {
> +	.halt_reg = 0x19010,
> +	.clkr = {
> +		.enable_reg = 0x19010,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_q6_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&q6_axi_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
> +	F(342857143, P_GPLL4, 3.5, 0, 0),
> +	{ }
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL4, 2 },
> +	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
> +};
> +
> +static struct clk_rcg2 q6_axim2_clk_src = {
> +	.cmd_rcgr = 0x25028,
> +	.freq_tbl = ftbl_q6_axim2_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "q6_axim2_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
> +	F(533333333, P_GPLL0, 1.5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
> +	.cmd_rcgr = 0x17004,
> +	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "nssnoc_memnoc_bfdcd_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_memnoc_clk = {
> +	.halt_reg = 0x17024,
> +	.clkr = {
> +		.enable_reg = 0x17024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_memnoc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
> +	.halt_reg = 0x17084,
> +	.clkr = {
> +		.enable_reg = 0x17084,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_mem_noc_1_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nss_tbu_clk = {
> +	.halt_reg = 0x12040,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(4),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nss_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_nssnoc_clk = {
> +	.halt_reg = 0x19014,
> +	.clkr = {
> +		.enable_reg = 0x19014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_nssnoc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
> +	F(133333333, P_GPLL0, 6, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 lpass_axim_clk_src = {
> +	.cmd_rcgr = 0x2700c,
> +	.freq_tbl = ftbl_lpass_axim_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "lpass_axim_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 lpass_sway_clk_src = {
> +	.cmd_rcgr = 0x27004,
> +	.freq_tbl = ftbl_lpass_axim_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "lpass_sway_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(100000000, P_GPLL0, 8, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 adss_pwm_clk_src = {
> +	.cmd_rcgr = 0x1c004,
> +	.freq_tbl = ftbl_adss_pwm_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "adss_pwm_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_adss_pwm_clk = {
> +	.halt_reg = 0x1c00c,
> +	.clkr = {
> +		.enable_reg = 0x1c00c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_adss_pwm_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&adss_pwm_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gp1_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gp1_clk_src = {
> +	.cmd_rcgr = 0x8004,
> +	.freq_tbl = ftbl_gp1_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gp1_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gp2_clk_src = {
> +	.cmd_rcgr = 0x9004,
> +	.freq_tbl = ftbl_gp1_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gp2_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gp3_clk_src = {
> +	.cmd_rcgr = 0xa004,
> +	.freq_tbl = ftbl_gp1_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gp3_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_xo_clk_src = {
> +	.halt_reg = 0x34004,
> +	.clkr = {
> +		.enable_reg = 0x34004,
> +		.enable_mask = BIT(1),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_xo_clk_src",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
> +	.halt_reg = 0x17074,
> +	.clkr = {
> +		.enable_reg = 0x17074,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_xo_dcd_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_xo_clk = {
> +	.halt_reg = 0x34018,
> +	.clkr = {
> +		.enable_reg = 0x34018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_xo_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_uniphy0_sys_clk = {
> +	.halt_reg = 0x17048,
> +	.clkr = {
> +		.enable_reg = 0x17048,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_uniphy0_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_uniphy1_sys_clk = {
> +	.halt_reg = 0x17058,
> +	.clkr = {
> +		.enable_reg = 0x17058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_uniphy1_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_uniphy2_sys_clk = {
> +	.halt_reg = 0x17068,
> +	.clkr = {
> +		.enable_reg = 0x17068,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_uniphy2_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_cmn_12gpll_sys_clk = {
> +	.halt_reg = 0x3a008,
> +	.clkr = {
> +		.enable_reg = 0x3a008,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_cmn_12gpll_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor gcc_xo_div4_clk_src = {
> +	.mult = 1,
> +	.div = 4,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "gcc_xo_div4_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gcc_xo_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
> +	.halt_reg = 0x1701c,
> +	.clkr = {
> +		.enable_reg = 0x1701c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_qosgen_ref_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_div4_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
> +	.halt_reg = 0x17020,
> +	.clkr = {
> +		.enable_reg = 0x17020,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_timeout_ref_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_div4_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_xo_div4_clk = {
> +	.halt_reg = 0x3401c,
> +	.clkr = {
> +		.enable_reg = 0x3401c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_xo_div4_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_div4_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_hw *gcc_ipq9574_hws[] = {
> +	&gpll0_out_main_div2.hw,
> +	&gcc_xo_div4_clk_src.hw,
> +	&qdss_dap_sync_clk_src.hw,
> +	&qdss_tsctr_div2_clk_src.hw,
> +	&qdss_tsctr_div8_clk_src.hw,
> +	&qdss_tsctr_div16_clk_src.hw,
> +	&qdss_tsctr_div3_clk_src.hw,
> +	&gcc_eud_at_div_clk_src.hw,
> +	&pcnoc_clk_src.hw,
> +};
> +

> +static int clk_dummy_is_enabled(struct clk_hw *hw)
> +{
> +	return 1;
> +};
> +
> +static int clk_dummy_enable(struct clk_hw *hw)
> +{
> +	return 0;
> +};
> +
> +static void clk_dummy_disable(struct clk_hw *hw)
> +{
> +	return;
> +};
> +
> +static u8 clk_dummy_get_parent(struct clk_hw *hw)
> +{
> +	return 0;
> +};
> +
> +static int clk_dummy_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	return 0;
> +};
> +
> +static int clk_dummy_set_rate(struct clk_hw *hw, unsigned long rate,
> +			      unsigned long parent_rate)
> +{
> +	return 0;
> +};
> +
> +static int clk_dummy_determine_rate(struct clk_hw *hw,
> +				    struct clk_rate_request *req)
> +{
> +	return 0;
> +};
> +
> +static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw,
> +					   unsigned long parent_rate)
> +{
> +	return parent_rate;
> +};
> +
> +static const struct clk_ops clk_dummy_ops = {
> +	.is_enabled = clk_dummy_is_enabled,
> +	.enable = clk_dummy_enable,
> +	.disable = clk_dummy_disable,
> +	.get_parent = clk_dummy_get_parent,
> +	.set_parent = clk_dummy_set_parent,
> +	.set_rate = clk_dummy_set_rate,
> +	.recalc_rate = clk_dummy_recalc_rate,
> +	.determine_rate = clk_dummy_determine_rate,
> +};
> +
> +#define DEFINE_DUMMY_CLK(clk_name)				\
> +(&(struct clk_regmap) {						\
> +	.hw.init = &(struct clk_init_data) {			\
> +		.name = #clk_name,				\
> +		.parent_names = (const char *[]) { "xo"},	\
> +		.num_parents = 1,				\
> +		.ops = &clk_dummy_ops,				\
> +	},							\
> +})
Definitely a big no.

> +
> +static struct clk_regmap *gcc_ipq9574_clks[] = {
> +	[GPLL0_MAIN] = &gpll0_main.clkr,
> +	[GPLL0] = &gpll0.clkr,
> +	[GPLL4_MAIN] = &gpll4_main.clkr,
> +	[GPLL4] = &gpll4.clkr,
> +	[GPLL2_MAIN] = &gpll2_main.clkr,
> +	[GPLL2] = &gpll2.clkr,
> +	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
> +	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
> +	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
> +	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
> +	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
> +	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
> +	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
> +	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
> +	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
> +	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
> +	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
> +	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> +	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> +	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
> +	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
> +	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
> +	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
> +	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
> +	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
> +	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
> +	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
> +	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
> +	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
> +	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
> +	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
> +	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
> +	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
> +	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
> +	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
> +	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
> +	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
> +	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
> +	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
> +	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
> +	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
> +	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
> +	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
> +	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
> +	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
> +	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
> +	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
> +	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
> +	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
> +	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
> +	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
> +	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
> +	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
> +	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
> +	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
> +	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
> +	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
> +	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
> +	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
> +	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
> +	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
> +	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
> +	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
> +	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
> +	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
> +	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
> +	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> +	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> +	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
> +	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
> +	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
> +	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
> +	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
> +	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
> +	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
> +	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
> +	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
> +	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
> +	[GCC_SNOC_PCNOC_AHB_CLK] = &gcc_snoc_pcnoc_ahb_clk.clkr,
> +	[GCC_ANOC_PCNOC_AHB_CLK] = &gcc_anoc_pcnoc_ahb_clk.clkr,
> +	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
> +	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
> +	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> +	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
> +	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
> +	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
> +	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
> +	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
> +	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
> +	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
> +	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
> +	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
> +	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
> +	[GCC_SYS_NOC_AXI_CLK] = &gcc_sys_noc_axi_clk.clkr,
> +	[GCC_ANOC0_AXI_CLK] = &gcc_anoc0_axi_clk.clkr,
> +	[GCC_ANOC1_AXI_CLK] = &gcc_anoc1_axi_clk.clkr,
> +	[GCC_ANOC0_TBU_CLK] = &gcc_anoc0_tbu_clk.clkr,
> +	[GCC_ANOC1_TBU_CLK] = &gcc_anoc1_tbu_clk.clkr,
> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = &gcc_mem_noc_snoc_axi_clk.clkr,
> +	[GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
> +	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
> +	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
> +	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
> +	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
> +	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
> +	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
> +	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
> +	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
> +	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
> +	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
> +	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
> +	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
> +	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
> +	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
> +	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
> +	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
> +	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
> +	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
> +	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
> +	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
> +	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
> +	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
> +	[GCC_SNOC_TS_CLK] = &gcc_snoc_ts_clk.clkr,
> +	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
> +	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
> +	[GCC_PCNOC_TS_CLK] = &gcc_pcnoc_ts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
> +	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
> +	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
> +	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
> +	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
> +	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
> +	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
> +	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
> +	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
> +	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
> +	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
> +	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
> +	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
> +	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
> +	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
> +	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
> +	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
> +	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
> +	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
> +	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
> +	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
> +	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
> +	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
> +	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
> +	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
> +	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
> +	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
> +	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
> +	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
> +	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
> +	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
> +	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
> +	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
> +	[GCC_PCNOC_DCC_CLK] = &gcc_pcnoc_dcc_clk.clkr,
> +};
> +
> +static struct clk_regmap *gcc_ipq9574_dummy_clks[] = {
> +	[GPLL0_MAIN] = DEFINE_DUMMY_CLK(gpll0_main),
> +	[GPLL0] = DEFINE_DUMMY_CLK(gpll0),
> +	[GPLL4_MAIN] = DEFINE_DUMMY_CLK(gpll4_main),
> +	[GPLL4] = DEFINE_DUMMY_CLK(gpll4),
> +	[GPLL2_MAIN] = DEFINE_DUMMY_CLK(gpll2_main),
> +	[GPLL2] = DEFINE_DUMMY_CLK(gpll2),
> +	[GCC_SLEEP_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_sleep_clk_src),
> +	[APSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(apss_ahb_clk_src),
> +	[APSS_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(apss_axi_clk_src),
> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_i2c_apps_clk_src),
> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_spi_apps_clk_src),
> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_i2c_apps_clk_src),
> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_spi_apps_clk_src),
> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_i2c_apps_clk_src),
> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_spi_apps_clk_src),
> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_i2c_apps_clk_src),
> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_spi_apps_clk_src),
> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_i2c_apps_clk_src),
> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_spi_apps_clk_src),
> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_i2c_apps_clk_src),
> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_spi_apps_clk_src),
> +	[BLSP1_UART1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart1_apps_clk_src),
> +	[BLSP1_UART2_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart2_apps_clk_src),
> +	[BLSP1_UART3_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart3_apps_clk_src),
> +	[BLSP1_UART4_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart4_apps_clk_src),
> +	[BLSP1_UART5_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart5_apps_clk_src),
> +	[BLSP1_UART6_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart6_apps_clk_src),
> +	[GCC_APSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_apss_ahb_clk),
> +	[GCC_APSS_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_apss_axi_clk),
> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_i2c_apps_clk),
> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_spi_apps_clk),
> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_i2c_apps_clk),
> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_spi_apps_clk),
> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_i2c_apps_clk),
> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_spi_apps_clk),
> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_i2c_apps_clk),
> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_spi_apps_clk),
> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_i2c_apps_clk),
> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_spi_apps_clk),
> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_i2c_apps_clk),
> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_spi_apps_clk),
> +	[GCC_BLSP1_UART1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart1_apps_clk),
> +	[GCC_BLSP1_UART2_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart2_apps_clk),
> +	[GCC_BLSP1_UART3_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart3_apps_clk),
> +	[GCC_BLSP1_UART4_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart4_apps_clk),
> +	[GCC_BLSP1_UART5_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart5_apps_clk),
> +	[GCC_BLSP1_UART6_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart6_apps_clk),
> +	[PCIE0_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_m_clk_src),
> +	[GCC_PCIE0_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_m_clk),
> +	[PCIE1_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_m_clk_src),
> +	[GCC_PCIE1_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_m_clk),
> +	[PCIE2_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_m_clk_src),
> +	[GCC_PCIE2_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_m_clk),
> +	[PCIE3_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_m_clk_src),
> +	[GCC_PCIE3_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_m_clk),
> +	[PCIE0_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_s_clk_src),
> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_bridge_clk),
> +	[GCC_PCIE0_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_clk),
> +	[PCIE1_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_s_clk_src),
> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_bridge_clk),
> +	[GCC_PCIE1_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_clk),
> +	[PCIE2_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_s_clk_src),
> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_bridge_clk),
> +	[GCC_PCIE2_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_clk),
> +	[PCIE3_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_s_clk_src),
> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_bridge_clk),
> +	[GCC_PCIE3_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_clk),
> +	[PCIE0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_pipe_clk_src),
> +	[PCIE1_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_pipe_clk_src),
> +	[PCIE2_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_pipe_clk_src),
> +	[PCIE3_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_pipe_clk_src),
> +	[PCIE_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(pcie_aux_clk_src),
> +	[GCC_PCIE0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_aux_clk),
> +	[GCC_PCIE1_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_aux_clk),
> +	[GCC_PCIE2_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_aux_clk),
> +	[GCC_PCIE3_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_aux_clk),
> +	[PCIE0_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_rchng_clk_src),
> +	[GCC_PCIE0_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_rchng_clk),
> +	[PCIE1_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_rchng_clk_src),
> +	[GCC_PCIE1_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_rchng_clk),
> +	[PCIE2_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_rchng_clk_src),
> +	[GCC_PCIE2_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_rchng_clk),
> +	[PCIE3_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_rchng_clk_src),
> +	[GCC_PCIE3_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_rchng_clk),
> +	[GCC_PCIE0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_ahb_clk),
> +	[GCC_PCIE1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_ahb_clk),
> +	[GCC_PCIE2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_ahb_clk),
> +	[GCC_PCIE3_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_ahb_clk),
> +	[USB0_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_aux_clk_src),
> +	[GCC_USB0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_aux_clk),
> +	[USB0_MASTER_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_master_clk_src),
> +	[GCC_USB0_MASTER_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_master_clk),
> +	[GCC_SNOC_USB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_usb_clk),
> +	[GCC_ANOC_USB_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_usb_axi_clk),
> +	[USB0_MOCK_UTMI_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_clk_src),
> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_div_clk_src),
> +	[GCC_USB0_MOCK_UTMI_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_mock_utmi_clk),
> +	[USB0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_pipe_clk_src),
> +	[GCC_USB0_PHY_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_phy_cfg_ahb_clk),
> +	[SDCC1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_apps_clk_src),
> +	[GCC_SDCC1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_apps_clk),
> +	[SDCC1_ICE_CORE_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_ice_core_clk_src),
> +	[GCC_SDCC1_ICE_CORE_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ice_core_clk),
> +	[GCC_SDCC1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ahb_clk),
> +	[PCNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(pcnoc_bfdcd_clk_src),
> +	[GCC_NSSCFG_CLK] = DEFINE_DUMMY_CLK(gcc_nsscfg_clk),
> +	[GCC_NSSNOC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_nsscc_clk),
> +	[GCC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nsscc_clk),
> +	[GCC_NSSNOC_PCNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_pcnoc_1_clk),
> +	[GCC_QDSS_DAP_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_ahb_clk),
> +	[GCC_QDSS_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_cfg_ahb_clk),
> +	[GCC_SNOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcnoc_ahb_clk),
> +	[GCC_ANOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcnoc_ahb_clk),
> +	[GCC_QPIC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_ahb_clk),
> +	[GCC_QPIC_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_clk),
> +	[GCC_BLSP1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_ahb_clk),
> +	[GCC_MDIO_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_mdio_ahb_clk),
> +	[GCC_PRNG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_prng_ahb_clk),
> +	[GCC_UNIPHY0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_ahb_clk),
> +	[GCC_UNIPHY1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_ahb_clk),
> +	[GCC_UNIPHY2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_ahb_clk),
> +	[GCC_CMN_12GPLL_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_ahb_clk),
> +	[GCC_CMN_12GPLL_APU_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_apu_clk),
> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(system_noc_bfdcd_clk_src),
> +	[GCC_NSSNOC_SNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_clk),
> +	[GCC_NSSNOC_SNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_1_clk),
> +	[GCC_QDSS_ETR_USB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_etr_usb_clk),
> +	[GCC_SYS_NOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_axi_clk),
> +	[GCC_ANOC0_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_axi_clk),
> +	[GCC_ANOC1_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_axi_clk),
> +	[GCC_ANOC0_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_tbu_clk),
> +	[GCC_ANOC1_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_tbu_clk),
> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_snoc_axi_clk),
> +	[GCC_IMEM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_imem_axi_clk),
> +	[WCSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_ahb_clk_src),
> +	[GCC_Q6_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_clk),
> +	[GCC_Q6_AHB_S_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_s_clk),
> +	[GCC_WCSS_ECAHB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_ecahb_clk),
> +	[GCC_WCSS_ACMT_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_acmt_clk),
> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_wcss_ahb_clk),
> +	[WCSS_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_axi_m_clk_src),
> +	[GCC_ANOC_WCSS_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_wcss_axi_m_clk),
> +	[QDSS_AT_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_at_clk_src),
> +	[GCC_Q6SS_ATBM_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_atbm_clk),
> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_atb_clk),
> +	[GCC_NSSNOC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_atb_clk),
> +	[GCC_QDSS_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_at_clk),
> +	[GCC_SYS_NOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_at_clk),
> +	[GCC_PCNOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_at_clk),
> +	[GCC_USB0_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_eud_at_clk),
> +	[GCC_QDSS_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_eud_at_clk),
> +	[QDSS_STM_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_stm_clk_src),
> +	[GCC_QDSS_STM_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_stm_clk),
> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_qdss_stm_axi_clk),
> +	[QDSS_TRACECLKIN_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_traceclkin_clk_src),
> +	[GCC_QDSS_TRACECLKIN_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_traceclkin_clk),
> +	[QDSS_TSCTR_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_tsctr_clk_src),
> +	[GCC_Q6_TSCTR_1TO2_CLK] = DEFINE_DUMMY_CLK(gcc_q6_tsctr_1to2_clk),
> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_nts_clk),
> +	[GCC_QDSS_TSCTR_DIV2_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div2_clk),
> +	[GCC_QDSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_ts_clk),
> +	[GCC_SNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_ts_clk),
> +	[GCC_MEM_NOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_ts_clk),
> +	[GCC_QDSS_TSCTR_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div4_clk),
> +	[GCC_NSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_nss_ts_clk),
> +	[GCC_QDSS_TSCTR_DIV8_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div8_clk),
> +	[GCC_PCNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_ts_clk),
> +	[GCC_QDSS_TSCTR_DIV16_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div16_clk),
> +	[GCC_Q6SS_PCLKDBG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_pclkdbg_clk),
> +	[GCC_Q6SS_TRIG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_trig_clk),
> +	[GCC_WCSS_DBG_IFC_APB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_apb_clk),
> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_dapbus_clk),
> +	[GCC_QDSS_DAP_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_clk),
> +	[GCC_QDSS_APB2JTAG_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_apb2jtag_clk),
> +	[GCC_QDSS_TSCTR_DIV3_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div3_clk),
> +	[QPIC_IO_MACRO_CLK_SRC] = DEFINE_DUMMY_CLK(qpic_io_macro_clk_src),
> +	[GCC_QPIC_IO_MACRO_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_io_macro_clk),
> +	[Q6_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axi_clk_src),
> +	[GCC_Q6_AXIM_CLK] = DEFINE_DUMMY_CLK(gcc_q6_axim_clk),
> +	[GCC_WCSS_Q6_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_q6_tbu_clk),
> +	[GCC_MEM_NOC_Q6_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_q6_axi_clk),
> +	[Q6_AXIM2_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axim2_clk_src),
> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(nssnoc_memnoc_bfdcd_clk_src),
> +	[GCC_NSSNOC_MEMNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_memnoc_clk),
> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_mem_noc_1_clk),
> +	[GCC_NSS_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_nss_tbu_clk),
> +	[GCC_MEM_NOC_NSSNOC_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_nssnoc_clk),
> +	[LPASS_AXIM_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_axim_clk_src),
> +	[LPASS_SWAY_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_sway_clk_src),
> +	[ADSS_PWM_CLK_SRC] = DEFINE_DUMMY_CLK(adss_pwm_clk_src),
> +	[GCC_ADSS_PWM_CLK] = DEFINE_DUMMY_CLK(gcc_adss_pwm_clk),
> +	[GP1_CLK_SRC] = DEFINE_DUMMY_CLK(gp1_clk_src),
> +	[GP2_CLK_SRC] = DEFINE_DUMMY_CLK(gp2_clk_src),
> +	[GP3_CLK_SRC] = DEFINE_DUMMY_CLK(gp3_clk_src),
> +	[DDRSS_SMS_SLOW_CLK_SRC] = DEFINE_DUMMY_CLK(ddrss_sms_slow_clk_src),
> +	[GCC_XO_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_xo_clk_src),
> +	[GCC_NSSNOC_XO_DCD_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_xo_dcd_clk),
> +	[GCC_XO_CLK] = DEFINE_DUMMY_CLK(gcc_xo_clk),
> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_qosgen_ref_clk),
> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_timeout_ref_clk),
> +	[GCC_XO_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_xo_div4_clk),
> +	[GCC_UNIPHY0_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_sys_clk),
> +	[GCC_UNIPHY1_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_sys_clk),
> +	[GCC_UNIPHY2_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_sys_clk),
> +	[GCC_CMN_12GPLL_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_sys_clk),
> +	[GCC_Q6SS_BOOT_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_boot_clk),
> +	[UNIPHY_SYS_CLK_SRC] = DEFINE_DUMMY_CLK(uniphy_sys_clk_src),
> +	[NSS_TS_CLK_SRC] = DEFINE_DUMMY_CLK(nss_ts_clk_src),
> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie0_1lane_m_clk),
> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie1_1lane_m_clk),
> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie2_2lane_m_clk),
> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie3_2lane_m_clk),
> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie0_1lane_s_clk),
> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie1_1lane_s_clk),
> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie2_2lane_s_clk),
> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie3_2lane_s_clk),
> +	[GCC_PCNOC_DCC_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_dcc_clk),
> +};
Drop.

> +
> +static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> +	[GCC_ADSS_BCR] = { 0x1c000, 0 },
> +	[GCC_ANOC0_TBU_BCR] = { 0x1203C, 0 },
> +	[GCC_ANOC1_TBU_BCR] = { 0x1204C, 0 },
> +	[GCC_ANOC_BCR] = { 0x2E074, 0 },
> +	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
> +	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
> +	[GCC_BLSP1_BCR] = { 0x01000, 0 },
> +	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
> +	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
> +	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
> +	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
> +	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
> +	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
> +	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
> +	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
> +	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
> +	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
> +	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
> +	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
> +	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
> +	[GCC_CMN_BLK_BCR] = { 0x3A000, 0 },
> +	[GCC_CMN_BLK_AHB_ARES] = { 0x3A010, 0 },
> +	[GCC_CMN_BLK_SYS_ARES] = { 0x3A010, 1 },
> +	[GCC_CMN_BLK_APU_ARES] = { 0x3A010, 2 },
> +	[GCC_DCC_BCR] = { 0x35000, 0 },
> +	[GCC_DDRSS_BCR] = { 0x11000, 0 },
> +	[GCC_IMEM_BCR] = { 0x0e000, 0 },
> +	[GCC_LPASS_BCR] = { 0x27000, 0 },
> +	[GCC_MDIO_BCR] = { 0x1703c, 0 },
> +	[GCC_MPM_BCR] = { 0x37000, 0 },
> +	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
> +	[GCC_NSS_BCR] = { 0x17000, 0 },
> +	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
> +	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
> +	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
> +	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
> +	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
> +	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
> +	[GCC_NSSCC_ARES] = { 0x17038, 8 },
> +	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
> +	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
> +	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
> +	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
> +	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
> +	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
> +	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
> +	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
> +	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
> +	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
> +	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
> +	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
> +	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
> +	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
> +	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
> +	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
> +	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
> +	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
> +	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
> +	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
> +	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
> +	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
> +	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
> +	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
> +	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
> +	[GCC_PCIE2_AHB_ARES] = { 0x2A058, 7 },
> +	[GCC_PCIE2_AUX_ARES] = { 0x2A058, 6 },
> +	[GCC_PCIE2_AXI_M_ARES] = { 0x2A058, 5 },
> +	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2A058, 4 },
> +	[GCC_PCIE2_AXI_S_ARES] = { 0x2A058, 3 },
> +	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2A058, 2 },
> +	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2A058, 1 },
> +	[GCC_PCIE2_PIPE_ARES] = { 0x2A058, 0 },
> +	[GCC_PCIE3_AHB_ARES] = { 0x2B058, 7 },
> +	[GCC_PCIE3_AUX_ARES] = { 0x2B058, 6 },
> +	[GCC_PCIE3_AXI_M_ARES] = { 0x2B058, 5 },
> +	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2B058, 4 },
> +	[GCC_PCIE3_AXI_S_ARES] = { 0x2B058, 3 },
> +	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2B058, 2 },
> +	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2B058, 1 },
> +	[GCC_PCIE3_PIPE_ARES] = { 0x2B058, 0 },
> +	[GCC_PCIE0_BCR] = { 0x28000, 0 },
> +	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
> +	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
> +	[GCC_PCIE1_BCR] = { 0x29000, 0 },
> +	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
> +	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
> +	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
> +	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
> +	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
> +	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
> +	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
> +	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
> +	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
> +	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
> +	[GCC_PCIE3_PHY_BCR] = { 0x2B060, 0 },
> +	[GCC_PCNOC_BCR] = { 0x31000, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
> +	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
> +	[GCC_PRNG_BCR] = { 0x13020, 0 },
> +	[GCC_Q6SS_DBG_ARES] = { 0x2506C, 4 },
> +	[GCC_Q6_AHB_ARES] = { 0x2506C, 3 },
> +	[GCC_Q6_AHB_S_ARES] = { 0x2506C, 2 },
> +	[GCC_Q6_AXIM2_ARES] = { 0x2506C, 1 },
> +	[GCC_Q6_AXIM_ARES] = { 0x2506C, 0 },
> +	[GCC_QDSS_BCR] = { 0x2d000, 0 },
> +	[GCC_QPIC_BCR] = { 0x32000, 0 },
> +	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
> +	[GCC_QPIC_ARES] = { 0x3201c, 0 },
> +	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
> +	[GCC_RBCPR_BCR] = { 0x39000, 0 },
> +	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
> +	[GCC_SDCC_BCR] = { 0x33000, 0 },
> +	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
> +	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
> +	[GCC_SNOC_BCR] = { 0x2E000, 0 },
> +	[GCC_SPDM_BCR] = { 0x36000, 0 },
> +	[GCC_TCSR_BCR] = { 0x3d000, 0 },
> +	[GCC_TLMM_BCR] = { 0x3e000, 0 },
> +	[GCC_TME_BCR] = { 0x10000, 0 },
> +	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
> +	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
> +	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
> +	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
> +	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
> +	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
> +	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
> +	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
> +	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
> +	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
> +	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
> +	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
> +	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
> +	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
> +	[GCC_USB_BCR] = { 0x2c000, 0 },
> +	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
> +	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
> +	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
> +	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
> +	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
> +	[GCC_WCSS_BCR] = { 0x18004, 0 },
> +	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
> +	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
> +	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
> +	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
> +	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
> +};
> +
> +static const struct of_device_id gcc_ipq9574_match_table[] = {
> +	{ .compatible = "qcom,gcc-ipq9574" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
> +
> +static const struct regmap_config gcc_ipq9574_regmap_config = {
> +	.reg_bits       = 32,
> +	.reg_stride     = 4,
> +	.val_bits       = 32,
> +	.max_register   = 0x7fffc,
> +	.fast_io	= true,
> +};
> +
> +static const struct qcom_cc_desc gcc_ipq9574_desc = {
> +	.config = &gcc_ipq9574_regmap_config,
> +	.clks = gcc_ipq9574_clks,
> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
> +	.resets = gcc_ipq9574_resets,
> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
> +	.clk_hws = gcc_ipq9574_hws,
> +	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
> +};
> +
> +static const struct qcom_cc_desc gcc_ipq9574_dummy_desc = {
> +	.config = &gcc_ipq9574_regmap_config,
> +	.clks = gcc_ipq9574_dummy_clks,
> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_dummy_clks),
> +	.resets = gcc_ipq9574_resets,
> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
> +};
> +
> +static int gcc_ipq9574_probe(struct platform_device *pdev)
> +{
> +	struct regmap *regmap;
> +	struct qcom_cc_desc ipq9574_desc = gcc_ipq9574_desc;
> +	struct device_node *np = (&pdev->dev)->of_node;
> +
> +	if (of_property_read_bool(np, "gcc-use-dummy"))
> +		ipq9574_desc = gcc_ipq9574_dummy_desc;
> +
> +	regmap = qcom_cc_map(pdev, &ipq9574_desc);
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	return qcom_cc_really_probe(pdev, &ipq9574_desc, regmap);
> +}
> +
> +static int gcc_ipq9574_remove(struct platform_device *pdev)
Generally you shouldn't remove the driver that ensures your platform
well, works..

Plus GCCs are always =y in mainline to make sure dependencies are met
so there's no removing.

> +{
> +	return 0;
> +}
> +
> +static struct platform_driver gcc_ipq9574_driver = {
> +	.probe = gcc_ipq9574_probe,
> +	.remove = gcc_ipq9574_remove,
> +	.driver = {
> +		.name   = "qcom,gcc-ipq9574",
> +		.of_match_table = gcc_ipq9574_match_table,
> +	},
> +};
> +
> +static int __init gcc_ipq9574_init(void)
> +{
> +	return platform_driver_register(&gcc_ipq9574_driver);
> +}
> +core_initcall(gcc_ipq9574_init);
> +
> +static void __exit gcc_ipq9574_exit(void)
> +{
> +	platform_driver_unregister(&gcc_ipq9574_driver);
> +}
> +module_exit(gcc_ipq9574_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
> +MODULE_LICENSE("GPL");

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Konrad Dybcio]

On 10.01.2023 13:13, devi priya wrote:
> Add Global Clock Controller (GCC) driver for ipq9574 based devices
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  drivers/clk/qcom/Kconfig       |    8 +
>  drivers/clk/qcom/Makefile      |    1 +
>  drivers/clk/qcom/gcc-ipq9574.c | 4706 ++++++++++++++++++++++++++++++++
>  3 files changed, 4715 insertions(+)
>  create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
> 
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index 70d43f0a8919..97517d1e3ba4 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -173,6 +173,14 @@ config IPQ_GCC_8074
>  	  i2c, USB, SD/eMMC, etc. Select this for the root clock
>  	  of ipq8074.
>  
> +config IPQ_GCC_9574
> +	tristate "IPQ9574 Global Clock Controller"
> +	help
> +	  Support for global clock controller on ipq9574 devices.
> +	  Say Y if you want to use peripheral devices such as UART, SPI,
> +	  i2c, USB, SD/eMMC, etc. Select this for the root clock
> +	  of ipq9574.
> +
>  config MSM_GCC_8660
>  	tristate "MSM8660 Global Clock Controller"
>  	help
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index f18c446a97ea..55c6ada326e0 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>  obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>  obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>  obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
> +obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>  obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>  obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>  obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
> new file mode 100644
> index 000000000000..f44a19c5f9a1
> --- /dev/null
> +++ b/drivers/clk/qcom/gcc-ipq9574.c
> @@ -0,0 +1,4706 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
Hm, interesting choice for a C driver..

> +/*
> + * Copyright (c) 2022 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk-provider.h>
> +#include <linux/regmap.h>
> +
> +#include <linux/reset-controller.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
> +
> +#include "common.h"
> +#include "clk-regmap.h"
> +#include "clk-pll.h"
> +#include "clk-rcg.h"
> +#include "clk-branch.h"
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap-divider.h"
> +#include "clk-regmap-mux.h"
> +#include "reset.h"
Many of these includes seem unnecessary..


> +
> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
Drop.

> +
> +/* Need to match the order of clocks in DT binding */
> +enum {
> +	DT_XO,
> +	DT_SLEEP_CLK,
> +	DT_BIAS_PLL_UBI_NC_CLK,
> +	DT_PCIE30_PHY0_PIPE_CLK,
> +	DT_PCIE30_PHY1_PIPE_CLK,
> +	DT_PCIE30_PHY2_PIPE_CLK,
> +	DT_PCIE30_PHY3_PIPE_CLK,
> +	DT_USB3PHY_0_CC_PIPE_CLK,
> +};
> +
> +enum {
> +	P_XO,
> +	P_PCIE30_PHY0_PIPE,
> +	P_PCIE30_PHY1_PIPE,
> +	P_PCIE30_PHY2_PIPE,
> +	P_PCIE30_PHY3_PIPE,
> +	P_USB3PHY_0_PIPE,
> +	P_GPLL0,
> +	P_GPLL0_DIV2,
> +	P_GPLL0_OUT_AUX,
> +	P_GPLL2,
> +	P_GPLL4,
> +	P_PI_SLEEP,
> +	P_BIAS_PLL_UBI_NC_CLK,
> +};
> +
> +static const struct parent_map gcc_xo_map[] = {
> +	{ P_XO, 0 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_data[] = {
> +	{ .index = DT_XO },
> +};
> +
> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
> +	{ .index = DT_SLEEP_CLK },
> +};
> +
> +static struct clk_alpha_pll gpll0_main = {
> +	.offset = 0x20000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.clkr = {
> +		.enable_reg = 0x0b000,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gpll0_main",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.ops = &clk_alpha_pll_ops,
> +			.flags = CLK_IS_CRITICAL,
Is it? Does it act as a CPU PLL source that's not managed by the
firmware?

> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor gpll0_out_main_div2 = {
> +	.mult = 1,
> +	.div = 2,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "gpll0_out_main_div2",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll0_main.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll0 = {
> +	.offset = 0x20000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.width = 4,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gpll0",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll0_main.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_alpha_pll gpll4_main = {
> +	.offset = 0x22000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.clkr = {
> +		.enable_reg = 0x0b000,
> +		.enable_mask = BIT(2),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gpll4_main",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.ops = &clk_alpha_pll_ops,
> +			.flags = CLK_IS_CRITICAL,
Again, is it?

> +		},
> +	},
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll4 = {
> +	.offset = 0x22000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.width = 4,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gpll4",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll4_main.clkr.hw },
Please put the }, in a new line.

> +		.num_parents = 1,
> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_alpha_pll gpll2_main = {
> +	.offset = 0x21000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.clkr = {
> +		.enable_reg = 0x0b000,
> +		.enable_mask = BIT(1),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gpll2_main",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.ops = &clk_alpha_pll_ops,
> +			.flags = CLK_IS_CRITICAL,
> +		},
> +	},
> +};
> +
> +static struct clk_alpha_pll_postdiv gpll2 = {
> +	.offset = 0x21000,
> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
> +	.width = 4,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gpll2",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gpll2_main.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_branch gcc_sleep_clk_src = {
> +	.halt_reg = 0x3400c,
> +	.clkr = {
> +		.enable_reg = 0x3400c,
> +		.enable_mask = BIT(1),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sleep_clk_src",
> +			.parent_data = gcc_sleep_clk_data,
> +			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
> +			.ops = &clk_branch2_ops,
> +			.flags = CLK_IS_CRITICAL,
> +		},
> +	},
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw},
Please consistently add a space before },

> +	{ .hw = &gpll0_out_main_div2.hw},
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL0_DIV2, 4 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .hw = &gpll4.clkr.hw },
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL4, 2 },
> +};
> +
> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
> +	{ .index = DT_XO },
> +	{ .hw = &gpll0.clkr.hw },
> +	{ .hw = &gpll0_out_main_div2.hw },
> +	{ .hw = &gpll0.clkr.hw },
> +};
> +
> +static const struct parent_map
> +gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
Pretty sure you can unwrap that line


> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL0_DIV2, 4 },
> +	{ P_GPLL0, 5 },
> +};
> +

[...]

> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
> +	.halt_reg = 0x07024,
> +	.clkr = {
> +		.enable_reg = 0x07024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_blsp1_qup6_i2c_apps_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Sounds very much like a hack..

[...]


> +static struct clk_branch gcc_snoc_usb_clk = {
> +	.halt_reg = 0x2E058,
Please lowercase hex all throughout the file.

> +	.clkr = {
> +		.enable_reg = 0x2E058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_snoc_usb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&usb0_master_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
[...]

> +
> +static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
> +	.cmd_rcgr = 0x31004,
> +	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "pcnoc_bfdcd_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> +		.ops = &clk_rcg2_ops,
> +		.flags = CLK_IS_CRITICAL,
> +	},
> +};
> +
> +static struct clk_fixed_factor pcnoc_clk_src = {
> +	.mult = 1,
> +	.div = 1,
Is there any benefit in keeping it instead of providing
the real rcg as a parent?

> +	.hw.init = &(struct clk_init_data) {
> +		.name = "pcnoc_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&pcnoc_bfdcd_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +

[...]
> +static struct clk_branch gcc_snoc_pcnoc_ahb_clk = {
> +	.halt_reg = 0x2E03C,
> +	.clkr = {
> +		.enable_reg = 0x2E03C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_snoc_pcnoc_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&pcnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Can it be turned off? Perhaps CLK_IS_CRITICAL would be more fitting,
with a comment explaining why.


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc_pcnoc_ahb_clk = {
> +	.halt_reg = 0x2E094,
> +	.clkr = {
> +		.enable_reg = 0x2E094,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc_pcnoc_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&pcnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Same thing

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +

> +
> +static struct clk_rcg2 system_noc_bfdcd_clk_src = {
> +	.cmd_rcgr = 0x2e004,
> +	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll4_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "system_noc_bfdcd_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll4,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
> +		.ops = &clk_rcg2_ops,
> +		.flags = CLK_IS_CRITICAL,
.flags goes before .ops in all other nodes, please be consistent.

> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_boot_clk = {
> +	.halt_reg = 0x25080,
> +	.halt_check = BRANCH_HALT_SKIP,
> +	.clkr = {
> +		.enable_reg = 0x25080,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_boot_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_snoc_clk = {
> +	.halt_reg = 0x17028,
> +	.clkr = {
> +		.enable_reg = 0x17028,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_snoc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Same story as with PCNoC
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_snoc_1_clk = {
> +	.halt_reg = 0x1707c,
> +	.clkr = {
> +		.enable_reg = 0x1707c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_snoc_1_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
And here

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_etr_usb_clk = {
> +	.halt_reg = 0x2D060,
> +	.clkr = {
> +		.enable_reg = 0x2D060,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_etr_usb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(133333333, P_GPLL0, 6, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 wcss_ahb_clk_src = {
> +	.cmd_rcgr = 0x25030,
> +	.freq_tbl = ftbl_wcss_ahb_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "wcss_ahb_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_ahb_clk = {
> +	.halt_reg = 0x25014,
> +	.clkr = {
> +		.enable_reg = 0x25014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
This sounds like a hack, perhaps it should be fed to a remoteproc node?


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_ahb_s_clk = {
> +	.halt_reg = 0x25018,
> +	.clkr = {
> +		.enable_reg = 0x25018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_ahb_s_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
And this one too

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_ecahb_clk = {
> +	.halt_reg = 0x25058,
> +	.clkr = {
> +		.enable_reg = 0x25058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_ecahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Similarly, this one should probably be fed to the wcss node and
properly managed with a driver, not left dangling

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_acmt_clk = {
> +	.halt_reg = 0x2505c,
> +	.clkr = {
> +		.enable_reg = 0x2505c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_acmt_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_axi_clk = {
> +	.halt_reg = 0x2e01c,
> +	.clkr = {
> +		.enable_reg = 0x2e01c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
CLK_IS_CRITICAL?

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc0_axi_clk = {
> +	.halt_reg = 0x2e078,
> +	.clkr = {
> +		.enable_reg = 0x2e078,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc0_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
If this it the same kind of ANoC(n) as on 8996/8998, this should
definitely be either CLK_IS_CRITICAL or managed through a driver..
Probably the second one..


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc1_axi_clk = {
> +	.halt_reg = 0x2e088,
> +	.clkr = {
> +		.enable_reg = 0x2e088,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc1_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc0_tbu_clk = {
> +	.halt_reg = 0x12038,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(3),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc0_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc1_tbu_clk = {
> +	.halt_reg = 0x12048,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(5),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc1_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_snoc_axi_clk = {
> +	.halt_reg = 0x19018,
> +	.clkr = {
> +		.enable_reg = 0x19018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_snoc_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
This one also smells of an interconnect clock more than anything else..


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_imem_axi_clk = {
> +	.halt_reg = 0xe004,
> +	.clkr = {
> +		.enable_reg = 0xb004,
> +		.enable_mask = BIT(12),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_imem_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&system_noc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
You could pass this one to the imem node

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
> +	.halt_reg = 0x2e030,
> +	.clkr = {
> +		.enable_reg = 0x2e030,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_wcss_ahb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_ahb_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Definitely handled through a driver..

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(133333333, P_GPLL0, 6, 0, 0),
> +	F(266666667, P_GPLL0, 3, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 wcss_axi_m_clk_src = {
> +	.cmd_rcgr = 0x25078,
> +	.freq_tbl = ftbl_wcss_axi_m_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "wcss_axi_m_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
> +	.halt_reg = 0x2e0a8,
> +	.clkr = {
> +		.enable_reg = 0x2e0a8,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_anoc_wcss_axi_m_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&wcss_axi_m_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
> +	F(240000000, P_GPLL4, 5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_at_clk_src = {
> +	.cmd_rcgr = 0x2d004,
> +	.freq_tbl = ftbl_qdss_at_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_at_clk_src",
> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_atbm_clk = {
> +	.halt_reg = 0x2501c,
> +	.clkr = {
> +		.enable_reg = 0x2501c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_atbm_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Ditto

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
> +	.halt_reg = 0x2503c,
> +	.clkr = {
> +		.enable_reg = 0x2503c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_atb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
Not gonna point out every similar occurence, you probably get me now

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_atb_clk = {
> +	.halt_reg = 0x17014,
> +	.clkr = {
> +		.enable_reg = 0x17014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_atb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_at_clk = {
> +	.halt_reg = 0x2D038,
> +	.clkr = {
> +		.enable_reg = 0x2D038,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Probably not critical, you don't need debug 24/7.


> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_at_clk = {
> +	.halt_reg = 0x2e038,
> +	.clkr = {
> +		.enable_reg = 0x2e038,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcnoc_at_clk = {
> +	.halt_reg = 0x31024,
> +	.clkr = {
> +		.enable_reg = 0x31024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_pcnoc_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_at_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
> +	.mult = 1,
> +	.div = 6,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "gcc_eud_at_div_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_at_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_usb0_eud_at_clk = {
> +	.halt_reg = 0x30004,
> +	.clkr = {
> +		.enable_reg = 0x30004,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_usb0_eud_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_eud_at_div_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Definitely not critical.

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_eud_at_clk = {
> +	.halt_reg = 0x2D06C,
> +	.clkr = {
> +		.enable_reg = 0x2D06C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_eud_at_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_eud_at_div_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Ditto.

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_stm_clk_src = {
> +	.cmd_rcgr = 0x2D00C,
> +	.freq_tbl = ftbl_qdss_stm_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_stm_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_stm_clk = {
> +	.halt_reg = 0x2D03C,
> +	.clkr = {
> +		.enable_reg = 0x2D03C,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_stm_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_stm_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
> +	.halt_reg = 0x2E034,
> +	.clkr = {
> +		.enable_reg = 0x2E034,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_sys_noc_qdss_stm_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_stm_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
> +	F(300000000, P_GPLL4, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_traceclkin_clk_src = {
> +	.cmd_rcgr = 0x2d014,
> +	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_traceclkin_clk_src",
> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_traceclkin_clk = {
> +	.halt_reg = 0x2D040,
> +	.clkr = {
> +		.enable_reg = 0x2D040,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_traceclkin_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_traceclkin_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
> +	F(600000000, P_GPLL4, 2, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qdss_tsctr_clk_src = {
> +	.cmd_rcgr = 0x2d01c,
> +	.freq_tbl = ftbl_qdss_tsctr_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_clk_src",
> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
> +	.mult = 1,
> +	.div = 2,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div2_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.flags = CLK_SET_RATE_PARENT,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_tsctr_1to2_clk = {
> +	.halt_reg = 0x25020,
> +	.clkr = {
> +		.enable_reg = 0x25020,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_tsctr_1to2_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
> +	.halt_reg = 0x25040,
> +	.clkr = {
> +		.enable_reg = 0x25040,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_nts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div2_clk = {
> +	.halt_reg = 0x2d044,
> +	.clkr = {
> +		.enable_reg = 0x2d044,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div2_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 uniphy_sys_clk_src = {
> +	.cmd_rcgr = 0x17090,
> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "uniphy_sys_clk_src",
> +		.parent_data = gcc_xo_data,
> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 nss_ts_clk_src = {
> +	.cmd_rcgr = 0x17088,
> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
> +	.mnd_width = 8,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "nss_ts_clk_src",
> +		.parent_data = gcc_xo_data,
> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_ts_clk = {
> +	.halt_reg = 0x2D078,
> +	.clkr = {
> +		.enable_reg = 0x2D078,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nss_ts_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_snoc_ts_clk = {
> +	.halt_reg = 0x2e068,
> +	.clkr = {
> +		.enable_reg = 0x2e068,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_snoc_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_ts_clk = {
> +	.halt_reg = 0x19028,
> +	.clkr = {
> +		.enable_reg = 0x19028,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div2_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_dap_sync_clk_src = {
> +	.mult = 1,
> +	.div = 4,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_dap_sync_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div4_clk = {
> +	.halt_reg = 0x2d04c,
> +	.clkr = {
> +		.enable_reg = 0x2d04c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div4_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
> +	.mult = 1,
> +	.div = 8,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div8_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_nss_ts_clk = {
> +	.halt_reg = 0x17018,
> +	.clkr = {
> +		.enable_reg = 0x17018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nss_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nss_ts_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div8_clk = {
> +	.halt_reg = 0x2d050,
> +	.clkr = {
> +		.enable_reg = 0x2d050,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div8_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div8_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcnoc_ts_clk = {
> +	.halt_reg = 0x3102c,
> +	.clkr = {
> +		.enable_reg = 0x3102c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_pcnoc_ts_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div8_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
> +	.mult = 1,
> +	.div = 16,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div16_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div16_clk = {
> +	.halt_reg = 0x2d054,
> +	.clkr = {
> +		.enable_reg = 0x2d054,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div16_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div16_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_pclkdbg_clk = {
> +	.halt_reg = 0x25024,
> +	.clkr = {
> +		.enable_reg = 0x25024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_pclkdbg_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_q6ss_trig_clk = {
> +	.halt_reg = 0x25068,
> +	.clkr = {
> +		.enable_reg = 0x25068,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6ss_trig_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
> +	.halt_reg = 0x25038,
> +	.clkr = {
> +		.enable_reg = 0x25038,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_apb_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
> +	.halt_reg = 0x25044,
> +	.clkr = {
> +		.enable_reg = 0x25044,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_dap_clk = {
> +	.halt_reg = 0x2d058,
> +	.clkr = {
> +		.enable_reg = 0x2d058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_dap_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
Probably not critical.

> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_apb2jtag_clk = {
> +	.halt_reg = 0x2d05c,
> +	.clkr = {
> +		.enable_reg = 0x2d05c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_apb2jtag_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_pcnoc_dcc_clk = {
> +	.halt_reg = 0x31080,
> +	.clkr = {
> +		.enable_reg = 0x31080,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_pcnoc_dcc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_dap_sync_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
> +	.mult = 1,
> +	.div = 3,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "qdss_tsctr_div3_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&qdss_tsctr_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qdss_tsctr_div3_clk = {
> +	.halt_reg = 0x2d048,
> +	.clkr = {
> +		.enable_reg = 0x2d048,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qdss_tsctr_div3_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qdss_tsctr_div3_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(100000000, P_GPLL0, 8, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	F(320000000, P_GPLL0, 2.5, 0, 0),
> +	F(400000000, P_GPLL0, 2, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 qpic_io_macro_clk_src = {
> +	.cmd_rcgr = 0x32004,
> +	.freq_tbl = ftbl_qpic_io_macro_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "qpic_io_macro_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_qpic_io_macro_clk = {
> +	.halt_reg = 0x3200c,
> +	.clkr = {
> +		.enable_reg = 0x3200c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_qpic_io_macro_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&qpic_io_macro_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
> +	F(533333333, P_GPLL0, 1.5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 q6_axi_clk_src = {
> +	.cmd_rcgr = 0x25004,
> +	.freq_tbl = ftbl_q6_axi_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "q6_axi_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_q6_axim_clk = {
> +	.halt_reg = 0x2500c,
> +	.clkr = {
> +		.enable_reg = 0x2500c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_q6_axim_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&q6_axi_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_wcss_q6_tbu_clk = {
> +	.halt_reg = 0x12050,
> +	.halt_check = BRANCH_HALT_DELAY,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(6),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_wcss_q6_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&q6_axi_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_q6_axi_clk = {
> +	.halt_reg = 0x19010,
> +	.clkr = {
> +		.enable_reg = 0x19010,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_q6_axi_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&q6_axi_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
> +	F(342857143, P_GPLL4, 3.5, 0, 0),
> +	{ }
> +};
> +
> +static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
> +	{ P_XO, 0 },
> +	{ P_GPLL0, 1 },
> +	{ P_GPLL4, 2 },
> +	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
> +};
> +
> +static struct clk_rcg2 q6_axim2_clk_src = {
> +	.cmd_rcgr = 0x25028,
> +	.freq_tbl = ftbl_q6_axim2_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "q6_axim2_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
> +	F(533333333, P_GPLL0, 1.5, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
> +	.cmd_rcgr = 0x17004,
> +	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "nssnoc_memnoc_bfdcd_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_memnoc_clk = {
> +	.halt_reg = 0x17024,
> +	.clkr = {
> +		.enable_reg = 0x17024,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_memnoc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
> +	.halt_reg = 0x17084,
> +	.clkr = {
> +		.enable_reg = 0x17084,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_mem_noc_1_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nss_tbu_clk = {
> +	.halt_reg = 0x12040,
> +	.clkr = {
> +		.enable_reg = 0xb00c,
> +		.enable_mask = BIT(4),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nss_tbu_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_mem_noc_nssnoc_clk = {
> +	.halt_reg = 0x19014,
> +	.clkr = {
> +		.enable_reg = 0x19014,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_mem_noc_nssnoc_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
> +	F(133333333, P_GPLL0, 6, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 lpass_axim_clk_src = {
> +	.cmd_rcgr = 0x2700c,
> +	.freq_tbl = ftbl_lpass_axim_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "lpass_axim_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 lpass_sway_clk_src = {
> +	.cmd_rcgr = 0x27004,
> +	.freq_tbl = ftbl_lpass_axim_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "lpass_sway_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(100000000, P_GPLL0, 8, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 adss_pwm_clk_src = {
> +	.cmd_rcgr = 0x1c004,
> +	.freq_tbl = ftbl_adss_pwm_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "adss_pwm_clk_src",
> +		.parent_data = gcc_xo_gpll0,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_adss_pwm_clk = {
> +	.halt_reg = 0x1c00c,
> +	.clkr = {
> +		.enable_reg = 0x1c00c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_adss_pwm_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&adss_pwm_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static const struct freq_tbl ftbl_gp1_clk_src[] = {
> +	F(24000000, P_XO, 1, 0, 0),
> +	F(200000000, P_GPLL0, 4, 0, 0),
> +	{ }
> +};
> +
> +static struct clk_rcg2 gp1_clk_src = {
> +	.cmd_rcgr = 0x8004,
> +	.freq_tbl = ftbl_gp1_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gp1_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gp2_clk_src = {
> +	.cmd_rcgr = 0x9004,
> +	.freq_tbl = ftbl_gp1_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gp2_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_rcg2 gp3_clk_src = {
> +	.cmd_rcgr = 0xa004,
> +	.freq_tbl = ftbl_gp1_clk_src,
> +	.hid_width = 5,
> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
> +	.clkr.hw.init = &(struct clk_init_data) {
> +		.name = "gp3_clk_src",
> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
> +		.ops = &clk_rcg2_ops,
> +	},
> +};
> +
> +static struct clk_branch gcc_xo_clk_src = {
> +	.halt_reg = 0x34004,
> +	.clkr = {
> +		.enable_reg = 0x34004,
> +		.enable_mask = BIT(1),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_xo_clk_src",
> +			.parent_data = gcc_xo_data,
> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
> +	.halt_reg = 0x17074,
> +	.clkr = {
> +		.enable_reg = 0x17074,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_xo_dcd_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_xo_clk = {
> +	.halt_reg = 0x34018,
> +	.clkr = {
> +		.enable_reg = 0x34018,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_xo_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_uniphy0_sys_clk = {
> +	.halt_reg = 0x17048,
> +	.clkr = {
> +		.enable_reg = 0x17048,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_uniphy0_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_uniphy1_sys_clk = {
> +	.halt_reg = 0x17058,
> +	.clkr = {
> +		.enable_reg = 0x17058,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_uniphy1_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_uniphy2_sys_clk = {
> +	.halt_reg = 0x17068,
> +	.clkr = {
> +		.enable_reg = 0x17068,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_uniphy2_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_cmn_12gpll_sys_clk = {
> +	.halt_reg = 0x3a008,
> +	.clkr = {
> +		.enable_reg = 0x3a008,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_cmn_12gpll_sys_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&uniphy_sys_clk_src.clkr.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_fixed_factor gcc_xo_div4_clk_src = {
> +	.mult = 1,
> +	.div = 4,
> +	.hw.init = &(struct clk_init_data) {
> +		.name = "gcc_xo_div4_clk_src",
> +		.parent_hws = (const struct clk_hw *[]) {
> +				&gcc_xo_clk_src.clkr.hw },
> +		.num_parents = 1,
> +		.ops = &clk_fixed_factor_ops,
> +		.flags = CLK_SET_RATE_PARENT,
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
> +	.halt_reg = 0x1701c,
> +	.clkr = {
> +		.enable_reg = 0x1701c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_qosgen_ref_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_div4_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
> +	.halt_reg = 0x17020,
> +	.clkr = {
> +		.enable_reg = 0x17020,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_nssnoc_timeout_ref_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_div4_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_branch gcc_xo_div4_clk = {
> +	.halt_reg = 0x3401c,
> +	.clkr = {
> +		.enable_reg = 0x3401c,
> +		.enable_mask = BIT(0),
> +		.hw.init = &(struct clk_init_data) {
> +			.name = "gcc_xo_div4_clk",
> +			.parent_hws = (const struct clk_hw *[]) {
> +					&gcc_xo_div4_clk_src.hw },
> +			.num_parents = 1,
> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> +			.ops = &clk_branch2_ops,
> +		},
> +	},
> +};
> +
> +static struct clk_hw *gcc_ipq9574_hws[] = {
> +	&gpll0_out_main_div2.hw,
> +	&gcc_xo_div4_clk_src.hw,
> +	&qdss_dap_sync_clk_src.hw,
> +	&qdss_tsctr_div2_clk_src.hw,
> +	&qdss_tsctr_div8_clk_src.hw,
> +	&qdss_tsctr_div16_clk_src.hw,
> +	&qdss_tsctr_div3_clk_src.hw,
> +	&gcc_eud_at_div_clk_src.hw,
> +	&pcnoc_clk_src.hw,
> +};
> +

> +static int clk_dummy_is_enabled(struct clk_hw *hw)
> +{
> +	return 1;
> +};
> +
> +static int clk_dummy_enable(struct clk_hw *hw)
> +{
> +	return 0;
> +};
> +
> +static void clk_dummy_disable(struct clk_hw *hw)
> +{
> +	return;
> +};
> +
> +static u8 clk_dummy_get_parent(struct clk_hw *hw)
> +{
> +	return 0;
> +};
> +
> +static int clk_dummy_set_parent(struct clk_hw *hw, u8 index)
> +{
> +	return 0;
> +};
> +
> +static int clk_dummy_set_rate(struct clk_hw *hw, unsigned long rate,
> +			      unsigned long parent_rate)
> +{
> +	return 0;
> +};
> +
> +static int clk_dummy_determine_rate(struct clk_hw *hw,
> +				    struct clk_rate_request *req)
> +{
> +	return 0;
> +};
> +
> +static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw,
> +					   unsigned long parent_rate)
> +{
> +	return parent_rate;
> +};
> +
> +static const struct clk_ops clk_dummy_ops = {
> +	.is_enabled = clk_dummy_is_enabled,
> +	.enable = clk_dummy_enable,
> +	.disable = clk_dummy_disable,
> +	.get_parent = clk_dummy_get_parent,
> +	.set_parent = clk_dummy_set_parent,
> +	.set_rate = clk_dummy_set_rate,
> +	.recalc_rate = clk_dummy_recalc_rate,
> +	.determine_rate = clk_dummy_determine_rate,
> +};
> +
> +#define DEFINE_DUMMY_CLK(clk_name)				\
> +(&(struct clk_regmap) {						\
> +	.hw.init = &(struct clk_init_data) {			\
> +		.name = #clk_name,				\
> +		.parent_names = (const char *[]) { "xo"},	\
> +		.num_parents = 1,				\
> +		.ops = &clk_dummy_ops,				\
> +	},							\
> +})
Definitely a big no.

> +
> +static struct clk_regmap *gcc_ipq9574_clks[] = {
> +	[GPLL0_MAIN] = &gpll0_main.clkr,
> +	[GPLL0] = &gpll0.clkr,
> +	[GPLL4_MAIN] = &gpll4_main.clkr,
> +	[GPLL4] = &gpll4.clkr,
> +	[GPLL2_MAIN] = &gpll2_main.clkr,
> +	[GPLL2] = &gpll2.clkr,
> +	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
> +	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
> +	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
> +	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
> +	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
> +	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
> +	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
> +	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
> +	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
> +	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
> +	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
> +	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
> +	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
> +	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
> +	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
> +	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
> +	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
> +	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
> +	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
> +	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
> +	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
> +	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
> +	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
> +	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
> +	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
> +	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
> +	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
> +	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
> +	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
> +	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
> +	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
> +	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
> +	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
> +	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
> +	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
> +	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
> +	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
> +	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
> +	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
> +	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
> +	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
> +	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
> +	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
> +	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
> +	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
> +	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
> +	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
> +	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
> +	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
> +	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
> +	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
> +	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
> +	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
> +	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
> +	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
> +	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
> +	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
> +	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
> +	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
> +	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
> +	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
> +	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
> +	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
> +	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
> +	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
> +	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
> +	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
> +	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
> +	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
> +	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
> +	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
> +	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
> +	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
> +	[GCC_SNOC_PCNOC_AHB_CLK] = &gcc_snoc_pcnoc_ahb_clk.clkr,
> +	[GCC_ANOC_PCNOC_AHB_CLK] = &gcc_anoc_pcnoc_ahb_clk.clkr,
> +	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
> +	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
> +	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
> +	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
> +	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
> +	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
> +	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
> +	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
> +	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
> +	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
> +	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
> +	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
> +	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
> +	[GCC_SYS_NOC_AXI_CLK] = &gcc_sys_noc_axi_clk.clkr,
> +	[GCC_ANOC0_AXI_CLK] = &gcc_anoc0_axi_clk.clkr,
> +	[GCC_ANOC1_AXI_CLK] = &gcc_anoc1_axi_clk.clkr,
> +	[GCC_ANOC0_TBU_CLK] = &gcc_anoc0_tbu_clk.clkr,
> +	[GCC_ANOC1_TBU_CLK] = &gcc_anoc1_tbu_clk.clkr,
> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = &gcc_mem_noc_snoc_axi_clk.clkr,
> +	[GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
> +	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
> +	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
> +	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
> +	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
> +	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
> +	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
> +	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
> +	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
> +	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
> +	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
> +	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
> +	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
> +	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
> +	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
> +	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
> +	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
> +	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
> +	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
> +	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
> +	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
> +	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
> +	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
> +	[GCC_SNOC_TS_CLK] = &gcc_snoc_ts_clk.clkr,
> +	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
> +	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
> +	[GCC_PCNOC_TS_CLK] = &gcc_pcnoc_ts_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
> +	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
> +	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
> +	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
> +	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
> +	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
> +	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
> +	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
> +	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
> +	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
> +	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
> +	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
> +	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
> +	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
> +	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
> +	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
> +	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
> +	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
> +	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
> +	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
> +	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
> +	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
> +	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
> +	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
> +	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
> +	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
> +	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
> +	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
> +	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
> +	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
> +	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
> +	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
> +	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
> +	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
> +	[GCC_PCNOC_DCC_CLK] = &gcc_pcnoc_dcc_clk.clkr,
> +};
> +
> +static struct clk_regmap *gcc_ipq9574_dummy_clks[] = {
> +	[GPLL0_MAIN] = DEFINE_DUMMY_CLK(gpll0_main),
> +	[GPLL0] = DEFINE_DUMMY_CLK(gpll0),
> +	[GPLL4_MAIN] = DEFINE_DUMMY_CLK(gpll4_main),
> +	[GPLL4] = DEFINE_DUMMY_CLK(gpll4),
> +	[GPLL2_MAIN] = DEFINE_DUMMY_CLK(gpll2_main),
> +	[GPLL2] = DEFINE_DUMMY_CLK(gpll2),
> +	[GCC_SLEEP_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_sleep_clk_src),
> +	[APSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(apss_ahb_clk_src),
> +	[APSS_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(apss_axi_clk_src),
> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_i2c_apps_clk_src),
> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_spi_apps_clk_src),
> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_i2c_apps_clk_src),
> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_spi_apps_clk_src),
> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_i2c_apps_clk_src),
> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_spi_apps_clk_src),
> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_i2c_apps_clk_src),
> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_spi_apps_clk_src),
> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_i2c_apps_clk_src),
> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_spi_apps_clk_src),
> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_i2c_apps_clk_src),
> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_spi_apps_clk_src),
> +	[BLSP1_UART1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart1_apps_clk_src),
> +	[BLSP1_UART2_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart2_apps_clk_src),
> +	[BLSP1_UART3_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart3_apps_clk_src),
> +	[BLSP1_UART4_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart4_apps_clk_src),
> +	[BLSP1_UART5_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart5_apps_clk_src),
> +	[BLSP1_UART6_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart6_apps_clk_src),
> +	[GCC_APSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_apss_ahb_clk),
> +	[GCC_APSS_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_apss_axi_clk),
> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_i2c_apps_clk),
> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_spi_apps_clk),
> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_i2c_apps_clk),
> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_spi_apps_clk),
> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_i2c_apps_clk),
> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_spi_apps_clk),
> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_i2c_apps_clk),
> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_spi_apps_clk),
> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_i2c_apps_clk),
> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_spi_apps_clk),
> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_i2c_apps_clk),
> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_spi_apps_clk),
> +	[GCC_BLSP1_UART1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart1_apps_clk),
> +	[GCC_BLSP1_UART2_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart2_apps_clk),
> +	[GCC_BLSP1_UART3_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart3_apps_clk),
> +	[GCC_BLSP1_UART4_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart4_apps_clk),
> +	[GCC_BLSP1_UART5_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart5_apps_clk),
> +	[GCC_BLSP1_UART6_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart6_apps_clk),
> +	[PCIE0_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_m_clk_src),
> +	[GCC_PCIE0_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_m_clk),
> +	[PCIE1_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_m_clk_src),
> +	[GCC_PCIE1_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_m_clk),
> +	[PCIE2_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_m_clk_src),
> +	[GCC_PCIE2_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_m_clk),
> +	[PCIE3_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_m_clk_src),
> +	[GCC_PCIE3_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_m_clk),
> +	[PCIE0_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_s_clk_src),
> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_bridge_clk),
> +	[GCC_PCIE0_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_clk),
> +	[PCIE1_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_s_clk_src),
> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_bridge_clk),
> +	[GCC_PCIE1_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_clk),
> +	[PCIE2_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_s_clk_src),
> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_bridge_clk),
> +	[GCC_PCIE2_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_clk),
> +	[PCIE3_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_s_clk_src),
> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_bridge_clk),
> +	[GCC_PCIE3_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_clk),
> +	[PCIE0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_pipe_clk_src),
> +	[PCIE1_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_pipe_clk_src),
> +	[PCIE2_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_pipe_clk_src),
> +	[PCIE3_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_pipe_clk_src),
> +	[PCIE_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(pcie_aux_clk_src),
> +	[GCC_PCIE0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_aux_clk),
> +	[GCC_PCIE1_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_aux_clk),
> +	[GCC_PCIE2_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_aux_clk),
> +	[GCC_PCIE3_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_aux_clk),
> +	[PCIE0_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_rchng_clk_src),
> +	[GCC_PCIE0_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_rchng_clk),
> +	[PCIE1_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_rchng_clk_src),
> +	[GCC_PCIE1_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_rchng_clk),
> +	[PCIE2_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_rchng_clk_src),
> +	[GCC_PCIE2_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_rchng_clk),
> +	[PCIE3_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_rchng_clk_src),
> +	[GCC_PCIE3_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_rchng_clk),
> +	[GCC_PCIE0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_ahb_clk),
> +	[GCC_PCIE1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_ahb_clk),
> +	[GCC_PCIE2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_ahb_clk),
> +	[GCC_PCIE3_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_ahb_clk),
> +	[USB0_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_aux_clk_src),
> +	[GCC_USB0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_aux_clk),
> +	[USB0_MASTER_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_master_clk_src),
> +	[GCC_USB0_MASTER_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_master_clk),
> +	[GCC_SNOC_USB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_usb_clk),
> +	[GCC_ANOC_USB_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_usb_axi_clk),
> +	[USB0_MOCK_UTMI_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_clk_src),
> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_div_clk_src),
> +	[GCC_USB0_MOCK_UTMI_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_mock_utmi_clk),
> +	[USB0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_pipe_clk_src),
> +	[GCC_USB0_PHY_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_phy_cfg_ahb_clk),
> +	[SDCC1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_apps_clk_src),
> +	[GCC_SDCC1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_apps_clk),
> +	[SDCC1_ICE_CORE_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_ice_core_clk_src),
> +	[GCC_SDCC1_ICE_CORE_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ice_core_clk),
> +	[GCC_SDCC1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ahb_clk),
> +	[PCNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(pcnoc_bfdcd_clk_src),
> +	[GCC_NSSCFG_CLK] = DEFINE_DUMMY_CLK(gcc_nsscfg_clk),
> +	[GCC_NSSNOC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_nsscc_clk),
> +	[GCC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nsscc_clk),
> +	[GCC_NSSNOC_PCNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_pcnoc_1_clk),
> +	[GCC_QDSS_DAP_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_ahb_clk),
> +	[GCC_QDSS_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_cfg_ahb_clk),
> +	[GCC_SNOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcnoc_ahb_clk),
> +	[GCC_ANOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcnoc_ahb_clk),
> +	[GCC_QPIC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_ahb_clk),
> +	[GCC_QPIC_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_clk),
> +	[GCC_BLSP1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_ahb_clk),
> +	[GCC_MDIO_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_mdio_ahb_clk),
> +	[GCC_PRNG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_prng_ahb_clk),
> +	[GCC_UNIPHY0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_ahb_clk),
> +	[GCC_UNIPHY1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_ahb_clk),
> +	[GCC_UNIPHY2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_ahb_clk),
> +	[GCC_CMN_12GPLL_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_ahb_clk),
> +	[GCC_CMN_12GPLL_APU_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_apu_clk),
> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(system_noc_bfdcd_clk_src),
> +	[GCC_NSSNOC_SNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_clk),
> +	[GCC_NSSNOC_SNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_1_clk),
> +	[GCC_QDSS_ETR_USB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_etr_usb_clk),
> +	[GCC_SYS_NOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_axi_clk),
> +	[GCC_ANOC0_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_axi_clk),
> +	[GCC_ANOC1_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_axi_clk),
> +	[GCC_ANOC0_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_tbu_clk),
> +	[GCC_ANOC1_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_tbu_clk),
> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_snoc_axi_clk),
> +	[GCC_IMEM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_imem_axi_clk),
> +	[WCSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_ahb_clk_src),
> +	[GCC_Q6_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_clk),
> +	[GCC_Q6_AHB_S_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_s_clk),
> +	[GCC_WCSS_ECAHB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_ecahb_clk),
> +	[GCC_WCSS_ACMT_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_acmt_clk),
> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_wcss_ahb_clk),
> +	[WCSS_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_axi_m_clk_src),
> +	[GCC_ANOC_WCSS_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_wcss_axi_m_clk),
> +	[QDSS_AT_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_at_clk_src),
> +	[GCC_Q6SS_ATBM_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_atbm_clk),
> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_atb_clk),
> +	[GCC_NSSNOC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_atb_clk),
> +	[GCC_QDSS_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_at_clk),
> +	[GCC_SYS_NOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_at_clk),
> +	[GCC_PCNOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_at_clk),
> +	[GCC_USB0_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_eud_at_clk),
> +	[GCC_QDSS_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_eud_at_clk),
> +	[QDSS_STM_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_stm_clk_src),
> +	[GCC_QDSS_STM_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_stm_clk),
> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_qdss_stm_axi_clk),
> +	[QDSS_TRACECLKIN_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_traceclkin_clk_src),
> +	[GCC_QDSS_TRACECLKIN_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_traceclkin_clk),
> +	[QDSS_TSCTR_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_tsctr_clk_src),
> +	[GCC_Q6_TSCTR_1TO2_CLK] = DEFINE_DUMMY_CLK(gcc_q6_tsctr_1to2_clk),
> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_nts_clk),
> +	[GCC_QDSS_TSCTR_DIV2_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div2_clk),
> +	[GCC_QDSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_ts_clk),
> +	[GCC_SNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_ts_clk),
> +	[GCC_MEM_NOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_ts_clk),
> +	[GCC_QDSS_TSCTR_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div4_clk),
> +	[GCC_NSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_nss_ts_clk),
> +	[GCC_QDSS_TSCTR_DIV8_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div8_clk),
> +	[GCC_PCNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_ts_clk),
> +	[GCC_QDSS_TSCTR_DIV16_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div16_clk),
> +	[GCC_Q6SS_PCLKDBG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_pclkdbg_clk),
> +	[GCC_Q6SS_TRIG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_trig_clk),
> +	[GCC_WCSS_DBG_IFC_APB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_apb_clk),
> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_dapbus_clk),
> +	[GCC_QDSS_DAP_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_clk),
> +	[GCC_QDSS_APB2JTAG_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_apb2jtag_clk),
> +	[GCC_QDSS_TSCTR_DIV3_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div3_clk),
> +	[QPIC_IO_MACRO_CLK_SRC] = DEFINE_DUMMY_CLK(qpic_io_macro_clk_src),
> +	[GCC_QPIC_IO_MACRO_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_io_macro_clk),
> +	[Q6_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axi_clk_src),
> +	[GCC_Q6_AXIM_CLK] = DEFINE_DUMMY_CLK(gcc_q6_axim_clk),
> +	[GCC_WCSS_Q6_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_q6_tbu_clk),
> +	[GCC_MEM_NOC_Q6_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_q6_axi_clk),
> +	[Q6_AXIM2_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axim2_clk_src),
> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(nssnoc_memnoc_bfdcd_clk_src),
> +	[GCC_NSSNOC_MEMNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_memnoc_clk),
> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_mem_noc_1_clk),
> +	[GCC_NSS_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_nss_tbu_clk),
> +	[GCC_MEM_NOC_NSSNOC_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_nssnoc_clk),
> +	[LPASS_AXIM_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_axim_clk_src),
> +	[LPASS_SWAY_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_sway_clk_src),
> +	[ADSS_PWM_CLK_SRC] = DEFINE_DUMMY_CLK(adss_pwm_clk_src),
> +	[GCC_ADSS_PWM_CLK] = DEFINE_DUMMY_CLK(gcc_adss_pwm_clk),
> +	[GP1_CLK_SRC] = DEFINE_DUMMY_CLK(gp1_clk_src),
> +	[GP2_CLK_SRC] = DEFINE_DUMMY_CLK(gp2_clk_src),
> +	[GP3_CLK_SRC] = DEFINE_DUMMY_CLK(gp3_clk_src),
> +	[DDRSS_SMS_SLOW_CLK_SRC] = DEFINE_DUMMY_CLK(ddrss_sms_slow_clk_src),
> +	[GCC_XO_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_xo_clk_src),
> +	[GCC_NSSNOC_XO_DCD_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_xo_dcd_clk),
> +	[GCC_XO_CLK] = DEFINE_DUMMY_CLK(gcc_xo_clk),
> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_qosgen_ref_clk),
> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_timeout_ref_clk),
> +	[GCC_XO_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_xo_div4_clk),
> +	[GCC_UNIPHY0_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_sys_clk),
> +	[GCC_UNIPHY1_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_sys_clk),
> +	[GCC_UNIPHY2_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_sys_clk),
> +	[GCC_CMN_12GPLL_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_sys_clk),
> +	[GCC_Q6SS_BOOT_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_boot_clk),
> +	[UNIPHY_SYS_CLK_SRC] = DEFINE_DUMMY_CLK(uniphy_sys_clk_src),
> +	[NSS_TS_CLK_SRC] = DEFINE_DUMMY_CLK(nss_ts_clk_src),
> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie0_1lane_m_clk),
> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie1_1lane_m_clk),
> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie2_2lane_m_clk),
> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie3_2lane_m_clk),
> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie0_1lane_s_clk),
> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie1_1lane_s_clk),
> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie2_2lane_s_clk),
> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie3_2lane_s_clk),
> +	[GCC_PCNOC_DCC_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_dcc_clk),
> +};
Drop.

> +
> +static const struct qcom_reset_map gcc_ipq9574_resets[] = {
> +	[GCC_ADSS_BCR] = { 0x1c000, 0 },
> +	[GCC_ANOC0_TBU_BCR] = { 0x1203C, 0 },
> +	[GCC_ANOC1_TBU_BCR] = { 0x1204C, 0 },
> +	[GCC_ANOC_BCR] = { 0x2E074, 0 },
> +	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
> +	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
> +	[GCC_BLSP1_BCR] = { 0x01000, 0 },
> +	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
> +	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
> +	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
> +	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
> +	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
> +	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
> +	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
> +	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
> +	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
> +	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
> +	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
> +	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
> +	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
> +	[GCC_CMN_BLK_BCR] = { 0x3A000, 0 },
> +	[GCC_CMN_BLK_AHB_ARES] = { 0x3A010, 0 },
> +	[GCC_CMN_BLK_SYS_ARES] = { 0x3A010, 1 },
> +	[GCC_CMN_BLK_APU_ARES] = { 0x3A010, 2 },
> +	[GCC_DCC_BCR] = { 0x35000, 0 },
> +	[GCC_DDRSS_BCR] = { 0x11000, 0 },
> +	[GCC_IMEM_BCR] = { 0x0e000, 0 },
> +	[GCC_LPASS_BCR] = { 0x27000, 0 },
> +	[GCC_MDIO_BCR] = { 0x1703c, 0 },
> +	[GCC_MPM_BCR] = { 0x37000, 0 },
> +	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
> +	[GCC_NSS_BCR] = { 0x17000, 0 },
> +	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
> +	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
> +	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
> +	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
> +	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
> +	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
> +	[GCC_NSSCC_ARES] = { 0x17038, 8 },
> +	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
> +	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
> +	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
> +	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
> +	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
> +	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
> +	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
> +	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
> +	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
> +	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
> +	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
> +	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
> +	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
> +	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
> +	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
> +	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
> +	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
> +	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
> +	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
> +	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
> +	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
> +	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
> +	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
> +	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
> +	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
> +	[GCC_PCIE2_AHB_ARES] = { 0x2A058, 7 },
> +	[GCC_PCIE2_AUX_ARES] = { 0x2A058, 6 },
> +	[GCC_PCIE2_AXI_M_ARES] = { 0x2A058, 5 },
> +	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2A058, 4 },
> +	[GCC_PCIE2_AXI_S_ARES] = { 0x2A058, 3 },
> +	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2A058, 2 },
> +	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2A058, 1 },
> +	[GCC_PCIE2_PIPE_ARES] = { 0x2A058, 0 },
> +	[GCC_PCIE3_AHB_ARES] = { 0x2B058, 7 },
> +	[GCC_PCIE3_AUX_ARES] = { 0x2B058, 6 },
> +	[GCC_PCIE3_AXI_M_ARES] = { 0x2B058, 5 },
> +	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2B058, 4 },
> +	[GCC_PCIE3_AXI_S_ARES] = { 0x2B058, 3 },
> +	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2B058, 2 },
> +	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2B058, 1 },
> +	[GCC_PCIE3_PIPE_ARES] = { 0x2B058, 0 },
> +	[GCC_PCIE0_BCR] = { 0x28000, 0 },
> +	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
> +	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
> +	[GCC_PCIE1_BCR] = { 0x29000, 0 },
> +	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
> +	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
> +	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
> +	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
> +	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
> +	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
> +	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
> +	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
> +	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
> +	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
> +	[GCC_PCIE3_PHY_BCR] = { 0x2B060, 0 },
> +	[GCC_PCNOC_BCR] = { 0x31000, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
> +	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
> +	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
> +	[GCC_PRNG_BCR] = { 0x13020, 0 },
> +	[GCC_Q6SS_DBG_ARES] = { 0x2506C, 4 },
> +	[GCC_Q6_AHB_ARES] = { 0x2506C, 3 },
> +	[GCC_Q6_AHB_S_ARES] = { 0x2506C, 2 },
> +	[GCC_Q6_AXIM2_ARES] = { 0x2506C, 1 },
> +	[GCC_Q6_AXIM_ARES] = { 0x2506C, 0 },
> +	[GCC_QDSS_BCR] = { 0x2d000, 0 },
> +	[GCC_QPIC_BCR] = { 0x32000, 0 },
> +	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
> +	[GCC_QPIC_ARES] = { 0x3201c, 0 },
> +	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
> +	[GCC_RBCPR_BCR] = { 0x39000, 0 },
> +	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
> +	[GCC_SDCC_BCR] = { 0x33000, 0 },
> +	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
> +	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
> +	[GCC_SNOC_BCR] = { 0x2E000, 0 },
> +	[GCC_SPDM_BCR] = { 0x36000, 0 },
> +	[GCC_TCSR_BCR] = { 0x3d000, 0 },
> +	[GCC_TLMM_BCR] = { 0x3e000, 0 },
> +	[GCC_TME_BCR] = { 0x10000, 0 },
> +	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
> +	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
> +	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
> +	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
> +	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
> +	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
> +	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
> +	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
> +	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
> +	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
> +	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
> +	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
> +	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
> +	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
> +	[GCC_USB_BCR] = { 0x2c000, 0 },
> +	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
> +	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
> +	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
> +	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
> +	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
> +	[GCC_WCSS_BCR] = { 0x18004, 0 },
> +	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
> +	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
> +	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
> +	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
> +	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
> +};
> +
> +static const struct of_device_id gcc_ipq9574_match_table[] = {
> +	{ .compatible = "qcom,gcc-ipq9574" },
> +	{ }
> +};
> +MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
> +
> +static const struct regmap_config gcc_ipq9574_regmap_config = {
> +	.reg_bits       = 32,
> +	.reg_stride     = 4,
> +	.val_bits       = 32,
> +	.max_register   = 0x7fffc,
> +	.fast_io	= true,
> +};
> +
> +static const struct qcom_cc_desc gcc_ipq9574_desc = {
> +	.config = &gcc_ipq9574_regmap_config,
> +	.clks = gcc_ipq9574_clks,
> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
> +	.resets = gcc_ipq9574_resets,
> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
> +	.clk_hws = gcc_ipq9574_hws,
> +	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
> +};
> +
> +static const struct qcom_cc_desc gcc_ipq9574_dummy_desc = {
> +	.config = &gcc_ipq9574_regmap_config,
> +	.clks = gcc_ipq9574_dummy_clks,
> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_dummy_clks),
> +	.resets = gcc_ipq9574_resets,
> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
> +};
> +
> +static int gcc_ipq9574_probe(struct platform_device *pdev)
> +{
> +	struct regmap *regmap;
> +	struct qcom_cc_desc ipq9574_desc = gcc_ipq9574_desc;
> +	struct device_node *np = (&pdev->dev)->of_node;
> +
> +	if (of_property_read_bool(np, "gcc-use-dummy"))
> +		ipq9574_desc = gcc_ipq9574_dummy_desc;
> +
> +	regmap = qcom_cc_map(pdev, &ipq9574_desc);
> +	if (IS_ERR(regmap))
> +		return PTR_ERR(regmap);
> +
> +	return qcom_cc_really_probe(pdev, &ipq9574_desc, regmap);
> +}
> +
> +static int gcc_ipq9574_remove(struct platform_device *pdev)
Generally you shouldn't remove the driver that ensures your platform
well, works..

Plus GCCs are always =y in mainline to make sure dependencies are met
so there's no removing.

> +{
> +	return 0;
> +}
> +
> +static struct platform_driver gcc_ipq9574_driver = {
> +	.probe = gcc_ipq9574_probe,
> +	.remove = gcc_ipq9574_remove,
> +	.driver = {
> +		.name   = "qcom,gcc-ipq9574",
> +		.of_match_table = gcc_ipq9574_match_table,
> +	},
> +};
> +
> +static int __init gcc_ipq9574_init(void)
> +{
> +	return platform_driver_register(&gcc_ipq9574_driver);
> +}
> +core_initcall(gcc_ipq9574_init);
> +
> +static void __exit gcc_ipq9574_exit(void)
> +{
> +	platform_driver_unregister(&gcc_ipq9574_driver);
> +}
> +module_exit(gcc_ipq9574_exit);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
> +MODULE_LICENSE("GPL");

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Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Devi Priya]

On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
> 
> 
> On 10.01.2023 13:13, devi priya wrote:
>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig       |    8 +
>>   drivers/clk/qcom/Makefile      |    1 +
>>   drivers/clk/qcom/gcc-ipq9574.c | 4706 ++++++++++++++++++++++++++++++++
>>   3 files changed, 4715 insertions(+)
>>   create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 70d43f0a8919..97517d1e3ba4 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -173,6 +173,14 @@ config IPQ_GCC_8074
>>   	  i2c, USB, SD/eMMC, etc. Select this for the root clock
>>   	  of ipq8074.
>>   
>> +config IPQ_GCC_9574
>> +	tristate "IPQ9574 Global Clock Controller"
>> +	help
>> +	  Support for global clock controller on ipq9574 devices.
>> +	  Say Y if you want to use peripheral devices such as UART, SPI,
>> +	  i2c, USB, SD/eMMC, etc. Select this for the root clock
>> +	  of ipq9574.
>> +
>>   config MSM_GCC_8660
>>   	tristate "MSM8660 Global Clock Controller"
>>   	help
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index f18c446a97ea..55c6ada326e0 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>>   obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>   obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>   obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>> +obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>   obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>   obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>   obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
>> new file mode 100644
>> index 000000000000..f44a19c5f9a1
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -0,0 +1,4706 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> Hm, interesting choice for a C driver..
> 
>> +/*
>> + * Copyright (c) 2022 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <linux/reset-controller.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +#include "common.h"
>> +#include "clk-regmap.h"
>> +#include "clk-pll.h"
>> +#include "clk-rcg.h"
>> +#include "clk-branch.h"
>> +#include "clk-alpha-pll.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "reset.h"
> Many of these includes seem unnecessary..
Sure, will remove
> 
> 
>> +
>> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
> Drop.
Okay
> 
>> +
>> +/* Need to match the order of clocks in DT binding */
>> +enum {
>> +	DT_XO,
>> +	DT_SLEEP_CLK,
>> +	DT_BIAS_PLL_UBI_NC_CLK,
>> +	DT_PCIE30_PHY0_PIPE_CLK,
>> +	DT_PCIE30_PHY1_PIPE_CLK,
>> +	DT_PCIE30_PHY2_PIPE_CLK,
>> +	DT_PCIE30_PHY3_PIPE_CLK,
>> +	DT_USB3PHY_0_CC_PIPE_CLK,
>> +};
>> +
>> +enum {
>> +	P_XO,
>> +	P_PCIE30_PHY0_PIPE,
>> +	P_PCIE30_PHY1_PIPE,
>> +	P_PCIE30_PHY2_PIPE,
>> +	P_PCIE30_PHY3_PIPE,
>> +	P_USB3PHY_0_PIPE,
>> +	P_GPLL0,
>> +	P_GPLL0_DIV2,
>> +	P_GPLL0_OUT_AUX,
>> +	P_GPLL2,
>> +	P_GPLL4,
>> +	P_PI_SLEEP,
>> +	P_BIAS_PLL_UBI_NC_CLK,
>> +};
>> +
>> +static const struct parent_map gcc_xo_map[] = {
>> +	{ P_XO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_data[] = {
>> +	{ .index = DT_XO },
>> +};
>> +
>> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
>> +	{ .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static struct clk_alpha_pll gpll0_main = {
>> +	.offset = 0x20000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.clkr = {
>> +		.enable_reg = 0x0b000,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gpll0_main",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.ops = &clk_alpha_pll_ops,
>> +			.flags = CLK_IS_CRITICAL,
> Is it? Does it act as a CPU PLL source that's not managed by the
> firmware?
Okay, will remove the critical flag as it is managed by the firmware
> 
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor gpll0_out_main_div2 = {
>> +	.mult = 1,
>> +	.div = 2,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll0_out_main_div2",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll0_main.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll0 = {
>> +	.offset = 0x20000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.width = 4,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll0",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll0_main.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll gpll4_main = {
>> +	.offset = 0x22000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.clkr = {
>> +		.enable_reg = 0x0b000,
>> +		.enable_mask = BIT(2),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gpll4_main",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.ops = &clk_alpha_pll_ops,
>> +			.flags = CLK_IS_CRITICAL,
> Again, is it?
okay, will remove
> 
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll4 = {
>> +	.offset = 0x22000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.width = 4,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll4",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll4_main.clkr.hw },
> Please put the }, in a new line.
okay
> 
>> +		.num_parents = 1,
>> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll gpll2_main = {
>> +	.offset = 0x21000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.clkr = {
>> +		.enable_reg = 0x0b000,
>> +		.enable_mask = BIT(1),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gpll2_main",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.ops = &clk_alpha_pll_ops,
>> +			.flags = CLK_IS_CRITICAL,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll2 = {
>> +	.offset = 0x21000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.width = 4,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll2",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll2_main.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sleep_clk_src = {
>> +	.halt_reg = 0x3400c,
>> +	.clkr = {
>> +		.enable_reg = 0x3400c,
>> +		.enable_mask = BIT(1),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sleep_clk_src",
>> +			.parent_data = gcc_sleep_clk_data,
>> +			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
>> +			.ops = &clk_branch2_ops,
>> +			.flags = CLK_IS_CRITICAL,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw},
> Please consistently add a space before },
sure, okay
> 
>> +	{ .hw = &gpll0_out_main_div2.hw},
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL0_DIV2, 4 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw },
>> +	{ .hw = &gpll4.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL4, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw },
>> +	{ .hw = &gpll0_out_main_div2.hw },
>> +	{ .hw = &gpll0.clkr.hw },
>> +};
>> +
>> +static const struct parent_map
>> +gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
> Pretty sure you can unwrap that line
okay
> 
> 
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL0_DIV2, 4 },
>> +	{ P_GPLL0, 5 },
>> +};
>> +
> 
> [...]
> 
>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>> +	.halt_reg = 0x07024,
>> +	.clkr = {
>> +		.enable_reg = 0x07024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_blsp1_qup6_i2c_apps_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Sounds very much like a hack..
Got it, will remove the clock entry as it is not being used in linux
> 
> [...]
> 
> 
>> +static struct clk_branch gcc_snoc_usb_clk = {
>> +	.halt_reg = 0x2E058,
> Please lowercase hex all throughout the file.
okay
> 
>> +	.clkr = {
>> +		.enable_reg = 0x2E058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_snoc_usb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&usb0_master_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
> [...]
> 
>> +
>> +static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
>> +	.cmd_rcgr = 0x31004,
>> +	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "pcnoc_bfdcd_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
>> +		.ops = &clk_rcg2_ops,
>> +		.flags = CLK_IS_CRITICAL,
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor pcnoc_clk_src = {
>> +	.mult = 1,
>> +	.div = 1,
> Is there any benefit in keeping it instead of providing
> the real rcg as a parent?
okay, understood..will remove
> 
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "pcnoc_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&pcnoc_bfdcd_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
> 
> [...]
>> +static struct clk_branch gcc_snoc_pcnoc_ahb_clk = {
>> +	.halt_reg = 0x2E03C,
>> +	.clkr = {
>> +		.enable_reg = 0x2E03C,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_snoc_pcnoc_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&pcnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Can it be turned off? Perhaps CLK_IS_CRITICAL would be more fitting,
> with a comment explaining why.
Okay, got it. Will remove the clock entry as it will be set by the 
bootloaders
> 
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc_pcnoc_ahb_clk = {
>> +	.halt_reg = 0x2E094,
>> +	.clkr = {
>> +		.enable_reg = 0x2E094,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc_pcnoc_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&pcnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Same thing
> 
Okay
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
> 
>> +
>> +static struct clk_rcg2 system_noc_bfdcd_clk_src = {
>> +	.cmd_rcgr = 0x2e004,
>> +	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll4_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "system_noc_bfdcd_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll4,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
>> +		.ops = &clk_rcg2_ops,
>> +		.flags = CLK_IS_CRITICAL,
> .flags goes before .ops in all other nodes, please be consistent.
okay
> 
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_boot_clk = {
>> +	.halt_reg = 0x25080,
>> +	.halt_check = BRANCH_HALT_SKIP,
>> +	.clkr = {
>> +		.enable_reg = 0x25080,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_boot_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_snoc_clk = {
>> +	.halt_reg = 0x17028,
>> +	.clkr = {
>> +		.enable_reg = 0x17028,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_snoc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Same story as with PCNoC
okay
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_snoc_1_clk = {
>> +	.halt_reg = 0x1707c,
>> +	.clkr = {
>> +		.enable_reg = 0x1707c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_snoc_1_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> And here
sure
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_etr_usb_clk = {
>> +	.halt_reg = 0x2D060,
>> +	.clkr = {
>> +		.enable_reg = 0x2D060,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_etr_usb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(133333333, P_GPLL0, 6, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 wcss_ahb_clk_src = {
>> +	.cmd_rcgr = 0x25030,
>> +	.freq_tbl = ftbl_wcss_ahb_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "wcss_ahb_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_ahb_clk = {
>> +	.halt_reg = 0x25014,
>> +	.clkr = {
>> +		.enable_reg = 0x25014,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> This sounds like a hack, perhaps it should be fed to a remoteproc node?
> 
Sure, will remove the ignore_unused flag and handle it in the 
corresponding driver
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_ahb_s_clk = {
>> +	.halt_reg = 0x25018,
>> +	.clkr = {
>> +		.enable_reg = 0x25018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_ahb_s_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> And this one too
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_ecahb_clk = {
>> +	.halt_reg = 0x25058,
>> +	.clkr = {
>> +		.enable_reg = 0x25058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_ecahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Similarly, this one should probably be fed to the wcss node and
> properly managed with a driver, not left dangling
Got it
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_acmt_clk = {
>> +	.halt_reg = 0x2505c,
>> +	.clkr = {
>> +		.enable_reg = 0x2505c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_acmt_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_axi_clk = {
>> +	.halt_reg = 0x2e01c,
>> +	.clkr = {
>> +		.enable_reg = 0x2e01c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> CLK_IS_CRITICAL?
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc0_axi_clk = {
>> +	.halt_reg = 0x2e078,
>> +	.clkr = {
>> +		.enable_reg = 0x2e078,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc0_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> If this it the same kind of ANoC(n) as on 8996/8998, this should
> definitely be either CLK_IS_CRITICAL or managed through a driver..
> Probably the second one..
Sure, will do
> 
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc1_axi_clk = {
>> +	.halt_reg = 0x2e088,
>> +	.clkr = {
>> +		.enable_reg = 0x2e088,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc1_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc0_tbu_clk = {
>> +	.halt_reg = 0x12038,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(3),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc0_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc1_tbu_clk = {
>> +	.halt_reg = 0x12048,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(5),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc1_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_snoc_axi_clk = {
>> +	.halt_reg = 0x19018,
>> +	.clkr = {
>> +		.enable_reg = 0x19018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_snoc_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> This one also smells of an interconnect clock more than anything else..
> 
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_imem_axi_clk = {
>> +	.halt_reg = 0xe004,
>> +	.clkr = {
>> +		.enable_reg = 0xb004,
>> +		.enable_mask = BIT(12),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_imem_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> You could pass this one to the imem node
> 
Sure okay
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
>> +	.halt_reg = 0x2e030,
>> +	.clkr = {
>> +		.enable_reg = 0x2e030,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_wcss_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Definitely handled through a driver..
Yes, okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(133333333, P_GPLL0, 6, 0, 0),
>> +	F(266666667, P_GPLL0, 3, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 wcss_axi_m_clk_src = {
>> +	.cmd_rcgr = 0x25078,
>> +	.freq_tbl = ftbl_wcss_axi_m_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "wcss_axi_m_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
>> +	.halt_reg = 0x2e0a8,
>> +	.clkr = {
>> +		.enable_reg = 0x2e0a8,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc_wcss_axi_m_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_axi_m_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
>> +	F(240000000, P_GPLL4, 5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_at_clk_src = {
>> +	.cmd_rcgr = 0x2d004,
>> +	.freq_tbl = ftbl_qdss_at_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_at_clk_src",
>> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_atbm_clk = {
>> +	.halt_reg = 0x2501c,
>> +	.clkr = {
>> +		.enable_reg = 0x2501c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_atbm_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
>> +	.halt_reg = 0x2503c,
>> +	.clkr = {
>> +		.enable_reg = 0x2503c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_atb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Not gonna point out every similar occurence, you probably get me now
Sure, understood. Will update them all
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_atb_clk = {
>> +	.halt_reg = 0x17014,
>> +	.clkr = {
>> +		.enable_reg = 0x17014,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_atb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_at_clk = {
>> +	.halt_reg = 0x2D038,
>> +	.clkr = {
>> +		.enable_reg = 0x2D038,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Probably not critical, you don't need debug 24/7.
okay
> 
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_at_clk = {
>> +	.halt_reg = 0x2e038,
>> +	.clkr = {
>> +		.enable_reg = 0x2e038,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_pcnoc_at_clk = {
>> +	.halt_reg = 0x31024,
>> +	.clkr = {
>> +		.enable_reg = 0x31024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_pcnoc_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
>> +	.mult = 1,
>> +	.div = 6,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "gcc_eud_at_div_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_at_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_usb0_eud_at_clk = {
>> +	.halt_reg = 0x30004,
>> +	.clkr = {
>> +		.enable_reg = 0x30004,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_usb0_eud_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_eud_at_div_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Definitely not critical.
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_eud_at_clk = {
>> +	.halt_reg = 0x2D06C,
>> +	.clkr = {
>> +		.enable_reg = 0x2D06C,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_eud_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_eud_at_div_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Ditto.
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(200000000, P_GPLL0, 4, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_stm_clk_src = {
>> +	.cmd_rcgr = 0x2D00C,
>> +	.freq_tbl = ftbl_qdss_stm_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_stm_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_stm_clk = {
>> +	.halt_reg = 0x2D03C,
>> +	.clkr = {
>> +		.enable_reg = 0x2D03C,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_stm_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_stm_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
>> +	.halt_reg = 0x2E034,
>> +	.clkr = {
>> +		.enable_reg = 0x2E034,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_qdss_stm_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_stm_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
>> +	F(300000000, P_GPLL4, 4, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_traceclkin_clk_src = {
>> +	.cmd_rcgr = 0x2d014,
>> +	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_traceclkin_clk_src",
>> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_traceclkin_clk = {
>> +	.halt_reg = 0x2D040,
>> +	.clkr = {
>> +		.enable_reg = 0x2D040,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_traceclkin_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_traceclkin_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
>> +	F(600000000, P_GPLL4, 2, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_tsctr_clk_src = {
>> +	.cmd_rcgr = 0x2d01c,
>> +	.freq_tbl = ftbl_qdss_tsctr_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_clk_src",
>> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
>> +	.mult = 1,
>> +	.div = 2,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div2_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_tsctr_1to2_clk = {
>> +	.halt_reg = 0x25020,
>> +	.clkr = {
>> +		.enable_reg = 0x25020,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_tsctr_1to2_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
>> +	.halt_reg = 0x25040,
>> +	.clkr = {
>> +		.enable_reg = 0x25040,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_nts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div2_clk = {
>> +	.halt_reg = 0x2d044,
>> +	.clkr = {
>> +		.enable_reg = 0x2d044,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div2_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 uniphy_sys_clk_src = {
>> +	.cmd_rcgr = 0x17090,
>> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
>> +	.mnd_width = 8,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "uniphy_sys_clk_src",
>> +		.parent_data = gcc_xo_data,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 nss_ts_clk_src = {
>> +	.cmd_rcgr = 0x17088,
>> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
>> +	.mnd_width = 8,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "nss_ts_clk_src",
>> +		.parent_data = gcc_xo_data,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_ts_clk = {
>> +	.halt_reg = 0x2D078,
>> +	.clkr = {
>> +		.enable_reg = 0x2D078,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nss_ts_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_snoc_ts_clk = {
>> +	.halt_reg = 0x2e068,
>> +	.clkr = {
>> +		.enable_reg = 0x2e068,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_snoc_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_ts_clk = {
>> +	.halt_reg = 0x19028,
>> +	.clkr = {
>> +		.enable_reg = 0x19028,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_dap_sync_clk_src = {
>> +	.mult = 1,
>> +	.div = 4,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_dap_sync_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div4_clk = {
>> +	.halt_reg = 0x2d04c,
>> +	.clkr = {
>> +		.enable_reg = 0x2d04c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div4_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
>> +	.mult = 1,
>> +	.div = 8,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div8_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nss_ts_clk = {
>> +	.halt_reg = 0x17018,
>> +	.clkr = {
>> +		.enable_reg = 0x17018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nss_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nss_ts_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div8_clk = {
>> +	.halt_reg = 0x2d050,
>> +	.clkr = {
>> +		.enable_reg = 0x2d050,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div8_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div8_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_pcnoc_ts_clk = {
>> +	.halt_reg = 0x3102c,
>> +	.clkr = {
>> +		.enable_reg = 0x3102c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_pcnoc_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div8_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
>> +	.mult = 1,
>> +	.div = 16,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div16_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div16_clk = {
>> +	.halt_reg = 0x2d054,
>> +	.clkr = {
>> +		.enable_reg = 0x2d054,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div16_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div16_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_pclkdbg_clk = {
>> +	.halt_reg = 0x25024,
>> +	.clkr = {
>> +		.enable_reg = 0x25024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_pclkdbg_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_trig_clk = {
>> +	.halt_reg = 0x25068,
>> +	.clkr = {
>> +		.enable_reg = 0x25068,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_trig_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
>> +	.halt_reg = 0x25038,
>> +	.clkr = {
>> +		.enable_reg = 0x25038,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_apb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
>> +	.halt_reg = 0x25044,
>> +	.clkr = {
>> +		.enable_reg = 0x25044,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_dap_clk = {
>> +	.halt_reg = 0x2d058,
>> +	.clkr = {
>> +		.enable_reg = 0x2d058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_dap_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Probably not critical.
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_apb2jtag_clk = {
>> +	.halt_reg = 0x2d05c,
>> +	.clkr = {
>> +		.enable_reg = 0x2d05c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_apb2jtag_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_pcnoc_dcc_clk = {
>> +	.halt_reg = 0x31080,
>> +	.clkr = {
>> +		.enable_reg = 0x31080,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_pcnoc_dcc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
>> +	.mult = 1,
>> +	.div = 3,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div3_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div3_clk = {
>> +	.halt_reg = 0x2d048,
>> +	.clkr = {
>> +		.enable_reg = 0x2d048,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div3_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div3_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(100000000, P_GPLL0, 8, 0, 0),
>> +	F(200000000, P_GPLL0, 4, 0, 0),
>> +	F(320000000, P_GPLL0, 2.5, 0, 0),
>> +	F(400000000, P_GPLL0, 2, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qpic_io_macro_clk_src = {
>> +	.cmd_rcgr = 0x32004,
>> +	.freq_tbl = ftbl_qpic_io_macro_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qpic_io_macro_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qpic_io_macro_clk = {
>> +	.halt_reg = 0x3200c,
>> +	.clkr = {
>> +		.enable_reg = 0x3200c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qpic_io_macro_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qpic_io_macro_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
>> +	F(533333333, P_GPLL0, 1.5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 q6_axi_clk_src = {
>> +	.cmd_rcgr = 0x25004,
>> +	.freq_tbl = ftbl_q6_axi_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "q6_axi_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_axim_clk = {
>> +	.halt_reg = 0x2500c,
>> +	.clkr = {
>> +		.enable_reg = 0x2500c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_axim_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&q6_axi_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_q6_tbu_clk = {
>> +	.halt_reg = 0x12050,
>> +	.halt_check = BRANCH_HALT_DELAY,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(6),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_q6_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&q6_axi_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_q6_axi_clk = {
>> +	.halt_reg = 0x19010,
>> +	.clkr = {
>> +		.enable_reg = 0x19010,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_q6_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&q6_axi_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
>> +	F(342857143, P_GPLL4, 3.5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL4, 2 },
>> +	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
>> +};
>> +
>> +static struct clk_rcg2 q6_axim2_clk_src = {
>> +	.cmd_rcgr = 0x25028,
>> +	.freq_tbl = ftbl_q6_axim2_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "q6_axim2_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
>> +	F(533333333, P_GPLL0, 1.5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
>> +	.cmd_rcgr = 0x17004,
>> +	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "nssnoc_memnoc_bfdcd_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_memnoc_clk = {
>> +	.halt_reg = 0x17024,
>> +	.clkr = {
>> +		.enable_reg = 0x17024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_memnoc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
>> +	.halt_reg = 0x17084,
>> +	.clkr = {
>> +		.enable_reg = 0x17084,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_mem_noc_1_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nss_tbu_clk = {
>> +	.halt_reg = 0x12040,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(4),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nss_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_nssnoc_clk = {
>> +	.halt_reg = 0x19014,
>> +	.clkr = {
>> +		.enable_reg = 0x19014,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_nssnoc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
>> +	F(133333333, P_GPLL0, 6, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 lpass_axim_clk_src = {
>> +	.cmd_rcgr = 0x2700c,
>> +	.freq_tbl = ftbl_lpass_axim_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "lpass_axim_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 lpass_sway_clk_src = {
>> +	.cmd_rcgr = 0x27004,
>> +	.freq_tbl = ftbl_lpass_axim_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "lpass_sway_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(100000000, P_GPLL0, 8, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 adss_pwm_clk_src = {
>> +	.cmd_rcgr = 0x1c004,
>> +	.freq_tbl = ftbl_adss_pwm_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "adss_pwm_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_adss_pwm_clk = {
>> +	.halt_reg = 0x1c00c,
>> +	.clkr = {
>> +		.enable_reg = 0x1c00c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_adss_pwm_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&adss_pwm_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_gp1_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(200000000, P_GPLL0, 4, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 gp1_clk_src = {
>> +	.cmd_rcgr = 0x8004,
>> +	.freq_tbl = ftbl_gp1_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gp1_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 gp2_clk_src = {
>> +	.cmd_rcgr = 0x9004,
>> +	.freq_tbl = ftbl_gp1_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gp2_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 gp3_clk_src = {
>> +	.cmd_rcgr = 0xa004,
>> +	.freq_tbl = ftbl_gp1_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gp3_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_xo_clk_src = {
>> +	.halt_reg = 0x34004,
>> +	.clkr = {
>> +		.enable_reg = 0x34004,
>> +		.enable_mask = BIT(1),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_xo_clk_src",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
>> +	.halt_reg = 0x17074,
>> +	.clkr = {
>> +		.enable_reg = 0x17074,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_xo_dcd_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_xo_clk = {
>> +	.halt_reg = 0x34018,
>> +	.clkr = {
>> +		.enable_reg = 0x34018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_xo_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_uniphy0_sys_clk = {
>> +	.halt_reg = 0x17048,
>> +	.clkr = {
>> +		.enable_reg = 0x17048,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_uniphy0_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_uniphy1_sys_clk = {
>> +	.halt_reg = 0x17058,
>> +	.clkr = {
>> +		.enable_reg = 0x17058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_uniphy1_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_uniphy2_sys_clk = {
>> +	.halt_reg = 0x17068,
>> +	.clkr = {
>> +		.enable_reg = 0x17068,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_uniphy2_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_cmn_12gpll_sys_clk = {
>> +	.halt_reg = 0x3a008,
>> +	.clkr = {
>> +		.enable_reg = 0x3a008,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_cmn_12gpll_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor gcc_xo_div4_clk_src = {
>> +	.mult = 1,
>> +	.div = 4,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "gcc_xo_div4_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gcc_xo_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
>> +	.halt_reg = 0x1701c,
>> +	.clkr = {
>> +		.enable_reg = 0x1701c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_qosgen_ref_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_div4_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
>> +	.halt_reg = 0x17020,
>> +	.clkr = {
>> +		.enable_reg = 0x17020,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_timeout_ref_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_div4_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_xo_div4_clk = {
>> +	.halt_reg = 0x3401c,
>> +	.clkr = {
>> +		.enable_reg = 0x3401c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_xo_div4_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_div4_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_hw *gcc_ipq9574_hws[] = {
>> +	&gpll0_out_main_div2.hw,
>> +	&gcc_xo_div4_clk_src.hw,
>> +	&qdss_dap_sync_clk_src.hw,
>> +	&qdss_tsctr_div2_clk_src.hw,
>> +	&qdss_tsctr_div8_clk_src.hw,
>> +	&qdss_tsctr_div16_clk_src.hw,
>> +	&qdss_tsctr_div3_clk_src.hw,
>> +	&gcc_eud_at_div_clk_src.hw,
>> +	&pcnoc_clk_src.hw,
>> +};
>> +
> 
>> +static int clk_dummy_is_enabled(struct clk_hw *hw)
>> +{
>> +	return 1;
>> +};
>> +
>> +static int clk_dummy_enable(struct clk_hw *hw)
>> +{
>> +	return 0;
>> +};
>> +
>> +static void clk_dummy_disable(struct clk_hw *hw)
>> +{
>> +	return;
>> +};
>> +
>> +static u8 clk_dummy_get_parent(struct clk_hw *hw)
>> +{
>> +	return 0;
>> +};
>> +
>> +static int clk_dummy_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> +	return 0;
>> +};
>> +
>> +static int clk_dummy_set_rate(struct clk_hw *hw, unsigned long rate,
>> +			      unsigned long parent_rate)
>> +{
>> +	return 0;
>> +};
>> +
>> +static int clk_dummy_determine_rate(struct clk_hw *hw,
>> +				    struct clk_rate_request *req)
>> +{
>> +	return 0;
>> +};
>> +
>> +static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw,
>> +					   unsigned long parent_rate)
>> +{
>> +	return parent_rate;
>> +};
>> +
>> +static const struct clk_ops clk_dummy_ops = {
>> +	.is_enabled = clk_dummy_is_enabled,
>> +	.enable = clk_dummy_enable,
>> +	.disable = clk_dummy_disable,
>> +	.get_parent = clk_dummy_get_parent,
>> +	.set_parent = clk_dummy_set_parent,
>> +	.set_rate = clk_dummy_set_rate,
>> +	.recalc_rate = clk_dummy_recalc_rate,
>> +	.determine_rate = clk_dummy_determine_rate,
>> +};
>> +
>> +#define DEFINE_DUMMY_CLK(clk_name)				\
>> +(&(struct clk_regmap) {						\
>> +	.hw.init = &(struct clk_init_data) {			\
>> +		.name = #clk_name,				\
>> +		.parent_names = (const char *[]) { "xo"},	\
>> +		.num_parents = 1,				\
>> +		.ops = &clk_dummy_ops,				\
>> +	},							\
>> +})
> Definitely a big no.
Sure, will drop
> 
>> +
>> +static struct clk_regmap *gcc_ipq9574_clks[] = {
>> +	[GPLL0_MAIN] = &gpll0_main.clkr,
>> +	[GPLL0] = &gpll0.clkr,
>> +	[GPLL4_MAIN] = &gpll4_main.clkr,
>> +	[GPLL4] = &gpll4.clkr,
>> +	[GPLL2_MAIN] = &gpll2_main.clkr,
>> +	[GPLL2] = &gpll2.clkr,
>> +	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
>> +	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
>> +	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
>> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
>> +	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
>> +	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
>> +	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
>> +	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
>> +	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
>> +	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
>> +	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
>> +	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
>> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
>> +	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
>> +	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
>> +	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
>> +	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
>> +	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
>> +	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
>> +	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
>> +	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
>> +	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
>> +	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
>> +	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
>> +	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
>> +	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
>> +	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
>> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
>> +	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
>> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
>> +	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
>> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
>> +	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
>> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
>> +	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
>> +	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
>> +	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
>> +	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
>> +	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
>> +	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
>> +	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
>> +	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
>> +	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
>> +	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
>> +	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
>> +	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
>> +	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
>> +	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
>> +	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
>> +	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
>> +	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
>> +	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
>> +	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
>> +	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
>> +	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
>> +	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
>> +	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
>> +	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
>> +	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
>> +	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
>> +	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
>> +	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
>> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
>> +	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
>> +	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
>> +	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
>> +	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
>> +	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
>> +	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
>> +	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
>> +	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
>> +	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
>> +	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
>> +	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
>> +	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
>> +	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
>> +	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
>> +	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
>> +	[GCC_SNOC_PCNOC_AHB_CLK] = &gcc_snoc_pcnoc_ahb_clk.clkr,
>> +	[GCC_ANOC_PCNOC_AHB_CLK] = &gcc_anoc_pcnoc_ahb_clk.clkr,
>> +	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
>> +	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
>> +	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
>> +	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
>> +	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
>> +	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
>> +	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
>> +	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
>> +	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
>> +	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
>> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
>> +	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
>> +	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
>> +	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
>> +	[GCC_SYS_NOC_AXI_CLK] = &gcc_sys_noc_axi_clk.clkr,
>> +	[GCC_ANOC0_AXI_CLK] = &gcc_anoc0_axi_clk.clkr,
>> +	[GCC_ANOC1_AXI_CLK] = &gcc_anoc1_axi_clk.clkr,
>> +	[GCC_ANOC0_TBU_CLK] = &gcc_anoc0_tbu_clk.clkr,
>> +	[GCC_ANOC1_TBU_CLK] = &gcc_anoc1_tbu_clk.clkr,
>> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = &gcc_mem_noc_snoc_axi_clk.clkr,
>> +	[GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
>> +	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
>> +	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
>> +	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
>> +	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
>> +	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
>> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
>> +	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
>> +	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
>> +	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
>> +	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
>> +	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
>> +	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
>> +	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
>> +	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
>> +	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
>> +	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
>> +	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
>> +	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
>> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
>> +	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
>> +	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
>> +	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
>> +	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
>> +	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
>> +	[GCC_SNOC_TS_CLK] = &gcc_snoc_ts_clk.clkr,
>> +	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
>> +	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
>> +	[GCC_PCNOC_TS_CLK] = &gcc_pcnoc_ts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
>> +	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
>> +	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
>> +	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
>> +	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
>> +	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
>> +	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
>> +	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
>> +	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
>> +	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
>> +	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
>> +	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
>> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
>> +	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
>> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
>> +	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
>> +	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
>> +	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
>> +	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
>> +	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
>> +	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
>> +	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
>> +	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
>> +	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
>> +	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
>> +	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
>> +	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
>> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
>> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
>> +	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
>> +	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
>> +	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
>> +	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
>> +	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
>> +	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
>> +	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
>> +	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
>> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
>> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
>> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
>> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
>> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
>> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
>> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
>> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
>> +	[GCC_PCNOC_DCC_CLK] = &gcc_pcnoc_dcc_clk.clkr,
>> +};
>> +
>> +static struct clk_regmap *gcc_ipq9574_dummy_clks[] = {
>> +	[GPLL0_MAIN] = DEFINE_DUMMY_CLK(gpll0_main),
>> +	[GPLL0] = DEFINE_DUMMY_CLK(gpll0),
>> +	[GPLL4_MAIN] = DEFINE_DUMMY_CLK(gpll4_main),
>> +	[GPLL4] = DEFINE_DUMMY_CLK(gpll4),
>> +	[GPLL2_MAIN] = DEFINE_DUMMY_CLK(gpll2_main),
>> +	[GPLL2] = DEFINE_DUMMY_CLK(gpll2),
>> +	[GCC_SLEEP_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_sleep_clk_src),
>> +	[APSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(apss_ahb_clk_src),
>> +	[APSS_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(apss_axi_clk_src),
>> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_i2c_apps_clk_src),
>> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_spi_apps_clk_src),
>> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_i2c_apps_clk_src),
>> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_spi_apps_clk_src),
>> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_i2c_apps_clk_src),
>> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_spi_apps_clk_src),
>> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_i2c_apps_clk_src),
>> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_spi_apps_clk_src),
>> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_i2c_apps_clk_src),
>> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_spi_apps_clk_src),
>> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_i2c_apps_clk_src),
>> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_spi_apps_clk_src),
>> +	[BLSP1_UART1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart1_apps_clk_src),
>> +	[BLSP1_UART2_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart2_apps_clk_src),
>> +	[BLSP1_UART3_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart3_apps_clk_src),
>> +	[BLSP1_UART4_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart4_apps_clk_src),
>> +	[BLSP1_UART5_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart5_apps_clk_src),
>> +	[BLSP1_UART6_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart6_apps_clk_src),
>> +	[GCC_APSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_apss_ahb_clk),
>> +	[GCC_APSS_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_apss_axi_clk),
>> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_spi_apps_clk),
>> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_spi_apps_clk),
>> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_spi_apps_clk),
>> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_spi_apps_clk),
>> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_spi_apps_clk),
>> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_spi_apps_clk),
>> +	[GCC_BLSP1_UART1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart1_apps_clk),
>> +	[GCC_BLSP1_UART2_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart2_apps_clk),
>> +	[GCC_BLSP1_UART3_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart3_apps_clk),
>> +	[GCC_BLSP1_UART4_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart4_apps_clk),
>> +	[GCC_BLSP1_UART5_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart5_apps_clk),
>> +	[GCC_BLSP1_UART6_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart6_apps_clk),
>> +	[PCIE0_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_m_clk_src),
>> +	[GCC_PCIE0_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_m_clk),
>> +	[PCIE1_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_m_clk_src),
>> +	[GCC_PCIE1_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_m_clk),
>> +	[PCIE2_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_m_clk_src),
>> +	[GCC_PCIE2_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_m_clk),
>> +	[PCIE3_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_m_clk_src),
>> +	[GCC_PCIE3_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_m_clk),
>> +	[PCIE0_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_s_clk_src),
>> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_bridge_clk),
>> +	[GCC_PCIE0_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_clk),
>> +	[PCIE1_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_s_clk_src),
>> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_bridge_clk),
>> +	[GCC_PCIE1_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_clk),
>> +	[PCIE2_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_s_clk_src),
>> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_bridge_clk),
>> +	[GCC_PCIE2_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_clk),
>> +	[PCIE3_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_s_clk_src),
>> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_bridge_clk),
>> +	[GCC_PCIE3_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_clk),
>> +	[PCIE0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_pipe_clk_src),
>> +	[PCIE1_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_pipe_clk_src),
>> +	[PCIE2_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_pipe_clk_src),
>> +	[PCIE3_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_pipe_clk_src),
>> +	[PCIE_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(pcie_aux_clk_src),
>> +	[GCC_PCIE0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_aux_clk),
>> +	[GCC_PCIE1_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_aux_clk),
>> +	[GCC_PCIE2_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_aux_clk),
>> +	[GCC_PCIE3_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_aux_clk),
>> +	[PCIE0_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_rchng_clk_src),
>> +	[GCC_PCIE0_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_rchng_clk),
>> +	[PCIE1_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_rchng_clk_src),
>> +	[GCC_PCIE1_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_rchng_clk),
>> +	[PCIE2_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_rchng_clk_src),
>> +	[GCC_PCIE2_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_rchng_clk),
>> +	[PCIE3_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_rchng_clk_src),
>> +	[GCC_PCIE3_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_rchng_clk),
>> +	[GCC_PCIE0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_ahb_clk),
>> +	[GCC_PCIE1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_ahb_clk),
>> +	[GCC_PCIE2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_ahb_clk),
>> +	[GCC_PCIE3_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_ahb_clk),
>> +	[USB0_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_aux_clk_src),
>> +	[GCC_USB0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_aux_clk),
>> +	[USB0_MASTER_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_master_clk_src),
>> +	[GCC_USB0_MASTER_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_master_clk),
>> +	[GCC_SNOC_USB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_usb_clk),
>> +	[GCC_ANOC_USB_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_usb_axi_clk),
>> +	[USB0_MOCK_UTMI_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_clk_src),
>> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_div_clk_src),
>> +	[GCC_USB0_MOCK_UTMI_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_mock_utmi_clk),
>> +	[USB0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_pipe_clk_src),
>> +	[GCC_USB0_PHY_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_phy_cfg_ahb_clk),
>> +	[SDCC1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_apps_clk_src),
>> +	[GCC_SDCC1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_apps_clk),
>> +	[SDCC1_ICE_CORE_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_ice_core_clk_src),
>> +	[GCC_SDCC1_ICE_CORE_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ice_core_clk),
>> +	[GCC_SDCC1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ahb_clk),
>> +	[PCNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(pcnoc_bfdcd_clk_src),
>> +	[GCC_NSSCFG_CLK] = DEFINE_DUMMY_CLK(gcc_nsscfg_clk),
>> +	[GCC_NSSNOC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_nsscc_clk),
>> +	[GCC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nsscc_clk),
>> +	[GCC_NSSNOC_PCNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_pcnoc_1_clk),
>> +	[GCC_QDSS_DAP_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_ahb_clk),
>> +	[GCC_QDSS_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_cfg_ahb_clk),
>> +	[GCC_SNOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcnoc_ahb_clk),
>> +	[GCC_ANOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcnoc_ahb_clk),
>> +	[GCC_QPIC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_ahb_clk),
>> +	[GCC_QPIC_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_clk),
>> +	[GCC_BLSP1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_ahb_clk),
>> +	[GCC_MDIO_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_mdio_ahb_clk),
>> +	[GCC_PRNG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_prng_ahb_clk),
>> +	[GCC_UNIPHY0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_ahb_clk),
>> +	[GCC_UNIPHY1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_ahb_clk),
>> +	[GCC_UNIPHY2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_ahb_clk),
>> +	[GCC_CMN_12GPLL_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_ahb_clk),
>> +	[GCC_CMN_12GPLL_APU_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_apu_clk),
>> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(system_noc_bfdcd_clk_src),
>> +	[GCC_NSSNOC_SNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_clk),
>> +	[GCC_NSSNOC_SNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_1_clk),
>> +	[GCC_QDSS_ETR_USB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_etr_usb_clk),
>> +	[GCC_SYS_NOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_axi_clk),
>> +	[GCC_ANOC0_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_axi_clk),
>> +	[GCC_ANOC1_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_axi_clk),
>> +	[GCC_ANOC0_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_tbu_clk),
>> +	[GCC_ANOC1_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_tbu_clk),
>> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_snoc_axi_clk),
>> +	[GCC_IMEM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_imem_axi_clk),
>> +	[WCSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_ahb_clk_src),
>> +	[GCC_Q6_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_clk),
>> +	[GCC_Q6_AHB_S_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_s_clk),
>> +	[GCC_WCSS_ECAHB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_ecahb_clk),
>> +	[GCC_WCSS_ACMT_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_acmt_clk),
>> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_wcss_ahb_clk),
>> +	[WCSS_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_axi_m_clk_src),
>> +	[GCC_ANOC_WCSS_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_wcss_axi_m_clk),
>> +	[QDSS_AT_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_at_clk_src),
>> +	[GCC_Q6SS_ATBM_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_atbm_clk),
>> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_atb_clk),
>> +	[GCC_NSSNOC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_atb_clk),
>> +	[GCC_QDSS_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_at_clk),
>> +	[GCC_SYS_NOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_at_clk),
>> +	[GCC_PCNOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_at_clk),
>> +	[GCC_USB0_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_eud_at_clk),
>> +	[GCC_QDSS_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_eud_at_clk),
>> +	[QDSS_STM_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_stm_clk_src),
>> +	[GCC_QDSS_STM_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_stm_clk),
>> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_qdss_stm_axi_clk),
>> +	[QDSS_TRACECLKIN_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_traceclkin_clk_src),
>> +	[GCC_QDSS_TRACECLKIN_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_traceclkin_clk),
>> +	[QDSS_TSCTR_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_tsctr_clk_src),
>> +	[GCC_Q6_TSCTR_1TO2_CLK] = DEFINE_DUMMY_CLK(gcc_q6_tsctr_1to2_clk),
>> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_nts_clk),
>> +	[GCC_QDSS_TSCTR_DIV2_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div2_clk),
>> +	[GCC_QDSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_ts_clk),
>> +	[GCC_SNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_ts_clk),
>> +	[GCC_MEM_NOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_ts_clk),
>> +	[GCC_QDSS_TSCTR_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div4_clk),
>> +	[GCC_NSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_nss_ts_clk),
>> +	[GCC_QDSS_TSCTR_DIV8_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div8_clk),
>> +	[GCC_PCNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_ts_clk),
>> +	[GCC_QDSS_TSCTR_DIV16_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div16_clk),
>> +	[GCC_Q6SS_PCLKDBG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_pclkdbg_clk),
>> +	[GCC_Q6SS_TRIG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_trig_clk),
>> +	[GCC_WCSS_DBG_IFC_APB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_apb_clk),
>> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_dapbus_clk),
>> +	[GCC_QDSS_DAP_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_clk),
>> +	[GCC_QDSS_APB2JTAG_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_apb2jtag_clk),
>> +	[GCC_QDSS_TSCTR_DIV3_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div3_clk),
>> +	[QPIC_IO_MACRO_CLK_SRC] = DEFINE_DUMMY_CLK(qpic_io_macro_clk_src),
>> +	[GCC_QPIC_IO_MACRO_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_io_macro_clk),
>> +	[Q6_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axi_clk_src),
>> +	[GCC_Q6_AXIM_CLK] = DEFINE_DUMMY_CLK(gcc_q6_axim_clk),
>> +	[GCC_WCSS_Q6_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_q6_tbu_clk),
>> +	[GCC_MEM_NOC_Q6_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_q6_axi_clk),
>> +	[Q6_AXIM2_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axim2_clk_src),
>> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(nssnoc_memnoc_bfdcd_clk_src),
>> +	[GCC_NSSNOC_MEMNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_memnoc_clk),
>> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_mem_noc_1_clk),
>> +	[GCC_NSS_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_nss_tbu_clk),
>> +	[GCC_MEM_NOC_NSSNOC_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_nssnoc_clk),
>> +	[LPASS_AXIM_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_axim_clk_src),
>> +	[LPASS_SWAY_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_sway_clk_src),
>> +	[ADSS_PWM_CLK_SRC] = DEFINE_DUMMY_CLK(adss_pwm_clk_src),
>> +	[GCC_ADSS_PWM_CLK] = DEFINE_DUMMY_CLK(gcc_adss_pwm_clk),
>> +	[GP1_CLK_SRC] = DEFINE_DUMMY_CLK(gp1_clk_src),
>> +	[GP2_CLK_SRC] = DEFINE_DUMMY_CLK(gp2_clk_src),
>> +	[GP3_CLK_SRC] = DEFINE_DUMMY_CLK(gp3_clk_src),
>> +	[DDRSS_SMS_SLOW_CLK_SRC] = DEFINE_DUMMY_CLK(ddrss_sms_slow_clk_src),
>> +	[GCC_XO_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_xo_clk_src),
>> +	[GCC_NSSNOC_XO_DCD_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_xo_dcd_clk),
>> +	[GCC_XO_CLK] = DEFINE_DUMMY_CLK(gcc_xo_clk),
>> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_qosgen_ref_clk),
>> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_timeout_ref_clk),
>> +	[GCC_XO_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_xo_div4_clk),
>> +	[GCC_UNIPHY0_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_sys_clk),
>> +	[GCC_UNIPHY1_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_sys_clk),
>> +	[GCC_UNIPHY2_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_sys_clk),
>> +	[GCC_CMN_12GPLL_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_sys_clk),
>> +	[GCC_Q6SS_BOOT_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_boot_clk),
>> +	[UNIPHY_SYS_CLK_SRC] = DEFINE_DUMMY_CLK(uniphy_sys_clk_src),
>> +	[NSS_TS_CLK_SRC] = DEFINE_DUMMY_CLK(nss_ts_clk_src),
>> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie0_1lane_m_clk),
>> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie1_1lane_m_clk),
>> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie2_2lane_m_clk),
>> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie3_2lane_m_clk),
>> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie0_1lane_s_clk),
>> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie1_1lane_s_clk),
>> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie2_2lane_s_clk),
>> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie3_2lane_s_clk),
>> +	[GCC_PCNOC_DCC_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_dcc_clk),
>> +};
> Drop.
Okay
> 
>> +
>> +static const struct qcom_reset_map gcc_ipq9574_resets[] = {
>> +	[GCC_ADSS_BCR] = { 0x1c000, 0 },
>> +	[GCC_ANOC0_TBU_BCR] = { 0x1203C, 0 },
>> +	[GCC_ANOC1_TBU_BCR] = { 0x1204C, 0 },
>> +	[GCC_ANOC_BCR] = { 0x2E074, 0 },
>> +	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
>> +	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
>> +	[GCC_BLSP1_BCR] = { 0x01000, 0 },
>> +	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
>> +	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
>> +	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
>> +	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
>> +	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
>> +	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
>> +	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
>> +	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
>> +	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
>> +	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
>> +	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
>> +	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
>> +	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
>> +	[GCC_CMN_BLK_BCR] = { 0x3A000, 0 },
>> +	[GCC_CMN_BLK_AHB_ARES] = { 0x3A010, 0 },
>> +	[GCC_CMN_BLK_SYS_ARES] = { 0x3A010, 1 },
>> +	[GCC_CMN_BLK_APU_ARES] = { 0x3A010, 2 },
>> +	[GCC_DCC_BCR] = { 0x35000, 0 },
>> +	[GCC_DDRSS_BCR] = { 0x11000, 0 },
>> +	[GCC_IMEM_BCR] = { 0x0e000, 0 },
>> +	[GCC_LPASS_BCR] = { 0x27000, 0 },
>> +	[GCC_MDIO_BCR] = { 0x1703c, 0 },
>> +	[GCC_MPM_BCR] = { 0x37000, 0 },
>> +	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
>> +	[GCC_NSS_BCR] = { 0x17000, 0 },
>> +	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
>> +	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
>> +	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
>> +	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
>> +	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
>> +	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
>> +	[GCC_NSSCC_ARES] = { 0x17038, 8 },
>> +	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
>> +	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
>> +	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
>> +	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
>> +	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
>> +	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
>> +	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
>> +	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
>> +	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
>> +	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
>> +	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
>> +	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
>> +	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
>> +	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
>> +	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
>> +	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
>> +	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
>> +	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
>> +	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
>> +	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
>> +	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
>> +	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
>> +	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
>> +	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
>> +	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
>> +	[GCC_PCIE2_AHB_ARES] = { 0x2A058, 7 },
>> +	[GCC_PCIE2_AUX_ARES] = { 0x2A058, 6 },
>> +	[GCC_PCIE2_AXI_M_ARES] = { 0x2A058, 5 },
>> +	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2A058, 4 },
>> +	[GCC_PCIE2_AXI_S_ARES] = { 0x2A058, 3 },
>> +	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2A058, 2 },
>> +	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2A058, 1 },
>> +	[GCC_PCIE2_PIPE_ARES] = { 0x2A058, 0 },
>> +	[GCC_PCIE3_AHB_ARES] = { 0x2B058, 7 },
>> +	[GCC_PCIE3_AUX_ARES] = { 0x2B058, 6 },
>> +	[GCC_PCIE3_AXI_M_ARES] = { 0x2B058, 5 },
>> +	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2B058, 4 },
>> +	[GCC_PCIE3_AXI_S_ARES] = { 0x2B058, 3 },
>> +	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2B058, 2 },
>> +	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2B058, 1 },
>> +	[GCC_PCIE3_PIPE_ARES] = { 0x2B058, 0 },
>> +	[GCC_PCIE0_BCR] = { 0x28000, 0 },
>> +	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
>> +	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
>> +	[GCC_PCIE1_BCR] = { 0x29000, 0 },
>> +	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
>> +	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
>> +	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
>> +	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
>> +	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
>> +	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
>> +	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
>> +	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
>> +	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
>> +	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
>> +	[GCC_PCIE3_PHY_BCR] = { 0x2B060, 0 },
>> +	[GCC_PCNOC_BCR] = { 0x31000, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
>> +	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
>> +	[GCC_PRNG_BCR] = { 0x13020, 0 },
>> +	[GCC_Q6SS_DBG_ARES] = { 0x2506C, 4 },
>> +	[GCC_Q6_AHB_ARES] = { 0x2506C, 3 },
>> +	[GCC_Q6_AHB_S_ARES] = { 0x2506C, 2 },
>> +	[GCC_Q6_AXIM2_ARES] = { 0x2506C, 1 },
>> +	[GCC_Q6_AXIM_ARES] = { 0x2506C, 0 },
>> +	[GCC_QDSS_BCR] = { 0x2d000, 0 },
>> +	[GCC_QPIC_BCR] = { 0x32000, 0 },
>> +	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
>> +	[GCC_QPIC_ARES] = { 0x3201c, 0 },
>> +	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
>> +	[GCC_RBCPR_BCR] = { 0x39000, 0 },
>> +	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
>> +	[GCC_SDCC_BCR] = { 0x33000, 0 },
>> +	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
>> +	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
>> +	[GCC_SNOC_BCR] = { 0x2E000, 0 },
>> +	[GCC_SPDM_BCR] = { 0x36000, 0 },
>> +	[GCC_TCSR_BCR] = { 0x3d000, 0 },
>> +	[GCC_TLMM_BCR] = { 0x3e000, 0 },
>> +	[GCC_TME_BCR] = { 0x10000, 0 },
>> +	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
>> +	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
>> +	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
>> +	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
>> +	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
>> +	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
>> +	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
>> +	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
>> +	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
>> +	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
>> +	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
>> +	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
>> +	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
>> +	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
>> +	[GCC_USB_BCR] = { 0x2c000, 0 },
>> +	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
>> +	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
>> +	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
>> +	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
>> +	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
>> +	[GCC_WCSS_BCR] = { 0x18004, 0 },
>> +	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
>> +	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
>> +	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
>> +	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
>> +	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
>> +};
>> +
>> +static const struct of_device_id gcc_ipq9574_match_table[] = {
>> +	{ .compatible = "qcom,gcc-ipq9574" },
>> +	{ }
>> +};
>> +MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
>> +
>> +static const struct regmap_config gcc_ipq9574_regmap_config = {
>> +	.reg_bits       = 32,
>> +	.reg_stride     = 4,
>> +	.val_bits       = 32,
>> +	.max_register   = 0x7fffc,
>> +	.fast_io	= true,
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_ipq9574_desc = {
>> +	.config = &gcc_ipq9574_regmap_config,
>> +	.clks = gcc_ipq9574_clks,
>> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
>> +	.resets = gcc_ipq9574_resets,
>> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
>> +	.clk_hws = gcc_ipq9574_hws,
>> +	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_ipq9574_dummy_desc = {
>> +	.config = &gcc_ipq9574_regmap_config,
>> +	.clks = gcc_ipq9574_dummy_clks,
>> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_dummy_clks),
>> +	.resets = gcc_ipq9574_resets,
>> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
>> +};
>> +
>> +static int gcc_ipq9574_probe(struct platform_device *pdev)
>> +{
>> +	struct regmap *regmap;
>> +	struct qcom_cc_desc ipq9574_desc = gcc_ipq9574_desc;
>> +	struct device_node *np = (&pdev->dev)->of_node;
>> +
>> +	if (of_property_read_bool(np, "gcc-use-dummy"))
>> +		ipq9574_desc = gcc_ipq9574_dummy_desc;
>> +
>> +	regmap = qcom_cc_map(pdev, &ipq9574_desc);
>> +	if (IS_ERR(regmap))
>> +		return PTR_ERR(regmap);
>> +
>> +	return qcom_cc_really_probe(pdev, &ipq9574_desc, regmap);
>> +}
>> +
>> +static int gcc_ipq9574_remove(struct platform_device *pdev)
> Generally you shouldn't remove the driver that ensures your platform
> well, works..
> 
> Plus GCCs are always =y in mainline to make sure dependencies are met
> so there's no removing.
Okay, understood!
> 
>> +{
>> +	return 0;
>> +}
>> +
>> +static struct platform_driver gcc_ipq9574_driver = {
>> +	.probe = gcc_ipq9574_probe,
>> +	.remove = gcc_ipq9574_remove,
>> +	.driver = {
>> +		.name   = "qcom,gcc-ipq9574",
>> +		.of_match_table = gcc_ipq9574_match_table,
>> +	},
>> +};
>> +
>> +static int __init gcc_ipq9574_init(void)
>> +{
>> +	return platform_driver_register(&gcc_ipq9574_driver);
>> +}
>> +core_initcall(gcc_ipq9574_init);
>> +
>> +static void __exit gcc_ipq9574_exit(void)
>> +{
>> +	platform_driver_unregister(&gcc_ipq9574_driver);
>> +}
>> +module_exit(gcc_ipq9574_exit);
>> +
>> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
>> +MODULE_LICENSE("GPL");

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Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Devi Priya]

On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
> 
> 
> On 10.01.2023 13:13, devi priya wrote:
>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/clk/qcom/Kconfig       |    8 +
>>   drivers/clk/qcom/Makefile      |    1 +
>>   drivers/clk/qcom/gcc-ipq9574.c | 4706 ++++++++++++++++++++++++++++++++
>>   3 files changed, 4715 insertions(+)
>>   create mode 100644 drivers/clk/qcom/gcc-ipq9574.c
>>
>> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
>> index 70d43f0a8919..97517d1e3ba4 100644
>> --- a/drivers/clk/qcom/Kconfig
>> +++ b/drivers/clk/qcom/Kconfig
>> @@ -173,6 +173,14 @@ config IPQ_GCC_8074
>>   	  i2c, USB, SD/eMMC, etc. Select this for the root clock
>>   	  of ipq8074.
>>   
>> +config IPQ_GCC_9574
>> +	tristate "IPQ9574 Global Clock Controller"
>> +	help
>> +	  Support for global clock controller on ipq9574 devices.
>> +	  Say Y if you want to use peripheral devices such as UART, SPI,
>> +	  i2c, USB, SD/eMMC, etc. Select this for the root clock
>> +	  of ipq9574.
>> +
>>   config MSM_GCC_8660
>>   	tristate "MSM8660 Global Clock Controller"
>>   	help
>> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
>> index f18c446a97ea..55c6ada326e0 100644
>> --- a/drivers/clk/qcom/Makefile
>> +++ b/drivers/clk/qcom/Makefile
>> @@ -27,6 +27,7 @@ obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
>>   obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o
>>   obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
>>   obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o
>> +obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o
>>   obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o
>>   obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o
>>   obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o
>> diff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c
>> new file mode 100644
>> index 000000000000..f44a19c5f9a1
>> --- /dev/null
>> +++ b/drivers/clk/qcom/gcc-ipq9574.c
>> @@ -0,0 +1,4706 @@
>> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> Hm, interesting choice for a C driver..
> 
>> +/*
>> + * Copyright (c) 2022 The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/kernel.h>
>> +#include <linux/err.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/clk-provider.h>
>> +#include <linux/regmap.h>
>> +
>> +#include <linux/reset-controller.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +#include "common.h"
>> +#include "clk-regmap.h"
>> +#include "clk-pll.h"
>> +#include "clk-rcg.h"
>> +#include "clk-branch.h"
>> +#include "clk-alpha-pll.h"
>> +#include "clk-regmap-divider.h"
>> +#include "clk-regmap-mux.h"
>> +#include "reset.h"
> Many of these includes seem unnecessary..
Sure, will remove
> 
> 
>> +
>> +#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
> Drop.
Okay
> 
>> +
>> +/* Need to match the order of clocks in DT binding */
>> +enum {
>> +	DT_XO,
>> +	DT_SLEEP_CLK,
>> +	DT_BIAS_PLL_UBI_NC_CLK,
>> +	DT_PCIE30_PHY0_PIPE_CLK,
>> +	DT_PCIE30_PHY1_PIPE_CLK,
>> +	DT_PCIE30_PHY2_PIPE_CLK,
>> +	DT_PCIE30_PHY3_PIPE_CLK,
>> +	DT_USB3PHY_0_CC_PIPE_CLK,
>> +};
>> +
>> +enum {
>> +	P_XO,
>> +	P_PCIE30_PHY0_PIPE,
>> +	P_PCIE30_PHY1_PIPE,
>> +	P_PCIE30_PHY2_PIPE,
>> +	P_PCIE30_PHY3_PIPE,
>> +	P_USB3PHY_0_PIPE,
>> +	P_GPLL0,
>> +	P_GPLL0_DIV2,
>> +	P_GPLL0_OUT_AUX,
>> +	P_GPLL2,
>> +	P_GPLL4,
>> +	P_PI_SLEEP,
>> +	P_BIAS_PLL_UBI_NC_CLK,
>> +};
>> +
>> +static const struct parent_map gcc_xo_map[] = {
>> +	{ P_XO, 0 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_data[] = {
>> +	{ .index = DT_XO },
>> +};
>> +
>> +static const struct clk_parent_data gcc_sleep_clk_data[] = {
>> +	{ .index = DT_SLEEP_CLK },
>> +};
>> +
>> +static struct clk_alpha_pll gpll0_main = {
>> +	.offset = 0x20000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.clkr = {
>> +		.enable_reg = 0x0b000,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gpll0_main",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.ops = &clk_alpha_pll_ops,
>> +			.flags = CLK_IS_CRITICAL,
> Is it? Does it act as a CPU PLL source that's not managed by the
> firmware?
Okay, will remove the critical flag as it is managed by the firmware
> 
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor gpll0_out_main_div2 = {
>> +	.mult = 1,
>> +	.div = 2,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll0_out_main_div2",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll0_main.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll0 = {
>> +	.offset = 0x20000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.width = 4,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll0",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll0_main.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll gpll4_main = {
>> +	.offset = 0x22000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.clkr = {
>> +		.enable_reg = 0x0b000,
>> +		.enable_mask = BIT(2),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gpll4_main",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.ops = &clk_alpha_pll_ops,
>> +			.flags = CLK_IS_CRITICAL,
> Again, is it?
okay, will remove
> 
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll4 = {
>> +	.offset = 0x22000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.width = 4,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll4",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll4_main.clkr.hw },
> Please put the }, in a new line.
okay
> 
>> +		.num_parents = 1,
>> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll gpll2_main = {
>> +	.offset = 0x21000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.clkr = {
>> +		.enable_reg = 0x0b000,
>> +		.enable_mask = BIT(1),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gpll2_main",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.ops = &clk_alpha_pll_ops,
>> +			.flags = CLK_IS_CRITICAL,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_alpha_pll_postdiv gpll2 = {
>> +	.offset = 0x21000,
>> +	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
>> +	.width = 4,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gpll2",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gpll2_main.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_alpha_pll_postdiv_ro_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sleep_clk_src = {
>> +	.halt_reg = 0x3400c,
>> +	.clkr = {
>> +		.enable_reg = 0x3400c,
>> +		.enable_mask = BIT(1),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sleep_clk_src",
>> +			.parent_data = gcc_sleep_clk_data,
>> +			.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),
>> +			.ops = &clk_branch2_ops,
>> +			.flags = CLK_IS_CRITICAL,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw},
> Please consistently add a space before },
sure, okay
> 
>> +	{ .hw = &gpll0_out_main_div2.hw},
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL0_DIV2, 4 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw },
>> +	{ .hw = &gpll4.clkr.hw },
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL4, 2 },
>> +};
>> +
>> +static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {
>> +	{ .index = DT_XO },
>> +	{ .hw = &gpll0.clkr.hw },
>> +	{ .hw = &gpll0_out_main_div2.hw },
>> +	{ .hw = &gpll0.clkr.hw },
>> +};
>> +
>> +static const struct parent_map
>> +gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {
> Pretty sure you can unwrap that line
okay
> 
> 
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL0_DIV2, 4 },
>> +	{ P_GPLL0, 5 },
>> +};
>> +
> 
> [...]
> 
>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>> +	.halt_reg = 0x07024,
>> +	.clkr = {
>> +		.enable_reg = 0x07024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_blsp1_qup6_i2c_apps_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Sounds very much like a hack..
Got it, will remove the clock entry as it is not being used in linux
> 
> [...]
> 
> 
>> +static struct clk_branch gcc_snoc_usb_clk = {
>> +	.halt_reg = 0x2E058,
> Please lowercase hex all throughout the file.
okay
> 
>> +	.clkr = {
>> +		.enable_reg = 0x2E058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_snoc_usb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&usb0_master_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
> [...]
> 
>> +
>> +static struct clk_rcg2 pcnoc_bfdcd_clk_src = {
>> +	.cmd_rcgr = 0x31004,
>> +	.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "pcnoc_bfdcd_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
>> +		.ops = &clk_rcg2_ops,
>> +		.flags = CLK_IS_CRITICAL,
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor pcnoc_clk_src = {
>> +	.mult = 1,
>> +	.div = 1,
> Is there any benefit in keeping it instead of providing
> the real rcg as a parent?
okay, understood..will remove
> 
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "pcnoc_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&pcnoc_bfdcd_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
> 
> [...]
>> +static struct clk_branch gcc_snoc_pcnoc_ahb_clk = {
>> +	.halt_reg = 0x2E03C,
>> +	.clkr = {
>> +		.enable_reg = 0x2E03C,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_snoc_pcnoc_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&pcnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Can it be turned off? Perhaps CLK_IS_CRITICAL would be more fitting,
> with a comment explaining why.
Okay, got it. Will remove the clock entry as it will be set by the 
bootloaders
> 
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc_pcnoc_ahb_clk = {
>> +	.halt_reg = 0x2E094,
>> +	.clkr = {
>> +		.enable_reg = 0x2E094,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc_pcnoc_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&pcnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Same thing
> 
Okay
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
> 
>> +
>> +static struct clk_rcg2 system_noc_bfdcd_clk_src = {
>> +	.cmd_rcgr = 0x2e004,
>> +	.freq_tbl = ftbl_system_noc_bfdcd_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll4_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "system_noc_bfdcd_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll4,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
>> +		.ops = &clk_rcg2_ops,
>> +		.flags = CLK_IS_CRITICAL,
> .flags goes before .ops in all other nodes, please be consistent.
okay
> 
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_boot_clk = {
>> +	.halt_reg = 0x25080,
>> +	.halt_check = BRANCH_HALT_SKIP,
>> +	.clkr = {
>> +		.enable_reg = 0x25080,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_boot_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_snoc_clk = {
>> +	.halt_reg = 0x17028,
>> +	.clkr = {
>> +		.enable_reg = 0x17028,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_snoc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Same story as with PCNoC
okay
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_snoc_1_clk = {
>> +	.halt_reg = 0x1707c,
>> +	.clkr = {
>> +		.enable_reg = 0x1707c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_snoc_1_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> And here
sure
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_etr_usb_clk = {
>> +	.halt_reg = 0x2D060,
>> +	.clkr = {
>> +		.enable_reg = 0x2D060,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_etr_usb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(133333333, P_GPLL0, 6, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 wcss_ahb_clk_src = {
>> +	.cmd_rcgr = 0x25030,
>> +	.freq_tbl = ftbl_wcss_ahb_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "wcss_ahb_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_ahb_clk = {
>> +	.halt_reg = 0x25014,
>> +	.clkr = {
>> +		.enable_reg = 0x25014,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> This sounds like a hack, perhaps it should be fed to a remoteproc node?
> 
Sure, will remove the ignore_unused flag and handle it in the 
corresponding driver
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_ahb_s_clk = {
>> +	.halt_reg = 0x25018,
>> +	.clkr = {
>> +		.enable_reg = 0x25018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_ahb_s_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> And this one too
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_ecahb_clk = {
>> +	.halt_reg = 0x25058,
>> +	.clkr = {
>> +		.enable_reg = 0x25058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_ecahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Similarly, this one should probably be fed to the wcss node and
> properly managed with a driver, not left dangling
Got it
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_acmt_clk = {
>> +	.halt_reg = 0x2505c,
>> +	.clkr = {
>> +		.enable_reg = 0x2505c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_acmt_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_axi_clk = {
>> +	.halt_reg = 0x2e01c,
>> +	.clkr = {
>> +		.enable_reg = 0x2e01c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> CLK_IS_CRITICAL?
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc0_axi_clk = {
>> +	.halt_reg = 0x2e078,
>> +	.clkr = {
>> +		.enable_reg = 0x2e078,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc0_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> If this it the same kind of ANoC(n) as on 8996/8998, this should
> definitely be either CLK_IS_CRITICAL or managed through a driver..
> Probably the second one..
Sure, will do
> 
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc1_axi_clk = {
>> +	.halt_reg = 0x2e088,
>> +	.clkr = {
>> +		.enable_reg = 0x2e088,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc1_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc0_tbu_clk = {
>> +	.halt_reg = 0x12038,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(3),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc0_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc1_tbu_clk = {
>> +	.halt_reg = 0x12048,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(5),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc1_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_snoc_axi_clk = {
>> +	.halt_reg = 0x19018,
>> +	.clkr = {
>> +		.enable_reg = 0x19018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_snoc_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> This one also smells of an interconnect clock more than anything else..
> 
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_imem_axi_clk = {
>> +	.halt_reg = 0xe004,
>> +	.clkr = {
>> +		.enable_reg = 0xb004,
>> +		.enable_mask = BIT(12),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_imem_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&system_noc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> You could pass this one to the imem node
> 
Sure okay
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {
>> +	.halt_reg = 0x2e030,
>> +	.clkr = {
>> +		.enable_reg = 0x2e030,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_wcss_ahb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_ahb_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Definitely handled through a driver..
Yes, okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(133333333, P_GPLL0, 6, 0, 0),
>> +	F(266666667, P_GPLL0, 3, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 wcss_axi_m_clk_src = {
>> +	.cmd_rcgr = 0x25078,
>> +	.freq_tbl = ftbl_wcss_axi_m_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "wcss_axi_m_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_anoc_wcss_axi_m_clk = {
>> +	.halt_reg = 0x2e0a8,
>> +	.clkr = {
>> +		.enable_reg = 0x2e0a8,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_anoc_wcss_axi_m_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&wcss_axi_m_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_at_clk_src[] = {
>> +	F(240000000, P_GPLL4, 5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_at_clk_src = {
>> +	.cmd_rcgr = 0x2d004,
>> +	.freq_tbl = ftbl_qdss_at_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_at_clk_src",
>> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_atbm_clk = {
>> +	.halt_reg = 0x2501c,
>> +	.clkr = {
>> +		.enable_reg = 0x2501c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_atbm_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Ditto
okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {
>> +	.halt_reg = 0x2503c,
>> +	.clkr = {
>> +		.enable_reg = 0x2503c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_atb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> Not gonna point out every similar occurence, you probably get me now
Sure, understood. Will update them all
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_atb_clk = {
>> +	.halt_reg = 0x17014,
>> +	.clkr = {
>> +		.enable_reg = 0x17014,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_atb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_at_clk = {
>> +	.halt_reg = 0x2D038,
>> +	.clkr = {
>> +		.enable_reg = 0x2D038,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Probably not critical, you don't need debug 24/7.
okay
> 
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_at_clk = {
>> +	.halt_reg = 0x2e038,
>> +	.clkr = {
>> +		.enable_reg = 0x2e038,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_pcnoc_at_clk = {
>> +	.halt_reg = 0x31024,
>> +	.clkr = {
>> +		.enable_reg = 0x31024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_pcnoc_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_at_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor gcc_eud_at_div_clk_src = {
>> +	.mult = 1,
>> +	.div = 6,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "gcc_eud_at_div_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_at_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_usb0_eud_at_clk = {
>> +	.halt_reg = 0x30004,
>> +	.clkr = {
>> +		.enable_reg = 0x30004,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_usb0_eud_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_eud_at_div_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Definitely not critical.
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_eud_at_clk = {
>> +	.halt_reg = 0x2D06C,
>> +	.clkr = {
>> +		.enable_reg = 0x2D06C,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_eud_at_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_eud_at_div_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Ditto.
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(200000000, P_GPLL0, 4, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_stm_clk_src = {
>> +	.cmd_rcgr = 0x2D00C,
>> +	.freq_tbl = ftbl_qdss_stm_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_stm_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_stm_clk = {
>> +	.halt_reg = 0x2D03C,
>> +	.clkr = {
>> +		.enable_reg = 0x2D03C,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_stm_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_stm_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {
>> +	.halt_reg = 0x2E034,
>> +	.clkr = {
>> +		.enable_reg = 0x2E034,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_sys_noc_qdss_stm_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_stm_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {
>> +	F(300000000, P_GPLL4, 4, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_traceclkin_clk_src = {
>> +	.cmd_rcgr = 0x2d014,
>> +	.freq_tbl = ftbl_qdss_traceclkin_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_traceclkin_clk_src",
>> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_traceclkin_clk = {
>> +	.halt_reg = 0x2D040,
>> +	.clkr = {
>> +		.enable_reg = 0x2D040,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_traceclkin_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_traceclkin_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
>> +	F(600000000, P_GPLL4, 2, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qdss_tsctr_clk_src = {
>> +	.cmd_rcgr = 0x2d01c,
>> +	.freq_tbl = ftbl_qdss_tsctr_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_clk_src",
>> +		.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {
>> +	.mult = 1,
>> +	.div = 2,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div2_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_tsctr_1to2_clk = {
>> +	.halt_reg = 0x25020,
>> +	.clkr = {
>> +		.enable_reg = 0x25020,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_tsctr_1to2_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {
>> +	.halt_reg = 0x25040,
>> +	.clkr = {
>> +		.enable_reg = 0x25040,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_nts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div2_clk = {
>> +	.halt_reg = 0x2d044,
>> +	.clkr = {
>> +		.enable_reg = 0x2d044,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div2_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 uniphy_sys_clk_src = {
>> +	.cmd_rcgr = 0x17090,
>> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
>> +	.mnd_width = 8,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "uniphy_sys_clk_src",
>> +		.parent_data = gcc_xo_data,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 nss_ts_clk_src = {
>> +	.cmd_rcgr = 0x17088,
>> +	.freq_tbl = ftbl_uniphy_sys_clk_src,
>> +	.mnd_width = 8,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "nss_ts_clk_src",
>> +		.parent_data = gcc_xo_data,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_ts_clk = {
>> +	.halt_reg = 0x2D078,
>> +	.clkr = {
>> +		.enable_reg = 0x2D078,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nss_ts_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_snoc_ts_clk = {
>> +	.halt_reg = 0x2e068,
>> +	.clkr = {
>> +		.enable_reg = 0x2e068,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_snoc_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_ts_clk = {
>> +	.halt_reg = 0x19028,
>> +	.clkr = {
>> +		.enable_reg = 0x19028,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div2_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_dap_sync_clk_src = {
>> +	.mult = 1,
>> +	.div = 4,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_dap_sync_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div4_clk = {
>> +	.halt_reg = 0x2d04c,
>> +	.clkr = {
>> +		.enable_reg = 0x2d04c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div4_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {
>> +	.mult = 1,
>> +	.div = 8,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div8_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nss_ts_clk = {
>> +	.halt_reg = 0x17018,
>> +	.clkr = {
>> +		.enable_reg = 0x17018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nss_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nss_ts_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div8_clk = {
>> +	.halt_reg = 0x2d050,
>> +	.clkr = {
>> +		.enable_reg = 0x2d050,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div8_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div8_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_pcnoc_ts_clk = {
>> +	.halt_reg = 0x3102c,
>> +	.clkr = {
>> +		.enable_reg = 0x3102c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_pcnoc_ts_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div8_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {
>> +	.mult = 1,
>> +	.div = 16,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div16_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div16_clk = {
>> +	.halt_reg = 0x2d054,
>> +	.clkr = {
>> +		.enable_reg = 0x2d054,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div16_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div16_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_pclkdbg_clk = {
>> +	.halt_reg = 0x25024,
>> +	.clkr = {
>> +		.enable_reg = 0x25024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_pclkdbg_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6ss_trig_clk = {
>> +	.halt_reg = 0x25068,
>> +	.clkr = {
>> +		.enable_reg = 0x25068,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6ss_trig_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {
>> +	.halt_reg = 0x25038,
>> +	.clkr = {
>> +		.enable_reg = 0x25038,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_apb_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {
>> +	.halt_reg = 0x25044,
>> +	.clkr = {
>> +		.enable_reg = 0x25044,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_dbg_ifc_dapbus_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_dap_clk = {
>> +	.halt_reg = 0x2d058,
>> +	.clkr = {
>> +		.enable_reg = 0x2d058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_dap_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
> Probably not critical.
Okay
> 
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_apb2jtag_clk = {
>> +	.halt_reg = 0x2d05c,
>> +	.clkr = {
>> +		.enable_reg = 0x2d05c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_apb2jtag_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_pcnoc_dcc_clk = {
>> +	.halt_reg = 0x31080,
>> +	.clkr = {
>> +		.enable_reg = 0x31080,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_pcnoc_dcc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_dap_sync_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {
>> +	.mult = 1,
>> +	.div = 3,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "qdss_tsctr_div3_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&qdss_tsctr_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qdss_tsctr_div3_clk = {
>> +	.halt_reg = 0x2d048,
>> +	.clkr = {
>> +		.enable_reg = 0x2d048,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qdss_tsctr_div3_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qdss_tsctr_div3_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(100000000, P_GPLL0, 8, 0, 0),
>> +	F(200000000, P_GPLL0, 4, 0, 0),
>> +	F(320000000, P_GPLL0, 2.5, 0, 0),
>> +	F(400000000, P_GPLL0, 2, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 qpic_io_macro_clk_src = {
>> +	.cmd_rcgr = 0x32004,
>> +	.freq_tbl = ftbl_qpic_io_macro_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "qpic_io_macro_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_qpic_io_macro_clk = {
>> +	.halt_reg = 0x3200c,
>> +	.clkr = {
>> +		.enable_reg = 0x3200c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_qpic_io_macro_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&qpic_io_macro_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_q6_axi_clk_src[] = {
>> +	F(533333333, P_GPLL0, 1.5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 q6_axi_clk_src = {
>> +	.cmd_rcgr = 0x25004,
>> +	.freq_tbl = ftbl_q6_axi_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "q6_axi_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_q6_axim_clk = {
>> +	.halt_reg = 0x2500c,
>> +	.clkr = {
>> +		.enable_reg = 0x2500c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_q6_axim_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&q6_axi_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_wcss_q6_tbu_clk = {
>> +	.halt_reg = 0x12050,
>> +	.halt_check = BRANCH_HALT_DELAY,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(6),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_wcss_q6_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&q6_axi_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_q6_axi_clk = {
>> +	.halt_reg = 0x19010,
>> +	.clkr = {
>> +		.enable_reg = 0x19010,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_q6_axi_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&q6_axi_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {
>> +	F(342857143, P_GPLL4, 3.5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {
>> +	{ P_XO, 0 },
>> +	{ P_GPLL0, 1 },
>> +	{ P_GPLL4, 2 },
>> +	{ P_BIAS_PLL_UBI_NC_CLK, 4 },
>> +};
>> +
>> +static struct clk_rcg2 q6_axim2_clk_src = {
>> +	.cmd_rcgr = 0x25028,
>> +	.freq_tbl = ftbl_q6_axim2_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "q6_axim2_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {
>> +	F(533333333, P_GPLL0, 1.5, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {
>> +	.cmd_rcgr = 0x17004,
>> +	.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "nssnoc_memnoc_bfdcd_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_memnoc_clk = {
>> +	.halt_reg = 0x17024,
>> +	.clkr = {
>> +		.enable_reg = 0x17024,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_memnoc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {
>> +	.halt_reg = 0x17084,
>> +	.clkr = {
>> +		.enable_reg = 0x17084,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_mem_noc_1_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nss_tbu_clk = {
>> +	.halt_reg = 0x12040,
>> +	.clkr = {
>> +		.enable_reg = 0xb00c,
>> +		.enable_mask = BIT(4),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nss_tbu_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_mem_noc_nssnoc_clk = {
>> +	.halt_reg = 0x19014,
>> +	.clkr = {
>> +		.enable_reg = 0x19014,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_mem_noc_nssnoc_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&nssnoc_memnoc_bfdcd_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {
>> +	F(133333333, P_GPLL0, 6, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 lpass_axim_clk_src = {
>> +	.cmd_rcgr = 0x2700c,
>> +	.freq_tbl = ftbl_lpass_axim_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "lpass_axim_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 lpass_sway_clk_src = {
>> +	.cmd_rcgr = 0x27004,
>> +	.freq_tbl = ftbl_lpass_axim_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "lpass_sway_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(100000000, P_GPLL0, 8, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 adss_pwm_clk_src = {
>> +	.cmd_rcgr = 0x1c004,
>> +	.freq_tbl = ftbl_adss_pwm_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "adss_pwm_clk_src",
>> +		.parent_data = gcc_xo_gpll0,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_adss_pwm_clk = {
>> +	.halt_reg = 0x1c00c,
>> +	.clkr = {
>> +		.enable_reg = 0x1c00c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_adss_pwm_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&adss_pwm_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static const struct freq_tbl ftbl_gp1_clk_src[] = {
>> +	F(24000000, P_XO, 1, 0, 0),
>> +	F(200000000, P_GPLL0, 4, 0, 0),
>> +	{ }
>> +};
>> +
>> +static struct clk_rcg2 gp1_clk_src = {
>> +	.cmd_rcgr = 0x8004,
>> +	.freq_tbl = ftbl_gp1_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gp1_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 gp2_clk_src = {
>> +	.cmd_rcgr = 0x9004,
>> +	.freq_tbl = ftbl_gp1_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gp2_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_rcg2 gp3_clk_src = {
>> +	.cmd_rcgr = 0xa004,
>> +	.freq_tbl = ftbl_gp1_clk_src,
>> +	.hid_width = 5,
>> +	.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,
>> +	.clkr.hw.init = &(struct clk_init_data) {
>> +		.name = "gp3_clk_src",
>> +		.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,
>> +		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),
>> +		.ops = &clk_rcg2_ops,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_xo_clk_src = {
>> +	.halt_reg = 0x34004,
>> +	.clkr = {
>> +		.enable_reg = 0x34004,
>> +		.enable_mask = BIT(1),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_xo_clk_src",
>> +			.parent_data = gcc_xo_data,
>> +			.num_parents = ARRAY_SIZE(gcc_xo_data),
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_xo_dcd_clk = {
>> +	.halt_reg = 0x17074,
>> +	.clkr = {
>> +		.enable_reg = 0x17074,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_xo_dcd_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_xo_clk = {
>> +	.halt_reg = 0x34018,
>> +	.clkr = {
>> +		.enable_reg = 0x34018,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_xo_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_uniphy0_sys_clk = {
>> +	.halt_reg = 0x17048,
>> +	.clkr = {
>> +		.enable_reg = 0x17048,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_uniphy0_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_uniphy1_sys_clk = {
>> +	.halt_reg = 0x17058,
>> +	.clkr = {
>> +		.enable_reg = 0x17058,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_uniphy1_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_uniphy2_sys_clk = {
>> +	.halt_reg = 0x17068,
>> +	.clkr = {
>> +		.enable_reg = 0x17068,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_uniphy2_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_cmn_12gpll_sys_clk = {
>> +	.halt_reg = 0x3a008,
>> +	.clkr = {
>> +		.enable_reg = 0x3a008,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_cmn_12gpll_sys_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&uniphy_sys_clk_src.clkr.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_fixed_factor gcc_xo_div4_clk_src = {
>> +	.mult = 1,
>> +	.div = 4,
>> +	.hw.init = &(struct clk_init_data) {
>> +		.name = "gcc_xo_div4_clk_src",
>> +		.parent_hws = (const struct clk_hw *[]) {
>> +				&gcc_xo_clk_src.clkr.hw },
>> +		.num_parents = 1,
>> +		.ops = &clk_fixed_factor_ops,
>> +		.flags = CLK_SET_RATE_PARENT,
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {
>> +	.halt_reg = 0x1701c,
>> +	.clkr = {
>> +		.enable_reg = 0x1701c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_qosgen_ref_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_div4_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_nssnoc_timeout_ref_clk = {
>> +	.halt_reg = 0x17020,
>> +	.clkr = {
>> +		.enable_reg = 0x17020,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_nssnoc_timeout_ref_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_div4_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_branch gcc_xo_div4_clk = {
>> +	.halt_reg = 0x3401c,
>> +	.clkr = {
>> +		.enable_reg = 0x3401c,
>> +		.enable_mask = BIT(0),
>> +		.hw.init = &(struct clk_init_data) {
>> +			.name = "gcc_xo_div4_clk",
>> +			.parent_hws = (const struct clk_hw *[]) {
>> +					&gcc_xo_div4_clk_src.hw },
>> +			.num_parents = 1,
>> +			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
>> +			.ops = &clk_branch2_ops,
>> +		},
>> +	},
>> +};
>> +
>> +static struct clk_hw *gcc_ipq9574_hws[] = {
>> +	&gpll0_out_main_div2.hw,
>> +	&gcc_xo_div4_clk_src.hw,
>> +	&qdss_dap_sync_clk_src.hw,
>> +	&qdss_tsctr_div2_clk_src.hw,
>> +	&qdss_tsctr_div8_clk_src.hw,
>> +	&qdss_tsctr_div16_clk_src.hw,
>> +	&qdss_tsctr_div3_clk_src.hw,
>> +	&gcc_eud_at_div_clk_src.hw,
>> +	&pcnoc_clk_src.hw,
>> +};
>> +
> 
>> +static int clk_dummy_is_enabled(struct clk_hw *hw)
>> +{
>> +	return 1;
>> +};
>> +
>> +static int clk_dummy_enable(struct clk_hw *hw)
>> +{
>> +	return 0;
>> +};
>> +
>> +static void clk_dummy_disable(struct clk_hw *hw)
>> +{
>> +	return;
>> +};
>> +
>> +static u8 clk_dummy_get_parent(struct clk_hw *hw)
>> +{
>> +	return 0;
>> +};
>> +
>> +static int clk_dummy_set_parent(struct clk_hw *hw, u8 index)
>> +{
>> +	return 0;
>> +};
>> +
>> +static int clk_dummy_set_rate(struct clk_hw *hw, unsigned long rate,
>> +			      unsigned long parent_rate)
>> +{
>> +	return 0;
>> +};
>> +
>> +static int clk_dummy_determine_rate(struct clk_hw *hw,
>> +				    struct clk_rate_request *req)
>> +{
>> +	return 0;
>> +};
>> +
>> +static unsigned long clk_dummy_recalc_rate(struct clk_hw *hw,
>> +					   unsigned long parent_rate)
>> +{
>> +	return parent_rate;
>> +};
>> +
>> +static const struct clk_ops clk_dummy_ops = {
>> +	.is_enabled = clk_dummy_is_enabled,
>> +	.enable = clk_dummy_enable,
>> +	.disable = clk_dummy_disable,
>> +	.get_parent = clk_dummy_get_parent,
>> +	.set_parent = clk_dummy_set_parent,
>> +	.set_rate = clk_dummy_set_rate,
>> +	.recalc_rate = clk_dummy_recalc_rate,
>> +	.determine_rate = clk_dummy_determine_rate,
>> +};
>> +
>> +#define DEFINE_DUMMY_CLK(clk_name)				\
>> +(&(struct clk_regmap) {						\
>> +	.hw.init = &(struct clk_init_data) {			\
>> +		.name = #clk_name,				\
>> +		.parent_names = (const char *[]) { "xo"},	\
>> +		.num_parents = 1,				\
>> +		.ops = &clk_dummy_ops,				\
>> +	},							\
>> +})
> Definitely a big no.
Sure, will drop
> 
>> +
>> +static struct clk_regmap *gcc_ipq9574_clks[] = {
>> +	[GPLL0_MAIN] = &gpll0_main.clkr,
>> +	[GPLL0] = &gpll0.clkr,
>> +	[GPLL4_MAIN] = &gpll4_main.clkr,
>> +	[GPLL4] = &gpll4.clkr,
>> +	[GPLL2_MAIN] = &gpll2_main.clkr,
>> +	[GPLL2] = &gpll2.clkr,
>> +	[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,
>> +	[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,
>> +	[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,
>> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
>> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
>> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
>> +	[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
>> +	[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
>> +	[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
>> +	[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
>> +	[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
>> +	[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
>> +	[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,
>> +	[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,
>> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
>> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
>> +	[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
>> +	[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
>> +	[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
>> +	[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
>> +	[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
>> +	[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
>> +	[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,
>> +	[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,
>> +	[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,
>> +	[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,
>> +	[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,
>> +	[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,
>> +	[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,
>> +	[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,
>> +	[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,
>> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,
>> +	[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,
>> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,
>> +	[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,
>> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,
>> +	[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,
>> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,
>> +	[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,
>> +	[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,
>> +	[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,
>> +	[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,
>> +	[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,
>> +	[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,
>> +	[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,
>> +	[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,
>> +	[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,
>> +	[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,
>> +	[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,
>> +	[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
>> +	[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,
>> +	[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,
>> +	[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,
>> +	[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,
>> +	[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,
>> +	[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,
>> +	[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,
>> +	[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,
>> +	[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,
>> +	[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,
>> +	[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,
>> +	[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,
>> +	[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,
>> +	[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,
>> +	[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,
>> +	[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,
>> +	[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,
>> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,
>> +	[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,
>> +	[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,
>> +	[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,
>> +	[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
>> +	[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
>> +	[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,
>> +	[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,
>> +	[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
>> +	[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,
>> +	[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,
>> +	[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,
>> +	[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,
>> +	[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,
>> +	[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,
>> +	[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,
>> +	[GCC_SNOC_PCNOC_AHB_CLK] = &gcc_snoc_pcnoc_ahb_clk.clkr,
>> +	[GCC_ANOC_PCNOC_AHB_CLK] = &gcc_anoc_pcnoc_ahb_clk.clkr,
>> +	[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,
>> +	[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,
>> +	[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
>> +	[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,
>> +	[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
>> +	[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,
>> +	[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,
>> +	[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,
>> +	[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,
>> +	[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,
>> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,
>> +	[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,
>> +	[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,
>> +	[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,
>> +	[GCC_SYS_NOC_AXI_CLK] = &gcc_sys_noc_axi_clk.clkr,
>> +	[GCC_ANOC0_AXI_CLK] = &gcc_anoc0_axi_clk.clkr,
>> +	[GCC_ANOC1_AXI_CLK] = &gcc_anoc1_axi_clk.clkr,
>> +	[GCC_ANOC0_TBU_CLK] = &gcc_anoc0_tbu_clk.clkr,
>> +	[GCC_ANOC1_TBU_CLK] = &gcc_anoc1_tbu_clk.clkr,
>> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = &gcc_mem_noc_snoc_axi_clk.clkr,
>> +	[GCC_IMEM_AXI_CLK] = &gcc_imem_axi_clk.clkr,
>> +	[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,
>> +	[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,
>> +	[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,
>> +	[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,
>> +	[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,
>> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,
>> +	[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,
>> +	[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,
>> +	[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
>> +	[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,
>> +	[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,
>> +	[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
>> +	[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,
>> +	[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,
>> +	[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,
>> +	[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,
>> +	[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,
>> +	[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,
>> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,
>> +	[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,
>> +	[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,
>> +	[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
>> +	[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,
>> +	[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,
>> +	[GCC_SNOC_TS_CLK] = &gcc_snoc_ts_clk.clkr,
>> +	[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,
>> +	[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,
>> +	[GCC_PCNOC_TS_CLK] = &gcc_pcnoc_ts_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,
>> +	[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,
>> +	[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,
>> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,
>> +	[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
>> +	[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,
>> +	[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,
>> +	[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,
>> +	[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,
>> +	[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,
>> +	[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,
>> +	[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,
>> +	[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,
>> +	[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,
>> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,
>> +	[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,
>> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,
>> +	[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,
>> +	[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,
>> +	[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,
>> +	[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,
>> +	[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
>> +	[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
>> +	[GP1_CLK_SRC] = &gp1_clk_src.clkr,
>> +	[GP2_CLK_SRC] = &gp2_clk_src.clkr,
>> +	[GP3_CLK_SRC] = &gp3_clk_src.clkr,
>> +	[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,
>> +	[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,
>> +	[GCC_XO_CLK] = &gcc_xo_clk.clkr,
>> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,
>> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,
>> +	[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,
>> +	[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,
>> +	[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,
>> +	[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,
>> +	[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,
>> +	[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,
>> +	[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,
>> +	[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,
>> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,
>> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,
>> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,
>> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,
>> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,
>> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,
>> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,
>> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,
>> +	[GCC_PCNOC_DCC_CLK] = &gcc_pcnoc_dcc_clk.clkr,
>> +};
>> +
>> +static struct clk_regmap *gcc_ipq9574_dummy_clks[] = {
>> +	[GPLL0_MAIN] = DEFINE_DUMMY_CLK(gpll0_main),
>> +	[GPLL0] = DEFINE_DUMMY_CLK(gpll0),
>> +	[GPLL4_MAIN] = DEFINE_DUMMY_CLK(gpll4_main),
>> +	[GPLL4] = DEFINE_DUMMY_CLK(gpll4),
>> +	[GPLL2_MAIN] = DEFINE_DUMMY_CLK(gpll2_main),
>> +	[GPLL2] = DEFINE_DUMMY_CLK(gpll2),
>> +	[GCC_SLEEP_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_sleep_clk_src),
>> +	[APSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(apss_ahb_clk_src),
>> +	[APSS_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(apss_axi_clk_src),
>> +	[BLSP1_QUP1_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_i2c_apps_clk_src),
>> +	[BLSP1_QUP1_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup1_spi_apps_clk_src),
>> +	[BLSP1_QUP2_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_i2c_apps_clk_src),
>> +	[BLSP1_QUP2_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup2_spi_apps_clk_src),
>> +	[BLSP1_QUP3_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_i2c_apps_clk_src),
>> +	[BLSP1_QUP3_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup3_spi_apps_clk_src),
>> +	[BLSP1_QUP4_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_i2c_apps_clk_src),
>> +	[BLSP1_QUP4_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup4_spi_apps_clk_src),
>> +	[BLSP1_QUP5_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_i2c_apps_clk_src),
>> +	[BLSP1_QUP5_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup5_spi_apps_clk_src),
>> +	[BLSP1_QUP6_I2C_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_i2c_apps_clk_src),
>> +	[BLSP1_QUP6_SPI_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_qup6_spi_apps_clk_src),
>> +	[BLSP1_UART1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart1_apps_clk_src),
>> +	[BLSP1_UART2_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart2_apps_clk_src),
>> +	[BLSP1_UART3_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart3_apps_clk_src),
>> +	[BLSP1_UART4_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart4_apps_clk_src),
>> +	[BLSP1_UART5_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart5_apps_clk_src),
>> +	[BLSP1_UART6_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(blsp1_uart6_apps_clk_src),
>> +	[GCC_APSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_apss_ahb_clk),
>> +	[GCC_APSS_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_apss_axi_clk),
>> +	[GCC_BLSP1_QUP1_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP1_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup1_spi_apps_clk),
>> +	[GCC_BLSP1_QUP2_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP2_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup2_spi_apps_clk),
>> +	[GCC_BLSP1_QUP3_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP3_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup3_spi_apps_clk),
>> +	[GCC_BLSP1_QUP4_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP4_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup4_spi_apps_clk),
>> +	[GCC_BLSP1_QUP5_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP5_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup5_spi_apps_clk),
>> +	[GCC_BLSP1_QUP6_I2C_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_i2c_apps_clk),
>> +	[GCC_BLSP1_QUP6_SPI_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_qup6_spi_apps_clk),
>> +	[GCC_BLSP1_UART1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart1_apps_clk),
>> +	[GCC_BLSP1_UART2_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart2_apps_clk),
>> +	[GCC_BLSP1_UART3_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart3_apps_clk),
>> +	[GCC_BLSP1_UART4_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart4_apps_clk),
>> +	[GCC_BLSP1_UART5_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart5_apps_clk),
>> +	[GCC_BLSP1_UART6_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_uart6_apps_clk),
>> +	[PCIE0_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_m_clk_src),
>> +	[GCC_PCIE0_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_m_clk),
>> +	[PCIE1_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_m_clk_src),
>> +	[GCC_PCIE1_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_m_clk),
>> +	[PCIE2_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_m_clk_src),
>> +	[GCC_PCIE2_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_m_clk),
>> +	[PCIE3_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_m_clk_src),
>> +	[GCC_PCIE3_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_m_clk),
>> +	[PCIE0_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_axi_s_clk_src),
>> +	[GCC_PCIE0_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_bridge_clk),
>> +	[GCC_PCIE0_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_axi_s_clk),
>> +	[PCIE1_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_axi_s_clk_src),
>> +	[GCC_PCIE1_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_bridge_clk),
>> +	[GCC_PCIE1_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_axi_s_clk),
>> +	[PCIE2_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_axi_s_clk_src),
>> +	[GCC_PCIE2_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_bridge_clk),
>> +	[GCC_PCIE2_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_axi_s_clk),
>> +	[PCIE3_AXI_S_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_axi_s_clk_src),
>> +	[GCC_PCIE3_AXI_S_BRIDGE_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_bridge_clk),
>> +	[GCC_PCIE3_AXI_S_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_axi_s_clk),
>> +	[PCIE0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_pipe_clk_src),
>> +	[PCIE1_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_pipe_clk_src),
>> +	[PCIE2_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_pipe_clk_src),
>> +	[PCIE3_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_pipe_clk_src),
>> +	[PCIE_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(pcie_aux_clk_src),
>> +	[GCC_PCIE0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_aux_clk),
>> +	[GCC_PCIE1_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_aux_clk),
>> +	[GCC_PCIE2_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_aux_clk),
>> +	[GCC_PCIE3_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_aux_clk),
>> +	[PCIE0_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie0_rchng_clk_src),
>> +	[GCC_PCIE0_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_rchng_clk),
>> +	[PCIE1_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie1_rchng_clk_src),
>> +	[GCC_PCIE1_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_rchng_clk),
>> +	[PCIE2_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie2_rchng_clk_src),
>> +	[GCC_PCIE2_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_rchng_clk),
>> +	[PCIE3_RCHNG_CLK_SRC] = DEFINE_DUMMY_CLK(pcie3_rchng_clk_src),
>> +	[GCC_PCIE3_RCHNG_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_rchng_clk),
>> +	[GCC_PCIE0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie0_ahb_clk),
>> +	[GCC_PCIE1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie1_ahb_clk),
>> +	[GCC_PCIE2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie2_ahb_clk),
>> +	[GCC_PCIE3_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_pcie3_ahb_clk),
>> +	[USB0_AUX_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_aux_clk_src),
>> +	[GCC_USB0_AUX_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_aux_clk),
>> +	[USB0_MASTER_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_master_clk_src),
>> +	[GCC_USB0_MASTER_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_master_clk),
>> +	[GCC_SNOC_USB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_usb_clk),
>> +	[GCC_ANOC_USB_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_usb_axi_clk),
>> +	[USB0_MOCK_UTMI_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_clk_src),
>> +	[USB0_MOCK_UTMI_DIV_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_mock_utmi_div_clk_src),
>> +	[GCC_USB0_MOCK_UTMI_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_mock_utmi_clk),
>> +	[USB0_PIPE_CLK_SRC] = DEFINE_DUMMY_CLK(usb0_pipe_clk_src),
>> +	[GCC_USB0_PHY_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_phy_cfg_ahb_clk),
>> +	[SDCC1_APPS_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_apps_clk_src),
>> +	[GCC_SDCC1_APPS_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_apps_clk),
>> +	[SDCC1_ICE_CORE_CLK_SRC] = DEFINE_DUMMY_CLK(sdcc1_ice_core_clk_src),
>> +	[GCC_SDCC1_ICE_CORE_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ice_core_clk),
>> +	[GCC_SDCC1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sdcc1_ahb_clk),
>> +	[PCNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(pcnoc_bfdcd_clk_src),
>> +	[GCC_NSSCFG_CLK] = DEFINE_DUMMY_CLK(gcc_nsscfg_clk),
>> +	[GCC_NSSNOC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_nsscc_clk),
>> +	[GCC_NSSCC_CLK] = DEFINE_DUMMY_CLK(gcc_nsscc_clk),
>> +	[GCC_NSSNOC_PCNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_pcnoc_1_clk),
>> +	[GCC_QDSS_DAP_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_ahb_clk),
>> +	[GCC_QDSS_CFG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_cfg_ahb_clk),
>> +	[GCC_SNOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcnoc_ahb_clk),
>> +	[GCC_ANOC_PCNOC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcnoc_ahb_clk),
>> +	[GCC_QPIC_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_ahb_clk),
>> +	[GCC_QPIC_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_clk),
>> +	[GCC_BLSP1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_blsp1_ahb_clk),
>> +	[GCC_MDIO_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_mdio_ahb_clk),
>> +	[GCC_PRNG_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_prng_ahb_clk),
>> +	[GCC_UNIPHY0_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_ahb_clk),
>> +	[GCC_UNIPHY1_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_ahb_clk),
>> +	[GCC_UNIPHY2_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_ahb_clk),
>> +	[GCC_CMN_12GPLL_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_ahb_clk),
>> +	[GCC_CMN_12GPLL_APU_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_apu_clk),
>> +	[SYSTEM_NOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(system_noc_bfdcd_clk_src),
>> +	[GCC_NSSNOC_SNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_clk),
>> +	[GCC_NSSNOC_SNOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_snoc_1_clk),
>> +	[GCC_QDSS_ETR_USB_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_etr_usb_clk),
>> +	[GCC_SYS_NOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_axi_clk),
>> +	[GCC_ANOC0_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_axi_clk),
>> +	[GCC_ANOC1_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_axi_clk),
>> +	[GCC_ANOC0_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc0_tbu_clk),
>> +	[GCC_ANOC1_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_anoc1_tbu_clk),
>> +	[GCC_MEM_NOC_SNOC_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_snoc_axi_clk),
>> +	[GCC_IMEM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_imem_axi_clk),
>> +	[WCSS_AHB_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_ahb_clk_src),
>> +	[GCC_Q6_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_clk),
>> +	[GCC_Q6_AHB_S_CLK] = DEFINE_DUMMY_CLK(gcc_q6_ahb_s_clk),
>> +	[GCC_WCSS_ECAHB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_ecahb_clk),
>> +	[GCC_WCSS_ACMT_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_acmt_clk),
>> +	[GCC_SYS_NOC_WCSS_AHB_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_wcss_ahb_clk),
>> +	[WCSS_AXI_M_CLK_SRC] = DEFINE_DUMMY_CLK(wcss_axi_m_clk_src),
>> +	[GCC_ANOC_WCSS_AXI_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_wcss_axi_m_clk),
>> +	[QDSS_AT_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_at_clk_src),
>> +	[GCC_Q6SS_ATBM_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_atbm_clk),
>> +	[GCC_WCSS_DBG_IFC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_atb_clk),
>> +	[GCC_NSSNOC_ATB_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_atb_clk),
>> +	[GCC_QDSS_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_at_clk),
>> +	[GCC_SYS_NOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_at_clk),
>> +	[GCC_PCNOC_AT_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_at_clk),
>> +	[GCC_USB0_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_usb0_eud_at_clk),
>> +	[GCC_QDSS_EUD_AT_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_eud_at_clk),
>> +	[QDSS_STM_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_stm_clk_src),
>> +	[GCC_QDSS_STM_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_stm_clk),
>> +	[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_sys_noc_qdss_stm_axi_clk),
>> +	[QDSS_TRACECLKIN_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_traceclkin_clk_src),
>> +	[GCC_QDSS_TRACECLKIN_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_traceclkin_clk),
>> +	[QDSS_TSCTR_CLK_SRC] = DEFINE_DUMMY_CLK(qdss_tsctr_clk_src),
>> +	[GCC_Q6_TSCTR_1TO2_CLK] = DEFINE_DUMMY_CLK(gcc_q6_tsctr_1to2_clk),
>> +	[GCC_WCSS_DBG_IFC_NTS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_nts_clk),
>> +	[GCC_QDSS_TSCTR_DIV2_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div2_clk),
>> +	[GCC_QDSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_ts_clk),
>> +	[GCC_SNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_ts_clk),
>> +	[GCC_MEM_NOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_ts_clk),
>> +	[GCC_QDSS_TSCTR_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div4_clk),
>> +	[GCC_NSS_TS_CLK] = DEFINE_DUMMY_CLK(gcc_nss_ts_clk),
>> +	[GCC_QDSS_TSCTR_DIV8_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div8_clk),
>> +	[GCC_PCNOC_TS_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_ts_clk),
>> +	[GCC_QDSS_TSCTR_DIV16_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div16_clk),
>> +	[GCC_Q6SS_PCLKDBG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_pclkdbg_clk),
>> +	[GCC_Q6SS_TRIG_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_trig_clk),
>> +	[GCC_WCSS_DBG_IFC_APB_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_apb_clk),
>> +	[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_dbg_ifc_dapbus_clk),
>> +	[GCC_QDSS_DAP_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_dap_clk),
>> +	[GCC_QDSS_APB2JTAG_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_apb2jtag_clk),
>> +	[GCC_QDSS_TSCTR_DIV3_CLK] = DEFINE_DUMMY_CLK(gcc_qdss_tsctr_div3_clk),
>> +	[QPIC_IO_MACRO_CLK_SRC] = DEFINE_DUMMY_CLK(qpic_io_macro_clk_src),
>> +	[GCC_QPIC_IO_MACRO_CLK] = DEFINE_DUMMY_CLK(gcc_qpic_io_macro_clk),
>> +	[Q6_AXI_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axi_clk_src),
>> +	[GCC_Q6_AXIM_CLK] = DEFINE_DUMMY_CLK(gcc_q6_axim_clk),
>> +	[GCC_WCSS_Q6_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_wcss_q6_tbu_clk),
>> +	[GCC_MEM_NOC_Q6_AXI_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_q6_axi_clk),
>> +	[Q6_AXIM2_CLK_SRC] = DEFINE_DUMMY_CLK(q6_axim2_clk_src),
>> +	[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = DEFINE_DUMMY_CLK(nssnoc_memnoc_bfdcd_clk_src),
>> +	[GCC_NSSNOC_MEMNOC_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_memnoc_clk),
>> +	[GCC_NSSNOC_MEM_NOC_1_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_mem_noc_1_clk),
>> +	[GCC_NSS_TBU_CLK] = DEFINE_DUMMY_CLK(gcc_nss_tbu_clk),
>> +	[GCC_MEM_NOC_NSSNOC_CLK] = DEFINE_DUMMY_CLK(gcc_mem_noc_nssnoc_clk),
>> +	[LPASS_AXIM_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_axim_clk_src),
>> +	[LPASS_SWAY_CLK_SRC] = DEFINE_DUMMY_CLK(lpass_sway_clk_src),
>> +	[ADSS_PWM_CLK_SRC] = DEFINE_DUMMY_CLK(adss_pwm_clk_src),
>> +	[GCC_ADSS_PWM_CLK] = DEFINE_DUMMY_CLK(gcc_adss_pwm_clk),
>> +	[GP1_CLK_SRC] = DEFINE_DUMMY_CLK(gp1_clk_src),
>> +	[GP2_CLK_SRC] = DEFINE_DUMMY_CLK(gp2_clk_src),
>> +	[GP3_CLK_SRC] = DEFINE_DUMMY_CLK(gp3_clk_src),
>> +	[DDRSS_SMS_SLOW_CLK_SRC] = DEFINE_DUMMY_CLK(ddrss_sms_slow_clk_src),
>> +	[GCC_XO_CLK_SRC] = DEFINE_DUMMY_CLK(gcc_xo_clk_src),
>> +	[GCC_NSSNOC_XO_DCD_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_xo_dcd_clk),
>> +	[GCC_XO_CLK] = DEFINE_DUMMY_CLK(gcc_xo_clk),
>> +	[GCC_NSSNOC_QOSGEN_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_qosgen_ref_clk),
>> +	[GCC_NSSNOC_TIMEOUT_REF_CLK] = DEFINE_DUMMY_CLK(gcc_nssnoc_timeout_ref_clk),
>> +	[GCC_XO_DIV4_CLK] = DEFINE_DUMMY_CLK(gcc_xo_div4_clk),
>> +	[GCC_UNIPHY0_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy0_sys_clk),
>> +	[GCC_UNIPHY1_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy1_sys_clk),
>> +	[GCC_UNIPHY2_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_uniphy2_sys_clk),
>> +	[GCC_CMN_12GPLL_SYS_CLK] = DEFINE_DUMMY_CLK(gcc_cmn_12gpll_sys_clk),
>> +	[GCC_Q6SS_BOOT_CLK] = DEFINE_DUMMY_CLK(gcc_q6ss_boot_clk),
>> +	[UNIPHY_SYS_CLK_SRC] = DEFINE_DUMMY_CLK(uniphy_sys_clk_src),
>> +	[NSS_TS_CLK_SRC] = DEFINE_DUMMY_CLK(nss_ts_clk_src),
>> +	[GCC_ANOC_PCIE0_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie0_1lane_m_clk),
>> +	[GCC_ANOC_PCIE1_1LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie1_1lane_m_clk),
>> +	[GCC_ANOC_PCIE2_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie2_2lane_m_clk),
>> +	[GCC_ANOC_PCIE3_2LANE_M_CLK] = DEFINE_DUMMY_CLK(gcc_anoc_pcie3_2lane_m_clk),
>> +	[GCC_SNOC_PCIE0_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie0_1lane_s_clk),
>> +	[GCC_SNOC_PCIE1_1LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie1_1lane_s_clk),
>> +	[GCC_SNOC_PCIE2_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie2_2lane_s_clk),
>> +	[GCC_SNOC_PCIE3_2LANE_S_CLK] = DEFINE_DUMMY_CLK(gcc_snoc_pcie3_2lane_s_clk),
>> +	[GCC_PCNOC_DCC_CLK] = DEFINE_DUMMY_CLK(gcc_pcnoc_dcc_clk),
>> +};
> Drop.
Okay
> 
>> +
>> +static const struct qcom_reset_map gcc_ipq9574_resets[] = {
>> +	[GCC_ADSS_BCR] = { 0x1c000, 0 },
>> +	[GCC_ANOC0_TBU_BCR] = { 0x1203C, 0 },
>> +	[GCC_ANOC1_TBU_BCR] = { 0x1204C, 0 },
>> +	[GCC_ANOC_BCR] = { 0x2E074, 0 },
>> +	[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },
>> +	[GCC_APSS_TCU_BCR] = { 0x12014, 0 },
>> +	[GCC_BLSP1_BCR] = { 0x01000, 0 },
>> +	[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },
>> +	[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },
>> +	[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },
>> +	[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },
>> +	[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },
>> +	[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },
>> +	[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },
>> +	[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },
>> +	[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },
>> +	[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },
>> +	[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },
>> +	[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },
>> +	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
>> +	[GCC_CMN_BLK_BCR] = { 0x3A000, 0 },
>> +	[GCC_CMN_BLK_AHB_ARES] = { 0x3A010, 0 },
>> +	[GCC_CMN_BLK_SYS_ARES] = { 0x3A010, 1 },
>> +	[GCC_CMN_BLK_APU_ARES] = { 0x3A010, 2 },
>> +	[GCC_DCC_BCR] = { 0x35000, 0 },
>> +	[GCC_DDRSS_BCR] = { 0x11000, 0 },
>> +	[GCC_IMEM_BCR] = { 0x0e000, 0 },
>> +	[GCC_LPASS_BCR] = { 0x27000, 0 },
>> +	[GCC_MDIO_BCR] = { 0x1703c, 0 },
>> +	[GCC_MPM_BCR] = { 0x37000, 0 },
>> +	[GCC_MSG_RAM_BCR] = { 0x26000, 0 },
>> +	[GCC_NSS_BCR] = { 0x17000, 0 },
>> +	[GCC_NSS_TBU_BCR] = { 0x12044, 0 },
>> +	[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },
>> +	[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },
>> +	[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },
>> +	[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },
>> +	[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },
>> +	[GCC_NSSCC_ARES] = { 0x17038, 8 },
>> +	[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },
>> +	[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },
>> +	[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },
>> +	[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },
>> +	[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },
>> +	[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },
>> +	[GCC_NSS_CFG_ARES] = { 0x17038, 1 },
>> +	[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },
>> +	[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },
>> +	[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },
>> +	[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },
>> +	[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },
>> +	[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },
>> +	[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },
>> +	[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },
>> +	[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },
>> +	[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },
>> +	[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },
>> +	[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },
>> +	[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },
>> +	[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },
>> +	[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },
>> +	[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },
>> +	[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },
>> +	[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },
>> +	[GCC_PCIE2_AHB_ARES] = { 0x2A058, 7 },
>> +	[GCC_PCIE2_AUX_ARES] = { 0x2A058, 6 },
>> +	[GCC_PCIE2_AXI_M_ARES] = { 0x2A058, 5 },
>> +	[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2A058, 4 },
>> +	[GCC_PCIE2_AXI_S_ARES] = { 0x2A058, 3 },
>> +	[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2A058, 2 },
>> +	[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2A058, 1 },
>> +	[GCC_PCIE2_PIPE_ARES] = { 0x2A058, 0 },
>> +	[GCC_PCIE3_AHB_ARES] = { 0x2B058, 7 },
>> +	[GCC_PCIE3_AUX_ARES] = { 0x2B058, 6 },
>> +	[GCC_PCIE3_AXI_M_ARES] = { 0x2B058, 5 },
>> +	[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2B058, 4 },
>> +	[GCC_PCIE3_AXI_S_ARES] = { 0x2B058, 3 },
>> +	[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2B058, 2 },
>> +	[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2B058, 1 },
>> +	[GCC_PCIE3_PIPE_ARES] = { 0x2B058, 0 },
>> +	[GCC_PCIE0_BCR] = { 0x28000, 0 },
>> +	[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },
>> +	[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },
>> +	[GCC_PCIE1_BCR] = { 0x29000, 0 },
>> +	[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },
>> +	[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },
>> +	[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },
>> +	[GCC_PCIE2_BCR] = { 0x2a000, 0 },
>> +	[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },
>> +	[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },
>> +	[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },
>> +	[GCC_PCIE3_BCR] = { 0x2b000, 0 },
>> +	[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },
>> +	[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },
>> +	[GCC_PCIE3_PHY_BCR] = { 0x2B060, 0 },
>> +	[GCC_PCNOC_BCR] = { 0x31000, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },
>> +	[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },
>> +	[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },
>> +	[GCC_PRNG_BCR] = { 0x13020, 0 },
>> +	[GCC_Q6SS_DBG_ARES] = { 0x2506C, 4 },
>> +	[GCC_Q6_AHB_ARES] = { 0x2506C, 3 },
>> +	[GCC_Q6_AHB_S_ARES] = { 0x2506C, 2 },
>> +	[GCC_Q6_AXIM2_ARES] = { 0x2506C, 1 },
>> +	[GCC_Q6_AXIM_ARES] = { 0x2506C, 0 },
>> +	[GCC_QDSS_BCR] = { 0x2d000, 0 },
>> +	[GCC_QPIC_BCR] = { 0x32000, 0 },
>> +	[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },
>> +	[GCC_QPIC_ARES] = { 0x3201c, 0 },
>> +	[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },
>> +	[GCC_RBCPR_BCR] = { 0x39000, 0 },
>> +	[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },
>> +	[GCC_SDCC_BCR] = { 0x33000, 0 },
>> +	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
>> +	[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },
>> +	[GCC_SNOC_BCR] = { 0x2E000, 0 },
>> +	[GCC_SPDM_BCR] = { 0x36000, 0 },
>> +	[GCC_TCSR_BCR] = { 0x3d000, 0 },
>> +	[GCC_TLMM_BCR] = { 0x3e000, 0 },
>> +	[GCC_TME_BCR] = { 0x10000, 0 },
>> +	[GCC_UNIPHY0_BCR] = { 0x17044, 0 },
>> +	[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },
>> +	[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },
>> +	[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },
>> +	[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },
>> +	[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },
>> +	[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },
>> +	[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },
>> +	[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },
>> +	[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },
>> +	[GCC_UNIPHY1_BCR] = { 0x17054, 0 },
>> +	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
>> +	[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },
>> +	[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },
>> +	[GCC_USB_BCR] = { 0x2c000, 0 },
>> +	[GCC_USB_MISC_RESET] = { 0x2c064, 0 },
>> +	[GCC_WCSSAON_RESET] = { 0x25074, 0 },
>> +	[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },
>> +	[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },
>> +	[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },
>> +	[GCC_WCSS_BCR] = { 0x18004, 0 },
>> +	[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },
>> +	[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },
>> +	[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },
>> +	[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },
>> +	[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },
>> +};
>> +
>> +static const struct of_device_id gcc_ipq9574_match_table[] = {
>> +	{ .compatible = "qcom,gcc-ipq9574" },
>> +	{ }
>> +};
>> +MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);
>> +
>> +static const struct regmap_config gcc_ipq9574_regmap_config = {
>> +	.reg_bits       = 32,
>> +	.reg_stride     = 4,
>> +	.val_bits       = 32,
>> +	.max_register   = 0x7fffc,
>> +	.fast_io	= true,
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_ipq9574_desc = {
>> +	.config = &gcc_ipq9574_regmap_config,
>> +	.clks = gcc_ipq9574_clks,
>> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),
>> +	.resets = gcc_ipq9574_resets,
>> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
>> +	.clk_hws = gcc_ipq9574_hws,
>> +	.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),
>> +};
>> +
>> +static const struct qcom_cc_desc gcc_ipq9574_dummy_desc = {
>> +	.config = &gcc_ipq9574_regmap_config,
>> +	.clks = gcc_ipq9574_dummy_clks,
>> +	.num_clks = ARRAY_SIZE(gcc_ipq9574_dummy_clks),
>> +	.resets = gcc_ipq9574_resets,
>> +	.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),
>> +};
>> +
>> +static int gcc_ipq9574_probe(struct platform_device *pdev)
>> +{
>> +	struct regmap *regmap;
>> +	struct qcom_cc_desc ipq9574_desc = gcc_ipq9574_desc;
>> +	struct device_node *np = (&pdev->dev)->of_node;
>> +
>> +	if (of_property_read_bool(np, "gcc-use-dummy"))
>> +		ipq9574_desc = gcc_ipq9574_dummy_desc;
>> +
>> +	regmap = qcom_cc_map(pdev, &ipq9574_desc);
>> +	if (IS_ERR(regmap))
>> +		return PTR_ERR(regmap);
>> +
>> +	return qcom_cc_really_probe(pdev, &ipq9574_desc, regmap);
>> +}
>> +
>> +static int gcc_ipq9574_remove(struct platform_device *pdev)
> Generally you shouldn't remove the driver that ensures your platform
> well, works..
> 
> Plus GCCs are always =y in mainline to make sure dependencies are met
> so there's no removing.
Okay, understood!
> 
>> +{
>> +	return 0;
>> +}
>> +
>> +static struct platform_driver gcc_ipq9574_driver = {
>> +	.probe = gcc_ipq9574_probe,
>> +	.remove = gcc_ipq9574_remove,
>> +	.driver = {
>> +		.name   = "qcom,gcc-ipq9574",
>> +		.of_match_table = gcc_ipq9574_match_table,
>> +	},
>> +};
>> +
>> +static int __init gcc_ipq9574_init(void)
>> +{
>> +	return platform_driver_register(&gcc_ipq9574_driver);
>> +}
>> +core_initcall(gcc_ipq9574_init);
>> +
>> +static void __exit gcc_ipq9574_exit(void)
>> +{
>> +	platform_driver_unregister(&gcc_ipq9574_driver);
>> +}
>> +module_exit(gcc_ipq9574_exit);
>> +
>> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ9574 Driver");
>> +MODULE_LICENSE("GPL");

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Konrad Dybcio]

On 13.01.2023 14:21, Devi Priya wrote:
> 
> 
> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>
>>
>> On 10.01.2023 13:13, devi priya wrote:
>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>> ---
[...]

>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>> +    .halt_reg = 0x07024,
>>> +    .clkr = {
>>> +        .enable_reg = 0x07024,
>>> +        .enable_mask = BIT(0),
>>> +        .hw.init = &(struct clk_init_data) {
>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>> +            .parent_hws = (const struct clk_hw *[]) {
>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>> +            .num_parents = 1,
>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> Sounds very much like a hack..
> Got it, will remove the clock entry as it is not being used in linux
I'm not sure removing it is the best option, somebody might have a
funky board where they use this particular QUP for I2C for whatever
reason and then the clock would have to be re-added..

Thanks for addressing all of the review comments so thoroughly!

Konrad

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Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Konrad Dybcio]

On 13.01.2023 14:21, Devi Priya wrote:
> 
> 
> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>
>>
>> On 10.01.2023 13:13, devi priya wrote:
>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>> ---
[...]

>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>> +    .halt_reg = 0x07024,
>>> +    .clkr = {
>>> +        .enable_reg = 0x07024,
>>> +        .enable_mask = BIT(0),
>>> +        .hw.init = &(struct clk_init_data) {
>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>> +            .parent_hws = (const struct clk_hw *[]) {
>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>> +            .num_parents = 1,
>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>> Sounds very much like a hack..
> Got it, will remove the clock entry as it is not being used in linux
I'm not sure removing it is the best option, somebody might have a
funky board where they use this particular QUP for I2C for whatever
reason and then the clock would have to be re-added..

Thanks for addressing all of the review comments so thoroughly!

Konrad

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Devi Priya]

On 1/13/2023 7:39 PM, Konrad Dybcio wrote:
> 
> 
> On 13.01.2023 14:21, Devi Priya wrote:
>>
>>
>> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 10.01.2023 13:13, devi priya wrote:
>>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>>
>>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>>> ---
> [...]
> 
>>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>>> +    .halt_reg = 0x07024,
>>>> +    .clkr = {
>>>> +        .enable_reg = 0x07024,
>>>> +        .enable_mask = BIT(0),
>>>> +        .hw.init = &(struct clk_init_data) {
>>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>>> +            .parent_hws = (const struct clk_hw *[]) {
>>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>>> +            .num_parents = 1,
>>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>> Sounds very much like a hack..
>> Got it, will remove the clock entry as it is not being used in linux
> I'm not sure removing it is the best option, somebody might have a
> funky board where they use this particular QUP for I2C for whatever
> reason and then the clock would have to be re-added..
Sure, Understood
This clock is used by the RPM component to communicate with PMIC and we
would add the critical flag here

> Thanks for addressing all of the review comments so thoroughly!
> 
> Konrad

Best Regards,
Devi Priya

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Devi Priya]

On 1/13/2023 7:39 PM, Konrad Dybcio wrote:
> 
> 
> On 13.01.2023 14:21, Devi Priya wrote:
>>
>>
>> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 10.01.2023 13:13, devi priya wrote:
>>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>>
>>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>>> ---
> [...]
> 
>>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>>> +    .halt_reg = 0x07024,
>>>> +    .clkr = {
>>>> +        .enable_reg = 0x07024,
>>>> +        .enable_mask = BIT(0),
>>>> +        .hw.init = &(struct clk_init_data) {
>>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>>> +            .parent_hws = (const struct clk_hw *[]) {
>>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>>> +            .num_parents = 1,
>>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>> Sounds very much like a hack..
>> Got it, will remove the clock entry as it is not being used in linux
> I'm not sure removing it is the best option, somebody might have a
> funky board where they use this particular QUP for I2C for whatever
> reason and then the clock would have to be re-added..
Sure, Understood
This clock is used by the RPM component to communicate with PMIC and we
would add the critical flag here

> Thanks for addressing all of the review comments so thoroughly!
> 
> Konrad

Best Regards,
Devi Priya

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Konrad Dybcio]

On 24.01.2023 08:27, Devi Priya wrote:
> 
> 
> On 1/13/2023 7:39 PM, Konrad Dybcio wrote:
>>
>>
>> On 13.01.2023 14:21, Devi Priya wrote:
>>>
>>>
>>> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>>>
>>>>
>>>> On 10.01.2023 13:13, devi priya wrote:
>>>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>>>
>>>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>>>> ---
>> [...]
>>
>>>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>>>> +    .halt_reg = 0x07024,
>>>>> +    .clkr = {
>>>>> +        .enable_reg = 0x07024,
>>>>> +        .enable_mask = BIT(0),
>>>>> +        .hw.init = &(struct clk_init_data) {
>>>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>>>> +            .parent_hws = (const struct clk_hw *[]) {
>>>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>>>> +            .num_parents = 1,
>>>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>>> Sounds very much like a hack..
>>> Got it, will remove the clock entry as it is not being used in linux
>> I'm not sure removing it is the best option, somebody might have a
>> funky board where they use this particular QUP for I2C for whatever
>> reason and then the clock would have to be re-added..
> Sure, Understood
> This clock is used by the RPM component to communicate with PMIC and we
> would add the critical flag here
Okay, so this SoC is intended to ship with some RPM PMICs and
*always* with an I2C companion that's required for some basic
functionality, correct?

Otherwise, if it's just for wifi/multimedia/etc (like PM8008ij
on some newer devices), you should not make it critical and
simply rely on Linux keeping it alive like so:

consumer takes a regulator
the regulator does not go to sleep because it's consumed
the PMIC is active because a regulator on it is being used
the I2C bus is active because its child PMIC is used
the I2C clocks are alive because there's an active user

Konrad
> 
>> Thanks for addressing all of the review comments so thoroughly!
>>
>> Konrad
> 
> Best Regards,
> Devi Priya

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Konrad Dybcio]

On 24.01.2023 08:27, Devi Priya wrote:
> 
> 
> On 1/13/2023 7:39 PM, Konrad Dybcio wrote:
>>
>>
>> On 13.01.2023 14:21, Devi Priya wrote:
>>>
>>>
>>> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>>>
>>>>
>>>> On 10.01.2023 13:13, devi priya wrote:
>>>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>>>
>>>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>>>> ---
>> [...]
>>
>>>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>>>> +    .halt_reg = 0x07024,
>>>>> +    .clkr = {
>>>>> +        .enable_reg = 0x07024,
>>>>> +        .enable_mask = BIT(0),
>>>>> +        .hw.init = &(struct clk_init_data) {
>>>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>>>> +            .parent_hws = (const struct clk_hw *[]) {
>>>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>>>> +            .num_parents = 1,
>>>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>>> Sounds very much like a hack..
>>> Got it, will remove the clock entry as it is not being used in linux
>> I'm not sure removing it is the best option, somebody might have a
>> funky board where they use this particular QUP for I2C for whatever
>> reason and then the clock would have to be re-added..
> Sure, Understood
> This clock is used by the RPM component to communicate with PMIC and we
> would add the critical flag here
Okay, so this SoC is intended to ship with some RPM PMICs and
*always* with an I2C companion that's required for some basic
functionality, correct?

Otherwise, if it's just for wifi/multimedia/etc (like PM8008ij
on some newer devices), you should not make it critical and
simply rely on Linux keeping it alive like so:

consumer takes a regulator
the regulator does not go to sleep because it's consumed
the PMIC is active because a regulator on it is being used
the I2C bus is active because its child PMIC is used
the I2C clocks are alive because there's an active user

Konrad
> 
>> Thanks for addressing all of the review comments so thoroughly!
>>
>> Konrad
> 
> Best Regards,
> Devi Priya

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Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Devi Priya]

On 1/24/2023 3:23 PM, Konrad Dybcio wrote:
> 
> 
> On 24.01.2023 08:27, Devi Priya wrote:
>>
>>
>> On 1/13/2023 7:39 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 13.01.2023 14:21, Devi Priya wrote:
>>>>
>>>>
>>>> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>>>>
>>>>>
>>>>> On 10.01.2023 13:13, devi priya wrote:
>>>>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>>>>
>>>>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>>>>> ---
>>> [...]
>>>
>>>>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>>>>> +    .halt_reg = 0x07024,
>>>>>> +    .clkr = {
>>>>>> +        .enable_reg = 0x07024,
>>>>>> +        .enable_mask = BIT(0),
>>>>>> +        .hw.init = &(struct clk_init_data) {
>>>>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>>>>> +            .parent_hws = (const struct clk_hw *[]) {
>>>>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>>>>> +            .num_parents = 1,
>>>>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>>>> Sounds very much like a hack..
>>>> Got it, will remove the clock entry as it is not being used in linux
>>> I'm not sure removing it is the best option, somebody might have a
>>> funky board where they use this particular QUP for I2C for whatever
>>> reason and then the clock would have to be re-added..
>> Sure, Understood
>> This clock is used by the RPM component to communicate with PMIC and we
>> would add the critical flag here
> Okay, so this SoC is intended to ship with some RPM PMICs and
> *always* with an I2C companion that's required for some basic
> functionality, correct?
> 
> Otherwise, if it's just for wifi/multimedia/etc (like PM8008ij
> on some newer devices), you should not make it critical and
> simply rely on Linux keeping it alive like so:
> 
> consumer takes a regulator
> the regulator does not go to sleep because it's consumed
> the PMIC is active because a regulator on it is being used
> the I2C bus is active because its child PMIC is used
> the I2C clocks are alive because there's an active user
> 
Yes correct, the SoC would always have an I2C companion
> Konrad
>>
>>> Thanks for addressing all of the review comments so thoroughly!
>>>
>>> Konrad
>>
>> Best Regards,
>> Devi Priya

Re: [PATCH 2/7] clk: qcom: Add Global Clock Controller driver for IPQ9574

[Devi Priya]

On 1/24/2023 3:23 PM, Konrad Dybcio wrote:
> 
> 
> On 24.01.2023 08:27, Devi Priya wrote:
>>
>>
>> On 1/13/2023 7:39 PM, Konrad Dybcio wrote:
>>>
>>>
>>> On 13.01.2023 14:21, Devi Priya wrote:
>>>>
>>>>
>>>> On 1/10/2023 6:07 PM, Konrad Dybcio wrote:
>>>>>
>>>>>
>>>>> On 10.01.2023 13:13, devi priya wrote:
>>>>>> Add Global Clock Controller (GCC) driver for ipq9574 based devices
>>>>>>
>>>>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>>>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>>>>> ---
>>> [...]
>>>
>>>>>> +static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
>>>>>> +    .halt_reg = 0x07024,
>>>>>> +    .clkr = {
>>>>>> +        .enable_reg = 0x07024,
>>>>>> +        .enable_mask = BIT(0),
>>>>>> +        .hw.init = &(struct clk_init_data) {
>>>>>> +            .name = "gcc_blsp1_qup6_i2c_apps_clk",
>>>>>> +            .parent_hws = (const struct clk_hw *[]) {
>>>>>> +                    &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
>>>>>> +            .num_parents = 1,
>>>>>> +            .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
>>>>> Sounds very much like a hack..
>>>> Got it, will remove the clock entry as it is not being used in linux
>>> I'm not sure removing it is the best option, somebody might have a
>>> funky board where they use this particular QUP for I2C for whatever
>>> reason and then the clock would have to be re-added..
>> Sure, Understood
>> This clock is used by the RPM component to communicate with PMIC and we
>> would add the critical flag here
> Okay, so this SoC is intended to ship with some RPM PMICs and
> *always* with an I2C companion that's required for some basic
> functionality, correct?
> 
> Otherwise, if it's just for wifi/multimedia/etc (like PM8008ij
> on some newer devices), you should not make it critical and
> simply rely on Linux keeping it alive like so:
> 
> consumer takes a regulator
> the regulator does not go to sleep because it's consumed
> the PMIC is active because a regulator on it is being used
> the I2C bus is active because its child PMIC is used
> the I2C clocks are alive because there's an active user
> 
Yes correct, the SoC would always have an I2C companion
> Konrad
>>
>>> Thanks for addressing all of the review comments so thoroughly!
>>>
>>> Konrad
>>
>> Best Regards,
>> Devi Priya

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[PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[devi priya]

Add device tree binding documentation details for ipq9574
pinctrl driver

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   | 129 ++++++++++++++++++
 1 file changed, 129 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
new file mode 100644
index 000000000000..f9cb457bc18d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
+
+maintainers:
+  - Anusha <quic_anusha@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  IPQ9574 platform.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,ipq9574-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  "#interrupt-cells": true
+  gpio-controller: true
+  gpio-reserved-ranges: true
+  "#gpio-cells": true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-ipq9574-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-ipq9574-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
+            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
+                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
+                      qdsd_data3 ]
+        minItems: 1
+        maxItems: 8
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+        enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+                audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
+                blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
+                blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
+                blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
+                cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
+                gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
+                mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
+                pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
+                prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
+                pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
+                pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
+                pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
+                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
+                dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
+                rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
+                wci20, wci21, wsa_swrm, audio_pdm0 ]
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    tlmm: pinctrl@1000000 {
+        compatible = "qcom,ipq9574-tlmm";
+        reg = <0x01000000 0x300000>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 65>;
+
+        uart2-state {
+                pins = "gpio34", "gpio35";
+                function = "blsp2_uart";
+                drive-strength = <8>;
+                bias-pull-down;
+        };
+    };
-- 
2.17.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[devi priya]

Add device tree binding documentation details for ipq9574
pinctrl driver

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   | 129 ++++++++++++++++++
 1 file changed, 129 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml

diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
new file mode 100644
index 000000000000..f9cb457bc18d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
+
+maintainers:
+  - Anusha <quic_anusha@quicinc.com>
+
+description: |
+  This binding describes the Top Level Mode Multiplexer block found in the
+  IPQ9574 platform.
+
+allOf:
+  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
+
+properties:
+  compatible:
+    const: qcom,ipq9574-tlmm
+
+  reg:
+    maxItems: 1
+
+  interrupts: true
+  interrupt-controller: true
+  "#interrupt-cells": true
+  gpio-controller: true
+  gpio-reserved-ranges: true
+  "#gpio-cells": true
+  gpio-ranges: true
+  wakeup-parent: true
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+patternProperties:
+  "-state$":
+    oneOf:
+      - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
+      - patternProperties:
+          "-pins$":
+            $ref: "#/$defs/qcom-ipq9574-tlmm-state"
+        additionalProperties: false
+
+$defs:
+  qcom-ipq9574-tlmm-state:
+    type: object
+    description:
+      Pinctrl node's client devices use subnodes for desired pin configuration.
+      Client device subnodes use below standard properties.
+    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
+
+    properties:
+      pins:
+        description:
+          List of gpio pins affected by the properties specified in this
+          subnode.
+        items:
+          oneOf:
+            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
+            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
+                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
+                      qdsd_data3 ]
+        minItems: 1
+        maxItems: 8
+
+      function:
+        description:
+          Specify the alternative function to be configured for the specified
+          pins.
+
+        enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
+                audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
+                blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
+                blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
+                blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
+                cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
+                gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
+                mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
+                pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
+                prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
+                pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
+                pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
+                pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
+                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
+                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
+                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
+                dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
+                rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
+                wci20, wci21, wsa_swrm, audio_pdm0 ]
+
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+      input-enable: true
+      output-high: true
+      output-low: true
+
+    required:
+      - pins
+
+    additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    tlmm: pinctrl@1000000 {
+        compatible = "qcom,ipq9574-tlmm";
+        reg = <0x01000000 0x300000>;
+        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+        gpio-controller;
+        #gpio-cells = <2>;
+        interrupt-controller;
+        #interrupt-cells = <2>;
+        gpio-ranges = <&tlmm 0 0 65>;
+
+        uart2-state {
+                pins = "gpio34", "gpio35";
+                function = "blsp2_uart";
+                drive-strength = <8>;
+                bias-pull-down;
+        };
+    };
-- 
2.17.1

Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Add device tree binding documentation details for ipq9574
> pinctrl driver
> 

Subject: drop second/last, redundant "bindings". The "dt-bindings"
prefix is already stating that these are bindings.

> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   | 129 ++++++++++++++++++
>  1 file changed, 129 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
> new file mode 100644
> index 000000000000..f9cb457bc18d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
> +
> +maintainers:
> +  - Anusha <quic_anusha@quicinc.com>
> +
> +description: |
> +  This binding describes the Top Level Mode Multiplexer block found in the
> +  IPQ9574 platform.

No, please rebase on recent changes. You started your work on some old
bindings so your binding likely includes all issues we fixed.

> +
> +allOf:
> +  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: qcom,ipq9574-tlmm
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts: true
> +  interrupt-controller: true
> +  "#interrupt-cells": true
> +  gpio-controller: true
> +  gpio-reserved-ranges: true
> +  "#gpio-cells": true
> +  gpio-ranges: true
> +  wakeup-parent: true

Missing gpio-line-names and constraints for ranges. Look at other bindings.

> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +patternProperties:
> +  "-state$":
> +    oneOf:
> +      - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
> +      - patternProperties:
> +          "-pins$":
> +            $ref: "#/$defs/qcom-ipq9574-tlmm-state"
> +        additionalProperties: false
> +
> +$defs:
> +  qcom-ipq9574-tlmm-state:
> +    type: object
> +    description:
> +      Pinctrl node's client devices use subnodes for desired pin configuration.
> +      Client device subnodes use below standard properties.
> +    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +
> +    properties:
> +      pins:
> +        description:
> +          List of gpio pins affected by the properties specified in this
> +          subnode.
> +        items:
> +          oneOf:
> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
> +                      qdsd_data3 ]

These are ordered by name.

> +        minItems: 1
> +        maxItems: 8
> +
> +      function:
> +        description:
> +          Specify the alternative function to be configured for the specified
> +          pins.
> +
> +        enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
> +                audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
> +                blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
> +                blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
> +                blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
> +                cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
> +                gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
> +                mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
> +                pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
> +                prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
> +                pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
> +                pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
> +                pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
> +                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
> +                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
> +                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
> +                dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
> +                rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
> +                wci20, wci21, wsa_swrm, audio_pdm0 ]

These too

> +
> +      bias-disable: true
> +      bias-pull-down: true
> +      bias-pull-up: true
> +      drive-strength: true
> +      input-enable: true
> +      output-high: true
> +      output-low: true
> +
> +    required:
> +      - pins
> +
> +    additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    tlmm: pinctrl@1000000 {
> +        compatible = "qcom,ipq9574-tlmm";
> +        reg = <0x01000000 0x300000>;
> +        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +        interrupt-controller;
> +        #interrupt-cells = <2>;
> +        gpio-ranges = <&tlmm 0 0 65>;
> +
> +        uart2-state {
> +                pins = "gpio34", "gpio35";

Wrong indentation.

> +                function = "blsp2_uart";
> +                drive-strength = <8>;
> +                bias-pull-down;
> +        };
> +    };

Best regards,
Krzysztof


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Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Add device tree binding documentation details for ipq9574
> pinctrl driver
> 

Subject: drop second/last, redundant "bindings". The "dt-bindings"
prefix is already stating that these are bindings.

> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   | 129 ++++++++++++++++++
>  1 file changed, 129 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
> 
> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
> new file mode 100644
> index 000000000000..f9cb457bc18d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
> @@ -0,0 +1,129 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
> +
> +maintainers:
> +  - Anusha <quic_anusha@quicinc.com>
> +
> +description: |
> +  This binding describes the Top Level Mode Multiplexer block found in the
> +  IPQ9574 platform.

No, please rebase on recent changes. You started your work on some old
bindings so your binding likely includes all issues we fixed.

> +
> +allOf:
> +  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: qcom,ipq9574-tlmm
> +
> +  reg:
> +    maxItems: 1
> +
> +  interrupts: true
> +  interrupt-controller: true
> +  "#interrupt-cells": true
> +  gpio-controller: true
> +  gpio-reserved-ranges: true
> +  "#gpio-cells": true
> +  gpio-ranges: true
> +  wakeup-parent: true

Missing gpio-line-names and constraints for ranges. Look at other bindings.

> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +patternProperties:
> +  "-state$":
> +    oneOf:
> +      - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
> +      - patternProperties:
> +          "-pins$":
> +            $ref: "#/$defs/qcom-ipq9574-tlmm-state"
> +        additionalProperties: false
> +
> +$defs:
> +  qcom-ipq9574-tlmm-state:
> +    type: object
> +    description:
> +      Pinctrl node's client devices use subnodes for desired pin configuration.
> +      Client device subnodes use below standard properties.
> +    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
> +
> +    properties:
> +      pins:
> +        description:
> +          List of gpio pins affected by the properties specified in this
> +          subnode.
> +        items:
> +          oneOf:
> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
> +                      qdsd_data3 ]

These are ordered by name.

> +        minItems: 1
> +        maxItems: 8
> +
> +      function:
> +        description:
> +          Specify the alternative function to be configured for the specified
> +          pins.
> +
> +        enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
> +                audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
> +                blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
> +                blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
> +                blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
> +                cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
> +                gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
> +                mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
> +                pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
> +                prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
> +                pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
> +                pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
> +                pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
> +                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
> +                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
> +                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
> +                dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
> +                rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
> +                wci20, wci21, wsa_swrm, audio_pdm0 ]

These too

> +
> +      bias-disable: true
> +      bias-pull-down: true
> +      bias-pull-up: true
> +      drive-strength: true
> +      input-enable: true
> +      output-high: true
> +      output-low: true
> +
> +    required:
> +      - pins
> +
> +    additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    tlmm: pinctrl@1000000 {
> +        compatible = "qcom,ipq9574-tlmm";
> +        reg = <0x01000000 0x300000>;
> +        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +        gpio-controller;
> +        #gpio-cells = <2>;
> +        interrupt-controller;
> +        #interrupt-cells = <2>;
> +        gpio-ranges = <&tlmm 0 0 65>;
> +
> +        uart2-state {
> +                pins = "gpio34", "gpio35";

Wrong indentation.

> +                function = "blsp2_uart";
> +                drive-strength = <8>;
> +                bias-pull-down;
> +        };
> +    };

Best regards,
Krzysztof

Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Devi Priya]

On 1/11/2023 3:09 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Add device tree binding documentation details for ipq9574
>> pinctrl driver
>>
> 
> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> prefix is already stating that these are bindings.
Sure, okay
> 
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   | 129 ++++++++++++++++++
>>   1 file changed, 129 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>> new file mode 100644
>> index 000000000000..f9cb457bc18d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>> @@ -0,0 +1,129 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
>> +
>> +maintainers:
>> +  - Anusha <quic_anusha@quicinc.com>
>> +
>> +description: |
>> +  This binding describes the Top Level Mode Multiplexer block found in the
>> +  IPQ9574 platform.
> 
> No, please rebase on recent changes. You started your work on some old
> bindings so your binding likely includes all issues we fixed.
Sure, will do
> 
>> +
>> +allOf:
>> +  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,ipq9574-tlmm
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts: true
>> +  interrupt-controller: true
>> +  "#interrupt-cells": true
>> +  gpio-controller: true
>> +  gpio-reserved-ranges: true
>> +  "#gpio-cells": true
>> +  gpio-ranges: true
>> +  wakeup-parent: true
> 
> Missing gpio-line-names and constraints for ranges. Look at other bindings.
Okay
> 
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +
>> +additionalProperties: false
>> +
>> +patternProperties:
>> +  "-state$":
>> +    oneOf:
>> +      - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
>> +      - patternProperties:
>> +          "-pins$":
>> +            $ref: "#/$defs/qcom-ipq9574-tlmm-state"
>> +        additionalProperties: false
>> +
>> +$defs:
>> +  qcom-ipq9574-tlmm-state:
>> +    type: object
>> +    description:
>> +      Pinctrl node's client devices use subnodes for desired pin configuration.
>> +      Client device subnodes use below standard properties.
>> +    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
>> +
>> +    properties:
>> +      pins:
>> +        description:
>> +          List of gpio pins affected by the properties specified in this
>> +          subnode.
>> +        items:
>> +          oneOf:
>> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
>> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
>> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
>> +                      qdsd_data3 ]
> 
> These are ordered by name.
The enum values seem to be ordered alphabetically.
could you please help us understand the ordering?
> 
>> +        minItems: 1
>> +        maxItems: 8
>> +
>> +      function:
>> +        description:
>> +          Specify the alternative function to be configured for the specified
>> +          pins.
>> +
>> +        enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
>> +                audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
>> +                blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
>> +                blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
>> +                blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
>> +                cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
>> +                gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
>> +                mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
>> +                pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
>> +                prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
>> +                pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
>> +                pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
>> +                pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
>> +                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
>> +                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
>> +                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
>> +                dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
>> +                rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
>> +                wci20, wci21, wsa_swrm, audio_pdm0 ]
> 
> These too
> 
>> +
>> +      bias-disable: true
>> +      bias-pull-down: true
>> +      bias-pull-up: true
>> +      drive-strength: true
>> +      input-enable: true
>> +      output-high: true
>> +      output-low: true
>> +
>> +    required:
>> +      - pins
>> +
>> +    additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    tlmm: pinctrl@1000000 {
>> +        compatible = "qcom,ipq9574-tlmm";
>> +        reg = <0x01000000 0x300000>;
>> +        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +        gpio-controller;
>> +        #gpio-cells = <2>;
>> +        interrupt-controller;
>> +        #interrupt-cells = <2>;
>> +        gpio-ranges = <&tlmm 0 0 65>;
>> +
>> +        uart2-state {
>> +                pins = "gpio34", "gpio35";
> 
> Wrong indentation.
Okay
> 
>> +                function = "blsp2_uart";
>> +                drive-strength = <8>;
>> +                bias-pull-down;
>> +        };
>> +    };
> 
> Best regards,
> Krzysztof
> 

Best Regards,
Devi Priya

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Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Devi Priya]

On 1/11/2023 3:09 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Add device tree binding documentation details for ipq9574
>> pinctrl driver
>>
> 
> Subject: drop second/last, redundant "bindings". The "dt-bindings"
> prefix is already stating that these are bindings.
Sure, okay
> 
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   .../bindings/pinctrl/qcom,ipq9574-tlmm.yaml   | 129 ++++++++++++++++++
>>   1 file changed, 129 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>> new file mode 100644
>> index 000000000000..f9cb457bc18d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9574-tlmm.yaml
>> @@ -0,0 +1,129 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9574-tlmm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Technologies, Inc. IPQ9574 TLMM block
>> +
>> +maintainers:
>> +  - Anusha <quic_anusha@quicinc.com>
>> +
>> +description: |
>> +  This binding describes the Top Level Mode Multiplexer block found in the
>> +  IPQ9574 platform.
> 
> No, please rebase on recent changes. You started your work on some old
> bindings so your binding likely includes all issues we fixed.
Sure, will do
> 
>> +
>> +allOf:
>> +  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,ipq9574-tlmm
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  interrupts: true
>> +  interrupt-controller: true
>> +  "#interrupt-cells": true
>> +  gpio-controller: true
>> +  gpio-reserved-ranges: true
>> +  "#gpio-cells": true
>> +  gpio-ranges: true
>> +  wakeup-parent: true
> 
> Missing gpio-line-names and constraints for ranges. Look at other bindings.
Okay
> 
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +
>> +additionalProperties: false
>> +
>> +patternProperties:
>> +  "-state$":
>> +    oneOf:
>> +      - $ref: "#/$defs/qcom-ipq9574-tlmm-state"
>> +      - patternProperties:
>> +          "-pins$":
>> +            $ref: "#/$defs/qcom-ipq9574-tlmm-state"
>> +        additionalProperties: false
>> +
>> +$defs:
>> +  qcom-ipq9574-tlmm-state:
>> +    type: object
>> +    description:
>> +      Pinctrl node's client devices use subnodes for desired pin configuration.
>> +      Client device subnodes use below standard properties.
>> +    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
>> +
>> +    properties:
>> +      pins:
>> +        description:
>> +          List of gpio pins affected by the properties specified in this
>> +          subnode.
>> +        items:
>> +          oneOf:
>> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
>> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
>> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
>> +                      qdsd_data3 ]
> 
> These are ordered by name.
The enum values seem to be ordered alphabetically.
could you please help us understand the ordering?
> 
>> +        minItems: 1
>> +        maxItems: 8
>> +
>> +      function:
>> +        description:
>> +          Specify the alternative function to be configured for the specified
>> +          pins.
>> +
>> +        enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
>> +                audio_pdm1, audio_pri, audio_sec, blsp0_spi, blsp0_uart,
>> +                blsp1_i2c, blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi,
>> +                blsp2_uart, blsp3_i2c, blsp3_spi, blsp3_uart, blsp4_i2c,
>> +                blsp4_spi, blsp4_uart, blsp5_i2c, blsp5_uart, cri_trng0,
>> +                cri_trng1, cri_trng3, cxc0, cxc1, dbg_out, dwc_ddrphy,
>> +                gcc_plltest, gcc_tlmm, mac00, mac01, mac10, mac11, mdc,
>> +                mdio, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake, pcie2_clk,
>> +                pcie2_wake, pcie3_clk, pcie3_wake, prng_rosc0, prng_rosc1,
>> +                prng_rosc2, prng_rosc3, pta1_0, pta1_1, pta1_2, pta20, pta21,
>> +                pwm00, pwm01, pwm02, pwm03, pwm04, pwm10, pwm11, pwm12, pwm13,
>> +                pwm14, pwm20, pwm21, pwm22, pwm23, pwm24, pwm30, pwm31, pwm32,
>> +                pwm33, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
>> +                qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, qdss_cti_trig_out_a1,
>> +                qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, qdss_traceclk_a,
>> +                qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
>> +                dss_tracedata_b, qdss_tracedata_b, qspi_clk, qspi_cs, qspi_data,
>> +                rx0, rx1, sdc_clk, sdc_cmd, sdc_data, sdc_rclk, tsens_max,
>> +                wci20, wci21, wsa_swrm, audio_pdm0 ]
> 
> These too
> 
>> +
>> +      bias-disable: true
>> +      bias-pull-down: true
>> +      bias-pull-up: true
>> +      drive-strength: true
>> +      input-enable: true
>> +      output-high: true
>> +      output-low: true
>> +
>> +    required:
>> +      - pins
>> +
>> +    additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +    tlmm: pinctrl@1000000 {
>> +        compatible = "qcom,ipq9574-tlmm";
>> +        reg = <0x01000000 0x300000>;
>> +        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +        gpio-controller;
>> +        #gpio-cells = <2>;
>> +        interrupt-controller;
>> +        #interrupt-cells = <2>;
>> +        gpio-ranges = <&tlmm 0 0 65>;
>> +
>> +        uart2-state {
>> +                pins = "gpio34", "gpio35";
> 
> Wrong indentation.
Okay
> 
>> +                function = "blsp2_uart";
>> +                drive-strength = <8>;
>> +                bias-pull-down;
>> +        };
>> +    };
> 
> Best regards,
> Krzysztof
> 

Best Regards,
Devi Priya

Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Krzysztof Kozlowski]

On 13/01/2023 14:24, Devi Priya wrote:
>>> +    properties:
>>> +      pins:
>>> +        description:
>>> +          List of gpio pins affected by the properties specified in this
>>> +          subnode.
>>> +        items:
>>> +          oneOf:
>>> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
>>> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
>>> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
>>> +                      qdsd_data3 ]
>>
>> These are ordered by name.
> The enum values seem to be ordered alphabetically.
> could you please help us understand the ordering?

q goes before s

>>
>>> +        minItems: 1
>>> +        maxItems: 8
>>> +

Best regards,
Krzysztof


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Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Krzysztof Kozlowski]

On 13/01/2023 14:24, Devi Priya wrote:
>>> +    properties:
>>> +      pins:
>>> +        description:
>>> +          List of gpio pins affected by the properties specified in this
>>> +          subnode.
>>> +        items:
>>> +          oneOf:
>>> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
>>> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
>>> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
>>> +                      qdsd_data3 ]
>>
>> These are ordered by name.
> The enum values seem to be ordered alphabetically.
> could you please help us understand the ordering?

q goes before s

>>
>>> +        minItems: 1
>>> +        maxItems: 8
>>> +

Best regards,
Krzysztof

Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Devi Priya]

On 1/13/2023 7:46 PM, Krzysztof Kozlowski wrote:
> On 13/01/2023 14:24, Devi Priya wrote:
>>>> +    properties:
>>>> +      pins:
>>>> +        description:
>>>> +          List of gpio pins affected by the properties specified in this
>>>> +          subnode.
>>>> +        items:
>>>> +          oneOf:
>>>> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
>>>> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
>>>> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
>>>> +                      qdsd_data3 ]
>>>
>>> These are ordered by name.
>> The enum values seem to be ordered alphabetically.
>> could you please help us understand the ordering?
> 
> q goes before s
Oops! sorry. Will update
> 
>>>
>>>> +        minItems: 1
>>>> +        maxItems: 8
>>>> +
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

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Re: [PATCH 3/7] dt-bindings: pinctrl: qcom: Add ipq9574 pinctrl bindings

[Devi Priya]

On 1/13/2023 7:46 PM, Krzysztof Kozlowski wrote:
> On 13/01/2023 14:24, Devi Priya wrote:
>>>> +    properties:
>>>> +      pins:
>>>> +        description:
>>>> +          List of gpio pins affected by the properties specified in this
>>>> +          subnode.
>>>> +        items:
>>>> +          oneOf:
>>>> +            - pattern: "^gpio([0-9]|[1-5][0-9]|6[0-4])$"
>>>> +            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
>>>> +                      sdc2_data, qdsd_cmd, qdsd_data0, qdsd_data1, qdsd_data2,
>>>> +                      qdsd_data3 ]
>>>
>>> These are ordered by name.
>> The enum values seem to be ordered alphabetically.
>> could you please help us understand the ordering?
> 
> q goes before s
Oops! sorry. Will update
> 
>>>
>>>> +        minItems: 1
>>>> +        maxItems: 8
>>>> +
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

[PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[devi priya]

Add pinctrl definitions for the TLMM of IPQ9574

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 drivers/pinctrl/qcom/Kconfig           |   10 +
 drivers/pinctrl/qcom/Makefile          |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
 3 files changed, 1014 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 1378ddca084f..a9b4b07e3de0 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
 	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
 	  IPQ6018.
 
+config PINCTRL_IPQ9574
+	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
+	depends on GPIOLIB && OF
+	select PINCTRL_MSM
+	help
+	  This is the pinctrl, pinmux, pinconf and gpiolib driver for
+          the Qualcomm Technologies Inc. TLMM block found on the
+          Qualcomm Technologies Inc. IPQ9574 platform. Select this for
+          IPQ9574.
+
 config PINCTRL_MSM8226
 	tristate "Qualcomm 8226 pin controller driver"
 	depends on OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index a5c40f552e5c..717c8b8000ba 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019)	+= pinctrl-ipq4019.o
 obj-$(CONFIG_PINCTRL_IPQ8064)	+= pinctrl-ipq8064.o
 obj-$(CONFIG_PINCTRL_IPQ8074)	+= pinctrl-ipq8074.o
 obj-$(CONFIG_PINCTRL_IPQ6018)	+= pinctrl-ipq6018.o
+obj-$(CONFIG_PINCTRL_IPQ9574)   += pinctrl-ipq9574.o
 obj-$(CONFIG_PINCTRL_MSM8226)	+= pinctrl-msm8226.o
 obj-$(CONFIG_PINCTRL_MSM8660)	+= pinctrl-msm8660.o
 obj-$(CONFIG_PINCTRL_MSM8960)	+= pinctrl-msm8960.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
new file mode 100644
index 000000000000..48be36279939
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
@@ -0,0 +1,1003 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2022 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname)			                \
+	[msm_mux_##fname] = {		                \
+		.name = #fname,				\
+		.groups = fname##_groups,               \
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+	}
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
+	{					        \
+		.name = "gpio" #id,			\
+		.pins = gpio##id##_pins,		\
+		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
+		.funcs = (int[]){			\
+			msm_mux_gpio, /* gpio mode */	\
+			msm_mux_##f1,			\
+			msm_mux_##f2,			\
+			msm_mux_##f3,			\
+			msm_mux_##f4,			\
+			msm_mux_##f5,			\
+			msm_mux_##f6,			\
+			msm_mux_##f7,			\
+			msm_mux_##f8,			\
+			msm_mux_##f9			\
+		},				        \
+		.nfuncs = 10,				\
+		.ctl_reg = REG_SIZE * id,			\
+		.io_reg = 0x4 + REG_SIZE * id,		\
+		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
+		.intr_status_reg = 0xc + REG_SIZE * id,	\
+		.intr_target_reg = 0x8 + REG_SIZE * id,	\
+		.mux_bit = 2,			\
+		.pull_bit = 0,			\
+		.drv_bit = 6,			\
+		.oe_bit = 9,			\
+		.in_bit = 0,			\
+		.out_bit = 1,			\
+		.intr_enable_bit = 0,		\
+		.intr_status_bit = 0,		\
+		.intr_target_bit = 5,		\
+		.intr_target_kpss_val = 3,	\
+		.intr_raw_status_bit = 4,	\
+		.intr_polarity_bit = 1,		\
+		.intr_detection_bit = 2,	\
+		.intr_detection_width = 2,	\
+	}
+
+static const struct pinctrl_pin_desc ipq9574_pins[] = {
+	PINCTRL_PIN(0, "GPIO_0"),
+	PINCTRL_PIN(1, "GPIO_1"),
+	PINCTRL_PIN(2, "GPIO_2"),
+	PINCTRL_PIN(3, "GPIO_3"),
+	PINCTRL_PIN(4, "GPIO_4"),
+	PINCTRL_PIN(5, "GPIO_5"),
+	PINCTRL_PIN(6, "GPIO_6"),
+	PINCTRL_PIN(7, "GPIO_7"),
+	PINCTRL_PIN(8, "GPIO_8"),
+	PINCTRL_PIN(9, "GPIO_9"),
+	PINCTRL_PIN(10, "GPIO_10"),
+	PINCTRL_PIN(11, "GPIO_11"),
+	PINCTRL_PIN(12, "GPIO_12"),
+	PINCTRL_PIN(13, "GPIO_13"),
+	PINCTRL_PIN(14, "GPIO_14"),
+	PINCTRL_PIN(15, "GPIO_15"),
+	PINCTRL_PIN(16, "GPIO_16"),
+	PINCTRL_PIN(17, "GPIO_17"),
+	PINCTRL_PIN(18, "GPIO_18"),
+	PINCTRL_PIN(19, "GPIO_19"),
+	PINCTRL_PIN(20, "GPIO_20"),
+	PINCTRL_PIN(21, "GPIO_21"),
+	PINCTRL_PIN(22, "GPIO_22"),
+	PINCTRL_PIN(23, "GPIO_23"),
+	PINCTRL_PIN(24, "GPIO_24"),
+	PINCTRL_PIN(25, "GPIO_25"),
+	PINCTRL_PIN(26, "GPIO_26"),
+	PINCTRL_PIN(27, "GPIO_27"),
+	PINCTRL_PIN(28, "GPIO_28"),
+	PINCTRL_PIN(29, "GPIO_29"),
+	PINCTRL_PIN(30, "GPIO_30"),
+	PINCTRL_PIN(31, "GPIO_31"),
+	PINCTRL_PIN(32, "GPIO_32"),
+	PINCTRL_PIN(33, "GPIO_33"),
+	PINCTRL_PIN(34, "GPIO_34"),
+	PINCTRL_PIN(35, "GPIO_35"),
+	PINCTRL_PIN(36, "GPIO_36"),
+	PINCTRL_PIN(37, "GPIO_37"),
+	PINCTRL_PIN(38, "GPIO_38"),
+	PINCTRL_PIN(39, "GPIO_39"),
+	PINCTRL_PIN(40, "GPIO_40"),
+	PINCTRL_PIN(41, "GPIO_41"),
+	PINCTRL_PIN(42, "GPIO_42"),
+	PINCTRL_PIN(43, "GPIO_43"),
+	PINCTRL_PIN(44, "GPIO_44"),
+	PINCTRL_PIN(45, "GPIO_45"),
+	PINCTRL_PIN(46, "GPIO_46"),
+	PINCTRL_PIN(47, "GPIO_47"),
+	PINCTRL_PIN(48, "GPIO_48"),
+	PINCTRL_PIN(49, "GPIO_49"),
+	PINCTRL_PIN(50, "GPIO_50"),
+	PINCTRL_PIN(51, "GPIO_51"),
+	PINCTRL_PIN(52, "GPIO_52"),
+	PINCTRL_PIN(53, "GPIO_53"),
+	PINCTRL_PIN(54, "GPIO_54"),
+	PINCTRL_PIN(55, "GPIO_55"),
+	PINCTRL_PIN(56, "GPIO_56"),
+	PINCTRL_PIN(57, "GPIO_57"),
+	PINCTRL_PIN(58, "GPIO_58"),
+	PINCTRL_PIN(59, "GPIO_59"),
+	PINCTRL_PIN(60, "GPIO_60"),
+	PINCTRL_PIN(61, "GPIO_61"),
+	PINCTRL_PIN(62, "GPIO_62"),
+	PINCTRL_PIN(63, "GPIO_63"),
+	PINCTRL_PIN(64, "GPIO_64"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+	static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+
+enum ipq9574_functions {
+	msm_mux_atest_char,
+	msm_mux_atest_char0,
+	msm_mux_atest_char1,
+	msm_mux_atest_char2,
+	msm_mux_atest_char3,
+	msm_mux_audio_pdm0,
+	msm_mux_audio_pdm1,
+	msm_mux_audio_pri,
+	msm_mux_audio_sec,
+	msm_mux_blsp0_spi,
+	msm_mux_blsp0_uart,
+	msm_mux_blsp1_i2c,
+	msm_mux_blsp1_spi,
+	msm_mux_blsp1_uart,
+	msm_mux_blsp2_i2c,
+	msm_mux_blsp2_spi,
+	msm_mux_blsp2_uart,
+	msm_mux_blsp3_i2c,
+	msm_mux_blsp3_spi,
+	msm_mux_blsp3_uart,
+	msm_mux_blsp4_i2c,
+	msm_mux_blsp4_spi,
+	msm_mux_blsp4_uart,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_uart,
+	msm_mux_cri_trng0,
+	msm_mux_cri_trng1,
+	msm_mux_cri_trng2,
+	msm_mux_cri_trng3,
+	msm_mux_cxc0,
+	msm_mux_cxc1,
+	msm_mux_dbg_out,
+	msm_mux_dwc_ddrphy,
+	msm_mux_gcc_plltest,
+	msm_mux_gcc_tlmm,
+	msm_mux_gpio,
+	msm_mux_mac00,
+	msm_mux_mac01,
+	msm_mux_mac10,
+	msm_mux_mac11,
+	msm_mux_mdc,
+	msm_mux_mdio,
+	msm_mux_pcie0_clk,
+	msm_mux_pcie0_wake,
+	msm_mux_pcie1_clk,
+	msm_mux_pcie1_wake,
+	msm_mux_pcie2_clk,
+	msm_mux_pcie2_wake,
+	msm_mux_pcie3_clk,
+	msm_mux_pcie3_wake,
+	msm_mux_prng_rosc0,
+	msm_mux_prng_rosc1,
+	msm_mux_prng_rosc2,
+	msm_mux_prng_rosc3,
+	msm_mux_pta1_0,
+	msm_mux_pta1_1,
+	msm_mux_pta1_2,
+	msm_mux_pta20,
+	msm_mux_pta21,
+	msm_mux_pwm00,
+	msm_mux_pwm01,
+	msm_mux_pwm02,
+	msm_mux_pwm03,
+	msm_mux_pwm04,
+	msm_mux_pwm10,
+	msm_mux_pwm11,
+	msm_mux_pwm12,
+	msm_mux_pwm13,
+	msm_mux_pwm14,
+	msm_mux_pwm20,
+	msm_mux_pwm21,
+	msm_mux_pwm22,
+	msm_mux_pwm23,
+	msm_mux_pwm24,
+	msm_mux_pwm30,
+	msm_mux_pwm31,
+	msm_mux_pwm32,
+	msm_mux_pwm33,
+	msm_mux_qdss_cti_trig_in_a0,
+	msm_mux_qdss_cti_trig_in_a1,
+	msm_mux_qdss_cti_trig_in_b0,
+	msm_mux_qdss_cti_trig_in_b1,
+	msm_mux_qdss_cti_trig_out_a0,
+	msm_mux_qdss_cti_trig_out_a1,
+	msm_mux_qdss_cti_trig_out_b0,
+	msm_mux_qdss_cti_trig_out_b1,
+	msm_mux_qdss_traceclk_a,
+	msm_mux_qdss_traceclk_b,
+	msm_mux_qdss_tracectl_a,
+	msm_mux_qdss_tracectl_b,
+	msm_mux_qdss_tracedata_a,
+	msm_mux_qdss_tracedata_b,
+	msm_mux_qspi_data,
+	msm_mux_qspi_clk,
+	msm_mux_qspi_cs,
+	msm_mux_rx0,
+	msm_mux_rx1,
+	msm_mux_sdc_data,
+	msm_mux_sdc_clk,
+	msm_mux_sdc_cmd,
+	msm_mux_sdc_rclk,
+	msm_mux_tsens_max,
+	msm_mux_wci20,
+	msm_mux_wci21,
+	msm_mux_wsa_swrm,
+	msm_mux__,
+};
+
+static const char * const gpio_groups[] = {
+	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+	"gpio64",
+};
+
+static const char * const sdc_data_groups[] = {
+	"gpio0",
+	"gpio1",
+	"gpio2",
+	"gpio3",
+	"gpio6",
+	"gpio7",
+	"gpio8",
+	"gpio9",
+};
+
+static const char * const qspi_data_groups[] = {
+	"gpio0",
+	"gpio1",
+	"gpio2",
+	"gpio3",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+	"gpio0",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+	"gpio1",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+	"gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
+	"gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
+	"gpio17",
+};
+
+static const char * const sdc_cmd_groups[] = {
+	"gpio4",
+};
+
+static const char * const qspi_cs_groups[] = {
+	"gpio4",
+};
+
+static const char * const sdc_clk_groups[] = {
+	"gpio5",
+};
+
+static const char * const qspi_clk_groups[] = {
+	"gpio5",
+};
+
+static const char * const sdc_rclk_groups[] = {
+	"gpio10",
+};
+
+static const char * const blsp0_spi_groups[] = {
+	"gpio11", "gpio12", "gpio13", "gpio14",
+};
+
+static const char * const blsp0_uart_groups[] = {
+	"gpio11", "gpio12", "gpio13", "gpio14",
+};
+
+static const char * const blsp3_spi_groups[] = {
+	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+};
+
+static const char * const blsp3_i2c_groups[] = {
+	"gpio15", "gpio16",
+};
+
+static const char * const blsp3_uart_groups[] = {
+	"gpio15", "gpio16", "gpio17", "gpio18",
+};
+
+static const char * const dbg_out_groups[] = {
+	"gpio17",
+};
+
+static const char * const cri_trng0_groups[] = {
+	"gpio20", "gpio38",
+};
+
+static const char * const cri_trng1_groups[] = {
+	"gpio21", "gpio34",
+};
+
+static const char * const pcie0_clk_groups[] = {
+	"gpio22",
+};
+
+static const char * const pta20_groups[] = {
+	"gpio22", "gpio23", "gpio24",
+};
+
+static const char * const wci21_groups[] = {
+	"gpio23", "gpio24",
+};
+
+static const char * const cxc0_groups[] = {
+	"gpio23", "gpio24",
+};
+
+static const char * const pcie0_wake_groups[] = {
+	"gpio24",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+	"gpio24",
+};
+
+static const char * const pcie1_clk_groups[] = {
+	"gpio25",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+	"gpio25",
+};
+
+static const char * const atest_char0_groups[] = {
+	"gpio26",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+	"gpio26",
+};
+
+static const char * const pcie1_wake_groups[] = {
+	"gpio27",
+};
+
+static const char * const atest_char1_groups[] = {
+	"gpio27",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+	"gpio27",
+};
+
+static const char * const pcie2_clk_groups[] = {
+	"gpio28",
+};
+
+static const char * const atest_char2_groups[] = {
+	"gpio28",
+};
+
+static const char * const atest_char3_groups[] = {
+	"gpio29",
+};
+
+static const char * const pcie2_wake_groups[] = {
+	"gpio30",
+};
+
+static const char * const pwm01_groups[] = {
+	"gpio30",
+};
+
+static const char * const atest_char_groups[] = {
+	"gpio30",
+};
+
+static const char * const pcie3_clk_groups[] = {
+	"gpio31",
+};
+
+static const char * const pwm11_groups[] = {
+	"gpio31",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+	"gpio31",
+};
+
+static const char * const pwm21_groups[] = {
+	"gpio32",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+	"gpio32",
+};
+
+static const char * const pcie3_wake_groups[] = {
+	"gpio33",
+};
+
+static const char * const pwm31_groups[] = {
+	"gpio33",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+	"gpio33",
+};
+
+static const char * const blsp2_uart_groups[] = {
+	"gpio34", "gpio35",
+};
+
+static const char * const blsp2_i2c_groups[] = {
+	"gpio34", "gpio35",
+};
+
+static const char * const blsp2_spi_groups[] = {
+	"gpio34", "gpio35", "gpio36", "gpio37",
+};
+
+static const char * const blsp1_uart_groups[] = {
+	"gpio34", "gpio35", "gpio36", "gpio37",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+	"gpio34",
+};
+
+static const char * const cri_trng2_groups[] = {
+	"gpio35",
+};
+
+static const char * const blsp1_i2c_groups[] = {
+	"gpio36", "gpio37",
+};
+
+static const char * const cri_trng3_groups[] = {
+	"gpio36",
+};
+
+static const char * const dwc_ddrphy_groups[] = {
+	"gpio37",
+};
+
+static const char * const mdc_groups[] = {
+	"gpio38",
+};
+
+static const char * const mdio_groups[] = {
+	"gpio39",
+};
+
+static const char * const audio_pri_groups[] = {
+	"gpio40", "gpio41", "gpio42", "gpio43", "gpio61", "gpio61",
+};
+
+static const char * const audio_pdm0_groups[] = {
+	"gpio40", "gpio41", "gpio42", "gpio43",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+	"gpio43",
+};
+
+static const char * const pwm00_groups[] = {
+	"gpio44",
+};
+
+static const char * const audio_sec_groups[] = {
+	"gpio44", "gpio45", "gpio46", "gpio47", "gpio62", "gpio62",
+};
+
+static const char * const wsa_swrm_groups[] = {
+	"gpio44", "gpio45",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+	"gpio44",
+};
+
+static const char * const pwm10_groups[] = {
+	"gpio45",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+	"gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
+	"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
+	"gpio59", "gpio60",
+};
+
+static const char * const pwm20_groups[] = {
+	"gpio46",
+};
+
+static const char * const rx1_groups[] = {
+	"gpio46",
+};
+
+static const char * const mac00_groups[] = {
+	"gpio46",
+};
+
+static const char * const pwm30_groups[] = {
+	"gpio47",
+};
+
+static const char * const mac01_groups[] = {
+	"gpio47",
+};
+
+static const char * const blsp5_i2c_groups[] = {
+	"gpio48", "gpio49",
+};
+
+static const char * const blsp5_uart_groups[] = {
+	"gpio48", "gpio49",
+};
+
+static const char * const blsp4_uart_groups[] = {
+	"gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const blsp4_i2c_groups[] = {
+	"gpio50", "gpio51",
+};
+
+static const char * const blsp4_spi_groups[] = {
+	"gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const pwm02_groups[] = {
+	"gpio50",
+};
+
+static const char * const pwm12_groups[] = {
+	"gpio51",
+};
+
+static const char * const pwm22_groups[] = {
+	"gpio52",
+};
+
+static const char * const pwm32_groups[] = {
+	"gpio53",
+};
+
+static const char * const pta1_1_groups[] = {
+	"gpio54",
+};
+
+static const char * const pwm04_groups[] = {
+	"gpio54",
+};
+
+static const char * const pta1_2_groups[] = {
+	"gpio55",
+};
+
+static const char * const pwm14_groups[] = {
+	"gpio55",
+};
+
+static const char * const pta1_0_groups[] = {
+	"gpio56",
+};
+
+static const char * const pwm24_groups[] = {
+	"gpio56",
+};
+
+static const char * const wci20_groups[] = {
+	"gpio57", "gpio58",
+};
+
+static const char * const cxc1_groups[] = {
+	"gpio57", "gpio58",
+};
+
+static const char * const mac10_groups[] = {
+	"gpio57",
+};
+
+static const char * const pwm03_groups[] = {
+	"gpio57",
+};
+
+static const char * const mac11_groups[] = {
+	"gpio58",
+};
+
+static const char * const pwm13_groups[] = {
+	"gpio58",
+};
+
+static const char * const rx0_groups[] = {
+	"gpio59",
+};
+
+static const char * const pwm23_groups[] = {
+	"gpio59",
+};
+
+static const char * const pwm33_groups[] = {
+	"gpio60",
+};
+
+static const char * const prng_rosc0_groups[] = {
+	"gpio60",
+};
+
+static const char * const gcc_plltest_groups[] = {
+	"gpio60", "gpio62",
+};
+
+static const char * const blsp1_spi_groups[] = {
+	"gpio61", "gpio62", "gpio63", "gpio64",
+};
+
+static const char * const audio_pdm1_groups[] = {
+	"gpio61", "gpio62", "gpio63", "gpio64",
+};
+
+static const char * const pta21_groups[] = {
+	"gpio61", "gpio62", "gpio63",
+};
+
+static const char * const prng_rosc1_groups[] = {
+	"gpio61",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+	"gpio61",
+};
+
+static const char * const prng_rosc2_groups[] = {
+	"gpio62",
+};
+
+static const char * const prng_rosc3_groups[] = {
+	"gpio63",
+};
+
+static const char * const tsens_max_groups[] = {
+	"gpio64",
+};
+
+static const struct msm_function ipq9574_functions[] = {
+	FUNCTION(atest_char),
+	FUNCTION(atest_char0),
+	FUNCTION(atest_char1),
+	FUNCTION(atest_char2),
+	FUNCTION(atest_char3),
+	FUNCTION(audio_pdm0),
+	FUNCTION(audio_pdm1),
+	FUNCTION(audio_pri),
+	FUNCTION(audio_sec),
+	FUNCTION(blsp0_spi),
+	FUNCTION(blsp0_uart),
+	FUNCTION(blsp1_i2c),
+	FUNCTION(blsp1_spi),
+	FUNCTION(blsp1_uart),
+	FUNCTION(blsp2_i2c),
+	FUNCTION(blsp2_spi),
+	FUNCTION(blsp2_uart),
+	FUNCTION(blsp3_i2c),
+	FUNCTION(blsp3_spi),
+	FUNCTION(blsp3_uart),
+	FUNCTION(blsp4_i2c),
+	FUNCTION(blsp4_spi),
+	FUNCTION(blsp4_uart),
+	FUNCTION(blsp5_i2c),
+	FUNCTION(blsp5_uart),
+	FUNCTION(cri_trng0),
+	FUNCTION(cri_trng1),
+	FUNCTION(cri_trng2),
+	FUNCTION(cri_trng3),
+	FUNCTION(cxc0),
+	FUNCTION(cxc1),
+	FUNCTION(dbg_out),
+	FUNCTION(dwc_ddrphy),
+	FUNCTION(gcc_plltest),
+	FUNCTION(gcc_tlmm),
+	FUNCTION(gpio),
+	FUNCTION(mac00),
+	FUNCTION(mac01),
+	FUNCTION(mac10),
+	FUNCTION(mac11),
+	FUNCTION(mdc),
+	FUNCTION(mdio),
+	FUNCTION(pcie0_clk),
+	FUNCTION(pcie0_wake),
+	FUNCTION(pcie1_clk),
+	FUNCTION(pcie1_wake),
+	FUNCTION(pcie2_clk),
+	FUNCTION(pcie2_wake),
+	FUNCTION(pcie3_clk),
+	FUNCTION(pcie3_wake),
+	FUNCTION(prng_rosc0),
+	FUNCTION(prng_rosc1),
+	FUNCTION(prng_rosc2),
+	FUNCTION(prng_rosc3),
+	FUNCTION(pta1_0),
+	FUNCTION(pta1_1),
+	FUNCTION(pta1_2),
+	FUNCTION(pta20),
+	FUNCTION(pta21),
+	FUNCTION(pwm00),
+	FUNCTION(pwm01),
+	FUNCTION(pwm02),
+	FUNCTION(pwm03),
+	FUNCTION(pwm04),
+	FUNCTION(pwm10),
+	FUNCTION(pwm11),
+	FUNCTION(pwm12),
+	FUNCTION(pwm13),
+	FUNCTION(pwm14),
+	FUNCTION(pwm20),
+	FUNCTION(pwm21),
+	FUNCTION(pwm22),
+	FUNCTION(pwm23),
+	FUNCTION(pwm24),
+	FUNCTION(pwm30),
+	FUNCTION(pwm31),
+	FUNCTION(pwm32),
+	FUNCTION(pwm33),
+	FUNCTION(qdss_cti_trig_in_a0),
+	FUNCTION(qdss_cti_trig_in_a1),
+	FUNCTION(qdss_cti_trig_in_b0),
+	FUNCTION(qdss_cti_trig_in_b1),
+	FUNCTION(qdss_cti_trig_out_a0),
+	FUNCTION(qdss_cti_trig_out_a1),
+	FUNCTION(qdss_cti_trig_out_b0),
+	FUNCTION(qdss_cti_trig_out_b1),
+	FUNCTION(qdss_traceclk_a),
+	FUNCTION(qdss_traceclk_b),
+	FUNCTION(qdss_tracectl_a),
+	FUNCTION(qdss_tracectl_b),
+	FUNCTION(qdss_tracedata_a),
+	FUNCTION(qdss_tracedata_b),
+	FUNCTION(qspi_data),
+	FUNCTION(qspi_clk),
+	FUNCTION(qspi_cs),
+	FUNCTION(rx0),
+	FUNCTION(rx1),
+	FUNCTION(sdc_data),
+	FUNCTION(sdc_clk),
+	FUNCTION(sdc_cmd),
+	FUNCTION(sdc_rclk),
+	FUNCTION(tsens_max),
+	FUNCTION(wci20),
+	FUNCTION(wci21),
+	FUNCTION(wsa_swrm),
+};
+
+static const struct msm_pingroup ipq9574_groups[] = {
+	PINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _),
+	PINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _),
+	PINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
+	PINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
+	PINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _),
+	PINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _,
+		 _),
+	PINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
+		 _, _, _, _),
+	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
+		 _, _, _, _),
+	PINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _,
+		 _, _, _),
+	PINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _),
+	PINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _),
+	PINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _),
+	PINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _),
+	PINGROUP(22, pcie0_clk, _, pta20, _, _, _, _, _, _),
+	PINGROUP(23, _, pta20, wci21, cxc0, _, _, _, _, _),
+	PINGROUP(24, pcie0_wake, _, pta20, wci21, cxc0, _,
+		 qdss_cti_trig_out_b0, _, _),
+	PINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _,
+		 _),
+	PINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _,
+		 _),
+	PINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _,
+		 _, _, _),
+	PINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _),
+	PINGROUP(29, atest_char3, _, _, _, _, _, _, _, _),
+	PINGROUP(30, pcie2_wake, pwm01, atest_char, _, _, _, _, _, _),
+	PINGROUP(31, pcie3_clk, pwm11, _, qdss_cti_trig_in_a1, _, _, _, _,
+		 _),
+	PINGROUP(32, pwm21, _, qdss_cti_trig_out_a1, _, _, _, _, _, _),
+	PINGROUP(33, pcie3_wake, pwm31, _, qdss_cti_trig_in_a0, _, _, _,
+		 _, _),
+	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
+		 cri_trng1, qdss_cti_trig_out_a0, _, _),
+	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
+		 cri_trng2, _, _, _),
+	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _,
+		 _, _),
+	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _,
+		 _, _),
+	PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _),
+	PINGROUP(39, mdio, _, _, _, _, _, _, _, _),
+	PINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
+	PINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
+	PINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
+	PINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _,
+		 _, _),
+	PINGROUP(44, pwm00, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _,
+		 _, _),
+	PINGROUP(45, pwm10, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _,
+		 _, _),
+	PINGROUP(46, pwm20, audio_sec, rx1, mac00, _, qdss_tracedata_a, _,
+		 _, _),
+	PINGROUP(47, pwm30, audio_sec, mac01, _, qdss_tracedata_a, _, _, _,
+		 _),
+	PINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
+		 _, _),
+	PINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
+		 _, _),
+	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm02, qdss_tracedata_a,
+		 _, _, _, _),
+	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm12, qdss_tracedata_a,
+		 _, _, _, _),
+	PINGROUP(52, blsp4_uart, blsp4_spi, pwm22, qdss_tracedata_a, _, _,
+		 _, _, _),
+	PINGROUP(53, blsp4_uart, blsp4_spi, pwm32, qdss_tracedata_a, _, _,
+		 _, _, _),
+	PINGROUP(54, pta1_1, pwm04, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(55, pta1_2, pwm14, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(56, pta1_0, pwm24, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(57, wci20, cxc1, mac10, pwm03, qdss_tracedata_a, _, _, _,
+		 _),
+	PINGROUP(58, wci20, cxc1, mac11, pwm13, qdss_tracedata_a, _, _, _,
+		 _),
+	PINGROUP(59, rx0, pwm23, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(60, pwm33, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _,
+		 _, _, _),
+	PINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta21,
+		 prng_rosc1, gcc_tlmm, _, _),
+	PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta21,
+		 prng_rosc2, gcc_plltest, _, _),
+	PINGROUP(63, blsp1_spi, audio_pdm1, pta21, prng_rosc3, _, _, _, _,
+		 _),
+	PINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _),
+};
+
+static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {
+	.pins = ipq9574_pins,
+	.npins = ARRAY_SIZE(ipq9574_pins),
+	.functions = ipq9574_functions,
+	.nfunctions = ARRAY_SIZE(ipq9574_functions),
+	.groups = ipq9574_groups,
+	.ngroups = ARRAY_SIZE(ipq9574_groups),
+	.ngpios = 65,
+};
+
+static int ipq9574_pinctrl_probe(struct platform_device *pdev)
+{
+	return msm_pinctrl_probe(pdev, &ipq9574_pinctrl);
+}
+
+static const struct of_device_id ipq9574_pinctrl_of_match[] = {
+	{ .compatible = "qcom,ipq9574-tlmm", },
+	{ },
+};
+
+static struct platform_driver ipq9574_pinctrl_driver = {
+	.driver = {
+		.name = "ipq9574-tlmm",
+		.owner = THIS_MODULE,
+		.of_match_table = ipq9574_pinctrl_of_match,
+	},
+	.probe = ipq9574_pinctrl_probe,
+	.remove = msm_pinctrl_remove,
+};
+
+static int __init ipq9574_pinctrl_init(void)
+{
+	return platform_driver_register(&ipq9574_pinctrl_driver);
+}
+arch_initcall(ipq9574_pinctrl_init);
+
+static void __exit ipq9574_pinctrl_exit(void)
+{
+	platform_driver_unregister(&ipq9574_pinctrl_driver);
+}
+module_exit(ipq9574_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);
-- 
2.17.1


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[PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[devi priya]

Add pinctrl definitions for the TLMM of IPQ9574

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 drivers/pinctrl/qcom/Kconfig           |   10 +
 drivers/pinctrl/qcom/Makefile          |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
 3 files changed, 1014 insertions(+)
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c

diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 1378ddca084f..a9b4b07e3de0 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
 	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
 	  IPQ6018.
 
+config PINCTRL_IPQ9574
+	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
+	depends on GPIOLIB && OF
+	select PINCTRL_MSM
+	help
+	  This is the pinctrl, pinmux, pinconf and gpiolib driver for
+          the Qualcomm Technologies Inc. TLMM block found on the
+          Qualcomm Technologies Inc. IPQ9574 platform. Select this for
+          IPQ9574.
+
 config PINCTRL_MSM8226
 	tristate "Qualcomm 8226 pin controller driver"
 	depends on OF
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index a5c40f552e5c..717c8b8000ba 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019)	+= pinctrl-ipq4019.o
 obj-$(CONFIG_PINCTRL_IPQ8064)	+= pinctrl-ipq8064.o
 obj-$(CONFIG_PINCTRL_IPQ8074)	+= pinctrl-ipq8074.o
 obj-$(CONFIG_PINCTRL_IPQ6018)	+= pinctrl-ipq6018.o
+obj-$(CONFIG_PINCTRL_IPQ9574)   += pinctrl-ipq9574.o
 obj-$(CONFIG_PINCTRL_MSM8226)	+= pinctrl-msm8226.o
 obj-$(CONFIG_PINCTRL_MSM8660)	+= pinctrl-msm8660.o
 obj-$(CONFIG_PINCTRL_MSM8960)	+= pinctrl-msm8960.o
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
new file mode 100644
index 000000000000..48be36279939
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
@@ -0,0 +1,1003 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright (c) 2022 The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname)			                \
+	[msm_mux_##fname] = {		                \
+		.name = #fname,				\
+		.groups = fname##_groups,               \
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+	}
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
+	{					        \
+		.name = "gpio" #id,			\
+		.pins = gpio##id##_pins,		\
+		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
+		.funcs = (int[]){			\
+			msm_mux_gpio, /* gpio mode */	\
+			msm_mux_##f1,			\
+			msm_mux_##f2,			\
+			msm_mux_##f3,			\
+			msm_mux_##f4,			\
+			msm_mux_##f5,			\
+			msm_mux_##f6,			\
+			msm_mux_##f7,			\
+			msm_mux_##f8,			\
+			msm_mux_##f9			\
+		},				        \
+		.nfuncs = 10,				\
+		.ctl_reg = REG_SIZE * id,			\
+		.io_reg = 0x4 + REG_SIZE * id,		\
+		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
+		.intr_status_reg = 0xc + REG_SIZE * id,	\
+		.intr_target_reg = 0x8 + REG_SIZE * id,	\
+		.mux_bit = 2,			\
+		.pull_bit = 0,			\
+		.drv_bit = 6,			\
+		.oe_bit = 9,			\
+		.in_bit = 0,			\
+		.out_bit = 1,			\
+		.intr_enable_bit = 0,		\
+		.intr_status_bit = 0,		\
+		.intr_target_bit = 5,		\
+		.intr_target_kpss_val = 3,	\
+		.intr_raw_status_bit = 4,	\
+		.intr_polarity_bit = 1,		\
+		.intr_detection_bit = 2,	\
+		.intr_detection_width = 2,	\
+	}
+
+static const struct pinctrl_pin_desc ipq9574_pins[] = {
+	PINCTRL_PIN(0, "GPIO_0"),
+	PINCTRL_PIN(1, "GPIO_1"),
+	PINCTRL_PIN(2, "GPIO_2"),
+	PINCTRL_PIN(3, "GPIO_3"),
+	PINCTRL_PIN(4, "GPIO_4"),
+	PINCTRL_PIN(5, "GPIO_5"),
+	PINCTRL_PIN(6, "GPIO_6"),
+	PINCTRL_PIN(7, "GPIO_7"),
+	PINCTRL_PIN(8, "GPIO_8"),
+	PINCTRL_PIN(9, "GPIO_9"),
+	PINCTRL_PIN(10, "GPIO_10"),
+	PINCTRL_PIN(11, "GPIO_11"),
+	PINCTRL_PIN(12, "GPIO_12"),
+	PINCTRL_PIN(13, "GPIO_13"),
+	PINCTRL_PIN(14, "GPIO_14"),
+	PINCTRL_PIN(15, "GPIO_15"),
+	PINCTRL_PIN(16, "GPIO_16"),
+	PINCTRL_PIN(17, "GPIO_17"),
+	PINCTRL_PIN(18, "GPIO_18"),
+	PINCTRL_PIN(19, "GPIO_19"),
+	PINCTRL_PIN(20, "GPIO_20"),
+	PINCTRL_PIN(21, "GPIO_21"),
+	PINCTRL_PIN(22, "GPIO_22"),
+	PINCTRL_PIN(23, "GPIO_23"),
+	PINCTRL_PIN(24, "GPIO_24"),
+	PINCTRL_PIN(25, "GPIO_25"),
+	PINCTRL_PIN(26, "GPIO_26"),
+	PINCTRL_PIN(27, "GPIO_27"),
+	PINCTRL_PIN(28, "GPIO_28"),
+	PINCTRL_PIN(29, "GPIO_29"),
+	PINCTRL_PIN(30, "GPIO_30"),
+	PINCTRL_PIN(31, "GPIO_31"),
+	PINCTRL_PIN(32, "GPIO_32"),
+	PINCTRL_PIN(33, "GPIO_33"),
+	PINCTRL_PIN(34, "GPIO_34"),
+	PINCTRL_PIN(35, "GPIO_35"),
+	PINCTRL_PIN(36, "GPIO_36"),
+	PINCTRL_PIN(37, "GPIO_37"),
+	PINCTRL_PIN(38, "GPIO_38"),
+	PINCTRL_PIN(39, "GPIO_39"),
+	PINCTRL_PIN(40, "GPIO_40"),
+	PINCTRL_PIN(41, "GPIO_41"),
+	PINCTRL_PIN(42, "GPIO_42"),
+	PINCTRL_PIN(43, "GPIO_43"),
+	PINCTRL_PIN(44, "GPIO_44"),
+	PINCTRL_PIN(45, "GPIO_45"),
+	PINCTRL_PIN(46, "GPIO_46"),
+	PINCTRL_PIN(47, "GPIO_47"),
+	PINCTRL_PIN(48, "GPIO_48"),
+	PINCTRL_PIN(49, "GPIO_49"),
+	PINCTRL_PIN(50, "GPIO_50"),
+	PINCTRL_PIN(51, "GPIO_51"),
+	PINCTRL_PIN(52, "GPIO_52"),
+	PINCTRL_PIN(53, "GPIO_53"),
+	PINCTRL_PIN(54, "GPIO_54"),
+	PINCTRL_PIN(55, "GPIO_55"),
+	PINCTRL_PIN(56, "GPIO_56"),
+	PINCTRL_PIN(57, "GPIO_57"),
+	PINCTRL_PIN(58, "GPIO_58"),
+	PINCTRL_PIN(59, "GPIO_59"),
+	PINCTRL_PIN(60, "GPIO_60"),
+	PINCTRL_PIN(61, "GPIO_61"),
+	PINCTRL_PIN(62, "GPIO_62"),
+	PINCTRL_PIN(63, "GPIO_63"),
+	PINCTRL_PIN(64, "GPIO_64"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+	static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+
+enum ipq9574_functions {
+	msm_mux_atest_char,
+	msm_mux_atest_char0,
+	msm_mux_atest_char1,
+	msm_mux_atest_char2,
+	msm_mux_atest_char3,
+	msm_mux_audio_pdm0,
+	msm_mux_audio_pdm1,
+	msm_mux_audio_pri,
+	msm_mux_audio_sec,
+	msm_mux_blsp0_spi,
+	msm_mux_blsp0_uart,
+	msm_mux_blsp1_i2c,
+	msm_mux_blsp1_spi,
+	msm_mux_blsp1_uart,
+	msm_mux_blsp2_i2c,
+	msm_mux_blsp2_spi,
+	msm_mux_blsp2_uart,
+	msm_mux_blsp3_i2c,
+	msm_mux_blsp3_spi,
+	msm_mux_blsp3_uart,
+	msm_mux_blsp4_i2c,
+	msm_mux_blsp4_spi,
+	msm_mux_blsp4_uart,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_uart,
+	msm_mux_cri_trng0,
+	msm_mux_cri_trng1,
+	msm_mux_cri_trng2,
+	msm_mux_cri_trng3,
+	msm_mux_cxc0,
+	msm_mux_cxc1,
+	msm_mux_dbg_out,
+	msm_mux_dwc_ddrphy,
+	msm_mux_gcc_plltest,
+	msm_mux_gcc_tlmm,
+	msm_mux_gpio,
+	msm_mux_mac00,
+	msm_mux_mac01,
+	msm_mux_mac10,
+	msm_mux_mac11,
+	msm_mux_mdc,
+	msm_mux_mdio,
+	msm_mux_pcie0_clk,
+	msm_mux_pcie0_wake,
+	msm_mux_pcie1_clk,
+	msm_mux_pcie1_wake,
+	msm_mux_pcie2_clk,
+	msm_mux_pcie2_wake,
+	msm_mux_pcie3_clk,
+	msm_mux_pcie3_wake,
+	msm_mux_prng_rosc0,
+	msm_mux_prng_rosc1,
+	msm_mux_prng_rosc2,
+	msm_mux_prng_rosc3,
+	msm_mux_pta1_0,
+	msm_mux_pta1_1,
+	msm_mux_pta1_2,
+	msm_mux_pta20,
+	msm_mux_pta21,
+	msm_mux_pwm00,
+	msm_mux_pwm01,
+	msm_mux_pwm02,
+	msm_mux_pwm03,
+	msm_mux_pwm04,
+	msm_mux_pwm10,
+	msm_mux_pwm11,
+	msm_mux_pwm12,
+	msm_mux_pwm13,
+	msm_mux_pwm14,
+	msm_mux_pwm20,
+	msm_mux_pwm21,
+	msm_mux_pwm22,
+	msm_mux_pwm23,
+	msm_mux_pwm24,
+	msm_mux_pwm30,
+	msm_mux_pwm31,
+	msm_mux_pwm32,
+	msm_mux_pwm33,
+	msm_mux_qdss_cti_trig_in_a0,
+	msm_mux_qdss_cti_trig_in_a1,
+	msm_mux_qdss_cti_trig_in_b0,
+	msm_mux_qdss_cti_trig_in_b1,
+	msm_mux_qdss_cti_trig_out_a0,
+	msm_mux_qdss_cti_trig_out_a1,
+	msm_mux_qdss_cti_trig_out_b0,
+	msm_mux_qdss_cti_trig_out_b1,
+	msm_mux_qdss_traceclk_a,
+	msm_mux_qdss_traceclk_b,
+	msm_mux_qdss_tracectl_a,
+	msm_mux_qdss_tracectl_b,
+	msm_mux_qdss_tracedata_a,
+	msm_mux_qdss_tracedata_b,
+	msm_mux_qspi_data,
+	msm_mux_qspi_clk,
+	msm_mux_qspi_cs,
+	msm_mux_rx0,
+	msm_mux_rx1,
+	msm_mux_sdc_data,
+	msm_mux_sdc_clk,
+	msm_mux_sdc_cmd,
+	msm_mux_sdc_rclk,
+	msm_mux_tsens_max,
+	msm_mux_wci20,
+	msm_mux_wci21,
+	msm_mux_wsa_swrm,
+	msm_mux__,
+};
+
+static const char * const gpio_groups[] = {
+	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+	"gpio64",
+};
+
+static const char * const sdc_data_groups[] = {
+	"gpio0",
+	"gpio1",
+	"gpio2",
+	"gpio3",
+	"gpio6",
+	"gpio7",
+	"gpio8",
+	"gpio9",
+};
+
+static const char * const qspi_data_groups[] = {
+	"gpio0",
+	"gpio1",
+	"gpio2",
+	"gpio3",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+	"gpio0",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+	"gpio1",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+	"gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
+	"gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
+	"gpio17",
+};
+
+static const char * const sdc_cmd_groups[] = {
+	"gpio4",
+};
+
+static const char * const qspi_cs_groups[] = {
+	"gpio4",
+};
+
+static const char * const sdc_clk_groups[] = {
+	"gpio5",
+};
+
+static const char * const qspi_clk_groups[] = {
+	"gpio5",
+};
+
+static const char * const sdc_rclk_groups[] = {
+	"gpio10",
+};
+
+static const char * const blsp0_spi_groups[] = {
+	"gpio11", "gpio12", "gpio13", "gpio14",
+};
+
+static const char * const blsp0_uart_groups[] = {
+	"gpio11", "gpio12", "gpio13", "gpio14",
+};
+
+static const char * const blsp3_spi_groups[] = {
+	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+};
+
+static const char * const blsp3_i2c_groups[] = {
+	"gpio15", "gpio16",
+};
+
+static const char * const blsp3_uart_groups[] = {
+	"gpio15", "gpio16", "gpio17", "gpio18",
+};
+
+static const char * const dbg_out_groups[] = {
+	"gpio17",
+};
+
+static const char * const cri_trng0_groups[] = {
+	"gpio20", "gpio38",
+};
+
+static const char * const cri_trng1_groups[] = {
+	"gpio21", "gpio34",
+};
+
+static const char * const pcie0_clk_groups[] = {
+	"gpio22",
+};
+
+static const char * const pta20_groups[] = {
+	"gpio22", "gpio23", "gpio24",
+};
+
+static const char * const wci21_groups[] = {
+	"gpio23", "gpio24",
+};
+
+static const char * const cxc0_groups[] = {
+	"gpio23", "gpio24",
+};
+
+static const char * const pcie0_wake_groups[] = {
+	"gpio24",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+	"gpio24",
+};
+
+static const char * const pcie1_clk_groups[] = {
+	"gpio25",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+	"gpio25",
+};
+
+static const char * const atest_char0_groups[] = {
+	"gpio26",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+	"gpio26",
+};
+
+static const char * const pcie1_wake_groups[] = {
+	"gpio27",
+};
+
+static const char * const atest_char1_groups[] = {
+	"gpio27",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+	"gpio27",
+};
+
+static const char * const pcie2_clk_groups[] = {
+	"gpio28",
+};
+
+static const char * const atest_char2_groups[] = {
+	"gpio28",
+};
+
+static const char * const atest_char3_groups[] = {
+	"gpio29",
+};
+
+static const char * const pcie2_wake_groups[] = {
+	"gpio30",
+};
+
+static const char * const pwm01_groups[] = {
+	"gpio30",
+};
+
+static const char * const atest_char_groups[] = {
+	"gpio30",
+};
+
+static const char * const pcie3_clk_groups[] = {
+	"gpio31",
+};
+
+static const char * const pwm11_groups[] = {
+	"gpio31",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+	"gpio31",
+};
+
+static const char * const pwm21_groups[] = {
+	"gpio32",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+	"gpio32",
+};
+
+static const char * const pcie3_wake_groups[] = {
+	"gpio33",
+};
+
+static const char * const pwm31_groups[] = {
+	"gpio33",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+	"gpio33",
+};
+
+static const char * const blsp2_uart_groups[] = {
+	"gpio34", "gpio35",
+};
+
+static const char * const blsp2_i2c_groups[] = {
+	"gpio34", "gpio35",
+};
+
+static const char * const blsp2_spi_groups[] = {
+	"gpio34", "gpio35", "gpio36", "gpio37",
+};
+
+static const char * const blsp1_uart_groups[] = {
+	"gpio34", "gpio35", "gpio36", "gpio37",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+	"gpio34",
+};
+
+static const char * const cri_trng2_groups[] = {
+	"gpio35",
+};
+
+static const char * const blsp1_i2c_groups[] = {
+	"gpio36", "gpio37",
+};
+
+static const char * const cri_trng3_groups[] = {
+	"gpio36",
+};
+
+static const char * const dwc_ddrphy_groups[] = {
+	"gpio37",
+};
+
+static const char * const mdc_groups[] = {
+	"gpio38",
+};
+
+static const char * const mdio_groups[] = {
+	"gpio39",
+};
+
+static const char * const audio_pri_groups[] = {
+	"gpio40", "gpio41", "gpio42", "gpio43", "gpio61", "gpio61",
+};
+
+static const char * const audio_pdm0_groups[] = {
+	"gpio40", "gpio41", "gpio42", "gpio43",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+	"gpio43",
+};
+
+static const char * const pwm00_groups[] = {
+	"gpio44",
+};
+
+static const char * const audio_sec_groups[] = {
+	"gpio44", "gpio45", "gpio46", "gpio47", "gpio62", "gpio62",
+};
+
+static const char * const wsa_swrm_groups[] = {
+	"gpio44", "gpio45",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+	"gpio44",
+};
+
+static const char * const pwm10_groups[] = {
+	"gpio45",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+	"gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
+	"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
+	"gpio59", "gpio60",
+};
+
+static const char * const pwm20_groups[] = {
+	"gpio46",
+};
+
+static const char * const rx1_groups[] = {
+	"gpio46",
+};
+
+static const char * const mac00_groups[] = {
+	"gpio46",
+};
+
+static const char * const pwm30_groups[] = {
+	"gpio47",
+};
+
+static const char * const mac01_groups[] = {
+	"gpio47",
+};
+
+static const char * const blsp5_i2c_groups[] = {
+	"gpio48", "gpio49",
+};
+
+static const char * const blsp5_uart_groups[] = {
+	"gpio48", "gpio49",
+};
+
+static const char * const blsp4_uart_groups[] = {
+	"gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const blsp4_i2c_groups[] = {
+	"gpio50", "gpio51",
+};
+
+static const char * const blsp4_spi_groups[] = {
+	"gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const pwm02_groups[] = {
+	"gpio50",
+};
+
+static const char * const pwm12_groups[] = {
+	"gpio51",
+};
+
+static const char * const pwm22_groups[] = {
+	"gpio52",
+};
+
+static const char * const pwm32_groups[] = {
+	"gpio53",
+};
+
+static const char * const pta1_1_groups[] = {
+	"gpio54",
+};
+
+static const char * const pwm04_groups[] = {
+	"gpio54",
+};
+
+static const char * const pta1_2_groups[] = {
+	"gpio55",
+};
+
+static const char * const pwm14_groups[] = {
+	"gpio55",
+};
+
+static const char * const pta1_0_groups[] = {
+	"gpio56",
+};
+
+static const char * const pwm24_groups[] = {
+	"gpio56",
+};
+
+static const char * const wci20_groups[] = {
+	"gpio57", "gpio58",
+};
+
+static const char * const cxc1_groups[] = {
+	"gpio57", "gpio58",
+};
+
+static const char * const mac10_groups[] = {
+	"gpio57",
+};
+
+static const char * const pwm03_groups[] = {
+	"gpio57",
+};
+
+static const char * const mac11_groups[] = {
+	"gpio58",
+};
+
+static const char * const pwm13_groups[] = {
+	"gpio58",
+};
+
+static const char * const rx0_groups[] = {
+	"gpio59",
+};
+
+static const char * const pwm23_groups[] = {
+	"gpio59",
+};
+
+static const char * const pwm33_groups[] = {
+	"gpio60",
+};
+
+static const char * const prng_rosc0_groups[] = {
+	"gpio60",
+};
+
+static const char * const gcc_plltest_groups[] = {
+	"gpio60", "gpio62",
+};
+
+static const char * const blsp1_spi_groups[] = {
+	"gpio61", "gpio62", "gpio63", "gpio64",
+};
+
+static const char * const audio_pdm1_groups[] = {
+	"gpio61", "gpio62", "gpio63", "gpio64",
+};
+
+static const char * const pta21_groups[] = {
+	"gpio61", "gpio62", "gpio63",
+};
+
+static const char * const prng_rosc1_groups[] = {
+	"gpio61",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+	"gpio61",
+};
+
+static const char * const prng_rosc2_groups[] = {
+	"gpio62",
+};
+
+static const char * const prng_rosc3_groups[] = {
+	"gpio63",
+};
+
+static const char * const tsens_max_groups[] = {
+	"gpio64",
+};
+
+static const struct msm_function ipq9574_functions[] = {
+	FUNCTION(atest_char),
+	FUNCTION(atest_char0),
+	FUNCTION(atest_char1),
+	FUNCTION(atest_char2),
+	FUNCTION(atest_char3),
+	FUNCTION(audio_pdm0),
+	FUNCTION(audio_pdm1),
+	FUNCTION(audio_pri),
+	FUNCTION(audio_sec),
+	FUNCTION(blsp0_spi),
+	FUNCTION(blsp0_uart),
+	FUNCTION(blsp1_i2c),
+	FUNCTION(blsp1_spi),
+	FUNCTION(blsp1_uart),
+	FUNCTION(blsp2_i2c),
+	FUNCTION(blsp2_spi),
+	FUNCTION(blsp2_uart),
+	FUNCTION(blsp3_i2c),
+	FUNCTION(blsp3_spi),
+	FUNCTION(blsp3_uart),
+	FUNCTION(blsp4_i2c),
+	FUNCTION(blsp4_spi),
+	FUNCTION(blsp4_uart),
+	FUNCTION(blsp5_i2c),
+	FUNCTION(blsp5_uart),
+	FUNCTION(cri_trng0),
+	FUNCTION(cri_trng1),
+	FUNCTION(cri_trng2),
+	FUNCTION(cri_trng3),
+	FUNCTION(cxc0),
+	FUNCTION(cxc1),
+	FUNCTION(dbg_out),
+	FUNCTION(dwc_ddrphy),
+	FUNCTION(gcc_plltest),
+	FUNCTION(gcc_tlmm),
+	FUNCTION(gpio),
+	FUNCTION(mac00),
+	FUNCTION(mac01),
+	FUNCTION(mac10),
+	FUNCTION(mac11),
+	FUNCTION(mdc),
+	FUNCTION(mdio),
+	FUNCTION(pcie0_clk),
+	FUNCTION(pcie0_wake),
+	FUNCTION(pcie1_clk),
+	FUNCTION(pcie1_wake),
+	FUNCTION(pcie2_clk),
+	FUNCTION(pcie2_wake),
+	FUNCTION(pcie3_clk),
+	FUNCTION(pcie3_wake),
+	FUNCTION(prng_rosc0),
+	FUNCTION(prng_rosc1),
+	FUNCTION(prng_rosc2),
+	FUNCTION(prng_rosc3),
+	FUNCTION(pta1_0),
+	FUNCTION(pta1_1),
+	FUNCTION(pta1_2),
+	FUNCTION(pta20),
+	FUNCTION(pta21),
+	FUNCTION(pwm00),
+	FUNCTION(pwm01),
+	FUNCTION(pwm02),
+	FUNCTION(pwm03),
+	FUNCTION(pwm04),
+	FUNCTION(pwm10),
+	FUNCTION(pwm11),
+	FUNCTION(pwm12),
+	FUNCTION(pwm13),
+	FUNCTION(pwm14),
+	FUNCTION(pwm20),
+	FUNCTION(pwm21),
+	FUNCTION(pwm22),
+	FUNCTION(pwm23),
+	FUNCTION(pwm24),
+	FUNCTION(pwm30),
+	FUNCTION(pwm31),
+	FUNCTION(pwm32),
+	FUNCTION(pwm33),
+	FUNCTION(qdss_cti_trig_in_a0),
+	FUNCTION(qdss_cti_trig_in_a1),
+	FUNCTION(qdss_cti_trig_in_b0),
+	FUNCTION(qdss_cti_trig_in_b1),
+	FUNCTION(qdss_cti_trig_out_a0),
+	FUNCTION(qdss_cti_trig_out_a1),
+	FUNCTION(qdss_cti_trig_out_b0),
+	FUNCTION(qdss_cti_trig_out_b1),
+	FUNCTION(qdss_traceclk_a),
+	FUNCTION(qdss_traceclk_b),
+	FUNCTION(qdss_tracectl_a),
+	FUNCTION(qdss_tracectl_b),
+	FUNCTION(qdss_tracedata_a),
+	FUNCTION(qdss_tracedata_b),
+	FUNCTION(qspi_data),
+	FUNCTION(qspi_clk),
+	FUNCTION(qspi_cs),
+	FUNCTION(rx0),
+	FUNCTION(rx1),
+	FUNCTION(sdc_data),
+	FUNCTION(sdc_clk),
+	FUNCTION(sdc_cmd),
+	FUNCTION(sdc_rclk),
+	FUNCTION(tsens_max),
+	FUNCTION(wci20),
+	FUNCTION(wci21),
+	FUNCTION(wsa_swrm),
+};
+
+static const struct msm_pingroup ipq9574_groups[] = {
+	PINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _),
+	PINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _),
+	PINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
+	PINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
+	PINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _),
+	PINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _,
+		 _),
+	PINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _),
+	PINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
+		 _, _),
+	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
+		 _, _, _, _),
+	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
+		 _, _, _, _),
+	PINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _,
+		 _, _, _),
+	PINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _),
+	PINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _),
+	PINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _),
+	PINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _),
+	PINGROUP(22, pcie0_clk, _, pta20, _, _, _, _, _, _),
+	PINGROUP(23, _, pta20, wci21, cxc0, _, _, _, _, _),
+	PINGROUP(24, pcie0_wake, _, pta20, wci21, cxc0, _,
+		 qdss_cti_trig_out_b0, _, _),
+	PINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _,
+		 _),
+	PINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _,
+		 _),
+	PINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _,
+		 _, _, _),
+	PINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _),
+	PINGROUP(29, atest_char3, _, _, _, _, _, _, _, _),
+	PINGROUP(30, pcie2_wake, pwm01, atest_char, _, _, _, _, _, _),
+	PINGROUP(31, pcie3_clk, pwm11, _, qdss_cti_trig_in_a1, _, _, _, _,
+		 _),
+	PINGROUP(32, pwm21, _, qdss_cti_trig_out_a1, _, _, _, _, _, _),
+	PINGROUP(33, pcie3_wake, pwm31, _, qdss_cti_trig_in_a0, _, _, _,
+		 _, _),
+	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
+		 cri_trng1, qdss_cti_trig_out_a0, _, _),
+	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
+		 cri_trng2, _, _, _),
+	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _,
+		 _, _),
+	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _,
+		 _, _),
+	PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _),
+	PINGROUP(39, mdio, _, _, _, _, _, _, _, _),
+	PINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
+	PINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
+	PINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
+	PINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _,
+		 _, _),
+	PINGROUP(44, pwm00, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _,
+		 _, _),
+	PINGROUP(45, pwm10, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _,
+		 _, _),
+	PINGROUP(46, pwm20, audio_sec, rx1, mac00, _, qdss_tracedata_a, _,
+		 _, _),
+	PINGROUP(47, pwm30, audio_sec, mac01, _, qdss_tracedata_a, _, _, _,
+		 _),
+	PINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
+		 _, _),
+	PINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
+		 _, _),
+	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm02, qdss_tracedata_a,
+		 _, _, _, _),
+	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm12, qdss_tracedata_a,
+		 _, _, _, _),
+	PINGROUP(52, blsp4_uart, blsp4_spi, pwm22, qdss_tracedata_a, _, _,
+		 _, _, _),
+	PINGROUP(53, blsp4_uart, blsp4_spi, pwm32, qdss_tracedata_a, _, _,
+		 _, _, _),
+	PINGROUP(54, pta1_1, pwm04, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(55, pta1_2, pwm14, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(56, pta1_0, pwm24, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(57, wci20, cxc1, mac10, pwm03, qdss_tracedata_a, _, _, _,
+		 _),
+	PINGROUP(58, wci20, cxc1, mac11, pwm13, qdss_tracedata_a, _, _, _,
+		 _),
+	PINGROUP(59, rx0, pwm23, qdss_tracedata_a, _, _, _, _, _, _),
+	PINGROUP(60, pwm33, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _,
+		 _, _, _),
+	PINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta21,
+		 prng_rosc1, gcc_tlmm, _, _),
+	PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta21,
+		 prng_rosc2, gcc_plltest, _, _),
+	PINGROUP(63, blsp1_spi, audio_pdm1, pta21, prng_rosc3, _, _, _, _,
+		 _),
+	PINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _),
+};
+
+static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {
+	.pins = ipq9574_pins,
+	.npins = ARRAY_SIZE(ipq9574_pins),
+	.functions = ipq9574_functions,
+	.nfunctions = ARRAY_SIZE(ipq9574_functions),
+	.groups = ipq9574_groups,
+	.ngroups = ARRAY_SIZE(ipq9574_groups),
+	.ngpios = 65,
+};
+
+static int ipq9574_pinctrl_probe(struct platform_device *pdev)
+{
+	return msm_pinctrl_probe(pdev, &ipq9574_pinctrl);
+}
+
+static const struct of_device_id ipq9574_pinctrl_of_match[] = {
+	{ .compatible = "qcom,ipq9574-tlmm", },
+	{ },
+};
+
+static struct platform_driver ipq9574_pinctrl_driver = {
+	.driver = {
+		.name = "ipq9574-tlmm",
+		.owner = THIS_MODULE,
+		.of_match_table = ipq9574_pinctrl_of_match,
+	},
+	.probe = ipq9574_pinctrl_probe,
+	.remove = msm_pinctrl_remove,
+};
+
+static int __init ipq9574_pinctrl_init(void)
+{
+	return platform_driver_register(&ipq9574_pinctrl_driver);
+}
+arch_initcall(ipq9574_pinctrl_init);
+
+static void __exit ipq9574_pinctrl_exit(void)
+{
+	platform_driver_unregister(&ipq9574_pinctrl_driver);
+}
+module_exit(ipq9574_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver");
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);
-- 
2.17.1

Re: [PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Add pinctrl definitions for the TLMM of IPQ9574
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  drivers/pinctrl/qcom/Kconfig           |   10 +
>  drivers/pinctrl/qcom/Makefile          |    1 +
>  drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
>  3 files changed, 1014 insertions(+)
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
> 
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 1378ddca084f..a9b4b07e3de0 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
>  	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
>  	  IPQ6018.
>  
> +config PINCTRL_IPQ9574
> +	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
> +	depends on GPIOLIB && OF

Look at other entries and use similar style.

Best regards,
Krzysztof


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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Add pinctrl definitions for the TLMM of IPQ9574
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  drivers/pinctrl/qcom/Kconfig           |   10 +
>  drivers/pinctrl/qcom/Makefile          |    1 +
>  drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
>  3 files changed, 1014 insertions(+)
>  create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
> 
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 1378ddca084f..a9b4b07e3de0 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
>  	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
>  	  IPQ6018.
>  
> +config PINCTRL_IPQ9574
> +	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
> +	depends on GPIOLIB && OF

Look at other entries and use similar style.

Best regards,
Krzysztof

Re: [PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[Devi Priya]

On 1/11/2023 3:16 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Add pinctrl definitions for the TLMM of IPQ9574
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/pinctrl/qcom/Kconfig           |   10 +
>>   drivers/pinctrl/qcom/Makefile          |    1 +
>>   drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
>>   3 files changed, 1014 insertions(+)
>>   create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index 1378ddca084f..a9b4b07e3de0 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
>>   	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
>>   	  IPQ6018.
>>   
>> +config PINCTRL_IPQ9574
>> +	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
>> +	depends on GPIOLIB && OF
> 
> Look at other entries and use similar style.
Sure, will do!
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
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Re: [PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[Devi Priya]

On 1/11/2023 3:16 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Add pinctrl definitions for the TLMM of IPQ9574
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   drivers/pinctrl/qcom/Kconfig           |   10 +
>>   drivers/pinctrl/qcom/Makefile          |    1 +
>>   drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
>>   3 files changed, 1014 insertions(+)
>>   create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
>>
>> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
>> index 1378ddca084f..a9b4b07e3de0 100644
>> --- a/drivers/pinctrl/qcom/Kconfig
>> +++ b/drivers/pinctrl/qcom/Kconfig
>> @@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
>>   	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
>>   	  IPQ6018.
>>   
>> +config PINCTRL_IPQ9574
>> +	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
>> +	depends on GPIOLIB && OF
> 
> Look at other entries and use similar style.
Sure, will do!
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

Re: [PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[Kathiravan Thirumoorthy]

On 1/10/2023 5:43 PM, devi priya wrote:
> Add pinctrl definitions for the TLMM of IPQ9574
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>   drivers/pinctrl/qcom/Kconfig           |   10 +
>   drivers/pinctrl/qcom/Makefile          |    1 +
>   drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
>   3 files changed, 1014 insertions(+)
>   create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 1378ddca084f..a9b4b07e3de0 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
>   	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
>   	  IPQ6018.
>   
> +config PINCTRL_IPQ9574
> +	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
> +	depends on GPIOLIB && OF
> +	select PINCTRL_MSM
> +	help
> +	  This is the pinctrl, pinmux, pinconf and gpiolib driver for
> +          the Qualcomm Technologies Inc. TLMM block found on the
> +          Qualcomm Technologies Inc. IPQ9574 platform. Select this for
> +          IPQ9574.
> +
>   config PINCTRL_MSM8226
>   	tristate "Qualcomm 8226 pin controller driver"
>   	depends on OF
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index a5c40f552e5c..717c8b8000ba 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019)	+= pinctrl-ipq4019.o
>   obj-$(CONFIG_PINCTRL_IPQ8064)	+= pinctrl-ipq8064.o
>   obj-$(CONFIG_PINCTRL_IPQ8074)	+= pinctrl-ipq8074.o
>   obj-$(CONFIG_PINCTRL_IPQ6018)	+= pinctrl-ipq6018.o
> +obj-$(CONFIG_PINCTRL_IPQ9574)   += pinctrl-ipq9574.o
>   obj-$(CONFIG_PINCTRL_MSM8226)	+= pinctrl-msm8226.o
>   obj-$(CONFIG_PINCTRL_MSM8660)	+= pinctrl-msm8660.o
>   obj-$(CONFIG_PINCTRL_MSM8960)	+= pinctrl-msm8960.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
> new file mode 100644
> index 000000000000..48be36279939
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
> @@ -0,0 +1,1003 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2022 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-msm.h"
> +
> +#define FUNCTION(fname)			                \
> +	[msm_mux_##fname] = {		                \
> +		.name = #fname,				\
> +		.groups = fname##_groups,               \
> +		.ngroups = ARRAY_SIZE(fname##_groups),	\
> +	}
> +
> +#define REG_SIZE 0x1000
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
> +	{					        \
> +		.name = "gpio" #id,			\
> +		.pins = gpio##id##_pins,		\
> +		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
> +		.funcs = (int[]){			\
> +			msm_mux_gpio, /* gpio mode */	\
> +			msm_mux_##f1,			\
> +			msm_mux_##f2,			\
> +			msm_mux_##f3,			\
> +			msm_mux_##f4,			\
> +			msm_mux_##f5,			\
> +			msm_mux_##f6,			\
> +			msm_mux_##f7,			\
> +			msm_mux_##f8,			\
> +			msm_mux_##f9			\
> +		},				        \
> +		.nfuncs = 10,				\
> +		.ctl_reg = REG_SIZE * id,			\
> +		.io_reg = 0x4 + REG_SIZE * id,		\
> +		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
> +		.intr_status_reg = 0xc + REG_SIZE * id,	\
> +		.intr_target_reg = 0x8 + REG_SIZE * id,	\
> +		.mux_bit = 2,			\
> +		.pull_bit = 0,			\
> +		.drv_bit = 6,			\
> +		.oe_bit = 9,			\
> +		.in_bit = 0,			\
> +		.out_bit = 1,			\
> +		.intr_enable_bit = 0,		\
> +		.intr_status_bit = 0,		\
> +		.intr_target_bit = 5,		\
> +		.intr_target_kpss_val = 3,	\
> +		.intr_raw_status_bit = 4,	\
> +		.intr_polarity_bit = 1,		\
> +		.intr_detection_bit = 2,	\
> +		.intr_detection_width = 2,	\
> +	}
> +
> +static const struct pinctrl_pin_desc ipq9574_pins[] = {
> +	PINCTRL_PIN(0, "GPIO_0"),
> +	PINCTRL_PIN(1, "GPIO_1"),
> +	PINCTRL_PIN(2, "GPIO_2"),
> +	PINCTRL_PIN(3, "GPIO_3"),
> +	PINCTRL_PIN(4, "GPIO_4"),
> +	PINCTRL_PIN(5, "GPIO_5"),
> +	PINCTRL_PIN(6, "GPIO_6"),
> +	PINCTRL_PIN(7, "GPIO_7"),
> +	PINCTRL_PIN(8, "GPIO_8"),
> +	PINCTRL_PIN(9, "GPIO_9"),
> +	PINCTRL_PIN(10, "GPIO_10"),
> +	PINCTRL_PIN(11, "GPIO_11"),
> +	PINCTRL_PIN(12, "GPIO_12"),
> +	PINCTRL_PIN(13, "GPIO_13"),
> +	PINCTRL_PIN(14, "GPIO_14"),
> +	PINCTRL_PIN(15, "GPIO_15"),
> +	PINCTRL_PIN(16, "GPIO_16"),
> +	PINCTRL_PIN(17, "GPIO_17"),
> +	PINCTRL_PIN(18, "GPIO_18"),
> +	PINCTRL_PIN(19, "GPIO_19"),
> +	PINCTRL_PIN(20, "GPIO_20"),
> +	PINCTRL_PIN(21, "GPIO_21"),
> +	PINCTRL_PIN(22, "GPIO_22"),
> +	PINCTRL_PIN(23, "GPIO_23"),
> +	PINCTRL_PIN(24, "GPIO_24"),
> +	PINCTRL_PIN(25, "GPIO_25"),
> +	PINCTRL_PIN(26, "GPIO_26"),
> +	PINCTRL_PIN(27, "GPIO_27"),
> +	PINCTRL_PIN(28, "GPIO_28"),
> +	PINCTRL_PIN(29, "GPIO_29"),
> +	PINCTRL_PIN(30, "GPIO_30"),
> +	PINCTRL_PIN(31, "GPIO_31"),
> +	PINCTRL_PIN(32, "GPIO_32"),
> +	PINCTRL_PIN(33, "GPIO_33"),
> +	PINCTRL_PIN(34, "GPIO_34"),
> +	PINCTRL_PIN(35, "GPIO_35"),
> +	PINCTRL_PIN(36, "GPIO_36"),
> +	PINCTRL_PIN(37, "GPIO_37"),
> +	PINCTRL_PIN(38, "GPIO_38"),
> +	PINCTRL_PIN(39, "GPIO_39"),
> +	PINCTRL_PIN(40, "GPIO_40"),
> +	PINCTRL_PIN(41, "GPIO_41"),
> +	PINCTRL_PIN(42, "GPIO_42"),
> +	PINCTRL_PIN(43, "GPIO_43"),
> +	PINCTRL_PIN(44, "GPIO_44"),
> +	PINCTRL_PIN(45, "GPIO_45"),
> +	PINCTRL_PIN(46, "GPIO_46"),
> +	PINCTRL_PIN(47, "GPIO_47"),
> +	PINCTRL_PIN(48, "GPIO_48"),
> +	PINCTRL_PIN(49, "GPIO_49"),
> +	PINCTRL_PIN(50, "GPIO_50"),
> +	PINCTRL_PIN(51, "GPIO_51"),
> +	PINCTRL_PIN(52, "GPIO_52"),
> +	PINCTRL_PIN(53, "GPIO_53"),
> +	PINCTRL_PIN(54, "GPIO_54"),
> +	PINCTRL_PIN(55, "GPIO_55"),
> +	PINCTRL_PIN(56, "GPIO_56"),
> +	PINCTRL_PIN(57, "GPIO_57"),
> +	PINCTRL_PIN(58, "GPIO_58"),
> +	PINCTRL_PIN(59, "GPIO_59"),
> +	PINCTRL_PIN(60, "GPIO_60"),
> +	PINCTRL_PIN(61, "GPIO_61"),
> +	PINCTRL_PIN(62, "GPIO_62"),
> +	PINCTRL_PIN(63, "GPIO_63"),
> +	PINCTRL_PIN(64, "GPIO_64"),
> +};
> +
> +#define DECLARE_MSM_GPIO_PINS(pin) \
> +	static const unsigned int gpio##pin##_pins[] = { pin }
> +DECLARE_MSM_GPIO_PINS(0);
> +DECLARE_MSM_GPIO_PINS(1);
> +DECLARE_MSM_GPIO_PINS(2);
> +DECLARE_MSM_GPIO_PINS(3);
> +DECLARE_MSM_GPIO_PINS(4);
> +DECLARE_MSM_GPIO_PINS(5);
> +DECLARE_MSM_GPIO_PINS(6);
> +DECLARE_MSM_GPIO_PINS(7);
> +DECLARE_MSM_GPIO_PINS(8);
> +DECLARE_MSM_GPIO_PINS(9);
> +DECLARE_MSM_GPIO_PINS(10);
> +DECLARE_MSM_GPIO_PINS(11);
> +DECLARE_MSM_GPIO_PINS(12);
> +DECLARE_MSM_GPIO_PINS(13);
> +DECLARE_MSM_GPIO_PINS(14);
> +DECLARE_MSM_GPIO_PINS(15);
> +DECLARE_MSM_GPIO_PINS(16);
> +DECLARE_MSM_GPIO_PINS(17);
> +DECLARE_MSM_GPIO_PINS(18);
> +DECLARE_MSM_GPIO_PINS(19);
> +DECLARE_MSM_GPIO_PINS(20);
> +DECLARE_MSM_GPIO_PINS(21);
> +DECLARE_MSM_GPIO_PINS(22);
> +DECLARE_MSM_GPIO_PINS(23);
> +DECLARE_MSM_GPIO_PINS(24);
> +DECLARE_MSM_GPIO_PINS(25);
> +DECLARE_MSM_GPIO_PINS(26);
> +DECLARE_MSM_GPIO_PINS(27);
> +DECLARE_MSM_GPIO_PINS(28);
> +DECLARE_MSM_GPIO_PINS(29);
> +DECLARE_MSM_GPIO_PINS(30);
> +DECLARE_MSM_GPIO_PINS(31);
> +DECLARE_MSM_GPIO_PINS(32);
> +DECLARE_MSM_GPIO_PINS(33);
> +DECLARE_MSM_GPIO_PINS(34);
> +DECLARE_MSM_GPIO_PINS(35);
> +DECLARE_MSM_GPIO_PINS(36);
> +DECLARE_MSM_GPIO_PINS(37);
> +DECLARE_MSM_GPIO_PINS(38);
> +DECLARE_MSM_GPIO_PINS(39);
> +DECLARE_MSM_GPIO_PINS(40);
> +DECLARE_MSM_GPIO_PINS(41);
> +DECLARE_MSM_GPIO_PINS(42);
> +DECLARE_MSM_GPIO_PINS(43);
> +DECLARE_MSM_GPIO_PINS(44);
> +DECLARE_MSM_GPIO_PINS(45);
> +DECLARE_MSM_GPIO_PINS(46);
> +DECLARE_MSM_GPIO_PINS(47);
> +DECLARE_MSM_GPIO_PINS(48);
> +DECLARE_MSM_GPIO_PINS(49);
> +DECLARE_MSM_GPIO_PINS(50);
> +DECLARE_MSM_GPIO_PINS(51);
> +DECLARE_MSM_GPIO_PINS(52);
> +DECLARE_MSM_GPIO_PINS(53);
> +DECLARE_MSM_GPIO_PINS(54);
> +DECLARE_MSM_GPIO_PINS(55);
> +DECLARE_MSM_GPIO_PINS(56);
> +DECLARE_MSM_GPIO_PINS(57);
> +DECLARE_MSM_GPIO_PINS(58);
> +DECLARE_MSM_GPIO_PINS(59);
> +DECLARE_MSM_GPIO_PINS(60);
> +DECLARE_MSM_GPIO_PINS(61);
> +DECLARE_MSM_GPIO_PINS(62);
> +DECLARE_MSM_GPIO_PINS(63);
> +DECLARE_MSM_GPIO_PINS(64);
> +
> +enum ipq9574_functions {
> +	msm_mux_atest_char,
> +	msm_mux_atest_char0,
> +	msm_mux_atest_char1,
> +	msm_mux_atest_char2,
> +	msm_mux_atest_char3,
> +	msm_mux_audio_pdm0,
> +	msm_mux_audio_pdm1,
> +	msm_mux_audio_pri,
> +	msm_mux_audio_sec,
> +	msm_mux_blsp0_spi,
> +	msm_mux_blsp0_uart,
> +	msm_mux_blsp1_i2c,
> +	msm_mux_blsp1_spi,
> +	msm_mux_blsp1_uart,
> +	msm_mux_blsp2_i2c,
> +	msm_mux_blsp2_spi,
> +	msm_mux_blsp2_uart,
> +	msm_mux_blsp3_i2c,
> +	msm_mux_blsp3_spi,
> +	msm_mux_blsp3_uart,
> +	msm_mux_blsp4_i2c,
> +	msm_mux_blsp4_spi,
> +	msm_mux_blsp4_uart,
> +	msm_mux_blsp5_i2c,
> +	msm_mux_blsp5_uart,
> +	msm_mux_cri_trng0,
> +	msm_mux_cri_trng1,
> +	msm_mux_cri_trng2,
> +	msm_mux_cri_trng3,
> +	msm_mux_cxc0,
> +	msm_mux_cxc1,
> +	msm_mux_dbg_out,
> +	msm_mux_dwc_ddrphy,
> +	msm_mux_gcc_plltest,
> +	msm_mux_gcc_tlmm,
> +	msm_mux_gpio,
> +	msm_mux_mac00,
> +	msm_mux_mac01,
> +	msm_mux_mac10,
> +	msm_mux_mac11,
> +	msm_mux_mdc,
> +	msm_mux_mdio,
> +	msm_mux_pcie0_clk,
> +	msm_mux_pcie0_wake,
> +	msm_mux_pcie1_clk,
> +	msm_mux_pcie1_wake,
> +	msm_mux_pcie2_clk,
> +	msm_mux_pcie2_wake,
> +	msm_mux_pcie3_clk,
> +	msm_mux_pcie3_wake,
> +	msm_mux_prng_rosc0,
> +	msm_mux_prng_rosc1,
> +	msm_mux_prng_rosc2,
> +	msm_mux_prng_rosc3,
> +	msm_mux_pta1_0,
> +	msm_mux_pta1_1,
> +	msm_mux_pta1_2,
> +	msm_mux_pta20,
> +	msm_mux_pta21,
> +	msm_mux_pwm00,
> +	msm_mux_pwm01,
> +	msm_mux_pwm02,
> +	msm_mux_pwm03,
> +	msm_mux_pwm04,
> +	msm_mux_pwm10,
> +	msm_mux_pwm11,
> +	msm_mux_pwm12,
> +	msm_mux_pwm13,
> +	msm_mux_pwm14,
> +	msm_mux_pwm20,
> +	msm_mux_pwm21,
> +	msm_mux_pwm22,
> +	msm_mux_pwm23,
> +	msm_mux_pwm24,
> +	msm_mux_pwm30,
> +	msm_mux_pwm31,
> +	msm_mux_pwm32,
> +	msm_mux_pwm33,
> +	msm_mux_qdss_cti_trig_in_a0,
> +	msm_mux_qdss_cti_trig_in_a1,
> +	msm_mux_qdss_cti_trig_in_b0,
> +	msm_mux_qdss_cti_trig_in_b1,
> +	msm_mux_qdss_cti_trig_out_a0,
> +	msm_mux_qdss_cti_trig_out_a1,
> +	msm_mux_qdss_cti_trig_out_b0,
> +	msm_mux_qdss_cti_trig_out_b1,
> +	msm_mux_qdss_traceclk_a,
> +	msm_mux_qdss_traceclk_b,
> +	msm_mux_qdss_tracectl_a,
> +	msm_mux_qdss_tracectl_b,
> +	msm_mux_qdss_tracedata_a,
> +	msm_mux_qdss_tracedata_b,
> +	msm_mux_qspi_data,
> +	msm_mux_qspi_clk,
> +	msm_mux_qspi_cs,
> +	msm_mux_rx0,
> +	msm_mux_rx1,
> +	msm_mux_sdc_data,
> +	msm_mux_sdc_clk,
> +	msm_mux_sdc_cmd,
> +	msm_mux_sdc_rclk,
> +	msm_mux_tsens_max,
> +	msm_mux_wci20,
> +	msm_mux_wci21,
> +	msm_mux_wsa_swrm,
> +	msm_mux__,
> +};
> +
> +static const char * const gpio_groups[] = {
> +	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> +	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> +	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> +	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> +	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> +	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> +	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> +	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> +	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> +	"gpio64",
> +};
> +
> +static const char * const sdc_data_groups[] = {
> +	"gpio0",
> +	"gpio1",
> +	"gpio2",
> +	"gpio3",
> +	"gpio6",
> +	"gpio7",
> +	"gpio8",
> +	"gpio9",
> +};
> +
> +static const char * const qspi_data_groups[] = {
> +	"gpio0",
> +	"gpio1",
> +	"gpio2",
> +	"gpio3",
> +};
> +
> +static const char * const qdss_traceclk_b_groups[] = {
> +	"gpio0",
> +};
> +
> +static const char * const qdss_tracectl_b_groups[] = {
> +	"gpio1",
> +};
> +
> +static const char * const qdss_tracedata_b_groups[] = {
> +	"gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
> +	"gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
> +	"gpio17",
> +};
> +
> +static const char * const sdc_cmd_groups[] = {
> +	"gpio4",
> +};
> +
> +static const char * const qspi_cs_groups[] = {
> +	"gpio4",
> +};
> +
> +static const char * const sdc_clk_groups[] = {
> +	"gpio5",
> +};
> +
> +static const char * const qspi_clk_groups[] = {
> +	"gpio5",
> +};
> +
> +static const char * const sdc_rclk_groups[] = {
> +	"gpio10",
> +};
> +
> +static const char * const blsp0_spi_groups[] = {
> +	"gpio11", "gpio12", "gpio13", "gpio14",
> +};
> +
> +static const char * const blsp0_uart_groups[] = {
> +	"gpio11", "gpio12", "gpio13", "gpio14",
> +};
> +
> +static const char * const blsp3_spi_groups[] = {
> +	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> +};
> +
> +static const char * const blsp3_i2c_groups[] = {
> +	"gpio15", "gpio16",
> +};
> +
> +static const char * const blsp3_uart_groups[] = {
> +	"gpio15", "gpio16", "gpio17", "gpio18",
> +};
> +
> +static const char * const dbg_out_groups[] = {
> +	"gpio17",
> +};
> +
> +static const char * const cri_trng0_groups[] = {
> +	"gpio20", "gpio38",
> +};
> +
> +static const char * const cri_trng1_groups[] = {
> +	"gpio21", "gpio34",
> +};
> +
> +static const char * const pcie0_clk_groups[] = {
> +	"gpio22",
> +};
> +
> +static const char * const pta20_groups[] = {
> +	"gpio22", "gpio23", "gpio24",
> +};
> +
> +static const char * const wci21_groups[] = {
> +	"gpio23", "gpio24",
> +};
> +
> +static const char * const cxc0_groups[] = {
> +	"gpio23", "gpio24",
> +};
> +
> +static const char * const pcie0_wake_groups[] = {
> +	"gpio24",
> +};
> +
> +static const char * const qdss_cti_trig_out_b0_groups[] = {
> +	"gpio24",
> +};
> +
> +static const char * const pcie1_clk_groups[] = {
> +	"gpio25",
> +};
> +
> +static const char * const qdss_cti_trig_in_b0_groups[] = {
> +	"gpio25",
> +};
> +
> +static const char * const atest_char0_groups[] = {
> +	"gpio26",
> +};
> +
> +static const char * const qdss_cti_trig_out_b1_groups[] = {
> +	"gpio26",
> +};
> +
> +static const char * const pcie1_wake_groups[] = {
> +	"gpio27",
> +};
> +
> +static const char * const atest_char1_groups[] = {
> +	"gpio27",
> +};
> +
> +static const char * const qdss_cti_trig_in_b1_groups[] = {
> +	"gpio27",
> +};
> +
> +static const char * const pcie2_clk_groups[] = {
> +	"gpio28",
> +};
> +
> +static const char * const atest_char2_groups[] = {
> +	"gpio28",
> +};
> +
> +static const char * const atest_char3_groups[] = {
> +	"gpio29",
> +};
> +
> +static const char * const pcie2_wake_groups[] = {
> +	"gpio30",
> +};
> +
> +static const char * const pwm01_groups[] = {
> +	"gpio30",
> +};
> +
> +static const char * const atest_char_groups[] = {
> +	"gpio30",
> +};
> +
> +static const char * const pcie3_clk_groups[] = {
> +	"gpio31",
> +};
> +
> +static const char * const pwm11_groups[] = {
> +	"gpio31",
> +};
> +
> +static const char * const qdss_cti_trig_in_a1_groups[] = {
> +	"gpio31",
> +};
> +
> +static const char * const pwm21_groups[] = {
> +	"gpio32",
> +};
> +
> +static const char * const qdss_cti_trig_out_a1_groups[] = {
> +	"gpio32",
> +};
> +
> +static const char * const pcie3_wake_groups[] = {
> +	"gpio33",
> +};
> +
> +static const char * const pwm31_groups[] = {
> +	"gpio33",
> +};
> +
> +static const char * const qdss_cti_trig_in_a0_groups[] = {
> +	"gpio33",
> +};
> +
> +static const char * const blsp2_uart_groups[] = {
> +	"gpio34", "gpio35",
> +};
> +
> +static const char * const blsp2_i2c_groups[] = {
> +	"gpio34", "gpio35",
> +};
> +
> +static const char * const blsp2_spi_groups[] = {
> +	"gpio34", "gpio35", "gpio36", "gpio37",
> +};
> +
> +static const char * const blsp1_uart_groups[] = {
> +	"gpio34", "gpio35", "gpio36", "gpio37",
> +};
> +
> +static const char * const qdss_cti_trig_out_a0_groups[] = {
> +	"gpio34",
> +};
> +
> +static const char * const cri_trng2_groups[] = {
> +	"gpio35",
> +};
> +
> +static const char * const blsp1_i2c_groups[] = {
> +	"gpio36", "gpio37",
> +};
> +
> +static const char * const cri_trng3_groups[] = {
> +	"gpio36",
> +};
> +
> +static const char * const dwc_ddrphy_groups[] = {
> +	"gpio37",
> +};
> +
> +static const char * const mdc_groups[] = {
> +	"gpio38",
> +};
> +
> +static const char * const mdio_groups[] = {
> +	"gpio39",
> +};
> +
> +static const char * const audio_pri_groups[] = {
> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio61", "gpio61",
> +};
> +
> +static const char * const audio_pdm0_groups[] = {
> +	"gpio40", "gpio41", "gpio42", "gpio43",
> +};
> +
> +static const char * const qdss_traceclk_a_groups[] = {
> +	"gpio43",
> +};
> +
> +static const char * const pwm00_groups[] = {
> +	"gpio44",
> +};
> +
> +static const char * const audio_sec_groups[] = {
> +	"gpio44", "gpio45", "gpio46", "gpio47", "gpio62", "gpio62",
> +};
> +
> +static const char * const wsa_swrm_groups[] = {
> +	"gpio44", "gpio45",
> +};
> +
> +static const char * const qdss_tracectl_a_groups[] = {
> +	"gpio44",
> +};
> +
> +static const char * const pwm10_groups[] = {
> +	"gpio45",
> +};
> +
> +static const char * const qdss_tracedata_a_groups[] = {
> +	"gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
> +	"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
> +	"gpio59", "gpio60",
> +};
> +
> +static const char * const pwm20_groups[] = {
> +	"gpio46",
> +};
> +
> +static const char * const rx1_groups[] = {
> +	"gpio46",
> +};
> +
> +static const char * const mac00_groups[] = {
> +	"gpio46",
> +};
> +
> +static const char * const pwm30_groups[] = {
> +	"gpio47",
> +};
> +
> +static const char * const mac01_groups[] = {
> +	"gpio47",
> +};
> +
> +static const char * const blsp5_i2c_groups[] = {
> +	"gpio48", "gpio49",
> +};
> +
> +static const char * const blsp5_uart_groups[] = {
> +	"gpio48", "gpio49",
> +};
> +
> +static const char * const blsp4_uart_groups[] = {
> +	"gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const blsp4_i2c_groups[] = {
> +	"gpio50", "gpio51",
> +};
> +
> +static const char * const blsp4_spi_groups[] = {
> +	"gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const pwm02_groups[] = {
> +	"gpio50",
> +};
> +
> +static const char * const pwm12_groups[] = {
> +	"gpio51",
> +};
> +
> +static const char * const pwm22_groups[] = {
> +	"gpio52",
> +};
> +
> +static const char * const pwm32_groups[] = {
> +	"gpio53",
> +};
> +
> +static const char * const pta1_1_groups[] = {
> +	"gpio54",
> +};
> +
> +static const char * const pwm04_groups[] = {
> +	"gpio54",
> +};
> +
> +static const char * const pta1_2_groups[] = {
> +	"gpio55",
> +};
> +
> +static const char * const pwm14_groups[] = {
> +	"gpio55",
> +};
> +
> +static const char * const pta1_0_groups[] = {
> +	"gpio56",
> +};
> +
> +static const char * const pwm24_groups[] = {
> +	"gpio56",
> +};
> +
> +static const char * const wci20_groups[] = {
> +	"gpio57", "gpio58",
> +};
> +
> +static const char * const cxc1_groups[] = {
> +	"gpio57", "gpio58",
> +};
> +
> +static const char * const mac10_groups[] = {
> +	"gpio57",
> +};
> +
> +static const char * const pwm03_groups[] = {
> +	"gpio57",
> +};
> +
> +static const char * const mac11_groups[] = {
> +	"gpio58",
> +};
> +
> +static const char * const pwm13_groups[] = {
> +	"gpio58",
> +};
> +
> +static const char * const rx0_groups[] = {
> +	"gpio59",
> +};
> +
> +static const char * const pwm23_groups[] = {
> +	"gpio59",
> +};
> +
> +static const char * const pwm33_groups[] = {
> +	"gpio60",
> +};
> +
> +static const char * const prng_rosc0_groups[] = {
> +	"gpio60",
> +};
> +
> +static const char * const gcc_plltest_groups[] = {
> +	"gpio60", "gpio62",
> +};
> +
> +static const char * const blsp1_spi_groups[] = {
> +	"gpio61", "gpio62", "gpio63", "gpio64",
> +};
> +
> +static const char * const audio_pdm1_groups[] = {
> +	"gpio61", "gpio62", "gpio63", "gpio64",
> +};
> +
> +static const char * const pta21_groups[] = {
> +	"gpio61", "gpio62", "gpio63",
> +};
> +
> +static const char * const prng_rosc1_groups[] = {
> +	"gpio61",
> +};
> +
> +static const char * const gcc_tlmm_groups[] = {
> +	"gpio61",
> +};
> +
> +static const char * const prng_rosc2_groups[] = {
> +	"gpio62",
> +};
> +
> +static const char * const prng_rosc3_groups[] = {
> +	"gpio63",
> +};
> +
> +static const char * const tsens_max_groups[] = {
> +	"gpio64",
> +};
> +
> +static const struct msm_function ipq9574_functions[] = {
> +	FUNCTION(atest_char),
> +	FUNCTION(atest_char0),
> +	FUNCTION(atest_char1),
> +	FUNCTION(atest_char2),
> +	FUNCTION(atest_char3),
> +	FUNCTION(audio_pdm0),
> +	FUNCTION(audio_pdm1),
> +	FUNCTION(audio_pri),
> +	FUNCTION(audio_sec),
> +	FUNCTION(blsp0_spi),
> +	FUNCTION(blsp0_uart),
> +	FUNCTION(blsp1_i2c),
> +	FUNCTION(blsp1_spi),
> +	FUNCTION(blsp1_uart),
> +	FUNCTION(blsp2_i2c),
> +	FUNCTION(blsp2_spi),
> +	FUNCTION(blsp2_uart),
> +	FUNCTION(blsp3_i2c),
> +	FUNCTION(blsp3_spi),
> +	FUNCTION(blsp3_uart),
> +	FUNCTION(blsp4_i2c),
> +	FUNCTION(blsp4_spi),
> +	FUNCTION(blsp4_uart),
> +	FUNCTION(blsp5_i2c),
> +	FUNCTION(blsp5_uart),
> +	FUNCTION(cri_trng0),
> +	FUNCTION(cri_trng1),
> +	FUNCTION(cri_trng2),
> +	FUNCTION(cri_trng3),
> +	FUNCTION(cxc0),
> +	FUNCTION(cxc1),
> +	FUNCTION(dbg_out),
> +	FUNCTION(dwc_ddrphy),
> +	FUNCTION(gcc_plltest),
> +	FUNCTION(gcc_tlmm),
> +	FUNCTION(gpio),
> +	FUNCTION(mac00),
> +	FUNCTION(mac01),
> +	FUNCTION(mac10),
> +	FUNCTION(mac11),
> +	FUNCTION(mdc),
> +	FUNCTION(mdio),
> +	FUNCTION(pcie0_clk),
> +	FUNCTION(pcie0_wake),
> +	FUNCTION(pcie1_clk),
> +	FUNCTION(pcie1_wake),
> +	FUNCTION(pcie2_clk),
> +	FUNCTION(pcie2_wake),
> +	FUNCTION(pcie3_clk),
> +	FUNCTION(pcie3_wake),
> +	FUNCTION(prng_rosc0),
> +	FUNCTION(prng_rosc1),
> +	FUNCTION(prng_rosc2),
> +	FUNCTION(prng_rosc3),
> +	FUNCTION(pta1_0),
> +	FUNCTION(pta1_1),
> +	FUNCTION(pta1_2),
> +	FUNCTION(pta20),
> +	FUNCTION(pta21),
> +	FUNCTION(pwm00),
> +	FUNCTION(pwm01),
> +	FUNCTION(pwm02),
> +	FUNCTION(pwm03),
> +	FUNCTION(pwm04),
> +	FUNCTION(pwm10),
> +	FUNCTION(pwm11),
> +	FUNCTION(pwm12),
> +	FUNCTION(pwm13),
> +	FUNCTION(pwm14),
> +	FUNCTION(pwm20),
> +	FUNCTION(pwm21),
> +	FUNCTION(pwm22),
> +	FUNCTION(pwm23),
> +	FUNCTION(pwm24),
> +	FUNCTION(pwm30),
> +	FUNCTION(pwm31),
> +	FUNCTION(pwm32),
> +	FUNCTION(pwm33),
> +	FUNCTION(qdss_cti_trig_in_a0),
> +	FUNCTION(qdss_cti_trig_in_a1),
> +	FUNCTION(qdss_cti_trig_in_b0),
> +	FUNCTION(qdss_cti_trig_in_b1),
> +	FUNCTION(qdss_cti_trig_out_a0),
> +	FUNCTION(qdss_cti_trig_out_a1),
> +	FUNCTION(qdss_cti_trig_out_b0),
> +	FUNCTION(qdss_cti_trig_out_b1),
> +	FUNCTION(qdss_traceclk_a),
> +	FUNCTION(qdss_traceclk_b),
> +	FUNCTION(qdss_tracectl_a),
> +	FUNCTION(qdss_tracectl_b),
> +	FUNCTION(qdss_tracedata_a),
> +	FUNCTION(qdss_tracedata_b),
> +	FUNCTION(qspi_data),
> +	FUNCTION(qspi_clk),
> +	FUNCTION(qspi_cs),
> +	FUNCTION(rx0),
> +	FUNCTION(rx1),
> +	FUNCTION(sdc_data),
> +	FUNCTION(sdc_clk),
> +	FUNCTION(sdc_cmd),
> +	FUNCTION(sdc_rclk),
> +	FUNCTION(tsens_max),
> +	FUNCTION(wci20),
> +	FUNCTION(wci21),
> +	FUNCTION(wsa_swrm),
> +};
> +
> +static const struct msm_pingroup ipq9574_groups[] = {
> +	PINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _),
> +	PINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _),
> +	PINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
> +	PINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
> +	PINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _),
> +	PINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _,
> +		 _),
> +	PINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
> +		 _, _, _, _),
> +	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
> +		 _, _, _, _),
> +	PINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _,
> +		 _, _, _),
> +	PINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _),
> +	PINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _),
> +	PINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _),
> +	PINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _),
> +	PINGROUP(22, pcie0_clk, _, pta20, _, _, _, _, _, _),
> +	PINGROUP(23, _, pta20, wci21, cxc0, _, _, _, _, _),
> +	PINGROUP(24, pcie0_wake, _, pta20, wci21, cxc0, _,
> +		 qdss_cti_trig_out_b0, _, _),
> +	PINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _,
> +		 _),
> +	PINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _,
> +		 _),
> +	PINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _,
> +		 _, _, _),
> +	PINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _),
> +	PINGROUP(29, atest_char3, _, _, _, _, _, _, _, _),
> +	PINGROUP(30, pcie2_wake, pwm01, atest_char, _, _, _, _, _, _),
> +	PINGROUP(31, pcie3_clk, pwm11, _, qdss_cti_trig_in_a1, _, _, _, _,
> +		 _),
> +	PINGROUP(32, pwm21, _, qdss_cti_trig_out_a1, _, _, _, _, _, _),
> +	PINGROUP(33, pcie3_wake, pwm31, _, qdss_cti_trig_in_a0, _, _, _,
> +		 _, _),
> +	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
> +		 cri_trng1, qdss_cti_trig_out_a0, _, _),
> +	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
> +		 cri_trng2, _, _, _),
> +	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _,
> +		 _, _),
> +	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _,
> +		 _, _),
> +	PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _),
> +	PINGROUP(39, mdio, _, _, _, _, _, _, _, _),
> +	PINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
> +	PINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
> +	PINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
> +	PINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _,
> +		 _, _),
> +	PINGROUP(44, pwm00, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _,
> +		 _, _),
> +	PINGROUP(45, pwm10, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _,
> +		 _, _),
> +	PINGROUP(46, pwm20, audio_sec, rx1, mac00, _, qdss_tracedata_a, _,
> +		 _, _),
> +	PINGROUP(47, pwm30, audio_sec, mac01, _, qdss_tracedata_a, _, _, _,
> +		 _),
> +	PINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
> +		 _, _),
> +	PINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
> +		 _, _),
> +	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm02, qdss_tracedata_a,
> +		 _, _, _, _),
> +	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm12, qdss_tracedata_a,
> +		 _, _, _, _),
> +	PINGROUP(52, blsp4_uart, blsp4_spi, pwm22, qdss_tracedata_a, _, _,
> +		 _, _, _),
> +	PINGROUP(53, blsp4_uart, blsp4_spi, pwm32, qdss_tracedata_a, _, _,
> +		 _, _, _),
> +	PINGROUP(54, pta1_1, pwm04, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(55, pta1_2, pwm14, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(56, pta1_0, pwm24, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(57, wci20, cxc1, mac10, pwm03, qdss_tracedata_a, _, _, _,
> +		 _),
> +	PINGROUP(58, wci20, cxc1, mac11, pwm13, qdss_tracedata_a, _, _, _,
> +		 _),
> +	PINGROUP(59, rx0, pwm23, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(60, pwm33, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _,
> +		 _, _, _),
> +	PINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta21,
> +		 prng_rosc1, gcc_tlmm, _, _),
> +	PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta21,
> +		 prng_rosc2, gcc_plltest, _, _),
> +	PINGROUP(63, blsp1_spi, audio_pdm1, pta21, prng_rosc3, _, _, _, _,
> +		 _),
> +	PINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _),
> +};
> +
> +static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {
> +	.pins = ipq9574_pins,
> +	.npins = ARRAY_SIZE(ipq9574_pins),
> +	.functions = ipq9574_functions,
> +	.nfunctions = ARRAY_SIZE(ipq9574_functions),
> +	.groups = ipq9574_groups,
> +	.ngroups = ARRAY_SIZE(ipq9574_groups),
> +	.ngpios = 65,
> +};
> +
> +static int ipq9574_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return msm_pinctrl_probe(pdev, &ipq9574_pinctrl);
> +}
> +
> +static const struct of_device_id ipq9574_pinctrl_of_match[] = {
> +	{ .compatible = "qcom,ipq9574-tlmm", },
> +	{ },
> +};
> +
> +static struct platform_driver ipq9574_pinctrl_driver = {
> +	.driver = {
> +		.name = "ipq9574-tlmm",
> +		.owner = THIS_MODULE,


Please drop the .owner field, it is taken care by 
platform_driver_register().


> +		.of_match_table = ipq9574_pinctrl_of_match,
> +	},
> +	.probe = ipq9574_pinctrl_probe,
> +	.remove = msm_pinctrl_remove,
> +};
> +
> +static int __init ipq9574_pinctrl_init(void)
> +{
> +	return platform_driver_register(&ipq9574_pinctrl_driver);
> +}
> +arch_initcall(ipq9574_pinctrl_init);
> +
> +static void __exit ipq9574_pinctrl_exit(void)
> +{
> +	platform_driver_unregister(&ipq9574_pinctrl_driver);
> +}
> +module_exit(ipq9574_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver");
> +MODULE_LICENSE("GPL");
> +MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);

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Re: [PATCH 4/7] pinctrl: qcom: Add IPQ9574 pinctrl driver

[Kathiravan Thirumoorthy]

On 1/10/2023 5:43 PM, devi priya wrote:
> Add pinctrl definitions for the TLMM of IPQ9574
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>   drivers/pinctrl/qcom/Kconfig           |   10 +
>   drivers/pinctrl/qcom/Makefile          |    1 +
>   drivers/pinctrl/qcom/pinctrl-ipq9574.c | 1003 ++++++++++++++++++++++++
>   3 files changed, 1014 insertions(+)
>   create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c
>
> diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
> index 1378ddca084f..a9b4b07e3de0 100644
> --- a/drivers/pinctrl/qcom/Kconfig
> +++ b/drivers/pinctrl/qcom/Kconfig
> @@ -70,6 +70,16 @@ config PINCTRL_IPQ6018
>   	  Qualcomm Technologies Inc. IPQ6018 platform. Select this for
>   	  IPQ6018.
>   
> +config PINCTRL_IPQ9574
> +	tristate "Qualcomm Technologies, Inc. IPQ9574 pin controller driver"
> +	depends on GPIOLIB && OF
> +	select PINCTRL_MSM
> +	help
> +	  This is the pinctrl, pinmux, pinconf and gpiolib driver for
> +          the Qualcomm Technologies Inc. TLMM block found on the
> +          Qualcomm Technologies Inc. IPQ9574 platform. Select this for
> +          IPQ9574.
> +
>   config PINCTRL_MSM8226
>   	tristate "Qualcomm 8226 pin controller driver"
>   	depends on OF
> diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
> index a5c40f552e5c..717c8b8000ba 100644
> --- a/drivers/pinctrl/qcom/Makefile
> +++ b/drivers/pinctrl/qcom/Makefile
> @@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_IPQ4019)	+= pinctrl-ipq4019.o
>   obj-$(CONFIG_PINCTRL_IPQ8064)	+= pinctrl-ipq8064.o
>   obj-$(CONFIG_PINCTRL_IPQ8074)	+= pinctrl-ipq8074.o
>   obj-$(CONFIG_PINCTRL_IPQ6018)	+= pinctrl-ipq6018.o
> +obj-$(CONFIG_PINCTRL_IPQ9574)   += pinctrl-ipq9574.o
>   obj-$(CONFIG_PINCTRL_MSM8226)	+= pinctrl-msm8226.o
>   obj-$(CONFIG_PINCTRL_MSM8660)	+= pinctrl-msm8660.o
>   obj-$(CONFIG_PINCTRL_MSM8960)	+= pinctrl-msm8960.o
> diff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
> new file mode 100644
> index 000000000000..48be36279939
> --- /dev/null
> +++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c
> @@ -0,0 +1,1003 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Copyright (c) 2022 The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-msm.h"
> +
> +#define FUNCTION(fname)			                \
> +	[msm_mux_##fname] = {		                \
> +		.name = #fname,				\
> +		.groups = fname##_groups,               \
> +		.ngroups = ARRAY_SIZE(fname##_groups),	\
> +	}
> +
> +#define REG_SIZE 0x1000
> +#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
> +	{					        \
> +		.name = "gpio" #id,			\
> +		.pins = gpio##id##_pins,		\
> +		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
> +		.funcs = (int[]){			\
> +			msm_mux_gpio, /* gpio mode */	\
> +			msm_mux_##f1,			\
> +			msm_mux_##f2,			\
> +			msm_mux_##f3,			\
> +			msm_mux_##f4,			\
> +			msm_mux_##f5,			\
> +			msm_mux_##f6,			\
> +			msm_mux_##f7,			\
> +			msm_mux_##f8,			\
> +			msm_mux_##f9			\
> +		},				        \
> +		.nfuncs = 10,				\
> +		.ctl_reg = REG_SIZE * id,			\
> +		.io_reg = 0x4 + REG_SIZE * id,		\
> +		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
> +		.intr_status_reg = 0xc + REG_SIZE * id,	\
> +		.intr_target_reg = 0x8 + REG_SIZE * id,	\
> +		.mux_bit = 2,			\
> +		.pull_bit = 0,			\
> +		.drv_bit = 6,			\
> +		.oe_bit = 9,			\
> +		.in_bit = 0,			\
> +		.out_bit = 1,			\
> +		.intr_enable_bit = 0,		\
> +		.intr_status_bit = 0,		\
> +		.intr_target_bit = 5,		\
> +		.intr_target_kpss_val = 3,	\
> +		.intr_raw_status_bit = 4,	\
> +		.intr_polarity_bit = 1,		\
> +		.intr_detection_bit = 2,	\
> +		.intr_detection_width = 2,	\
> +	}
> +
> +static const struct pinctrl_pin_desc ipq9574_pins[] = {
> +	PINCTRL_PIN(0, "GPIO_0"),
> +	PINCTRL_PIN(1, "GPIO_1"),
> +	PINCTRL_PIN(2, "GPIO_2"),
> +	PINCTRL_PIN(3, "GPIO_3"),
> +	PINCTRL_PIN(4, "GPIO_4"),
> +	PINCTRL_PIN(5, "GPIO_5"),
> +	PINCTRL_PIN(6, "GPIO_6"),
> +	PINCTRL_PIN(7, "GPIO_7"),
> +	PINCTRL_PIN(8, "GPIO_8"),
> +	PINCTRL_PIN(9, "GPIO_9"),
> +	PINCTRL_PIN(10, "GPIO_10"),
> +	PINCTRL_PIN(11, "GPIO_11"),
> +	PINCTRL_PIN(12, "GPIO_12"),
> +	PINCTRL_PIN(13, "GPIO_13"),
> +	PINCTRL_PIN(14, "GPIO_14"),
> +	PINCTRL_PIN(15, "GPIO_15"),
> +	PINCTRL_PIN(16, "GPIO_16"),
> +	PINCTRL_PIN(17, "GPIO_17"),
> +	PINCTRL_PIN(18, "GPIO_18"),
> +	PINCTRL_PIN(19, "GPIO_19"),
> +	PINCTRL_PIN(20, "GPIO_20"),
> +	PINCTRL_PIN(21, "GPIO_21"),
> +	PINCTRL_PIN(22, "GPIO_22"),
> +	PINCTRL_PIN(23, "GPIO_23"),
> +	PINCTRL_PIN(24, "GPIO_24"),
> +	PINCTRL_PIN(25, "GPIO_25"),
> +	PINCTRL_PIN(26, "GPIO_26"),
> +	PINCTRL_PIN(27, "GPIO_27"),
> +	PINCTRL_PIN(28, "GPIO_28"),
> +	PINCTRL_PIN(29, "GPIO_29"),
> +	PINCTRL_PIN(30, "GPIO_30"),
> +	PINCTRL_PIN(31, "GPIO_31"),
> +	PINCTRL_PIN(32, "GPIO_32"),
> +	PINCTRL_PIN(33, "GPIO_33"),
> +	PINCTRL_PIN(34, "GPIO_34"),
> +	PINCTRL_PIN(35, "GPIO_35"),
> +	PINCTRL_PIN(36, "GPIO_36"),
> +	PINCTRL_PIN(37, "GPIO_37"),
> +	PINCTRL_PIN(38, "GPIO_38"),
> +	PINCTRL_PIN(39, "GPIO_39"),
> +	PINCTRL_PIN(40, "GPIO_40"),
> +	PINCTRL_PIN(41, "GPIO_41"),
> +	PINCTRL_PIN(42, "GPIO_42"),
> +	PINCTRL_PIN(43, "GPIO_43"),
> +	PINCTRL_PIN(44, "GPIO_44"),
> +	PINCTRL_PIN(45, "GPIO_45"),
> +	PINCTRL_PIN(46, "GPIO_46"),
> +	PINCTRL_PIN(47, "GPIO_47"),
> +	PINCTRL_PIN(48, "GPIO_48"),
> +	PINCTRL_PIN(49, "GPIO_49"),
> +	PINCTRL_PIN(50, "GPIO_50"),
> +	PINCTRL_PIN(51, "GPIO_51"),
> +	PINCTRL_PIN(52, "GPIO_52"),
> +	PINCTRL_PIN(53, "GPIO_53"),
> +	PINCTRL_PIN(54, "GPIO_54"),
> +	PINCTRL_PIN(55, "GPIO_55"),
> +	PINCTRL_PIN(56, "GPIO_56"),
> +	PINCTRL_PIN(57, "GPIO_57"),
> +	PINCTRL_PIN(58, "GPIO_58"),
> +	PINCTRL_PIN(59, "GPIO_59"),
> +	PINCTRL_PIN(60, "GPIO_60"),
> +	PINCTRL_PIN(61, "GPIO_61"),
> +	PINCTRL_PIN(62, "GPIO_62"),
> +	PINCTRL_PIN(63, "GPIO_63"),
> +	PINCTRL_PIN(64, "GPIO_64"),
> +};
> +
> +#define DECLARE_MSM_GPIO_PINS(pin) \
> +	static const unsigned int gpio##pin##_pins[] = { pin }
> +DECLARE_MSM_GPIO_PINS(0);
> +DECLARE_MSM_GPIO_PINS(1);
> +DECLARE_MSM_GPIO_PINS(2);
> +DECLARE_MSM_GPIO_PINS(3);
> +DECLARE_MSM_GPIO_PINS(4);
> +DECLARE_MSM_GPIO_PINS(5);
> +DECLARE_MSM_GPIO_PINS(6);
> +DECLARE_MSM_GPIO_PINS(7);
> +DECLARE_MSM_GPIO_PINS(8);
> +DECLARE_MSM_GPIO_PINS(9);
> +DECLARE_MSM_GPIO_PINS(10);
> +DECLARE_MSM_GPIO_PINS(11);
> +DECLARE_MSM_GPIO_PINS(12);
> +DECLARE_MSM_GPIO_PINS(13);
> +DECLARE_MSM_GPIO_PINS(14);
> +DECLARE_MSM_GPIO_PINS(15);
> +DECLARE_MSM_GPIO_PINS(16);
> +DECLARE_MSM_GPIO_PINS(17);
> +DECLARE_MSM_GPIO_PINS(18);
> +DECLARE_MSM_GPIO_PINS(19);
> +DECLARE_MSM_GPIO_PINS(20);
> +DECLARE_MSM_GPIO_PINS(21);
> +DECLARE_MSM_GPIO_PINS(22);
> +DECLARE_MSM_GPIO_PINS(23);
> +DECLARE_MSM_GPIO_PINS(24);
> +DECLARE_MSM_GPIO_PINS(25);
> +DECLARE_MSM_GPIO_PINS(26);
> +DECLARE_MSM_GPIO_PINS(27);
> +DECLARE_MSM_GPIO_PINS(28);
> +DECLARE_MSM_GPIO_PINS(29);
> +DECLARE_MSM_GPIO_PINS(30);
> +DECLARE_MSM_GPIO_PINS(31);
> +DECLARE_MSM_GPIO_PINS(32);
> +DECLARE_MSM_GPIO_PINS(33);
> +DECLARE_MSM_GPIO_PINS(34);
> +DECLARE_MSM_GPIO_PINS(35);
> +DECLARE_MSM_GPIO_PINS(36);
> +DECLARE_MSM_GPIO_PINS(37);
> +DECLARE_MSM_GPIO_PINS(38);
> +DECLARE_MSM_GPIO_PINS(39);
> +DECLARE_MSM_GPIO_PINS(40);
> +DECLARE_MSM_GPIO_PINS(41);
> +DECLARE_MSM_GPIO_PINS(42);
> +DECLARE_MSM_GPIO_PINS(43);
> +DECLARE_MSM_GPIO_PINS(44);
> +DECLARE_MSM_GPIO_PINS(45);
> +DECLARE_MSM_GPIO_PINS(46);
> +DECLARE_MSM_GPIO_PINS(47);
> +DECLARE_MSM_GPIO_PINS(48);
> +DECLARE_MSM_GPIO_PINS(49);
> +DECLARE_MSM_GPIO_PINS(50);
> +DECLARE_MSM_GPIO_PINS(51);
> +DECLARE_MSM_GPIO_PINS(52);
> +DECLARE_MSM_GPIO_PINS(53);
> +DECLARE_MSM_GPIO_PINS(54);
> +DECLARE_MSM_GPIO_PINS(55);
> +DECLARE_MSM_GPIO_PINS(56);
> +DECLARE_MSM_GPIO_PINS(57);
> +DECLARE_MSM_GPIO_PINS(58);
> +DECLARE_MSM_GPIO_PINS(59);
> +DECLARE_MSM_GPIO_PINS(60);
> +DECLARE_MSM_GPIO_PINS(61);
> +DECLARE_MSM_GPIO_PINS(62);
> +DECLARE_MSM_GPIO_PINS(63);
> +DECLARE_MSM_GPIO_PINS(64);
> +
> +enum ipq9574_functions {
> +	msm_mux_atest_char,
> +	msm_mux_atest_char0,
> +	msm_mux_atest_char1,
> +	msm_mux_atest_char2,
> +	msm_mux_atest_char3,
> +	msm_mux_audio_pdm0,
> +	msm_mux_audio_pdm1,
> +	msm_mux_audio_pri,
> +	msm_mux_audio_sec,
> +	msm_mux_blsp0_spi,
> +	msm_mux_blsp0_uart,
> +	msm_mux_blsp1_i2c,
> +	msm_mux_blsp1_spi,
> +	msm_mux_blsp1_uart,
> +	msm_mux_blsp2_i2c,
> +	msm_mux_blsp2_spi,
> +	msm_mux_blsp2_uart,
> +	msm_mux_blsp3_i2c,
> +	msm_mux_blsp3_spi,
> +	msm_mux_blsp3_uart,
> +	msm_mux_blsp4_i2c,
> +	msm_mux_blsp4_spi,
> +	msm_mux_blsp4_uart,
> +	msm_mux_blsp5_i2c,
> +	msm_mux_blsp5_uart,
> +	msm_mux_cri_trng0,
> +	msm_mux_cri_trng1,
> +	msm_mux_cri_trng2,
> +	msm_mux_cri_trng3,
> +	msm_mux_cxc0,
> +	msm_mux_cxc1,
> +	msm_mux_dbg_out,
> +	msm_mux_dwc_ddrphy,
> +	msm_mux_gcc_plltest,
> +	msm_mux_gcc_tlmm,
> +	msm_mux_gpio,
> +	msm_mux_mac00,
> +	msm_mux_mac01,
> +	msm_mux_mac10,
> +	msm_mux_mac11,
> +	msm_mux_mdc,
> +	msm_mux_mdio,
> +	msm_mux_pcie0_clk,
> +	msm_mux_pcie0_wake,
> +	msm_mux_pcie1_clk,
> +	msm_mux_pcie1_wake,
> +	msm_mux_pcie2_clk,
> +	msm_mux_pcie2_wake,
> +	msm_mux_pcie3_clk,
> +	msm_mux_pcie3_wake,
> +	msm_mux_prng_rosc0,
> +	msm_mux_prng_rosc1,
> +	msm_mux_prng_rosc2,
> +	msm_mux_prng_rosc3,
> +	msm_mux_pta1_0,
> +	msm_mux_pta1_1,
> +	msm_mux_pta1_2,
> +	msm_mux_pta20,
> +	msm_mux_pta21,
> +	msm_mux_pwm00,
> +	msm_mux_pwm01,
> +	msm_mux_pwm02,
> +	msm_mux_pwm03,
> +	msm_mux_pwm04,
> +	msm_mux_pwm10,
> +	msm_mux_pwm11,
> +	msm_mux_pwm12,
> +	msm_mux_pwm13,
> +	msm_mux_pwm14,
> +	msm_mux_pwm20,
> +	msm_mux_pwm21,
> +	msm_mux_pwm22,
> +	msm_mux_pwm23,
> +	msm_mux_pwm24,
> +	msm_mux_pwm30,
> +	msm_mux_pwm31,
> +	msm_mux_pwm32,
> +	msm_mux_pwm33,
> +	msm_mux_qdss_cti_trig_in_a0,
> +	msm_mux_qdss_cti_trig_in_a1,
> +	msm_mux_qdss_cti_trig_in_b0,
> +	msm_mux_qdss_cti_trig_in_b1,
> +	msm_mux_qdss_cti_trig_out_a0,
> +	msm_mux_qdss_cti_trig_out_a1,
> +	msm_mux_qdss_cti_trig_out_b0,
> +	msm_mux_qdss_cti_trig_out_b1,
> +	msm_mux_qdss_traceclk_a,
> +	msm_mux_qdss_traceclk_b,
> +	msm_mux_qdss_tracectl_a,
> +	msm_mux_qdss_tracectl_b,
> +	msm_mux_qdss_tracedata_a,
> +	msm_mux_qdss_tracedata_b,
> +	msm_mux_qspi_data,
> +	msm_mux_qspi_clk,
> +	msm_mux_qspi_cs,
> +	msm_mux_rx0,
> +	msm_mux_rx1,
> +	msm_mux_sdc_data,
> +	msm_mux_sdc_clk,
> +	msm_mux_sdc_cmd,
> +	msm_mux_sdc_rclk,
> +	msm_mux_tsens_max,
> +	msm_mux_wci20,
> +	msm_mux_wci21,
> +	msm_mux_wsa_swrm,
> +	msm_mux__,
> +};
> +
> +static const char * const gpio_groups[] = {
> +	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
> +	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
> +	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> +	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
> +	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
> +	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
> +	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
> +	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
> +	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
> +	"gpio64",
> +};
> +
> +static const char * const sdc_data_groups[] = {
> +	"gpio0",
> +	"gpio1",
> +	"gpio2",
> +	"gpio3",
> +	"gpio6",
> +	"gpio7",
> +	"gpio8",
> +	"gpio9",
> +};
> +
> +static const char * const qspi_data_groups[] = {
> +	"gpio0",
> +	"gpio1",
> +	"gpio2",
> +	"gpio3",
> +};
> +
> +static const char * const qdss_traceclk_b_groups[] = {
> +	"gpio0",
> +};
> +
> +static const char * const qdss_tracectl_b_groups[] = {
> +	"gpio1",
> +};
> +
> +static const char * const qdss_tracedata_b_groups[] = {
> +	"gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
> +	"gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", "gpio16",
> +	"gpio17",
> +};
> +
> +static const char * const sdc_cmd_groups[] = {
> +	"gpio4",
> +};
> +
> +static const char * const qspi_cs_groups[] = {
> +	"gpio4",
> +};
> +
> +static const char * const sdc_clk_groups[] = {
> +	"gpio5",
> +};
> +
> +static const char * const qspi_clk_groups[] = {
> +	"gpio5",
> +};
> +
> +static const char * const sdc_rclk_groups[] = {
> +	"gpio10",
> +};
> +
> +static const char * const blsp0_spi_groups[] = {
> +	"gpio11", "gpio12", "gpio13", "gpio14",
> +};
> +
> +static const char * const blsp0_uart_groups[] = {
> +	"gpio11", "gpio12", "gpio13", "gpio14",
> +};
> +
> +static const char * const blsp3_spi_groups[] = {
> +	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
> +};
> +
> +static const char * const blsp3_i2c_groups[] = {
> +	"gpio15", "gpio16",
> +};
> +
> +static const char * const blsp3_uart_groups[] = {
> +	"gpio15", "gpio16", "gpio17", "gpio18",
> +};
> +
> +static const char * const dbg_out_groups[] = {
> +	"gpio17",
> +};
> +
> +static const char * const cri_trng0_groups[] = {
> +	"gpio20", "gpio38",
> +};
> +
> +static const char * const cri_trng1_groups[] = {
> +	"gpio21", "gpio34",
> +};
> +
> +static const char * const pcie0_clk_groups[] = {
> +	"gpio22",
> +};
> +
> +static const char * const pta20_groups[] = {
> +	"gpio22", "gpio23", "gpio24",
> +};
> +
> +static const char * const wci21_groups[] = {
> +	"gpio23", "gpio24",
> +};
> +
> +static const char * const cxc0_groups[] = {
> +	"gpio23", "gpio24",
> +};
> +
> +static const char * const pcie0_wake_groups[] = {
> +	"gpio24",
> +};
> +
> +static const char * const qdss_cti_trig_out_b0_groups[] = {
> +	"gpio24",
> +};
> +
> +static const char * const pcie1_clk_groups[] = {
> +	"gpio25",
> +};
> +
> +static const char * const qdss_cti_trig_in_b0_groups[] = {
> +	"gpio25",
> +};
> +
> +static const char * const atest_char0_groups[] = {
> +	"gpio26",
> +};
> +
> +static const char * const qdss_cti_trig_out_b1_groups[] = {
> +	"gpio26",
> +};
> +
> +static const char * const pcie1_wake_groups[] = {
> +	"gpio27",
> +};
> +
> +static const char * const atest_char1_groups[] = {
> +	"gpio27",
> +};
> +
> +static const char * const qdss_cti_trig_in_b1_groups[] = {
> +	"gpio27",
> +};
> +
> +static const char * const pcie2_clk_groups[] = {
> +	"gpio28",
> +};
> +
> +static const char * const atest_char2_groups[] = {
> +	"gpio28",
> +};
> +
> +static const char * const atest_char3_groups[] = {
> +	"gpio29",
> +};
> +
> +static const char * const pcie2_wake_groups[] = {
> +	"gpio30",
> +};
> +
> +static const char * const pwm01_groups[] = {
> +	"gpio30",
> +};
> +
> +static const char * const atest_char_groups[] = {
> +	"gpio30",
> +};
> +
> +static const char * const pcie3_clk_groups[] = {
> +	"gpio31",
> +};
> +
> +static const char * const pwm11_groups[] = {
> +	"gpio31",
> +};
> +
> +static const char * const qdss_cti_trig_in_a1_groups[] = {
> +	"gpio31",
> +};
> +
> +static const char * const pwm21_groups[] = {
> +	"gpio32",
> +};
> +
> +static const char * const qdss_cti_trig_out_a1_groups[] = {
> +	"gpio32",
> +};
> +
> +static const char * const pcie3_wake_groups[] = {
> +	"gpio33",
> +};
> +
> +static const char * const pwm31_groups[] = {
> +	"gpio33",
> +};
> +
> +static const char * const qdss_cti_trig_in_a0_groups[] = {
> +	"gpio33",
> +};
> +
> +static const char * const blsp2_uart_groups[] = {
> +	"gpio34", "gpio35",
> +};
> +
> +static const char * const blsp2_i2c_groups[] = {
> +	"gpio34", "gpio35",
> +};
> +
> +static const char * const blsp2_spi_groups[] = {
> +	"gpio34", "gpio35", "gpio36", "gpio37",
> +};
> +
> +static const char * const blsp1_uart_groups[] = {
> +	"gpio34", "gpio35", "gpio36", "gpio37",
> +};
> +
> +static const char * const qdss_cti_trig_out_a0_groups[] = {
> +	"gpio34",
> +};
> +
> +static const char * const cri_trng2_groups[] = {
> +	"gpio35",
> +};
> +
> +static const char * const blsp1_i2c_groups[] = {
> +	"gpio36", "gpio37",
> +};
> +
> +static const char * const cri_trng3_groups[] = {
> +	"gpio36",
> +};
> +
> +static const char * const dwc_ddrphy_groups[] = {
> +	"gpio37",
> +};
> +
> +static const char * const mdc_groups[] = {
> +	"gpio38",
> +};
> +
> +static const char * const mdio_groups[] = {
> +	"gpio39",
> +};
> +
> +static const char * const audio_pri_groups[] = {
> +	"gpio40", "gpio41", "gpio42", "gpio43", "gpio61", "gpio61",
> +};
> +
> +static const char * const audio_pdm0_groups[] = {
> +	"gpio40", "gpio41", "gpio42", "gpio43",
> +};
> +
> +static const char * const qdss_traceclk_a_groups[] = {
> +	"gpio43",
> +};
> +
> +static const char * const pwm00_groups[] = {
> +	"gpio44",
> +};
> +
> +static const char * const audio_sec_groups[] = {
> +	"gpio44", "gpio45", "gpio46", "gpio47", "gpio62", "gpio62",
> +};
> +
> +static const char * const wsa_swrm_groups[] = {
> +	"gpio44", "gpio45",
> +};
> +
> +static const char * const qdss_tracectl_a_groups[] = {
> +	"gpio44",
> +};
> +
> +static const char * const pwm10_groups[] = {
> +	"gpio45",
> +};
> +
> +static const char * const qdss_tracedata_a_groups[] = {
> +	"gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
> +	"gpio52", "gpio53", "gpio54", "gpio55", "gpio56", "gpio57", "gpio58",
> +	"gpio59", "gpio60",
> +};
> +
> +static const char * const pwm20_groups[] = {
> +	"gpio46",
> +};
> +
> +static const char * const rx1_groups[] = {
> +	"gpio46",
> +};
> +
> +static const char * const mac00_groups[] = {
> +	"gpio46",
> +};
> +
> +static const char * const pwm30_groups[] = {
> +	"gpio47",
> +};
> +
> +static const char * const mac01_groups[] = {
> +	"gpio47",
> +};
> +
> +static const char * const blsp5_i2c_groups[] = {
> +	"gpio48", "gpio49",
> +};
> +
> +static const char * const blsp5_uart_groups[] = {
> +	"gpio48", "gpio49",
> +};
> +
> +static const char * const blsp4_uart_groups[] = {
> +	"gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const blsp4_i2c_groups[] = {
> +	"gpio50", "gpio51",
> +};
> +
> +static const char * const blsp4_spi_groups[] = {
> +	"gpio50", "gpio51", "gpio52", "gpio53",
> +};
> +
> +static const char * const pwm02_groups[] = {
> +	"gpio50",
> +};
> +
> +static const char * const pwm12_groups[] = {
> +	"gpio51",
> +};
> +
> +static const char * const pwm22_groups[] = {
> +	"gpio52",
> +};
> +
> +static const char * const pwm32_groups[] = {
> +	"gpio53",
> +};
> +
> +static const char * const pta1_1_groups[] = {
> +	"gpio54",
> +};
> +
> +static const char * const pwm04_groups[] = {
> +	"gpio54",
> +};
> +
> +static const char * const pta1_2_groups[] = {
> +	"gpio55",
> +};
> +
> +static const char * const pwm14_groups[] = {
> +	"gpio55",
> +};
> +
> +static const char * const pta1_0_groups[] = {
> +	"gpio56",
> +};
> +
> +static const char * const pwm24_groups[] = {
> +	"gpio56",
> +};
> +
> +static const char * const wci20_groups[] = {
> +	"gpio57", "gpio58",
> +};
> +
> +static const char * const cxc1_groups[] = {
> +	"gpio57", "gpio58",
> +};
> +
> +static const char * const mac10_groups[] = {
> +	"gpio57",
> +};
> +
> +static const char * const pwm03_groups[] = {
> +	"gpio57",
> +};
> +
> +static const char * const mac11_groups[] = {
> +	"gpio58",
> +};
> +
> +static const char * const pwm13_groups[] = {
> +	"gpio58",
> +};
> +
> +static const char * const rx0_groups[] = {
> +	"gpio59",
> +};
> +
> +static const char * const pwm23_groups[] = {
> +	"gpio59",
> +};
> +
> +static const char * const pwm33_groups[] = {
> +	"gpio60",
> +};
> +
> +static const char * const prng_rosc0_groups[] = {
> +	"gpio60",
> +};
> +
> +static const char * const gcc_plltest_groups[] = {
> +	"gpio60", "gpio62",
> +};
> +
> +static const char * const blsp1_spi_groups[] = {
> +	"gpio61", "gpio62", "gpio63", "gpio64",
> +};
> +
> +static const char * const audio_pdm1_groups[] = {
> +	"gpio61", "gpio62", "gpio63", "gpio64",
> +};
> +
> +static const char * const pta21_groups[] = {
> +	"gpio61", "gpio62", "gpio63",
> +};
> +
> +static const char * const prng_rosc1_groups[] = {
> +	"gpio61",
> +};
> +
> +static const char * const gcc_tlmm_groups[] = {
> +	"gpio61",
> +};
> +
> +static const char * const prng_rosc2_groups[] = {
> +	"gpio62",
> +};
> +
> +static const char * const prng_rosc3_groups[] = {
> +	"gpio63",
> +};
> +
> +static const char * const tsens_max_groups[] = {
> +	"gpio64",
> +};
> +
> +static const struct msm_function ipq9574_functions[] = {
> +	FUNCTION(atest_char),
> +	FUNCTION(atest_char0),
> +	FUNCTION(atest_char1),
> +	FUNCTION(atest_char2),
> +	FUNCTION(atest_char3),
> +	FUNCTION(audio_pdm0),
> +	FUNCTION(audio_pdm1),
> +	FUNCTION(audio_pri),
> +	FUNCTION(audio_sec),
> +	FUNCTION(blsp0_spi),
> +	FUNCTION(blsp0_uart),
> +	FUNCTION(blsp1_i2c),
> +	FUNCTION(blsp1_spi),
> +	FUNCTION(blsp1_uart),
> +	FUNCTION(blsp2_i2c),
> +	FUNCTION(blsp2_spi),
> +	FUNCTION(blsp2_uart),
> +	FUNCTION(blsp3_i2c),
> +	FUNCTION(blsp3_spi),
> +	FUNCTION(blsp3_uart),
> +	FUNCTION(blsp4_i2c),
> +	FUNCTION(blsp4_spi),
> +	FUNCTION(blsp4_uart),
> +	FUNCTION(blsp5_i2c),
> +	FUNCTION(blsp5_uart),
> +	FUNCTION(cri_trng0),
> +	FUNCTION(cri_trng1),
> +	FUNCTION(cri_trng2),
> +	FUNCTION(cri_trng3),
> +	FUNCTION(cxc0),
> +	FUNCTION(cxc1),
> +	FUNCTION(dbg_out),
> +	FUNCTION(dwc_ddrphy),
> +	FUNCTION(gcc_plltest),
> +	FUNCTION(gcc_tlmm),
> +	FUNCTION(gpio),
> +	FUNCTION(mac00),
> +	FUNCTION(mac01),
> +	FUNCTION(mac10),
> +	FUNCTION(mac11),
> +	FUNCTION(mdc),
> +	FUNCTION(mdio),
> +	FUNCTION(pcie0_clk),
> +	FUNCTION(pcie0_wake),
> +	FUNCTION(pcie1_clk),
> +	FUNCTION(pcie1_wake),
> +	FUNCTION(pcie2_clk),
> +	FUNCTION(pcie2_wake),
> +	FUNCTION(pcie3_clk),
> +	FUNCTION(pcie3_wake),
> +	FUNCTION(prng_rosc0),
> +	FUNCTION(prng_rosc1),
> +	FUNCTION(prng_rosc2),
> +	FUNCTION(prng_rosc3),
> +	FUNCTION(pta1_0),
> +	FUNCTION(pta1_1),
> +	FUNCTION(pta1_2),
> +	FUNCTION(pta20),
> +	FUNCTION(pta21),
> +	FUNCTION(pwm00),
> +	FUNCTION(pwm01),
> +	FUNCTION(pwm02),
> +	FUNCTION(pwm03),
> +	FUNCTION(pwm04),
> +	FUNCTION(pwm10),
> +	FUNCTION(pwm11),
> +	FUNCTION(pwm12),
> +	FUNCTION(pwm13),
> +	FUNCTION(pwm14),
> +	FUNCTION(pwm20),
> +	FUNCTION(pwm21),
> +	FUNCTION(pwm22),
> +	FUNCTION(pwm23),
> +	FUNCTION(pwm24),
> +	FUNCTION(pwm30),
> +	FUNCTION(pwm31),
> +	FUNCTION(pwm32),
> +	FUNCTION(pwm33),
> +	FUNCTION(qdss_cti_trig_in_a0),
> +	FUNCTION(qdss_cti_trig_in_a1),
> +	FUNCTION(qdss_cti_trig_in_b0),
> +	FUNCTION(qdss_cti_trig_in_b1),
> +	FUNCTION(qdss_cti_trig_out_a0),
> +	FUNCTION(qdss_cti_trig_out_a1),
> +	FUNCTION(qdss_cti_trig_out_b0),
> +	FUNCTION(qdss_cti_trig_out_b1),
> +	FUNCTION(qdss_traceclk_a),
> +	FUNCTION(qdss_traceclk_b),
> +	FUNCTION(qdss_tracectl_a),
> +	FUNCTION(qdss_tracectl_b),
> +	FUNCTION(qdss_tracedata_a),
> +	FUNCTION(qdss_tracedata_b),
> +	FUNCTION(qspi_data),
> +	FUNCTION(qspi_clk),
> +	FUNCTION(qspi_cs),
> +	FUNCTION(rx0),
> +	FUNCTION(rx1),
> +	FUNCTION(sdc_data),
> +	FUNCTION(sdc_clk),
> +	FUNCTION(sdc_cmd),
> +	FUNCTION(sdc_rclk),
> +	FUNCTION(tsens_max),
> +	FUNCTION(wci20),
> +	FUNCTION(wci21),
> +	FUNCTION(wsa_swrm),
> +};
> +
> +static const struct msm_pingroup ipq9574_groups[] = {
> +	PINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _),
> +	PINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _),
> +	PINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
> +	PINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),
> +	PINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _),
> +	PINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _,
> +		 _),
> +	PINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _),
> +	PINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _,
> +		 _, _),
> +	PINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
> +		 _, _, _, _),
> +	PINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _,
> +		 _, _, _, _),
> +	PINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _,
> +		 _, _, _),
> +	PINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _),
> +	PINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _),
> +	PINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _),
> +	PINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _),
> +	PINGROUP(22, pcie0_clk, _, pta20, _, _, _, _, _, _),
> +	PINGROUP(23, _, pta20, wci21, cxc0, _, _, _, _, _),
> +	PINGROUP(24, pcie0_wake, _, pta20, wci21, cxc0, _,
> +		 qdss_cti_trig_out_b0, _, _),
> +	PINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _,
> +		 _),
> +	PINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _,
> +		 _),
> +	PINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _,
> +		 _, _, _),
> +	PINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _),
> +	PINGROUP(29, atest_char3, _, _, _, _, _, _, _, _),
> +	PINGROUP(30, pcie2_wake, pwm01, atest_char, _, _, _, _, _, _),
> +	PINGROUP(31, pcie3_clk, pwm11, _, qdss_cti_trig_in_a1, _, _, _, _,
> +		 _),
> +	PINGROUP(32, pwm21, _, qdss_cti_trig_out_a1, _, _, _, _, _, _),
> +	PINGROUP(33, pcie3_wake, pwm31, _, qdss_cti_trig_in_a0, _, _, _,
> +		 _, _),
> +	PINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
> +		 cri_trng1, qdss_cti_trig_out_a0, _, _),
> +	PINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _,
> +		 cri_trng2, _, _, _),
> +	PINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _,
> +		 _, _),
> +	PINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _,
> +		 _, _),
> +	PINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _),
> +	PINGROUP(39, mdio, _, _, _, _, _, _, _, _),
> +	PINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
> +	PINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
> +	PINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _),
> +	PINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _,
> +		 _, _),
> +	PINGROUP(44, pwm00, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _,
> +		 _, _),
> +	PINGROUP(45, pwm10, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _,
> +		 _, _),
> +	PINGROUP(46, pwm20, audio_sec, rx1, mac00, _, qdss_tracedata_a, _,
> +		 _, _),
> +	PINGROUP(47, pwm30, audio_sec, mac01, _, qdss_tracedata_a, _, _, _,
> +		 _),
> +	PINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
> +		 _, _),
> +	PINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _,
> +		 _, _),
> +	PINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm02, qdss_tracedata_a,
> +		 _, _, _, _),
> +	PINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm12, qdss_tracedata_a,
> +		 _, _, _, _),
> +	PINGROUP(52, blsp4_uart, blsp4_spi, pwm22, qdss_tracedata_a, _, _,
> +		 _, _, _),
> +	PINGROUP(53, blsp4_uart, blsp4_spi, pwm32, qdss_tracedata_a, _, _,
> +		 _, _, _),
> +	PINGROUP(54, pta1_1, pwm04, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(55, pta1_2, pwm14, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(56, pta1_0, pwm24, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(57, wci20, cxc1, mac10, pwm03, qdss_tracedata_a, _, _, _,
> +		 _),
> +	PINGROUP(58, wci20, cxc1, mac11, pwm13, qdss_tracedata_a, _, _, _,
> +		 _),
> +	PINGROUP(59, rx0, pwm23, qdss_tracedata_a, _, _, _, _, _, _),
> +	PINGROUP(60, pwm33, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _,
> +		 _, _, _),
> +	PINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta21,
> +		 prng_rosc1, gcc_tlmm, _, _),
> +	PINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta21,
> +		 prng_rosc2, gcc_plltest, _, _),
> +	PINGROUP(63, blsp1_spi, audio_pdm1, pta21, prng_rosc3, _, _, _, _,
> +		 _),
> +	PINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _),
> +};
> +
> +static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {
> +	.pins = ipq9574_pins,
> +	.npins = ARRAY_SIZE(ipq9574_pins),
> +	.functions = ipq9574_functions,
> +	.nfunctions = ARRAY_SIZE(ipq9574_functions),
> +	.groups = ipq9574_groups,
> +	.ngroups = ARRAY_SIZE(ipq9574_groups),
> +	.ngpios = 65,
> +};
> +
> +static int ipq9574_pinctrl_probe(struct platform_device *pdev)
> +{
> +	return msm_pinctrl_probe(pdev, &ipq9574_pinctrl);
> +}
> +
> +static const struct of_device_id ipq9574_pinctrl_of_match[] = {
> +	{ .compatible = "qcom,ipq9574-tlmm", },
> +	{ },
> +};
> +
> +static struct platform_driver ipq9574_pinctrl_driver = {
> +	.driver = {
> +		.name = "ipq9574-tlmm",
> +		.owner = THIS_MODULE,


Please drop the .owner field, it is taken care by 
platform_driver_register().


> +		.of_match_table = ipq9574_pinctrl_of_match,
> +	},
> +	.probe = ipq9574_pinctrl_probe,
> +	.remove = msm_pinctrl_remove,
> +};
> +
> +static int __init ipq9574_pinctrl_init(void)
> +{
> +	return platform_driver_register(&ipq9574_pinctrl_driver);
> +}
> +arch_initcall(ipq9574_pinctrl_init);
> +
> +static void __exit ipq9574_pinctrl_exit(void)
> +{
> +	platform_driver_unregister(&ipq9574_pinctrl_driver);
> +}
> +module_exit(ipq9574_pinctrl_exit);
> +
> +MODULE_DESCRIPTION("QTI IPQ9574 TLMM driver");
> +MODULE_LICENSE("GPL");
> +MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);

[PATCH 5/7] dt-bindings: qcom: Add ipq9574 bindings

[devi priya]

Document the new ipq9574 SOC/board device tree bindings

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 27063a045bd0..83102fe2d366 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -32,6 +32,7 @@ description: |
         ipq4018
         ipq6018
         ipq8074
+        ipq9574
         mdm9615
         msm8226
         msm8916
@@ -80,6 +81,7 @@ description: |
         hk01
         hk10-c1
         hk10-c2
+        ap-al02-c7
         idp
         liquid
         mtp
@@ -304,6 +306,11 @@ properties:
               - qcom,ipq8074-hk10-c2
           - const: qcom,ipq8074
 
+      - items:
+          - enum:
+              - qcom,ipq9574-ap-al02-c7
+          - const: qcom,ipq9574
+
       - description: Sierra Wireless MangOH Green with WP8548 Module
         items:
           - const: swir,mangoh-green-wp8548
-- 
2.17.1


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[PATCH 5/7] dt-bindings: qcom: Add ipq9574 bindings

[devi priya]

Document the new ipq9574 SOC/board device tree bindings

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 27063a045bd0..83102fe2d366 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -32,6 +32,7 @@ description: |
         ipq4018
         ipq6018
         ipq8074
+        ipq9574
         mdm9615
         msm8226
         msm8916
@@ -80,6 +81,7 @@ description: |
         hk01
         hk10-c1
         hk10-c2
+        ap-al02-c7
         idp
         liquid
         mtp
@@ -304,6 +306,11 @@ properties:
               - qcom,ipq8074-hk10-c2
           - const: qcom,ipq8074
 
+      - items:
+          - enum:
+              - qcom,ipq9574-ap-al02-c7
+          - const: qcom,ipq9574
+
       - description: Sierra Wireless MangOH Green with WP8548 Module
         items:
           - const: swir,mangoh-green-wp8548
-- 
2.17.1

Re: [PATCH 5/7] dt-bindings: qcom: Add ipq9574 bindings

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Document the new ipq9574 SOC/board device tree bindings
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 27063a045bd0..83102fe2d366 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -32,6 +32,7 @@ description: |
>          ipq4018
>          ipq6018
>          ipq8074
> +        ipq9574
>          mdm9615
>          msm8226
>          msm8916
> @@ -80,6 +81,7 @@ description: |
>          hk01
>          hk10-c1
>          hk10-c2
> +        ap-al02-c7

'a' rarely goes after 'h'.

>          idp
>          liquid
>          mtp
> @@ -304,6 +306,11 @@ properties:
>                - qcom,ipq8074-hk10-c2
>            - const: qcom,ipq8074

Best regards,
Krzysztof


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Re: [PATCH 5/7] dt-bindings: qcom: Add ipq9574 bindings

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> Document the new ipq9574 SOC/board device tree bindings
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 27063a045bd0..83102fe2d366 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -32,6 +32,7 @@ description: |
>          ipq4018
>          ipq6018
>          ipq8074
> +        ipq9574
>          mdm9615
>          msm8226
>          msm8916
> @@ -80,6 +81,7 @@ description: |
>          hk01
>          hk10-c1
>          hk10-c2
> +        ap-al02-c7

'a' rarely goes after 'h'.

>          idp
>          liquid
>          mtp
> @@ -304,6 +306,11 @@ properties:
>                - qcom,ipq8074-hk10-c2
>            - const: qcom,ipq8074

Best regards,
Krzysztof

Re: [PATCH 5/7] dt-bindings: qcom: Add ipq9574 bindings

[Devi Priya]

On 1/11/2023 3:09 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Document the new ipq9574 SOC/board device tree bindings
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 27063a045bd0..83102fe2d366 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -32,6 +32,7 @@ description: |
>>           ipq4018
>>           ipq6018
>>           ipq8074
>> +        ipq9574
>>           mdm9615
>>           msm8226
>>           msm8916
>> @@ -80,6 +81,7 @@ description: |
>>           hk01
>>           hk10-c1
>>           hk10-c2
>> +        ap-al02-c7
> 
> 'a' rarely goes after 'h'.
Sure, will update!
> 
>>           idp
>>           liquid
>>           mtp
>> @@ -304,6 +306,11 @@ properties:
>>                 - qcom,ipq8074-hk10-c2
>>             - const: qcom,ipq8074
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 5/7] dt-bindings: qcom: Add ipq9574 bindings

[Devi Priya]

On 1/11/2023 3:09 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> Document the new ipq9574 SOC/board device tree bindings
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
>> index 27063a045bd0..83102fe2d366 100644
>> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
>> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
>> @@ -32,6 +32,7 @@ description: |
>>           ipq4018
>>           ipq6018
>>           ipq8074
>> +        ipq9574
>>           mdm9615
>>           msm8226
>>           msm8916
>> @@ -80,6 +81,7 @@ description: |
>>           hk01
>>           hk10-c1
>>           hk10-c2
>> +        ap-al02-c7
> 
> 'a' rarely goes after 'h'.
Sure, will update!
> 
>>           idp
>>           liquid
>>           mtp
>> @@ -304,6 +306,11 @@ properties:
>>                 - qcom,ipq8074-hk10-c2
>>             - const: qcom,ipq8074
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

[PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[devi priya]

From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>

Add initial device tree support for Qualcomm IPQ9574 SoC
and AL02 board

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Co-developed-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile            |   1 +
 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
 3 files changed, 388 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 3e79496292e7..872c62028a0b 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
new file mode 100644
index 000000000000..ae3c32f3e16a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * IPQ9574 AL02-C7 board device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq9574.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
+	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &blsp1_uart2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&blsp1_uart2 {
+	pinctrl-0 = <&uart2_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&sdhc_1 {
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tlmm {
+	emmc_pins: emmc-state {
+		emmc-clk-pins {
+			pins = "gpio5";
+			function = "sdc_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		emmc-cmd-pins {
+			pins = "gpio4";
+			function = "sdc_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		emmc-data-pins {
+			pins = "gpio0", "gpio1", "gpio2",
+			     "gpio3", "gpio6", "gpio7",
+			     "gpio8", "gpio9";
+			function = "sdc_data";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		emmc-rclk-pins {
+			pins = "gpio10";
+			function = "sdc_rclk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
new file mode 100644
index 000000000000..188d18688a77
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * IPQ9574 SoC device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
+#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clocks {
+		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <353000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x1>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x2>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x3>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x40000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a73-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tz_region: memory@4a600000 {
+			reg = <0x0 0x4a600000 0x0 0x400000>;
+			no-map;
+		};
+	};
+
+	soc: soc@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,ipq9574-tlmm";
+			reg = <0x01000000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 65>;
+			gpio-reserved-ranges = <59 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart2_pins: uart2-state {
+				pins = "gpio34", "gpio35";
+				function = "blsp2_uart";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-ipq9574";
+			reg = <0x1800000 0x80000>;
+			clocks = <&xo_board_clk>,
+				<&sleep_clk>,
+				<&bias_pll_ubi_nc_clk>,
+				<&pcie30_phy0_pipe_clk>,
+				<&pcie30_phy1_pipe_clk>,
+				<&pcie30_phy2_pipe_clk>,
+				<&pcie30_phy3_pipe_clk>,
+				<&usb3phy_0_cc_pipe_clk>;
+			clock-names = "xo",
+				"sleep_clk",
+				"bias_pll_ubi_nc_clk",
+				"pcie30_phy0_pipe_clk",
+				"pcie30_phy1_pipe_clk",
+				"pcie30_phy2_pipe_clk",
+				"pcie30_phy3_pipe_clk",
+				"usb3phy_0_cc_pipe_clk";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		sdhc_1: sdhci@7804000 {
+			compatible = "qcom,sdhci-msm-v5";
+			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
+			reg-names = "hc_mem", "cmdq_mem";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&xo_board_clk>,
+			       <&gcc GCC_SDCC1_AHB_CLK>,
+			       <&gcc GCC_SDCC1_APPS_CLK>;
+			clock-names = "xo", "iface", "core";
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			mmc-hs400-enhanced-strobe;
+			max-frequency = <384000000>;
+			bus-width = <8>;
+			non-removable;
+			status = "disabled";
+		};
+
+		blsp1_uart2: serial@78b1000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b1000 0x200>;
+			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			reg = <0x0b000000 0x1000>,  /* GICD */
+			      <0x0b002000 0x1000>,  /* GICC */
+			      <0x0b001000 0x1000>,  /* GICH */
+			      <0x0b004000 0x1000>;  /* GICV */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			ranges = <0 0x0b00c000 0x3000>;
+
+			v2m0: v2m@0 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x0 0xffd>;
+				msi-controller;
+			};
+
+			v2m1: v2m@1 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x1000 0xffd>;
+				msi-controller;
+			};
+
+			v2m2: v2m@2 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x2000 0xffd>;
+				msi-controller;
+			};
+		};
+
+		timer@b120000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0xb120000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clock-frequency = <24000000>;
+
+			frame@b120000 {
+				reg = <0xb121000 0x1000>,
+				      <0xb122000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@b123000 {
+				reg = <0xb123000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				reg = <0xb124000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				reg = <0xb125000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				reg = <0xb126000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				reg = <0xb127000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				reg = <0xb128000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+	};
+};
-- 
2.17.1


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[PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[devi priya]

From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>

Add initial device tree support for Qualcomm IPQ9574 SoC
and AL02 board

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Co-developed-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
---
 arch/arm64/boot/dts/qcom/Makefile            |   1 +
 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
 arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
 3 files changed, 388 insertions(+)
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
 create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 3e79496292e7..872c62028a0b 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
+dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
 dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
new file mode 100644
index 000000000000..ae3c32f3e16a
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * IPQ9574 AL02-C7 board device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+/dts-v1/;
+
+#include "ipq9574.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
+	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &blsp1_uart2;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&blsp1_uart2 {
+	pinctrl-0 = <&uart2_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&sdhc_1 {
+	pinctrl-0 = <&emmc_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&tlmm {
+	emmc_pins: emmc-state {
+		emmc-clk-pins {
+			pins = "gpio5";
+			function = "sdc_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+		emmc-cmd-pins {
+			pins = "gpio4";
+			function = "sdc_cmd";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		emmc-data-pins {
+			pins = "gpio0", "gpio1", "gpio2",
+			     "gpio3", "gpio6", "gpio7",
+			     "gpio8", "gpio9";
+			function = "sdc_data";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+		emmc-rclk-pins {
+			pins = "gpio10";
+			function = "sdc_rclk";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+};
diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
new file mode 100644
index 000000000000..188d18688a77
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * IPQ9574 SoC device tree source
+ *
+ * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
+#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
+
+/ {
+	interrupt-parent = <&intc>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	clocks {
+		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <353000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <250000000>;
+			#clock-cells = <0>;
+		};
+
+		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
+			compatible = "fixed-clock";
+			clock-frequency = <125000000>;
+			#clock-cells = <0>;
+		};
+
+		sleep_clk: sleep-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
+
+		xo_board_clk: xo-board-clk {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		CPU0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x1>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x2>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		CPU3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a73";
+			reg = <0x3>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		L2_0: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		/* We expect the bootloader to fill in the size */
+		reg = <0x0 0x40000000 0x0 0x0>;
+	};
+
+	pmu {
+		compatible = "arm,cortex-a73-pmu";
+		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		tz_region: memory@4a600000 {
+			reg = <0x0 0x4a600000 0x0 0x400000>;
+			no-map;
+		};
+	};
+
+	soc: soc@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0 0 0xffffffff>;
+		compatible = "simple-bus";
+
+		tlmm: pinctrl@1000000 {
+			compatible = "qcom,ipq9574-tlmm";
+			reg = <0x01000000 0x300000>;
+			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&tlmm 0 0 65>;
+			gpio-reserved-ranges = <59 1>;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			uart2_pins: uart2-state {
+				pins = "gpio34", "gpio35";
+				function = "blsp2_uart";
+				drive-strength = <8>;
+				bias-disable;
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-ipq9574";
+			reg = <0x1800000 0x80000>;
+			clocks = <&xo_board_clk>,
+				<&sleep_clk>,
+				<&bias_pll_ubi_nc_clk>,
+				<&pcie30_phy0_pipe_clk>,
+				<&pcie30_phy1_pipe_clk>,
+				<&pcie30_phy2_pipe_clk>,
+				<&pcie30_phy3_pipe_clk>,
+				<&usb3phy_0_cc_pipe_clk>;
+			clock-names = "xo",
+				"sleep_clk",
+				"bias_pll_ubi_nc_clk",
+				"pcie30_phy0_pipe_clk",
+				"pcie30_phy1_pipe_clk",
+				"pcie30_phy2_pipe_clk",
+				"pcie30_phy3_pipe_clk",
+				"usb3phy_0_cc_pipe_clk";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		sdhc_1: sdhci@7804000 {
+			compatible = "qcom,sdhci-msm-v5";
+			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
+			reg-names = "hc_mem", "cmdq_mem";
+
+			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "hc_irq", "pwr_irq";
+
+			clocks = <&xo_board_clk>,
+			       <&gcc GCC_SDCC1_AHB_CLK>,
+			       <&gcc GCC_SDCC1_APPS_CLK>;
+			clock-names = "xo", "iface", "core";
+			mmc-ddr-1_8v;
+			mmc-hs200-1_8v;
+			mmc-hs400-1_8v;
+			mmc-hs400-enhanced-strobe;
+			max-frequency = <384000000>;
+			bus-width = <8>;
+			non-removable;
+			status = "disabled";
+		};
+
+		blsp1_uart2: serial@78b1000 {
+			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+			reg = <0x078b1000 0x200>;
+			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			status = "disabled";
+		};
+
+		intc: interrupt-controller@b000000 {
+			compatible = "qcom,msm-qgic2";
+			reg = <0x0b000000 0x1000>,  /* GICD */
+			      <0x0b002000 0x1000>,  /* GICC */
+			      <0x0b001000 0x1000>,  /* GICH */
+			      <0x0b004000 0x1000>;  /* GICV */
+			#address-cells = <1>;
+			#size-cells = <1>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+			ranges = <0 0x0b00c000 0x3000>;
+
+			v2m0: v2m@0 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x0 0xffd>;
+				msi-controller;
+			};
+
+			v2m1: v2m@1 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x1000 0xffd>;
+				msi-controller;
+			};
+
+			v2m2: v2m@2 {
+				compatible = "arm,gic-v2m-frame";
+				reg = <0x2000 0xffd>;
+				msi-controller;
+			};
+		};
+
+		timer@b120000 {
+			compatible = "arm,armv7-timer-mem";
+			reg = <0xb120000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+			clock-frequency = <24000000>;
+
+			frame@b120000 {
+				reg = <0xb121000 0x1000>,
+				      <0xb122000 0x1000>;
+				frame-number = <0>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			frame@b123000 {
+				reg = <0xb123000 0x1000>;
+				frame-number = <1>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b124000 {
+				reg = <0xb124000 0x1000>;
+				frame-number = <2>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b125000 {
+				reg = <0xb125000 0x1000>;
+				frame-number = <3>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b126000 {
+				reg = <0xb126000 0x1000>;
+				frame-number = <4>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b127000 {
+				reg = <0xb127000 0x1000>;
+				frame-number = <5>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+
+			frame@b128000 {
+				reg = <0xb128000 0x1000>;
+				frame-number = <6>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				status = "disabled";
+			};
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+		clock-frequency = <24000000>;
+	};
+};
-- 
2.17.1

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Konrad Dybcio]

On 10.01.2023 13:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>  3 files changed, 388 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..872c62028a0b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> new file mode 100644
> index 000000000000..ae3c32f3e16a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0-only
BSD3?

> +/*
> + * IPQ9574 AL02-C7 board device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
Happy new year!

> + */
> +
> +/dts-v1/;
> +
> +#include "ipq9574.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
> +	interrupt-parent = <&intc>;
> +
> +	aliases {
> +		serial0 = &blsp1_uart2;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&blsp1_uart2 {
> +	pinctrl-0 = <&uart2_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&sdhc_1 {
> +	pinctrl-0 = <&emmc_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&tlmm {
> +	emmc_pins: emmc-state {
sdc_default? I suppose you'll introduce a corresponding sleep state
later on, so that'll be easier to distinguish.

> +		emmc-clk-pins {
> +			pins = "gpio5";
> +			function = "sdc_clk";
> +			drive-strength = <8>;
> +			bias-disable;
> +		};
Please add a newline between subsequent nodes.
> +		emmc-cmd-pins {
> +			pins = "gpio4";
> +			function = "sdc_cmd";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-data-pins {
> +			pins = "gpio0", "gpio1", "gpio2",
> +			     "gpio3", "gpio6", "gpio7",
> +			     "gpio8", "gpio9";
The indentation here is wrong.

> +			function = "sdc_data";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-rclk-pins {
> +			pins = "gpio10";
> +			function = "sdc_rclk";
> +			drive-strength = <8>;
> +			bias-pull-down;
> +		};
> +	};
> +
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> new file mode 100644
> index 000000000000..188d18688a77
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -0,0 +1,318 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * IPQ9574 SoC device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
Could you tell us something about the purpose of this clock? First
time seeing it, your gcc driver reveals it's connected to at least
PCIe.

> +			compatible = "fixed-clock";
> +			clock-frequency = <353000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <125000000>;
> +			#clock-cells = <0>;
> +		};
Do not define these pipe clocks. You can leave the GCC entries as <0>
until you introduce the QMPPHY support, which then you can feed as it
provides these clocks.

> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
The clock frequency should be moved to the device DT, because the
clock is on the board and not on the SoC.

> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		L2_0: l2-cache {
> +			compatible = "cache";
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		/* We expect the bootloader to fill in the size */
> +		reg = <0x0 0x40000000 0x0 0x0>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a73-pmu";
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		tz_region: memory@4a600000 {
> +			reg = <0x0 0x4a600000 0x0 0x400000>;
> +			no-map;
> +		};
That's.. surprisingly little reserved memory.. No hyp? No PIL regions
that make the board explode when something touches them?

> +	};
> +
> +	soc: soc@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0xffffffff>;
Is 32 bits enough for this SoC's bus? Newer ones use 36 or more..

> +		compatible = "simple-bus";
> +
> +		tlmm: pinctrl@1000000 {
> +			compatible = "qcom,ipq9574-tlmm";
> +			reg = <0x01000000 0x300000>;
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 65>;
> +			gpio-reserved-ranges = <59 1>;
I see it's assigned to [rx0, pwm23, qdss_tracedata_a].. Is this
board-specific or is this pin supposed to be forbidden on all IPQ9574
boards?

> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart2_pins: uart2-state {
> +				pins = "gpio34", "gpio35";
> +				function = "blsp2_uart";
> +				drive-strength = <8>;
> +				bias-disable;
> +			};
> +		};
> +
> +		gcc: clock-controller@1800000 {
> +			compatible = "qcom,gcc-ipq9574";
> +			reg = <0x1800000 0x80000>;
> +			clocks = <&xo_board_clk>,
> +				<&sleep_clk>,
> +				<&bias_pll_ubi_nc_clk>,
> +				<&pcie30_phy0_pipe_clk>,
> +				<&pcie30_phy1_pipe_clk>,
> +				<&pcie30_phy2_pipe_clk>,
> +				<&pcie30_phy3_pipe_clk>,
> +				<&usb3phy_0_cc_pipe_clk>;
> +			clock-names = "xo",
> +				"sleep_clk",
> +				"bias_pll_ubi_nc_clk",
> +				"pcie30_phy0_pipe_clk",
> +				"pcie30_phy1_pipe_clk",
> +				"pcie30_phy2_pipe_clk",
> +				"pcie30_phy3_pipe_clk",
> +				"usb3phy_0_cc_pipe_clk";
Please touch up the indentation.

> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		sdhc_1: sdhci@7804000 {
> +			compatible = "qcom,sdhci-msm-v5";
> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
> +			reg-names = "hc_mem", "cmdq_mem";
> +
> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
Please touch up the indentation.

> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&xo_board_clk>,
> +			       <&gcc GCC_SDCC1_AHB_CLK>,
> +			       <&gcc GCC_SDCC1_APPS_CLK>;
Please touch up the indentation.

> +			clock-names = "xo", "iface", "core";
The order should be "iface", "core", "xo" as per Documentation/devicetree/bindings/mmc/sdhci-msm.yaml

> +			mmc-ddr-1_8v;
> +			mmc-hs200-1_8v;
> +			mmc-hs400-1_8v;
> +			mmc-hs400-enhanced-strobe;
Are these the limitations of the controller? Otherwise they should
probably be moved to the device-specific DT.

> +			max-frequency = <384000000>;
> +			bus-width = <8>;

> +			non-removable;
And this property too.
> +			status = "disabled";
> +		};
> +
> +		blsp1_uart2: serial@78b1000 {
> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +			reg = <0x078b1000 0x200>;
> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
> +				 <&gcc GCC_BLSP1_AHB_CLK>;
> +			clock-names = "core", "iface";
> +			status = "disabled";
> +		};
> +
> +		intc: interrupt-controller@b000000 {
> +			compatible = "qcom,msm-qgic2";
> +			reg = <0x0b000000 0x1000>,  /* GICD */
> +			      <0x0b002000 0x1000>,  /* GICC */
> +			      <0x0b001000 0x1000>,  /* GICH */
> +			      <0x0b004000 0x1000>;  /* GICV */
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			ranges = <0 0x0b00c000 0x3000>;
> +
> +			v2m0: v2m@0 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x0 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m1: v2m@1 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x1000 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m2: v2m@2 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x2000 0xffd>;
> +				msi-controller;
> +			};
> +		};
> +
> +		timer@b120000 {
> +			compatible = "arm,armv7-timer-mem";
> +			reg = <0xb120000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			clock-frequency = <24000000>;
Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.

> +
> +			frame@b120000 {
> +				reg = <0xb121000 0x1000>,
> +				      <0xb122000 0x1000>;
> +				frame-number = <0>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			frame@b123000 {
> +				reg = <0xb123000 0x1000>;
> +				frame-number = <1>;
> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b124000 {
> +				reg = <0xb124000 0x1000>;
> +				frame-number = <2>;
> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b125000 {
> +				reg = <0xb125000 0x1000>;
> +				frame-number = <3>;
> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b126000 {
> +				reg = <0xb126000 0x1000>;
> +				frame-number = <4>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b127000 {
> +				reg = <0xb127000 0x1000>;
> +				frame-number = <5>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b128000 {
> +				reg = <0xb128000 0x1000>;
> +				frame-number = <6>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24000000>;
Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.

Konrad
> +	};
> +};

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Konrad Dybcio]

On 10.01.2023 13:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>  3 files changed, 388 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..872c62028a0b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> new file mode 100644
> index 000000000000..ae3c32f3e16a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0-only
BSD3?

> +/*
> + * IPQ9574 AL02-C7 board device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
Happy new year!

> + */
> +
> +/dts-v1/;
> +
> +#include "ipq9574.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
> +	interrupt-parent = <&intc>;
> +
> +	aliases {
> +		serial0 = &blsp1_uart2;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&blsp1_uart2 {
> +	pinctrl-0 = <&uart2_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&sdhc_1 {
> +	pinctrl-0 = <&emmc_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&tlmm {
> +	emmc_pins: emmc-state {
sdc_default? I suppose you'll introduce a corresponding sleep state
later on, so that'll be easier to distinguish.

> +		emmc-clk-pins {
> +			pins = "gpio5";
> +			function = "sdc_clk";
> +			drive-strength = <8>;
> +			bias-disable;
> +		};
Please add a newline between subsequent nodes.
> +		emmc-cmd-pins {
> +			pins = "gpio4";
> +			function = "sdc_cmd";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-data-pins {
> +			pins = "gpio0", "gpio1", "gpio2",
> +			     "gpio3", "gpio6", "gpio7",
> +			     "gpio8", "gpio9";
The indentation here is wrong.

> +			function = "sdc_data";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-rclk-pins {
> +			pins = "gpio10";
> +			function = "sdc_rclk";
> +			drive-strength = <8>;
> +			bias-pull-down;
> +		};
> +	};
> +
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> new file mode 100644
> index 000000000000..188d18688a77
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -0,0 +1,318 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * IPQ9574 SoC device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
Could you tell us something about the purpose of this clock? First
time seeing it, your gcc driver reveals it's connected to at least
PCIe.

> +			compatible = "fixed-clock";
> +			clock-frequency = <353000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <125000000>;
> +			#clock-cells = <0>;
> +		};
Do not define these pipe clocks. You can leave the GCC entries as <0>
until you introduce the QMPPHY support, which then you can feed as it
provides these clocks.

> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;
The clock frequency should be moved to the device DT, because the
clock is on the board and not on the SoC.

> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		L2_0: l2-cache {
> +			compatible = "cache";
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		/* We expect the bootloader to fill in the size */
> +		reg = <0x0 0x40000000 0x0 0x0>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a73-pmu";
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		tz_region: memory@4a600000 {
> +			reg = <0x0 0x4a600000 0x0 0x400000>;
> +			no-map;
> +		};
That's.. surprisingly little reserved memory.. No hyp? No PIL regions
that make the board explode when something touches them?

> +	};
> +
> +	soc: soc@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0xffffffff>;
Is 32 bits enough for this SoC's bus? Newer ones use 36 or more..

> +		compatible = "simple-bus";
> +
> +		tlmm: pinctrl@1000000 {
> +			compatible = "qcom,ipq9574-tlmm";
> +			reg = <0x01000000 0x300000>;
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 65>;
> +			gpio-reserved-ranges = <59 1>;
I see it's assigned to [rx0, pwm23, qdss_tracedata_a].. Is this
board-specific or is this pin supposed to be forbidden on all IPQ9574
boards?

> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart2_pins: uart2-state {
> +				pins = "gpio34", "gpio35";
> +				function = "blsp2_uart";
> +				drive-strength = <8>;
> +				bias-disable;
> +			};
> +		};
> +
> +		gcc: clock-controller@1800000 {
> +			compatible = "qcom,gcc-ipq9574";
> +			reg = <0x1800000 0x80000>;
> +			clocks = <&xo_board_clk>,
> +				<&sleep_clk>,
> +				<&bias_pll_ubi_nc_clk>,
> +				<&pcie30_phy0_pipe_clk>,
> +				<&pcie30_phy1_pipe_clk>,
> +				<&pcie30_phy2_pipe_clk>,
> +				<&pcie30_phy3_pipe_clk>,
> +				<&usb3phy_0_cc_pipe_clk>;
> +			clock-names = "xo",
> +				"sleep_clk",
> +				"bias_pll_ubi_nc_clk",
> +				"pcie30_phy0_pipe_clk",
> +				"pcie30_phy1_pipe_clk",
> +				"pcie30_phy2_pipe_clk",
> +				"pcie30_phy3_pipe_clk",
> +				"usb3phy_0_cc_pipe_clk";
Please touch up the indentation.

> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		sdhc_1: sdhci@7804000 {
> +			compatible = "qcom,sdhci-msm-v5";
> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
> +			reg-names = "hc_mem", "cmdq_mem";
> +
> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
Please touch up the indentation.

> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&xo_board_clk>,
> +			       <&gcc GCC_SDCC1_AHB_CLK>,
> +			       <&gcc GCC_SDCC1_APPS_CLK>;
Please touch up the indentation.

> +			clock-names = "xo", "iface", "core";
The order should be "iface", "core", "xo" as per Documentation/devicetree/bindings/mmc/sdhci-msm.yaml

> +			mmc-ddr-1_8v;
> +			mmc-hs200-1_8v;
> +			mmc-hs400-1_8v;
> +			mmc-hs400-enhanced-strobe;
Are these the limitations of the controller? Otherwise they should
probably be moved to the device-specific DT.

> +			max-frequency = <384000000>;
> +			bus-width = <8>;

> +			non-removable;
And this property too.
> +			status = "disabled";
> +		};
> +
> +		blsp1_uart2: serial@78b1000 {
> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +			reg = <0x078b1000 0x200>;
> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
> +				 <&gcc GCC_BLSP1_AHB_CLK>;
> +			clock-names = "core", "iface";
> +			status = "disabled";
> +		};
> +
> +		intc: interrupt-controller@b000000 {
> +			compatible = "qcom,msm-qgic2";
> +			reg = <0x0b000000 0x1000>,  /* GICD */
> +			      <0x0b002000 0x1000>,  /* GICC */
> +			      <0x0b001000 0x1000>,  /* GICH */
> +			      <0x0b004000 0x1000>;  /* GICV */
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			ranges = <0 0x0b00c000 0x3000>;
> +
> +			v2m0: v2m@0 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x0 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m1: v2m@1 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x1000 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m2: v2m@2 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x2000 0xffd>;
> +				msi-controller;
> +			};
> +		};
> +
> +		timer@b120000 {
> +			compatible = "arm,armv7-timer-mem";
> +			reg = <0xb120000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			clock-frequency = <24000000>;
Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.

> +
> +			frame@b120000 {
> +				reg = <0xb121000 0x1000>,
> +				      <0xb122000 0x1000>;
> +				frame-number = <0>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			frame@b123000 {
> +				reg = <0xb123000 0x1000>;
> +				frame-number = <1>;
> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b124000 {
> +				reg = <0xb124000 0x1000>;
> +				frame-number = <2>;
> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b125000 {
> +				reg = <0xb125000 0x1000>;
> +				frame-number = <3>;
> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b126000 {
> +				reg = <0xb126000 0x1000>;
> +				frame-number = <4>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b127000 {
> +				reg = <0xb127000 0x1000>;
> +				frame-number = <5>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b128000 {
> +				reg = <0xb128000 0x1000>;
> +				frame-number = <6>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24000000>;
Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.

Konrad
> +	};
> +};

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/10/2023 6:20 PM, Konrad Dybcio wrote:
> 
> 
> On 10.01.2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>   3 files changed, 388 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -0,0 +1,69 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
> BSD3?
> 
Sure, will add dual license
>> +/*
>> + * IPQ9574 AL02-C7 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> Happy new year!
> 
Sure, will update!
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>> +	interrupt-parent = <&intc>;
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	pinctrl-0 = <&uart2_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&sdhc_1 {
>> +	pinctrl-0 = <&emmc_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&tlmm {
>> +	emmc_pins: emmc-state {
> sdc_default? I suppose you'll introduce a corresponding sleep state
> later on, so that'll be easier to distinguish.
Sure, will update the node name. But, we don't have power management 
states. It would always be in the running state.
> 
>> +		emmc-clk-pins {
>> +			pins = "gpio5";
>> +			function = "sdc_clk";
>> +			drive-strength = <8>;
>> +			bias-disable;
>> +		};
> Please add a newline between subsequent nodes.
Sure, okay
>> +		emmc-cmd-pins {
>> +			pins = "gpio4";
>> +			function = "sdc_cmd";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-data-pins {
>> +			pins = "gpio0", "gpio1", "gpio2",
>> +			     "gpio3", "gpio6", "gpio7",
>> +			     "gpio8", "gpio9";
> The indentation here is wrong.
Sure, will update
> 
>> +			function = "sdc_data";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-rclk-pins {
>> +			pins = "gpio10";
>> +			function = "sdc_rclk";
>> +			drive-strength = <8>;
>> +			bias-pull-down;
>> +		};
>> +	};
>> +
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> new file mode 100644
>> index 000000000000..188d18688a77
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -0,0 +1,318 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * IPQ9574 SoC device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
> Could you tell us something about the purpose of this clock? First
> time seeing it, your gcc driver reveals it's connected to at least
> PCIe.
Bias_pll_ubi_nc_clk (353MHz) is a backup source for 
Q6_AXIM2_CLK/PCIE2_AXIM_CLK/PCIE3_AXIM_CLK/SNOC-CLK.
> 
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <353000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <125000000>;
>> +			#clock-cells = <0>;
>> +		};
> Do not define these pipe clocks. You can leave the GCC entries as <0>
> until you introduce the QMPPHY support, which then you can feed as it
> provides these clocks.
Sure, okay
> 
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
> The clock frequency should be moved to the device DT, because the
> clock is on the board and not on the SoC.
Okay, will move to device DT
> 
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x0>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x1>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x2>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x3>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		L2_0: l2-cache {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +		};
>> +	};
>> +
>> +	memory@40000000 {
>> +		device_type = "memory";
>> +		/* We expect the bootloader to fill in the size */
>> +		reg = <0x0 0x40000000 0x0 0x0>;
>> +	};
>> +
>> +	pmu {
>> +		compatible = "arm,cortex-a73-pmu";
>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-1.0";
>> +		method = "smc";
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		tz_region: memory@4a600000 {
>> +			reg = <0x0 0x4a600000 0x0 0x400000>;
>> +			no-map;
>> +		};
> That's.. surprisingly little reserved memory.. No hyp? No PIL regions
> that make the board explode when something touches them?
> 
The reserved memory for TZ region is 4Mb. yes,we have hypervisor and PIL 
regions.
The memory for PIL region will be separately reserved by the remoteproc
>> +	};
>> +
>> +	soc: soc@0 {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0 0 0 0xffffffff>;
> Is 32 bits enough for this SoC's bus? Newer ones use 36 or more..
Yes, as the maximum range supported by ipq9574 is 4GB, 32 bits would be 
sufficient
> 
>> +		compatible = "simple-bus";
>> +
>> +		tlmm: pinctrl@1000000 {
>> +			compatible = "qcom,ipq9574-tlmm";
>> +			reg = <0x01000000 0x300000>;
>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&tlmm 0 0 65>;
>> +			gpio-reserved-ranges = <59 1>;
> I see it's assigned to [rx0, pwm23, qdss_tracedata_a].. Is this
> board-specific or is this pin supposed to be forbidden on all IPQ9574
> boards?
This pin is reserved by TZ and is forbidden on all IPQ9574 boards.
> 
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart2_pins: uart2-state {
>> +				pins = "gpio34", "gpio35";
>> +				function = "blsp2_uart";
>> +				drive-strength = <8>;
>> +				bias-disable;
>> +			};
>> +		};
>> +
>> +		gcc: clock-controller@1800000 {
>> +			compatible = "qcom,gcc-ipq9574";
>> +			reg = <0x1800000 0x80000>;
>> +			clocks = <&xo_board_clk>,
>> +				<&sleep_clk>,
>> +				<&bias_pll_ubi_nc_clk>,
>> +				<&pcie30_phy0_pipe_clk>,
>> +				<&pcie30_phy1_pipe_clk>,
>> +				<&pcie30_phy2_pipe_clk>,
>> +				<&pcie30_phy3_pipe_clk>,
>> +				<&usb3phy_0_cc_pipe_clk>;
>> +			clock-names = "xo",
>> +				"sleep_clk",
>> +				"bias_pll_ubi_nc_clk",
>> +				"pcie30_phy0_pipe_clk",
>> +				"pcie30_phy1_pipe_clk",
>> +				"pcie30_phy2_pipe_clk",
>> +				"pcie30_phy3_pipe_clk",
>> +				"usb3phy_0_cc_pipe_clk";
> Please touch up the indentation.
> 
Sure okay
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		sdhc_1: sdhci@7804000 {
>> +			compatible = "qcom,sdhci-msm-v5";
>> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>> +			reg-names = "hc_mem", "cmdq_mem";
>> +
>> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> Please touch up the indentation.
Okay
> 
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&xo_board_clk>,
>> +			       <&gcc GCC_SDCC1_AHB_CLK>,
>> +			       <&gcc GCC_SDCC1_APPS_CLK>;
> Please touch up the indentation.
> 
Sure, will do
>> +			clock-names = "xo", "iface", "core";
> The order should be "iface", "core", "xo" as per Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
Got it, will update
> 
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
>> +			mmc-hs400-1_8v;
>> +			mmc-hs400-enhanced-strobe;
> Are these the limitations of the controller? Otherwise they should
> probably be moved to the device-specific DT.
Yes, these are specific to the controller, hence added them in SoC
> 
>> +			max-frequency = <384000000>;
>> +			bus-width = <8>;
> 
>> +			non-removable;
> And this property too.
Yes, it is specific to the controller
>> +			status = "disabled";
>> +		};
>> +
>> +		blsp1_uart2: serial@78b1000 {
>> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +			reg = <0x078b1000 0x200>;
>> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> +				 <&gcc GCC_BLSP1_AHB_CLK>;
>> +			clock-names = "core", "iface";
>> +			status = "disabled";
>> +		};
>> +
>> +		intc: interrupt-controller@b000000 {
>> +			compatible = "qcom,msm-qgic2";
>> +			reg = <0x0b000000 0x1000>,  /* GICD */
>> +			      <0x0b002000 0x1000>,  /* GICC */
>> +			      <0x0b001000 0x1000>,  /* GICH */
>> +			      <0x0b004000 0x1000>;  /* GICV */
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges = <0 0x0b00c000 0x3000>;
>> +
>> +			v2m0: v2m@0 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x0 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m1: v2m@1 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x1000 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m2: v2m@2 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x2000 0xffd>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		timer@b120000 {
>> +			compatible = "arm,armv7-timer-mem";
>> +			reg = <0xb120000 0x1000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			clock-frequency = <24000000>;
> Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.
> 
Sure, okay
>> +
>> +			frame@b120000 {
>> +				reg = <0xb121000 0x1000>,
>> +				      <0xb122000 0x1000>;
>> +				frame-number = <0>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			frame@b123000 {
>> +				reg = <0xb123000 0x1000>;
>> +				frame-number = <1>;
>> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b124000 {
>> +				reg = <0xb124000 0x1000>;
>> +				frame-number = <2>;
>> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b125000 {
>> +				reg = <0xb125000 0x1000>;
>> +				frame-number = <3>;
>> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b126000 {
>> +				reg = <0xb126000 0x1000>;
>> +				frame-number = <4>;
>> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b127000 {
>> +				reg = <0xb127000 0x1000>;
>> +				frame-number = <5>;
>> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b128000 {
>> +				reg = <0xb128000 0x1000>;
>> +				frame-number = <6>;
>> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +		clock-frequency = <24000000>;
> Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.
> 
Okay
> Konrad
>> +	};
>> +};
Best Regards,
Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/10/2023 6:20 PM, Konrad Dybcio wrote:
> 
> 
> On 10.01.2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>   3 files changed, 388 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -0,0 +1,69 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
> BSD3?
> 
Sure, will add dual license
>> +/*
>> + * IPQ9574 AL02-C7 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> Happy new year!
> 
Sure, will update!
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>> +	interrupt-parent = <&intc>;
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	pinctrl-0 = <&uart2_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&sdhc_1 {
>> +	pinctrl-0 = <&emmc_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&tlmm {
>> +	emmc_pins: emmc-state {
> sdc_default? I suppose you'll introduce a corresponding sleep state
> later on, so that'll be easier to distinguish.
Sure, will update the node name. But, we don't have power management 
states. It would always be in the running state.
> 
>> +		emmc-clk-pins {
>> +			pins = "gpio5";
>> +			function = "sdc_clk";
>> +			drive-strength = <8>;
>> +			bias-disable;
>> +		};
> Please add a newline between subsequent nodes.
Sure, okay
>> +		emmc-cmd-pins {
>> +			pins = "gpio4";
>> +			function = "sdc_cmd";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-data-pins {
>> +			pins = "gpio0", "gpio1", "gpio2",
>> +			     "gpio3", "gpio6", "gpio7",
>> +			     "gpio8", "gpio9";
> The indentation here is wrong.
Sure, will update
> 
>> +			function = "sdc_data";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-rclk-pins {
>> +			pins = "gpio10";
>> +			function = "sdc_rclk";
>> +			drive-strength = <8>;
>> +			bias-pull-down;
>> +		};
>> +	};
>> +
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> new file mode 100644
>> index 000000000000..188d18688a77
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -0,0 +1,318 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * IPQ9574 SoC device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
> Could you tell us something about the purpose of this clock? First
> time seeing it, your gcc driver reveals it's connected to at least
> PCIe.
Bias_pll_ubi_nc_clk (353MHz) is a backup source for 
Q6_AXIM2_CLK/PCIE2_AXIM_CLK/PCIE3_AXIM_CLK/SNOC-CLK.
> 
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <353000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <125000000>;
>> +			#clock-cells = <0>;
>> +		};
> Do not define these pipe clocks. You can leave the GCC entries as <0>
> until you introduce the QMPPHY support, which then you can feed as it
> provides these clocks.
Sure, okay
> 
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
> The clock frequency should be moved to the device DT, because the
> clock is on the board and not on the SoC.
Okay, will move to device DT
> 
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x0>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x1>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x2>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x3>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		L2_0: l2-cache {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +		};
>> +	};
>> +
>> +	memory@40000000 {
>> +		device_type = "memory";
>> +		/* We expect the bootloader to fill in the size */
>> +		reg = <0x0 0x40000000 0x0 0x0>;
>> +	};
>> +
>> +	pmu {
>> +		compatible = "arm,cortex-a73-pmu";
>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-1.0";
>> +		method = "smc";
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		tz_region: memory@4a600000 {
>> +			reg = <0x0 0x4a600000 0x0 0x400000>;
>> +			no-map;
>> +		};
> That's.. surprisingly little reserved memory.. No hyp? No PIL regions
> that make the board explode when something touches them?
> 
The reserved memory for TZ region is 4Mb. yes,we have hypervisor and PIL 
regions.
The memory for PIL region will be separately reserved by the remoteproc
>> +	};
>> +
>> +	soc: soc@0 {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0 0 0 0xffffffff>;
> Is 32 bits enough for this SoC's bus? Newer ones use 36 or more..
Yes, as the maximum range supported by ipq9574 is 4GB, 32 bits would be 
sufficient
> 
>> +		compatible = "simple-bus";
>> +
>> +		tlmm: pinctrl@1000000 {
>> +			compatible = "qcom,ipq9574-tlmm";
>> +			reg = <0x01000000 0x300000>;
>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&tlmm 0 0 65>;
>> +			gpio-reserved-ranges = <59 1>;
> I see it's assigned to [rx0, pwm23, qdss_tracedata_a].. Is this
> board-specific or is this pin supposed to be forbidden on all IPQ9574
> boards?
This pin is reserved by TZ and is forbidden on all IPQ9574 boards.
> 
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart2_pins: uart2-state {
>> +				pins = "gpio34", "gpio35";
>> +				function = "blsp2_uart";
>> +				drive-strength = <8>;
>> +				bias-disable;
>> +			};
>> +		};
>> +
>> +		gcc: clock-controller@1800000 {
>> +			compatible = "qcom,gcc-ipq9574";
>> +			reg = <0x1800000 0x80000>;
>> +			clocks = <&xo_board_clk>,
>> +				<&sleep_clk>,
>> +				<&bias_pll_ubi_nc_clk>,
>> +				<&pcie30_phy0_pipe_clk>,
>> +				<&pcie30_phy1_pipe_clk>,
>> +				<&pcie30_phy2_pipe_clk>,
>> +				<&pcie30_phy3_pipe_clk>,
>> +				<&usb3phy_0_cc_pipe_clk>;
>> +			clock-names = "xo",
>> +				"sleep_clk",
>> +				"bias_pll_ubi_nc_clk",
>> +				"pcie30_phy0_pipe_clk",
>> +				"pcie30_phy1_pipe_clk",
>> +				"pcie30_phy2_pipe_clk",
>> +				"pcie30_phy3_pipe_clk",
>> +				"usb3phy_0_cc_pipe_clk";
> Please touch up the indentation.
> 
Sure okay
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		sdhc_1: sdhci@7804000 {
>> +			compatible = "qcom,sdhci-msm-v5";
>> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>> +			reg-names = "hc_mem", "cmdq_mem";
>> +
>> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> Please touch up the indentation.
Okay
> 
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&xo_board_clk>,
>> +			       <&gcc GCC_SDCC1_AHB_CLK>,
>> +			       <&gcc GCC_SDCC1_APPS_CLK>;
> Please touch up the indentation.
> 
Sure, will do
>> +			clock-names = "xo", "iface", "core";
> The order should be "iface", "core", "xo" as per Documentation/devicetree/bindings/mmc/sdhci-msm.yaml
Got it, will update
> 
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
>> +			mmc-hs400-1_8v;
>> +			mmc-hs400-enhanced-strobe;
> Are these the limitations of the controller? Otherwise they should
> probably be moved to the device-specific DT.
Yes, these are specific to the controller, hence added them in SoC
> 
>> +			max-frequency = <384000000>;
>> +			bus-width = <8>;
> 
>> +			non-removable;
> And this property too.
Yes, it is specific to the controller
>> +			status = "disabled";
>> +		};
>> +
>> +		blsp1_uart2: serial@78b1000 {
>> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +			reg = <0x078b1000 0x200>;
>> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> +				 <&gcc GCC_BLSP1_AHB_CLK>;
>> +			clock-names = "core", "iface";
>> +			status = "disabled";
>> +		};
>> +
>> +		intc: interrupt-controller@b000000 {
>> +			compatible = "qcom,msm-qgic2";
>> +			reg = <0x0b000000 0x1000>,  /* GICD */
>> +			      <0x0b002000 0x1000>,  /* GICC */
>> +			      <0x0b001000 0x1000>,  /* GICH */
>> +			      <0x0b004000 0x1000>;  /* GICV */
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges = <0 0x0b00c000 0x3000>;
>> +
>> +			v2m0: v2m@0 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x0 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m1: v2m@1 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x1000 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m2: v2m@2 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x2000 0xffd>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		timer@b120000 {
>> +			compatible = "arm,armv7-timer-mem";
>> +			reg = <0xb120000 0x1000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			clock-frequency = <24000000>;
> Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.
> 
Sure, okay
>> +
>> +			frame@b120000 {
>> +				reg = <0xb121000 0x1000>,
>> +				      <0xb122000 0x1000>;
>> +				frame-number = <0>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			frame@b123000 {
>> +				reg = <0xb123000 0x1000>;
>> +				frame-number = <1>;
>> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b124000 {
>> +				reg = <0xb124000 0x1000>;
>> +				frame-number = <2>;
>> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b125000 {
>> +				reg = <0xb125000 0x1000>;
>> +				frame-number = <3>;
>> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b126000 {
>> +				reg = <0xb126000 0x1000>;
>> +				frame-number = <4>;
>> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b127000 {
>> +				reg = <0xb127000 0x1000>;
>> +				frame-number = <5>;
>> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b128000 {
>> +				reg = <0xb128000 0x1000>;
>> +				frame-number = <6>;
>> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +		clock-frequency = <24000000>;
> Drop, something earlier in the boot chain already writes to CNTFRQ_ELn.
> 
Okay
> Konrad
>> +	};
>> +};
Best Regards,
Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>  3 files changed, 388 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..872c62028a0b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> new file mode 100644
> index 000000000000..ae3c32f3e16a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0-only

Not dual licensed? Not BSD?

> +/*
> + * IPQ9574 AL02-C7 board device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq9574.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
> +	interrupt-parent = <&intc>;
> +
> +	aliases {
> +		serial0 = &blsp1_uart2;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&blsp1_uart2 {
> +	pinctrl-0 = <&uart2_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&sdhc_1 {
> +	pinctrl-0 = <&emmc_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&tlmm {
> +	emmc_pins: emmc-state {
> +		emmc-clk-pins {
> +			pins = "gpio5";
> +			function = "sdc_clk";
> +			drive-strength = <8>;
> +			bias-disable;
> +		};
> +		emmc-cmd-pins {
> +			pins = "gpio4";
> +			function = "sdc_cmd";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-data-pins {
> +			pins = "gpio0", "gpio1", "gpio2",
> +			     "gpio3", "gpio6", "gpio7",
> +			     "gpio8", "gpio9";
> +			function = "sdc_data";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-rclk-pins {
> +			pins = "gpio10";
> +			function = "sdc_rclk";
> +			drive-strength = <8>;
> +			bias-pull-down;
> +		};
> +	};
> +
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> new file mode 100644
> index 000000000000..188d18688a77
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -0,0 +1,318 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * IPQ9574 SoC device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {

No undercores in node names.

> +			compatible = "fixed-clock";
> +			clock-frequency = <353000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <125000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32000>;

That's not a property of the SoC, but board. Either entire clock or at
least frequency to indicate that the board is providing the clock.

> +			#clock-cells = <0>;> +		};
> +
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;

Ditto.

> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		L2_0: l2-cache {
> +			compatible = "cache";
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		/* We expect the bootloader to fill in the size */
> +		reg = <0x0 0x40000000 0x0 0x0>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a73-pmu";
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		tz_region: memory@4a600000 {
> +			reg = <0x0 0x4a600000 0x0 0x400000>;
> +			no-map;
> +		};
> +	};
> +
> +	soc: soc@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0xffffffff>;
> +		compatible = "simple-bus";
> +
> +		tlmm: pinctrl@1000000 {
> +			compatible = "qcom,ipq9574-tlmm";
> +			reg = <0x01000000 0x300000>;
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 65>;
> +			gpio-reserved-ranges = <59 1>;

Hm, why reserved ranges are in SoC?

> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart2_pins: uart2-state {
> +				pins = "gpio34", "gpio35";
> +				function = "blsp2_uart";
> +				drive-strength = <8>;
> +				bias-disable;
> +			};
> +		};
> +
> +		gcc: clock-controller@1800000 {
> +			compatible = "qcom,gcc-ipq9574";
> +			reg = <0x1800000 0x80000>;
> +			clocks = <&xo_board_clk>,
> +				<&sleep_clk>,
> +				<&bias_pll_ubi_nc_clk>,
> +				<&pcie30_phy0_pipe_clk>,
> +				<&pcie30_phy1_pipe_clk>,
> +				<&pcie30_phy2_pipe_clk>,
> +				<&pcie30_phy3_pipe_clk>,
> +				<&usb3phy_0_cc_pipe_clk>;
> +			clock-names = "xo",
> +				"sleep_clk",

Misaligned. Multiple other places probably as well.

> +				"bias_pll_ubi_nc_clk",
> +				"pcie30_phy0_pipe_clk",
> +				"pcie30_phy1_pipe_clk",
> +				"pcie30_phy2_pipe_clk",
> +				"pcie30_phy3_pipe_clk",
> +				"usb3phy_0_cc_pipe_clk";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		sdhc_1: sdhci@7804000 {
> +			compatible = "qcom,sdhci-msm-v5";
> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
> +			reg-names = "hc_mem", "cmdq_mem";
> +
> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

Like here.

> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&xo_board_clk>,
> +			       <&gcc GCC_SDCC1_AHB_CLK>,
> +			       <&gcc GCC_SDCC1_APPS_CLK>;

And here

> +			clock-names = "xo", "iface", "core";

Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).

> +			mmc-ddr-1_8v;
> +			mmc-hs200-1_8v;
> +			mmc-hs400-1_8v;
> +			mmc-hs400-enhanced-strobe;
> +			max-frequency = <384000000>;
> +			bus-width = <8>;
> +			non-removable;
> +			status = "disabled";
> +		};
> +
> +		blsp1_uart2: serial@78b1000 {
> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +			reg = <0x078b1000 0x200>;
> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
> +				 <&gcc GCC_BLSP1_AHB_CLK>;
> +			clock-names = "core", "iface";
> +			status = "disabled";
> +		};
> +
> +		intc: interrupt-controller@b000000 {
> +			compatible = "qcom,msm-qgic2";
> +			reg = <0x0b000000 0x1000>,  /* GICD */
> +			      <0x0b002000 0x1000>,  /* GICC */
> +			      <0x0b001000 0x1000>,  /* GICH */
> +			      <0x0b004000 0x1000>;  /* GICV */
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			ranges = <0 0x0b00c000 0x3000>;
> +
> +			v2m0: v2m@0 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x0 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m1: v2m@1 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x1000 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m2: v2m@2 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x2000 0xffd>;
> +				msi-controller;
> +			};
> +		};
> +
> +		timer@b120000 {
> +			compatible = "arm,armv7-timer-mem";
> +			reg = <0xb120000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			clock-frequency = <24000000>;
> +
> +			frame@b120000 {
> +				reg = <0xb121000 0x1000>,
> +				      <0xb122000 0x1000>;
> +				frame-number = <0>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			frame@b123000 {
> +				reg = <0xb123000 0x1000>;
> +				frame-number = <1>;
> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b124000 {
> +				reg = <0xb124000 0x1000>;
> +				frame-number = <2>;
> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b125000 {
> +				reg = <0xb125000 0x1000>;
> +				frame-number = <3>;
> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b126000 {
> +				reg = <0xb126000 0x1000>;
> +				frame-number = <4>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b127000 {
> +				reg = <0xb127000 0x1000>;
> +				frame-number = <5>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b128000 {
> +				reg = <0xb128000 0x1000>;
> +				frame-number = <6>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24000000>;

Is this allowed in recent designs?

> +	};
> +};

Best regards,
Krzysztof


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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>  3 files changed, 388 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..872c62028a0b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> new file mode 100644
> index 000000000000..ae3c32f3e16a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> @@ -0,0 +1,69 @@
> +// SPDX-License-Identifier: GPL-2.0-only

Not dual licensed? Not BSD?

> +/*
> + * IPQ9574 AL02-C7 board device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "ipq9574.dtsi"
> +
> +/ {
> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
> +	interrupt-parent = <&intc>;
> +
> +	aliases {
> +		serial0 = &blsp1_uart2;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +};
> +
> +&blsp1_uart2 {
> +	pinctrl-0 = <&uart2_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&sdhc_1 {
> +	pinctrl-0 = <&emmc_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +};
> +
> +&tlmm {
> +	emmc_pins: emmc-state {
> +		emmc-clk-pins {
> +			pins = "gpio5";
> +			function = "sdc_clk";
> +			drive-strength = <8>;
> +			bias-disable;
> +		};
> +		emmc-cmd-pins {
> +			pins = "gpio4";
> +			function = "sdc_cmd";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-data-pins {
> +			pins = "gpio0", "gpio1", "gpio2",
> +			     "gpio3", "gpio6", "gpio7",
> +			     "gpio8", "gpio9";
> +			function = "sdc_data";
> +			drive-strength = <8>;
> +			bias-pull-up;
> +		};
> +		emmc-rclk-pins {
> +			pins = "gpio10";
> +			function = "sdc_rclk";
> +			drive-strength = <8>;
> +			bias-pull-down;
> +		};
> +	};
> +
> +};
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> new file mode 100644
> index 000000000000..188d18688a77
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
> @@ -0,0 +1,318 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * IPQ9574 SoC device tree source
> + *
> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
> +
> +/ {
> +	interrupt-parent = <&intc>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	clocks {
> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {

No undercores in node names.

> +			compatible = "fixed-clock";
> +			clock-frequency = <353000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <250000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <125000000>;
> +			#clock-cells = <0>;
> +		};
> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <32000>;

That's not a property of the SoC, but board. Either entire clock or at
least frequency to indicate that the board is providing the clock.

> +			#clock-cells = <0>;> +		};
> +
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			clock-frequency = <24000000>;

Ditto.

> +			#clock-cells = <0>;
> +		};
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		CPU0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		CPU3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a73";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			next-level-cache = <&L2_0>;
> +		};
> +
> +		L2_0: l2-cache {
> +			compatible = "cache";
> +			cache-level = <2>;
> +		};
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		/* We expect the bootloader to fill in the size */
> +		reg = <0x0 0x40000000 0x0 0x0>;
> +	};
> +
> +	pmu {
> +		compatible = "arm,cortex-a73-pmu";
> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		tz_region: memory@4a600000 {
> +			reg = <0x0 0x4a600000 0x0 0x400000>;
> +			no-map;
> +		};
> +	};
> +
> +	soc: soc@0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0 0 0xffffffff>;
> +		compatible = "simple-bus";
> +
> +		tlmm: pinctrl@1000000 {
> +			compatible = "qcom,ipq9574-tlmm";
> +			reg = <0x01000000 0x300000>;
> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-ranges = <&tlmm 0 0 65>;
> +			gpio-reserved-ranges = <59 1>;

Hm, why reserved ranges are in SoC?

> +			interrupt-controller;
> +			#interrupt-cells = <2>;
> +
> +			uart2_pins: uart2-state {
> +				pins = "gpio34", "gpio35";
> +				function = "blsp2_uart";
> +				drive-strength = <8>;
> +				bias-disable;
> +			};
> +		};
> +
> +		gcc: clock-controller@1800000 {
> +			compatible = "qcom,gcc-ipq9574";
> +			reg = <0x1800000 0x80000>;
> +			clocks = <&xo_board_clk>,
> +				<&sleep_clk>,
> +				<&bias_pll_ubi_nc_clk>,
> +				<&pcie30_phy0_pipe_clk>,
> +				<&pcie30_phy1_pipe_clk>,
> +				<&pcie30_phy2_pipe_clk>,
> +				<&pcie30_phy3_pipe_clk>,
> +				<&usb3phy_0_cc_pipe_clk>;
> +			clock-names = "xo",
> +				"sleep_clk",

Misaligned. Multiple other places probably as well.

> +				"bias_pll_ubi_nc_clk",
> +				"pcie30_phy0_pipe_clk",
> +				"pcie30_phy1_pipe_clk",
> +				"pcie30_phy2_pipe_clk",
> +				"pcie30_phy3_pipe_clk",
> +				"usb3phy_0_cc_pipe_clk";
> +			#clock-cells = <1>;
> +			#reset-cells = <1>;
> +		};
> +
> +		sdhc_1: sdhci@7804000 {
> +			compatible = "qcom,sdhci-msm-v5";
> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
> +			reg-names = "hc_mem", "cmdq_mem";
> +
> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

Like here.

> +			interrupt-names = "hc_irq", "pwr_irq";
> +
> +			clocks = <&xo_board_clk>,
> +			       <&gcc GCC_SDCC1_AHB_CLK>,
> +			       <&gcc GCC_SDCC1_APPS_CLK>;

And here

> +			clock-names = "xo", "iface", "core";

Does not look like you tested the bindings. Please run `make
dt_binding_check` (see
Documentation/devicetree/bindings/writing-schema.rst for instructions).

> +			mmc-ddr-1_8v;
> +			mmc-hs200-1_8v;
> +			mmc-hs400-1_8v;
> +			mmc-hs400-enhanced-strobe;
> +			max-frequency = <384000000>;
> +			bus-width = <8>;
> +			non-removable;
> +			status = "disabled";
> +		};
> +
> +		blsp1_uart2: serial@78b1000 {
> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> +			reg = <0x078b1000 0x200>;
> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
> +				 <&gcc GCC_BLSP1_AHB_CLK>;
> +			clock-names = "core", "iface";
> +			status = "disabled";
> +		};
> +
> +		intc: interrupt-controller@b000000 {
> +			compatible = "qcom,msm-qgic2";
> +			reg = <0x0b000000 0x1000>,  /* GICD */
> +			      <0x0b002000 0x1000>,  /* GICC */
> +			      <0x0b001000 0x1000>,  /* GICH */
> +			      <0x0b004000 0x1000>;  /* GICV */
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			ranges = <0 0x0b00c000 0x3000>;
> +
> +			v2m0: v2m@0 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x0 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m1: v2m@1 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x1000 0xffd>;
> +				msi-controller;
> +			};
> +
> +			v2m2: v2m@2 {
> +				compatible = "arm,gic-v2m-frame";
> +				reg = <0x2000 0xffd>;
> +				msi-controller;
> +			};
> +		};
> +
> +		timer@b120000 {
> +			compatible = "arm,armv7-timer-mem";
> +			reg = <0xb120000 0x1000>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges;
> +			clock-frequency = <24000000>;
> +
> +			frame@b120000 {
> +				reg = <0xb121000 0x1000>,
> +				      <0xb122000 0x1000>;
> +				frame-number = <0>;
> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			frame@b123000 {
> +				reg = <0xb123000 0x1000>;
> +				frame-number = <1>;
> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b124000 {
> +				reg = <0xb124000 0x1000>;
> +				frame-number = <2>;
> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b125000 {
> +				reg = <0xb125000 0x1000>;
> +				frame-number = <3>;
> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b126000 {
> +				reg = <0xb126000 0x1000>;
> +				frame-number = <4>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b127000 {
> +				reg = <0xb127000 0x1000>;
> +				frame-number = <5>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +
> +			frame@b128000 {
> +				reg = <0xb128000 0x1000>;
> +				frame-number = <6>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +		clock-frequency = <24000000>;

Is this allowed in recent designs?

> +	};
> +};

Best regards,
Krzysztof

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 11/01/2023 10:44, Krzysztof Kozlowski wrote:
> And here
> 
>> +			clock-names = "xo", "iface", "core";
> 
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).

Apologies, wrong template. Correct comment:

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

Best regards,
Krzysztof


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linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 11/01/2023 10:44, Krzysztof Kozlowski wrote:
> And here
> 
>> +			clock-names = "xo", "iface", "core";
> 
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).

Apologies, wrong template. Correct comment:

Does not look like you tested the DTS against bindings. Please run `make
dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
for instructions).

Best regards,
Krzysztof

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 3:18 PM, Krzysztof Kozlowski wrote:
> On 11/01/2023 10:44, Krzysztof Kozlowski wrote:
>> And here
>>
>>> +			clock-names = "xo", "iface", "core";
>>
>> Does not look like you tested the bindings. Please run `make
>> dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> 
> Apologies, wrong template. Correct comment:
> 
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
> 
Sure, will check
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

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linux-arm-kernel mailing list
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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 3:18 PM, Krzysztof Kozlowski wrote:
> On 11/01/2023 10:44, Krzysztof Kozlowski wrote:
>> And here
>>
>>> +			clock-names = "xo", "iface", "core";
>>
>> Does not look like you tested the bindings. Please run `make
>> dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
> 
> Apologies, wrong template. Correct comment:
> 
> Does not look like you tested the DTS against bindings. Please run `make
> dtbs_check` (see Documentation/devicetree/bindings/writing-schema.rst
> for instructions).
> 
Sure, will check
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Kathiravan Thirumoorthy]

On 1/11/2023 3:14 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>   3 files changed, 388 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -0,0 +1,69 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
> Not dual licensed? Not BSD?
>
>> +/*
>> + * IPQ9574 AL02-C7 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>> +	interrupt-parent = <&intc>;
Can this be droppeed? since it is already part of DTSI.
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	pinctrl-0 = <&uart2_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&sdhc_1 {
>> +	pinctrl-0 = <&emmc_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&tlmm {
>> +	emmc_pins: emmc-state {
>> +		emmc-clk-pins {
>> +			pins = "gpio5";
>> +			function = "sdc_clk";
>> +			drive-strength = <8>;
>> +			bias-disable;
>> +		};
>> +		emmc-cmd-pins {
>> +			pins = "gpio4";
>> +			function = "sdc_cmd";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-data-pins {
>> +			pins = "gpio0", "gpio1", "gpio2",
>> +			     "gpio3", "gpio6", "gpio7",
>> +			     "gpio8", "gpio9";
>> +			function = "sdc_data";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-rclk-pins {
>> +			pins = "gpio10";
>> +			function = "sdc_rclk";
>> +			drive-strength = <8>;
>> +			bias-pull-down;
>> +		};
>> +	};
>> +
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> new file mode 100644
>> index 000000000000..188d18688a77
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -0,0 +1,318 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * IPQ9574 SoC device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
> No undercores in node names.
>
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <353000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <125000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32000>;
> That's not a property of the SoC, but board. Either entire clock or at
> least frequency to indicate that the board is providing the clock.
>
>> +			#clock-cells = <0>;> +		};
>> +
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
> Ditto.
>
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x0>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x1>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x2>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x3>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		L2_0: l2-cache {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +		};
>> +	};
>> +
>> +	memory@40000000 {
>> +		device_type = "memory";
>> +		/* We expect the bootloader to fill in the size */
>> +		reg = <0x0 0x40000000 0x0 0x0>;
>> +	};
>> +
>> +	pmu {
>> +		compatible = "arm,cortex-a73-pmu";
>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-1.0";
>> +		method = "smc";
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		tz_region: memory@4a600000 {
>> +			reg = <0x0 0x4a600000 0x0 0x400000>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	soc: soc@0 {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0 0 0 0xffffffff>;
>> +		compatible = "simple-bus";
>> +
>> +		tlmm: pinctrl@1000000 {
>> +			compatible = "qcom,ipq9574-tlmm";
>> +			reg = <0x01000000 0x300000>;
>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&tlmm 0 0 65>;
>> +			gpio-reserved-ranges = <59 1>;
> Hm, why reserved ranges are in SoC?
>
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart2_pins: uart2-state {
>> +				pins = "gpio34", "gpio35";
>> +				function = "blsp2_uart";
>> +				drive-strength = <8>;
>> +				bias-disable;
>> +			};
>> +		};
>> +
>> +		gcc: clock-controller@1800000 {
>> +			compatible = "qcom,gcc-ipq9574";
>> +			reg = <0x1800000 0x80000>;
Address can be padded to 8-hex-digits. Please take care of this in all 
nodes.
>> +			clocks = <&xo_board_clk>,
>> +				<&sleep_clk>,
>> +				<&bias_pll_ubi_nc_clk>,
>> +				<&pcie30_phy0_pipe_clk>,
>> +				<&pcie30_phy1_pipe_clk>,
>> +				<&pcie30_phy2_pipe_clk>,
>> +				<&pcie30_phy3_pipe_clk>,
>> +				<&usb3phy_0_cc_pipe_clk>;
>> +			clock-names = "xo",
>> +				"sleep_clk",
> Misaligned. Multiple other places probably as well.
>
>> +				"bias_pll_ubi_nc_clk",
>> +				"pcie30_phy0_pipe_clk",
>> +				"pcie30_phy1_pipe_clk",
>> +				"pcie30_phy2_pipe_clk",
>> +				"pcie30_phy3_pipe_clk",
>> +				"usb3phy_0_cc_pipe_clk";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		sdhc_1: sdhci@7804000 {
>> +			compatible = "qcom,sdhci-msm-v5";
>> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>> +			reg-names = "hc_mem", "cmdq_mem";
>> +
>> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> Like here.
>
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&xo_board_clk>,
>> +			       <&gcc GCC_SDCC1_AHB_CLK>,
>> +			       <&gcc GCC_SDCC1_APPS_CLK>;
> And here
>
>> +			clock-names = "xo", "iface", "core";
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
>> +			mmc-hs400-1_8v;
>> +			mmc-hs400-enhanced-strobe;
>> +			max-frequency = <384000000>;
>> +			bus-width = <8>;
>> +			non-removable;
>> +			status = "disabled";
>> +		};
>> +
>> +		blsp1_uart2: serial@78b1000 {
>> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +			reg = <0x078b1000 0x200>;
>> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> +				 <&gcc GCC_BLSP1_AHB_CLK>;
>> +			clock-names = "core", "iface";
>> +			status = "disabled";
>> +		};
>> +
>> +		intc: interrupt-controller@b000000 {
>> +			compatible = "qcom,msm-qgic2";
>> +			reg = <0x0b000000 0x1000>,  /* GICD */
>> +			      <0x0b002000 0x1000>,  /* GICC */
>> +			      <0x0b001000 0x1000>,  /* GICH */
>> +			      <0x0b004000 0x1000>;  /* GICV */
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges = <0 0x0b00c000 0x3000>;
>> +
>> +			v2m0: v2m@0 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x0 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m1: v2m@1 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x1000 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m2: v2m@2 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x2000 0xffd>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		timer@b120000 {
>> +			compatible = "arm,armv7-timer-mem";
>> +			reg = <0xb120000 0x1000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			clock-frequency = <24000000>;
>> +
>> +			frame@b120000 {
>> +				reg = <0xb121000 0x1000>,
>> +				      <0xb122000 0x1000>;
>> +				frame-number = <0>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			frame@b123000 {
>> +				reg = <0xb123000 0x1000>;
>> +				frame-number = <1>;
>> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b124000 {
>> +				reg = <0xb124000 0x1000>;
>> +				frame-number = <2>;
>> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b125000 {
>> +				reg = <0xb125000 0x1000>;
>> +				frame-number = <3>;
>> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b126000 {
>> +				reg = <0xb126000 0x1000>;
>> +				frame-number = <4>;
>> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b127000 {
>> +				reg = <0xb127000 0x1000>;
>> +				frame-number = <5>;
>> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b128000 {
>> +				reg = <0xb128000 0x1000>;
>> +				frame-number = <6>;
>> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +		clock-frequency = <24000000>;
> Is this allowed in recent designs?
>
>> +	};
>> +};
> Best regards,
> Krzysztof
>

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Kathiravan Thirumoorthy]

On 1/11/2023 3:14 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>   3 files changed, 388 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -0,0 +1,69 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
> Not dual licensed? Not BSD?
>
>> +/*
>> + * IPQ9574 AL02-C7 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>> +	interrupt-parent = <&intc>;
Can this be droppeed? since it is already part of DTSI.
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	pinctrl-0 = <&uart2_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&sdhc_1 {
>> +	pinctrl-0 = <&emmc_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&tlmm {
>> +	emmc_pins: emmc-state {
>> +		emmc-clk-pins {
>> +			pins = "gpio5";
>> +			function = "sdc_clk";
>> +			drive-strength = <8>;
>> +			bias-disable;
>> +		};
>> +		emmc-cmd-pins {
>> +			pins = "gpio4";
>> +			function = "sdc_cmd";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-data-pins {
>> +			pins = "gpio0", "gpio1", "gpio2",
>> +			     "gpio3", "gpio6", "gpio7",
>> +			     "gpio8", "gpio9";
>> +			function = "sdc_data";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-rclk-pins {
>> +			pins = "gpio10";
>> +			function = "sdc_rclk";
>> +			drive-strength = <8>;
>> +			bias-pull-down;
>> +		};
>> +	};
>> +
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> new file mode 100644
>> index 000000000000..188d18688a77
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -0,0 +1,318 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * IPQ9574 SoC device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
> No undercores in node names.
>
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <353000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <125000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32000>;
> That's not a property of the SoC, but board. Either entire clock or at
> least frequency to indicate that the board is providing the clock.
>
>> +			#clock-cells = <0>;> +		};
>> +
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
> Ditto.
>
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x0>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x1>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x2>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x3>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		L2_0: l2-cache {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +		};
>> +	};
>> +
>> +	memory@40000000 {
>> +		device_type = "memory";
>> +		/* We expect the bootloader to fill in the size */
>> +		reg = <0x0 0x40000000 0x0 0x0>;
>> +	};
>> +
>> +	pmu {
>> +		compatible = "arm,cortex-a73-pmu";
>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-1.0";
>> +		method = "smc";
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		tz_region: memory@4a600000 {
>> +			reg = <0x0 0x4a600000 0x0 0x400000>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	soc: soc@0 {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0 0 0 0xffffffff>;
>> +		compatible = "simple-bus";
>> +
>> +		tlmm: pinctrl@1000000 {
>> +			compatible = "qcom,ipq9574-tlmm";
>> +			reg = <0x01000000 0x300000>;
>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&tlmm 0 0 65>;
>> +			gpio-reserved-ranges = <59 1>;
> Hm, why reserved ranges are in SoC?
>
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart2_pins: uart2-state {
>> +				pins = "gpio34", "gpio35";
>> +				function = "blsp2_uart";
>> +				drive-strength = <8>;
>> +				bias-disable;
>> +			};
>> +		};
>> +
>> +		gcc: clock-controller@1800000 {
>> +			compatible = "qcom,gcc-ipq9574";
>> +			reg = <0x1800000 0x80000>;
Address can be padded to 8-hex-digits. Please take care of this in all 
nodes.
>> +			clocks = <&xo_board_clk>,
>> +				<&sleep_clk>,
>> +				<&bias_pll_ubi_nc_clk>,
>> +				<&pcie30_phy0_pipe_clk>,
>> +				<&pcie30_phy1_pipe_clk>,
>> +				<&pcie30_phy2_pipe_clk>,
>> +				<&pcie30_phy3_pipe_clk>,
>> +				<&usb3phy_0_cc_pipe_clk>;
>> +			clock-names = "xo",
>> +				"sleep_clk",
> Misaligned. Multiple other places probably as well.
>
>> +				"bias_pll_ubi_nc_clk",
>> +				"pcie30_phy0_pipe_clk",
>> +				"pcie30_phy1_pipe_clk",
>> +				"pcie30_phy2_pipe_clk",
>> +				"pcie30_phy3_pipe_clk",
>> +				"usb3phy_0_cc_pipe_clk";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		sdhc_1: sdhci@7804000 {
>> +			compatible = "qcom,sdhci-msm-v5";
>> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>> +			reg-names = "hc_mem", "cmdq_mem";
>> +
>> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> Like here.
>
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&xo_board_clk>,
>> +			       <&gcc GCC_SDCC1_AHB_CLK>,
>> +			       <&gcc GCC_SDCC1_APPS_CLK>;
> And here
>
>> +			clock-names = "xo", "iface", "core";
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
>> +			mmc-hs400-1_8v;
>> +			mmc-hs400-enhanced-strobe;
>> +			max-frequency = <384000000>;
>> +			bus-width = <8>;
>> +			non-removable;
>> +			status = "disabled";
>> +		};
>> +
>> +		blsp1_uart2: serial@78b1000 {
>> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +			reg = <0x078b1000 0x200>;
>> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> +				 <&gcc GCC_BLSP1_AHB_CLK>;
>> +			clock-names = "core", "iface";
>> +			status = "disabled";
>> +		};
>> +
>> +		intc: interrupt-controller@b000000 {
>> +			compatible = "qcom,msm-qgic2";
>> +			reg = <0x0b000000 0x1000>,  /* GICD */
>> +			      <0x0b002000 0x1000>,  /* GICC */
>> +			      <0x0b001000 0x1000>,  /* GICH */
>> +			      <0x0b004000 0x1000>;  /* GICV */
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges = <0 0x0b00c000 0x3000>;
>> +
>> +			v2m0: v2m@0 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x0 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m1: v2m@1 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x1000 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m2: v2m@2 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x2000 0xffd>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		timer@b120000 {
>> +			compatible = "arm,armv7-timer-mem";
>> +			reg = <0xb120000 0x1000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			clock-frequency = <24000000>;
>> +
>> +			frame@b120000 {
>> +				reg = <0xb121000 0x1000>,
>> +				      <0xb122000 0x1000>;
>> +				frame-number = <0>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			frame@b123000 {
>> +				reg = <0xb123000 0x1000>;
>> +				frame-number = <1>;
>> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b124000 {
>> +				reg = <0xb124000 0x1000>;
>> +				frame-number = <2>;
>> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b125000 {
>> +				reg = <0xb125000 0x1000>;
>> +				frame-number = <3>;
>> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b126000 {
>> +				reg = <0xb126000 0x1000>;
>> +				frame-number = <4>;
>> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b127000 {
>> +				reg = <0xb127000 0x1000>;
>> +				frame-number = <5>;
>> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b128000 {
>> +				reg = <0xb128000 0x1000>;
>> +				frame-number = <6>;
>> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +		clock-frequency = <24000000>;
> Is this allowed in recent designs?
>
>> +	};
>> +};
> Best regards,
> Krzysztof
>

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 8:22 PM, Kathiravan Thirumoorthy wrote:
> 
> On 1/11/2023 3:14 PM, Krzysztof Kozlowski wrote:
>> On 10/01/2023 13:13, devi priya wrote:
>>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>>
>>> Add initial device tree support for Qualcomm IPQ9574 SoC
>>> and AL02 board
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>>   3 files changed, 388 insertions(+)
>>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile 
>>> b/arch/arm64/boot/dts/qcom/Makefile
>>> index 3e79496292e7..872c62028a0b 100644
>>> --- a/arch/arm64/boot/dts/qcom/Makefile
>>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)    += ipq6018-cp01-c1.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk01.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c1.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c2.dtb
>>> +dtb-$(CONFIG_ARCH_QCOM)    += ipq9574-al02-c7.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += msm8916-alcatel-idol347.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += msm8916-asus-z00l.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += msm8916-huawei-g7.dtb
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts 
>>> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>> new file mode 100644
>>> index 000000000000..ae3c32f3e16a
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>> @@ -0,0 +1,69 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>> Not dual licensed? Not BSD?
>>
>>> +/*
>>> + * IPQ9574 AL02-C7 board device tree source
>>> + *
>>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights 
>>> reserved.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "ipq9574.dtsi"
>>> +
>>> +/ {
>>> +    model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>>> +    compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>>> +    interrupt-parent = <&intc>;
> Can this be droppeed? since it is already part of DTSI.
Sure okay
>>> +
>>> +    aliases {
>>> +        serial0 = &blsp1_uart2;
>>> +    };
>>> +
>>> +    chosen {
>>> +        stdout-path = "serial0:115200n8";
>>> +    };
>>> +};
>>> +
>>> +&blsp1_uart2 {
>>> +    pinctrl-0 = <&uart2_pins>;
>>> +    pinctrl-names = "default";
>>> +    status = "okay";
>>> +};
>>> +
>>> +&sdhc_1 {
>>> +    pinctrl-0 = <&emmc_pins>;
>>> +    pinctrl-names = "default";
>>> +    status = "okay";
>>> +};
>>> +
>>> +&tlmm {
>>> +    emmc_pins: emmc-state {
>>> +        emmc-clk-pins {
>>> +            pins = "gpio5";
>>> +            function = "sdc_clk";
>>> +            drive-strength = <8>;
>>> +            bias-disable;
>>> +        };
>>> +        emmc-cmd-pins {
>>> +            pins = "gpio4";
>>> +            function = "sdc_cmd";
>>> +            drive-strength = <8>;
>>> +            bias-pull-up;
>>> +        };
>>> +        emmc-data-pins {
>>> +            pins = "gpio0", "gpio1", "gpio2",
>>> +                 "gpio3", "gpio6", "gpio7",
>>> +                 "gpio8", "gpio9";
>>> +            function = "sdc_data";
>>> +            drive-strength = <8>;
>>> +            bias-pull-up;
>>> +        };
>>> +        emmc-rclk-pins {
>>> +            pins = "gpio10";
>>> +            function = "sdc_rclk";
>>> +            drive-strength = <8>;
>>> +            bias-pull-down;
>>> +        };
>>> +    };
>>> +
>>> +};
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi 
>>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> new file mode 100644
>>> index 000000000000..188d18688a77
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> @@ -0,0 +1,318 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * IPQ9574 SoC device tree source
>>> + *
>>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights 
>>> reserved.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>>> +
>>> +/ {
>>> +    interrupt-parent = <&intc>;
>>> +    #address-cells = <2>;
>>> +    #size-cells = <2>;
>>> +
>>> +    clocks {
>>> +        bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
>> No undercores in node names.
>>
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <353000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <125000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        sleep_clk: sleep-clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <32000>;
>> That's not a property of the SoC, but board. Either entire clock or at
>> least frequency to indicate that the board is providing the clock.
>>
>>> +            #clock-cells = <0>;> +        };
>>> +
>>> +        xo_board_clk: xo-board-clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <24000000>;
>> Ditto.
>>
>>> +            #clock-cells = <0>;
>>> +        };
>>> +    };
>>> +
>>> +    cpus {
>>> +        #address-cells = <1>;
>>> +        #size-cells = <0>;
>>> +
>>> +        CPU0: cpu@0 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x0>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        CPU1: cpu@1 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x1>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        CPU2: cpu@2 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x2>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        CPU3: cpu@3 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x3>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        L2_0: l2-cache {
>>> +            compatible = "cache";
>>> +            cache-level = <2>;
>>> +        };
>>> +    };
>>> +
>>> +    memory@40000000 {
>>> +        device_type = "memory";
>>> +        /* We expect the bootloader to fill in the size */
>>> +        reg = <0x0 0x40000000 0x0 0x0>;
>>> +    };
>>> +
>>> +    pmu {
>>> +        compatible = "arm,cortex-a73-pmu";
>>> +        interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_HIGH)>;
>>> +    };
>>> +
>>> +    psci {
>>> +        compatible = "arm,psci-1.0";
>>> +        method = "smc";
>>> +    };
>>> +
>>> +    reserved-memory {
>>> +        #address-cells = <2>;
>>> +        #size-cells = <2>;
>>> +        ranges;
>>> +
>>> +        tz_region: memory@4a600000 {
>>> +            reg = <0x0 0x4a600000 0x0 0x400000>;
>>> +            no-map;
>>> +        };
>>> +    };
>>> +
>>> +    soc: soc@0 {
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        ranges = <0 0 0 0xffffffff>;
>>> +        compatible = "simple-bus";
>>> +
>>> +        tlmm: pinctrl@1000000 {
>>> +            compatible = "qcom,ipq9574-tlmm";
>>> +            reg = <0x01000000 0x300000>;
>>> +            interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>> +            gpio-controller;
>>> +            #gpio-cells = <2>;
>>> +            gpio-ranges = <&tlmm 0 0 65>;
>>> +            gpio-reserved-ranges = <59 1>;
>> Hm, why reserved ranges are in SoC?
>>
>>> +            interrupt-controller;
>>> +            #interrupt-cells = <2>;
>>> +
>>> +            uart2_pins: uart2-state {
>>> +                pins = "gpio34", "gpio35";
>>> +                function = "blsp2_uart";
>>> +                drive-strength = <8>;
>>> +                bias-disable;
>>> +            };
>>> +        };
>>> +
>>> +        gcc: clock-controller@1800000 {
>>> +            compatible = "qcom,gcc-ipq9574";
>>> +            reg = <0x1800000 0x80000>;
> Address can be padded to 8-hex-digits. Please take care of this in all 
> nodes.
Sure, will do
>>> +            clocks = <&xo_board_clk>,
>>> +                <&sleep_clk>,
>>> +                <&bias_pll_ubi_nc_clk>,
>>> +                <&pcie30_phy0_pipe_clk>,
>>> +                <&pcie30_phy1_pipe_clk>,
>>> +                <&pcie30_phy2_pipe_clk>,
>>> +                <&pcie30_phy3_pipe_clk>,
>>> +                <&usb3phy_0_cc_pipe_clk>;
>>> +            clock-names = "xo",
>>> +                "sleep_clk",
>> Misaligned. Multiple other places probably as well.
>>
>>> +                "bias_pll_ubi_nc_clk",
>>> +                "pcie30_phy0_pipe_clk",
>>> +                "pcie30_phy1_pipe_clk",
>>> +                "pcie30_phy2_pipe_clk",
>>> +                "pcie30_phy3_pipe_clk",
>>> +                "usb3phy_0_cc_pipe_clk";
>>> +            #clock-cells = <1>;
>>> +            #reset-cells = <1>;
>>> +        };
>>> +
>>> +        sdhc_1: sdhci@7804000 {
>>> +            compatible = "qcom,sdhci-msm-v5";
>>> +            reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>>> +            reg-names = "hc_mem", "cmdq_mem";
>>> +
>>> +            interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>>> +                   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> Like here.
>>
>>> +            interrupt-names = "hc_irq", "pwr_irq";
>>> +
>>> +            clocks = <&xo_board_clk>,
>>> +                   <&gcc GCC_SDCC1_AHB_CLK>,
>>> +                   <&gcc GCC_SDCC1_APPS_CLK>;
>> And here
>>
>>> +            clock-names = "xo", "iface", "core";
>> Does not look like you tested the bindings. Please run `make
>> dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>
>>> +            mmc-ddr-1_8v;
>>> +            mmc-hs200-1_8v;
>>> +            mmc-hs400-1_8v;
>>> +            mmc-hs400-enhanced-strobe;
>>> +            max-frequency = <384000000>;
>>> +            bus-width = <8>;
>>> +            non-removable;
>>> +            status = "disabled";
>>> +        };
>>> +
>>> +        blsp1_uart2: serial@78b1000 {
>>> +            compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>>> +            reg = <0x078b1000 0x200>;
>>> +            interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>>> +            clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>>> +                 <&gcc GCC_BLSP1_AHB_CLK>;
>>> +            clock-names = "core", "iface";
>>> +            status = "disabled";
>>> +        };
>>> +
>>> +        intc: interrupt-controller@b000000 {
>>> +            compatible = "qcom,msm-qgic2";
>>> +            reg = <0x0b000000 0x1000>,  /* GICD */
>>> +                  <0x0b002000 0x1000>,  /* GICC */
>>> +                  <0x0b001000 0x1000>,  /* GICH */
>>> +                  <0x0b004000 0x1000>;  /* GICV */
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            interrupt-controller;
>>> +            #interrupt-cells = <3>;
>>> +            interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>> +            ranges = <0 0x0b00c000 0x3000>;
>>> +
>>> +            v2m0: v2m@0 {
>>> +                compatible = "arm,gic-v2m-frame";
>>> +                reg = <0x0 0xffd>;
>>> +                msi-controller;
>>> +            };
>>> +
>>> +            v2m1: v2m@1 {
>>> +                compatible = "arm,gic-v2m-frame";
>>> +                reg = <0x1000 0xffd>;
>>> +                msi-controller;
>>> +            };
>>> +
>>> +            v2m2: v2m@2 {
>>> +                compatible = "arm,gic-v2m-frame";
>>> +                reg = <0x2000 0xffd>;
>>> +                msi-controller;
>>> +            };
>>> +        };
>>> +
>>> +        timer@b120000 {
>>> +            compatible = "arm,armv7-timer-mem";
>>> +            reg = <0xb120000 0x1000>;
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            ranges;
>>> +            clock-frequency = <24000000>;
>>> +
>>> +            frame@b120000 {
>>> +                reg = <0xb121000 0x1000>,
>>> +                      <0xb122000 0x1000>;
>>> +                frame-number = <0>;
>>> +                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>>> +                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>>> +            };
>>> +
>>> +            frame@b123000 {
>>> +                reg = <0xb123000 0x1000>;
>>> +                frame-number = <1>;
>>> +                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b124000 {
>>> +                reg = <0xb124000 0x1000>;
>>> +                frame-number = <2>;
>>> +                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b125000 {
>>> +                reg = <0xb125000 0x1000>;
>>> +                frame-number = <3>;
>>> +                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b126000 {
>>> +                reg = <0xb126000 0x1000>;
>>> +                frame-number = <4>;
>>> +                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b127000 {
>>> +                reg = <0xb127000 0x1000>;
>>> +                frame-number = <5>;
>>> +                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b128000 {
>>> +                reg = <0xb128000 0x1000>;
>>> +                frame-number = <6>;
>>> +                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +        };
>>> +    };
>>> +
>>> +    timer {
>>> +        compatible = "arm,armv8-timer";
>>> +        interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>;
>>> +        clock-frequency = <24000000>;
>> Is this allowed in recent designs?
>>
>>> +    };
>>> +};
>> Best regards,
>> Krzysztof
>>
Best Regards,
Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 8:22 PM, Kathiravan Thirumoorthy wrote:
> 
> On 1/11/2023 3:14 PM, Krzysztof Kozlowski wrote:
>> On 10/01/2023 13:13, devi priya wrote:
>>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>>
>>> Add initial device tree support for Qualcomm IPQ9574 SoC
>>> and AL02 board
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>>   3 files changed, 388 insertions(+)
>>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/Makefile 
>>> b/arch/arm64/boot/dts/qcom/Makefile
>>> index 3e79496292e7..872c62028a0b 100644
>>> --- a/arch/arm64/boot/dts/qcom/Makefile
>>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)    += ipq6018-cp01-c1.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk01.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c1.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c2.dtb
>>> +dtb-$(CONFIG_ARCH_QCOM)    += ipq9574-al02-c7.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += msm8916-alcatel-idol347.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += msm8916-asus-z00l.dtb
>>>   dtb-$(CONFIG_ARCH_QCOM)    += msm8916-huawei-g7.dtb
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts 
>>> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>> new file mode 100644
>>> index 000000000000..ae3c32f3e16a
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>> @@ -0,0 +1,69 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>> Not dual licensed? Not BSD?
>>
>>> +/*
>>> + * IPQ9574 AL02-C7 board device tree source
>>> + *
>>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights 
>>> reserved.
>>> + */
>>> +
>>> +/dts-v1/;
>>> +
>>> +#include "ipq9574.dtsi"
>>> +
>>> +/ {
>>> +    model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>>> +    compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>>> +    interrupt-parent = <&intc>;
> Can this be droppeed? since it is already part of DTSI.
Sure okay
>>> +
>>> +    aliases {
>>> +        serial0 = &blsp1_uart2;
>>> +    };
>>> +
>>> +    chosen {
>>> +        stdout-path = "serial0:115200n8";
>>> +    };
>>> +};
>>> +
>>> +&blsp1_uart2 {
>>> +    pinctrl-0 = <&uart2_pins>;
>>> +    pinctrl-names = "default";
>>> +    status = "okay";
>>> +};
>>> +
>>> +&sdhc_1 {
>>> +    pinctrl-0 = <&emmc_pins>;
>>> +    pinctrl-names = "default";
>>> +    status = "okay";
>>> +};
>>> +
>>> +&tlmm {
>>> +    emmc_pins: emmc-state {
>>> +        emmc-clk-pins {
>>> +            pins = "gpio5";
>>> +            function = "sdc_clk";
>>> +            drive-strength = <8>;
>>> +            bias-disable;
>>> +        };
>>> +        emmc-cmd-pins {
>>> +            pins = "gpio4";
>>> +            function = "sdc_cmd";
>>> +            drive-strength = <8>;
>>> +            bias-pull-up;
>>> +        };
>>> +        emmc-data-pins {
>>> +            pins = "gpio0", "gpio1", "gpio2",
>>> +                 "gpio3", "gpio6", "gpio7",
>>> +                 "gpio8", "gpio9";
>>> +            function = "sdc_data";
>>> +            drive-strength = <8>;
>>> +            bias-pull-up;
>>> +        };
>>> +        emmc-rclk-pins {
>>> +            pins = "gpio10";
>>> +            function = "sdc_rclk";
>>> +            drive-strength = <8>;
>>> +            bias-pull-down;
>>> +        };
>>> +    };
>>> +
>>> +};
>>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi 
>>> b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> new file mode 100644
>>> index 000000000000..188d18688a77
>>> --- /dev/null
>>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>> @@ -0,0 +1,318 @@
>>> +// SPDX-License-Identifier: GPL-2.0-only
>>> +/*
>>> + * IPQ9574 SoC device tree source
>>> + *
>>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights 
>>> reserved.
>>> + */
>>> +
>>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>>> +
>>> +/ {
>>> +    interrupt-parent = <&intc>;
>>> +    #address-cells = <2>;
>>> +    #size-cells = <2>;
>>> +
>>> +    clocks {
>>> +        bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
>> No undercores in node names.
>>
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <353000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <250000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <125000000>;
>>> +            #clock-cells = <0>;
>>> +        };
>>> +
>>> +        sleep_clk: sleep-clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <32000>;
>> That's not a property of the SoC, but board. Either entire clock or at
>> least frequency to indicate that the board is providing the clock.
>>
>>> +            #clock-cells = <0>;> +        };
>>> +
>>> +        xo_board_clk: xo-board-clk {
>>> +            compatible = "fixed-clock";
>>> +            clock-frequency = <24000000>;
>> Ditto.
>>
>>> +            #clock-cells = <0>;
>>> +        };
>>> +    };
>>> +
>>> +    cpus {
>>> +        #address-cells = <1>;
>>> +        #size-cells = <0>;
>>> +
>>> +        CPU0: cpu@0 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x0>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        CPU1: cpu@1 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x1>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        CPU2: cpu@2 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x2>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        CPU3: cpu@3 {
>>> +            device_type = "cpu";
>>> +            compatible = "arm,cortex-a73";
>>> +            reg = <0x3>;
>>> +            enable-method = "psci";
>>> +            next-level-cache = <&L2_0>;
>>> +        };
>>> +
>>> +        L2_0: l2-cache {
>>> +            compatible = "cache";
>>> +            cache-level = <2>;
>>> +        };
>>> +    };
>>> +
>>> +    memory@40000000 {
>>> +        device_type = "memory";
>>> +        /* We expect the bootloader to fill in the size */
>>> +        reg = <0x0 0x40000000 0x0 0x0>;
>>> +    };
>>> +
>>> +    pmu {
>>> +        compatible = "arm,cortex-a73-pmu";
>>> +        interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_HIGH)>;
>>> +    };
>>> +
>>> +    psci {
>>> +        compatible = "arm,psci-1.0";
>>> +        method = "smc";
>>> +    };
>>> +
>>> +    reserved-memory {
>>> +        #address-cells = <2>;
>>> +        #size-cells = <2>;
>>> +        ranges;
>>> +
>>> +        tz_region: memory@4a600000 {
>>> +            reg = <0x0 0x4a600000 0x0 0x400000>;
>>> +            no-map;
>>> +        };
>>> +    };
>>> +
>>> +    soc: soc@0 {
>>> +        #address-cells = <1>;
>>> +        #size-cells = <1>;
>>> +        ranges = <0 0 0 0xffffffff>;
>>> +        compatible = "simple-bus";
>>> +
>>> +        tlmm: pinctrl@1000000 {
>>> +            compatible = "qcom,ipq9574-tlmm";
>>> +            reg = <0x01000000 0x300000>;
>>> +            interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>> +            gpio-controller;
>>> +            #gpio-cells = <2>;
>>> +            gpio-ranges = <&tlmm 0 0 65>;
>>> +            gpio-reserved-ranges = <59 1>;
>> Hm, why reserved ranges are in SoC?
>>
>>> +            interrupt-controller;
>>> +            #interrupt-cells = <2>;
>>> +
>>> +            uart2_pins: uart2-state {
>>> +                pins = "gpio34", "gpio35";
>>> +                function = "blsp2_uart";
>>> +                drive-strength = <8>;
>>> +                bias-disable;
>>> +            };
>>> +        };
>>> +
>>> +        gcc: clock-controller@1800000 {
>>> +            compatible = "qcom,gcc-ipq9574";
>>> +            reg = <0x1800000 0x80000>;
> Address can be padded to 8-hex-digits. Please take care of this in all 
> nodes.
Sure, will do
>>> +            clocks = <&xo_board_clk>,
>>> +                <&sleep_clk>,
>>> +                <&bias_pll_ubi_nc_clk>,
>>> +                <&pcie30_phy0_pipe_clk>,
>>> +                <&pcie30_phy1_pipe_clk>,
>>> +                <&pcie30_phy2_pipe_clk>,
>>> +                <&pcie30_phy3_pipe_clk>,
>>> +                <&usb3phy_0_cc_pipe_clk>;
>>> +            clock-names = "xo",
>>> +                "sleep_clk",
>> Misaligned. Multiple other places probably as well.
>>
>>> +                "bias_pll_ubi_nc_clk",
>>> +                "pcie30_phy0_pipe_clk",
>>> +                "pcie30_phy1_pipe_clk",
>>> +                "pcie30_phy2_pipe_clk",
>>> +                "pcie30_phy3_pipe_clk",
>>> +                "usb3phy_0_cc_pipe_clk";
>>> +            #clock-cells = <1>;
>>> +            #reset-cells = <1>;
>>> +        };
>>> +
>>> +        sdhc_1: sdhci@7804000 {
>>> +            compatible = "qcom,sdhci-msm-v5";
>>> +            reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>>> +            reg-names = "hc_mem", "cmdq_mem";
>>> +
>>> +            interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>>> +                   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
>> Like here.
>>
>>> +            interrupt-names = "hc_irq", "pwr_irq";
>>> +
>>> +            clocks = <&xo_board_clk>,
>>> +                   <&gcc GCC_SDCC1_AHB_CLK>,
>>> +                   <&gcc GCC_SDCC1_APPS_CLK>;
>> And here
>>
>>> +            clock-names = "xo", "iface", "core";
>> Does not look like you tested the bindings. Please run `make
>> dt_binding_check` (see
>> Documentation/devicetree/bindings/writing-schema.rst for instructions).
>>
>>> +            mmc-ddr-1_8v;
>>> +            mmc-hs200-1_8v;
>>> +            mmc-hs400-1_8v;
>>> +            mmc-hs400-enhanced-strobe;
>>> +            max-frequency = <384000000>;
>>> +            bus-width = <8>;
>>> +            non-removable;
>>> +            status = "disabled";
>>> +        };
>>> +
>>> +        blsp1_uart2: serial@78b1000 {
>>> +            compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>>> +            reg = <0x078b1000 0x200>;
>>> +            interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>>> +            clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>>> +                 <&gcc GCC_BLSP1_AHB_CLK>;
>>> +            clock-names = "core", "iface";
>>> +            status = "disabled";
>>> +        };
>>> +
>>> +        intc: interrupt-controller@b000000 {
>>> +            compatible = "qcom,msm-qgic2";
>>> +            reg = <0x0b000000 0x1000>,  /* GICD */
>>> +                  <0x0b002000 0x1000>,  /* GICC */
>>> +                  <0x0b001000 0x1000>,  /* GICH */
>>> +                  <0x0b004000 0x1000>;  /* GICV */
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            interrupt-controller;
>>> +            #interrupt-cells = <3>;
>>> +            interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>> +            ranges = <0 0x0b00c000 0x3000>;
>>> +
>>> +            v2m0: v2m@0 {
>>> +                compatible = "arm,gic-v2m-frame";
>>> +                reg = <0x0 0xffd>;
>>> +                msi-controller;
>>> +            };
>>> +
>>> +            v2m1: v2m@1 {
>>> +                compatible = "arm,gic-v2m-frame";
>>> +                reg = <0x1000 0xffd>;
>>> +                msi-controller;
>>> +            };
>>> +
>>> +            v2m2: v2m@2 {
>>> +                compatible = "arm,gic-v2m-frame";
>>> +                reg = <0x2000 0xffd>;
>>> +                msi-controller;
>>> +            };
>>> +        };
>>> +
>>> +        timer@b120000 {
>>> +            compatible = "arm,armv7-timer-mem";
>>> +            reg = <0xb120000 0x1000>;
>>> +            #address-cells = <1>;
>>> +            #size-cells = <1>;
>>> +            ranges;
>>> +            clock-frequency = <24000000>;
>>> +
>>> +            frame@b120000 {
>>> +                reg = <0xb121000 0x1000>,
>>> +                      <0xb122000 0x1000>;
>>> +                frame-number = <0>;
>>> +                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>>> +                         <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>>> +            };
>>> +
>>> +            frame@b123000 {
>>> +                reg = <0xb123000 0x1000>;
>>> +                frame-number = <1>;
>>> +                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b124000 {
>>> +                reg = <0xb124000 0x1000>;
>>> +                frame-number = <2>;
>>> +                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b125000 {
>>> +                reg = <0xb125000 0x1000>;
>>> +                frame-number = <3>;
>>> +                interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b126000 {
>>> +                reg = <0xb126000 0x1000>;
>>> +                frame-number = <4>;
>>> +                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b127000 {
>>> +                reg = <0xb127000 0x1000>;
>>> +                frame-number = <5>;
>>> +                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +
>>> +            frame@b128000 {
>>> +                reg = <0xb128000 0x1000>;
>>> +                frame-number = <6>;
>>> +                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>>> +                status = "disabled";
>>> +            };
>>> +        };
>>> +    };
>>> +
>>> +    timer {
>>> +        compatible = "arm,armv8-timer";
>>> +        interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>,
>>> +                 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | 
>>> IRQ_TYPE_LEVEL_LOW)>;
>>> +        clock-frequency = <24000000>;
>> Is this allowed in recent designs?
>>
>>> +    };
>>> +};
>> Best regards,
>> Krzysztof
>>
Best Regards,
Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 3:14 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>   3 files changed, 388 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -0,0 +1,69 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
> 
> Not dual licensed? Not BSD?
Okay, will add dual license
> 
>> +/*
>> + * IPQ9574 AL02-C7 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>> +	interrupt-parent = <&intc>;
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	pinctrl-0 = <&uart2_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&sdhc_1 {
>> +	pinctrl-0 = <&emmc_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&tlmm {
>> +	emmc_pins: emmc-state {
>> +		emmc-clk-pins {
>> +			pins = "gpio5";
>> +			function = "sdc_clk";
>> +			drive-strength = <8>;
>> +			bias-disable;
>> +		};
>> +		emmc-cmd-pins {
>> +			pins = "gpio4";
>> +			function = "sdc_cmd";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-data-pins {
>> +			pins = "gpio0", "gpio1", "gpio2",
>> +			     "gpio3", "gpio6", "gpio7",
>> +			     "gpio8", "gpio9";
>> +			function = "sdc_data";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-rclk-pins {
>> +			pins = "gpio10";
>> +			function = "sdc_rclk";
>> +			drive-strength = <8>;
>> +			bias-pull-down;
>> +		};
>> +	};
>> +
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> new file mode 100644
>> index 000000000000..188d18688a77
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -0,0 +1,318 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * IPQ9574 SoC device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
> 
> No undercores in node names.
Okay
> 
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <353000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <125000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32000>;
> 
> That's not a property of the SoC, but board. Either entire clock or at
> least frequency to indicate that the board is providing the clock.
Sure, will move it to board dts
> 
>> +			#clock-cells = <0>;> +		};
>> +
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
> 
> Ditto.
Okay
> 
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x0>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x1>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x2>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x3>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		L2_0: l2-cache {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +		};
>> +	};
>> +
>> +	memory@40000000 {
>> +		device_type = "memory";
>> +		/* We expect the bootloader to fill in the size */
>> +		reg = <0x0 0x40000000 0x0 0x0>;
>> +	};
>> +
>> +	pmu {
>> +		compatible = "arm,cortex-a73-pmu";
>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-1.0";
>> +		method = "smc";
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		tz_region: memory@4a600000 {
>> +			reg = <0x0 0x4a600000 0x0 0x400000>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	soc: soc@0 {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0 0 0 0xffffffff>;
>> +		compatible = "simple-bus";
>> +
>> +		tlmm: pinctrl@1000000 {
>> +			compatible = "qcom,ipq9574-tlmm";
>> +			reg = <0x01000000 0x300000>;
>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&tlmm 0 0 65>;
>> +			gpio-reserved-ranges = <59 1>;
> 
> Hm, why reserved ranges are in SoC?
As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
> 
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart2_pins: uart2-state {
>> +				pins = "gpio34", "gpio35";
>> +				function = "blsp2_uart";
>> +				drive-strength = <8>;
>> +				bias-disable;
>> +			};
>> +		};
>> +
>> +		gcc: clock-controller@1800000 {
>> +			compatible = "qcom,gcc-ipq9574";
>> +			reg = <0x1800000 0x80000>;
>> +			clocks = <&xo_board_clk>,
>> +				<&sleep_clk>,
>> +				<&bias_pll_ubi_nc_clk>,
>> +				<&pcie30_phy0_pipe_clk>,
>> +				<&pcie30_phy1_pipe_clk>,
>> +				<&pcie30_phy2_pipe_clk>,
>> +				<&pcie30_phy3_pipe_clk>,
>> +				<&usb3phy_0_cc_pipe_clk>;
>> +			clock-names = "xo",
>> +				"sleep_clk",
> 
> Misaligned. Multiple other places probably as well.
Sure, will do
> 
>> +				"bias_pll_ubi_nc_clk",
>> +				"pcie30_phy0_pipe_clk",
>> +				"pcie30_phy1_pipe_clk",
>> +				"pcie30_phy2_pipe_clk",
>> +				"pcie30_phy3_pipe_clk",
>> +				"usb3phy_0_cc_pipe_clk";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		sdhc_1: sdhci@7804000 {
>> +			compatible = "qcom,sdhci-msm-v5";
>> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>> +			reg-names = "hc_mem", "cmdq_mem";
>> +
>> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> 
> Like here.
Okay
> 
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&xo_board_clk>,
>> +			       <&gcc GCC_SDCC1_AHB_CLK>,
>> +			       <&gcc GCC_SDCC1_APPS_CLK>;
> 
> And here
Okay
> 
>> +			clock-names = "xo", "iface", "core";
> 
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
Sure, will do
> 
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
>> +			mmc-hs400-1_8v;
>> +			mmc-hs400-enhanced-strobe;
>> +			max-frequency = <384000000>;
>> +			bus-width = <8>;
>> +			non-removable;
>> +			status = "disabled";
>> +		};
>> +
>> +		blsp1_uart2: serial@78b1000 {
>> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +			reg = <0x078b1000 0x200>;
>> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> +				 <&gcc GCC_BLSP1_AHB_CLK>;
>> +			clock-names = "core", "iface";
>> +			status = "disabled";
>> +		};
>> +
>> +		intc: interrupt-controller@b000000 {
>> +			compatible = "qcom,msm-qgic2";
>> +			reg = <0x0b000000 0x1000>,  /* GICD */
>> +			      <0x0b002000 0x1000>,  /* GICC */
>> +			      <0x0b001000 0x1000>,  /* GICH */
>> +			      <0x0b004000 0x1000>;  /* GICV */
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges = <0 0x0b00c000 0x3000>;
>> +
>> +			v2m0: v2m@0 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x0 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m1: v2m@1 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x1000 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m2: v2m@2 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x2000 0xffd>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		timer@b120000 {
>> +			compatible = "arm,armv7-timer-mem";
>> +			reg = <0xb120000 0x1000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			clock-frequency = <24000000>;
>> +
>> +			frame@b120000 {
>> +				reg = <0xb121000 0x1000>,
>> +				      <0xb122000 0x1000>;
>> +				frame-number = <0>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			frame@b123000 {
>> +				reg = <0xb123000 0x1000>;
>> +				frame-number = <1>;
>> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b124000 {
>> +				reg = <0xb124000 0x1000>;
>> +				frame-number = <2>;
>> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b125000 {
>> +				reg = <0xb125000 0x1000>;
>> +				frame-number = <3>;
>> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b126000 {
>> +				reg = <0xb126000 0x1000>;
>> +				frame-number = <4>;
>> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b127000 {
>> +				reg = <0xb127000 0x1000>;
>> +				frame-number = <5>;
>> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b128000 {
>> +				reg = <0xb128000 0x1000>;
>> +				frame-number = <6>;
>> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +		clock-frequency = <24000000>;
> 
> Is this allowed in recent designs?
Okay, will drop
> 
>> +	};
>> +};
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 3:14 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>   arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>   3 files changed, 388 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>   create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>>   dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> @@ -0,0 +1,69 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
> 
> Not dual licensed? Not BSD?
Okay, will add dual license
> 
>> +/*
>> + * IPQ9574 AL02-C7 board device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "ipq9574.dtsi"
>> +
>> +/ {
>> +	model = "Qualcomm Technologies, Inc. IPQ9574/AP-AL02-C7";
>> +	compatible = "qcom,ipq9574-ap-al02-c7", "qcom,ipq9574";
>> +	interrupt-parent = <&intc>;
>> +
>> +	aliases {
>> +		serial0 = &blsp1_uart2;
>> +	};
>> +
>> +	chosen {
>> +		stdout-path = "serial0:115200n8";
>> +	};
>> +};
>> +
>> +&blsp1_uart2 {
>> +	pinctrl-0 = <&uart2_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&sdhc_1 {
>> +	pinctrl-0 = <&emmc_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +};
>> +
>> +&tlmm {
>> +	emmc_pins: emmc-state {
>> +		emmc-clk-pins {
>> +			pins = "gpio5";
>> +			function = "sdc_clk";
>> +			drive-strength = <8>;
>> +			bias-disable;
>> +		};
>> +		emmc-cmd-pins {
>> +			pins = "gpio4";
>> +			function = "sdc_cmd";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-data-pins {
>> +			pins = "gpio0", "gpio1", "gpio2",
>> +			     "gpio3", "gpio6", "gpio7",
>> +			     "gpio8", "gpio9";
>> +			function = "sdc_data";
>> +			drive-strength = <8>;
>> +			bias-pull-up;
>> +		};
>> +		emmc-rclk-pins {
>> +			pins = "gpio10";
>> +			function = "sdc_rclk";
>> +			drive-strength = <8>;
>> +			bias-pull-down;
>> +		};
>> +	};
>> +
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> new file mode 100644
>> index 000000000000..188d18688a77
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -0,0 +1,318 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * IPQ9574 SoC device tree source
>> + *
>> + * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/clock/qcom,gcc-ipq9574.h>
>> +#include <dt-bindings/reset/qcom,gcc-ipq9574.h>
>> +
>> +/ {
>> +	interrupt-parent = <&intc>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	clocks {
>> +		bias_pll_ubi_nc_clk: bias_pll_ubi_nc_clk {
> 
> No undercores in node names.
Okay
> 
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <353000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy0_pipe_clk: pcie30_phy0_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy1_pipe_clk: pcie30_phy1_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy2_pipe_clk: pcie30_phy2_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		pcie30_phy3_pipe_clk: pcie30_phy3_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <250000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		usb3phy_0_cc_pipe_clk: usb3phy_0_cc_pipe_clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <125000000>;
>> +			#clock-cells = <0>;
>> +		};
>> +
>> +		sleep_clk: sleep-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <32000>;
> 
> That's not a property of the SoC, but board. Either entire clock or at
> least frequency to indicate that the board is providing the clock.
Sure, will move it to board dts
> 
>> +			#clock-cells = <0>;> +		};
>> +
>> +		xo_board_clk: xo-board-clk {
>> +			compatible = "fixed-clock";
>> +			clock-frequency = <24000000>;
> 
> Ditto.
Okay
> 
>> +			#clock-cells = <0>;
>> +		};
>> +	};
>> +
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		CPU0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x0>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x1>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x2>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		CPU3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a73";
>> +			reg = <0x3>;
>> +			enable-method = "psci";
>> +			next-level-cache = <&L2_0>;
>> +		};
>> +
>> +		L2_0: l2-cache {
>> +			compatible = "cache";
>> +			cache-level = <2>;
>> +		};
>> +	};
>> +
>> +	memory@40000000 {
>> +		device_type = "memory";
>> +		/* We expect the bootloader to fill in the size */
>> +		reg = <0x0 0x40000000 0x0 0x0>;
>> +	};
>> +
>> +	pmu {
>> +		compatible = "arm,cortex-a73-pmu";
>> +		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-1.0";
>> +		method = "smc";
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		tz_region: memory@4a600000 {
>> +			reg = <0x0 0x4a600000 0x0 0x400000>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	soc: soc@0 {
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges = <0 0 0 0xffffffff>;
>> +		compatible = "simple-bus";
>> +
>> +		tlmm: pinctrl@1000000 {
>> +			compatible = "qcom,ipq9574-tlmm";
>> +			reg = <0x01000000 0x300000>;
>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>> +			gpio-controller;
>> +			#gpio-cells = <2>;
>> +			gpio-ranges = <&tlmm 0 0 65>;
>> +			gpio-reserved-ranges = <59 1>;
> 
> Hm, why reserved ranges are in SoC?
As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
> 
>> +			interrupt-controller;
>> +			#interrupt-cells = <2>;
>> +
>> +			uart2_pins: uart2-state {
>> +				pins = "gpio34", "gpio35";
>> +				function = "blsp2_uart";
>> +				drive-strength = <8>;
>> +				bias-disable;
>> +			};
>> +		};
>> +
>> +		gcc: clock-controller@1800000 {
>> +			compatible = "qcom,gcc-ipq9574";
>> +			reg = <0x1800000 0x80000>;
>> +			clocks = <&xo_board_clk>,
>> +				<&sleep_clk>,
>> +				<&bias_pll_ubi_nc_clk>,
>> +				<&pcie30_phy0_pipe_clk>,
>> +				<&pcie30_phy1_pipe_clk>,
>> +				<&pcie30_phy2_pipe_clk>,
>> +				<&pcie30_phy3_pipe_clk>,
>> +				<&usb3phy_0_cc_pipe_clk>;
>> +			clock-names = "xo",
>> +				"sleep_clk",
> 
> Misaligned. Multiple other places probably as well.
Sure, will do
> 
>> +				"bias_pll_ubi_nc_clk",
>> +				"pcie30_phy0_pipe_clk",
>> +				"pcie30_phy1_pipe_clk",
>> +				"pcie30_phy2_pipe_clk",
>> +				"pcie30_phy3_pipe_clk",
>> +				"usb3phy_0_cc_pipe_clk";
>> +			#clock-cells = <1>;
>> +			#reset-cells = <1>;
>> +		};
>> +
>> +		sdhc_1: sdhci@7804000 {
>> +			compatible = "qcom,sdhci-msm-v5";
>> +			reg = <0x7804000 0x1000>, <0x7805000 0x1000>;
>> +			reg-names = "hc_mem", "cmdq_mem";
>> +
>> +			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
>> +				   <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
> 
> Like here.
Okay
> 
>> +			interrupt-names = "hc_irq", "pwr_irq";
>> +
>> +			clocks = <&xo_board_clk>,
>> +			       <&gcc GCC_SDCC1_AHB_CLK>,
>> +			       <&gcc GCC_SDCC1_APPS_CLK>;
> 
> And here
Okay
> 
>> +			clock-names = "xo", "iface", "core";
> 
> Does not look like you tested the bindings. Please run `make
> dt_binding_check` (see
> Documentation/devicetree/bindings/writing-schema.rst for instructions).
Sure, will do
> 
>> +			mmc-ddr-1_8v;
>> +			mmc-hs200-1_8v;
>> +			mmc-hs400-1_8v;
>> +			mmc-hs400-enhanced-strobe;
>> +			max-frequency = <384000000>;
>> +			bus-width = <8>;
>> +			non-removable;
>> +			status = "disabled";
>> +		};
>> +
>> +		blsp1_uart2: serial@78b1000 {
>> +			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
>> +			reg = <0x078b1000 0x200>;
>> +			interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>,
>> +				 <&gcc GCC_BLSP1_AHB_CLK>;
>> +			clock-names = "core", "iface";
>> +			status = "disabled";
>> +		};
>> +
>> +		intc: interrupt-controller@b000000 {
>> +			compatible = "qcom,msm-qgic2";
>> +			reg = <0x0b000000 0x1000>,  /* GICD */
>> +			      <0x0b002000 0x1000>,  /* GICC */
>> +			      <0x0b001000 0x1000>,  /* GICH */
>> +			      <0x0b004000 0x1000>;  /* GICV */
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +			ranges = <0 0x0b00c000 0x3000>;
>> +
>> +			v2m0: v2m@0 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x0 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m1: v2m@1 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x1000 0xffd>;
>> +				msi-controller;
>> +			};
>> +
>> +			v2m2: v2m@2 {
>> +				compatible = "arm,gic-v2m-frame";
>> +				reg = <0x2000 0xffd>;
>> +				msi-controller;
>> +			};
>> +		};
>> +
>> +		timer@b120000 {
>> +			compatible = "arm,armv7-timer-mem";
>> +			reg = <0xb120000 0x1000>;
>> +			#address-cells = <1>;
>> +			#size-cells = <1>;
>> +			ranges;
>> +			clock-frequency = <24000000>;
>> +
>> +			frame@b120000 {
>> +				reg = <0xb121000 0x1000>,
>> +				      <0xb122000 0x1000>;
>> +				frame-number = <0>;
>> +				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
>> +					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +			};
>> +
>> +			frame@b123000 {
>> +				reg = <0xb123000 0x1000>;
>> +				frame-number = <1>;
>> +				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b124000 {
>> +				reg = <0xb124000 0x1000>;
>> +				frame-number = <2>;
>> +				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b125000 {
>> +				reg = <0xb125000 0x1000>;
>> +				frame-number = <3>;
>> +				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b126000 {
>> +				reg = <0xb126000 0x1000>;
>> +				frame-number = <4>;
>> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b127000 {
>> +				reg = <0xb127000 0x1000>;
>> +				frame-number = <5>;
>> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +
>> +			frame@b128000 {
>> +				reg = <0xb128000 0x1000>;
>> +				frame-number = <6>;
>> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> +				status = "disabled";
>> +			};
>> +		};
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +		clock-frequency = <24000000>;
> 
> Is this allowed in recent designs?
Okay, will drop
> 
>> +	};
>> +};
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 13/01/2023 14:29, Devi Priya wrote:
>>> +
>>> +	soc: soc@0 {
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>> +		ranges = <0 0 0 0xffffffff>;
>>> +		compatible = "simple-bus";
>>> +
>>> +		tlmm: pinctrl@1000000 {
>>> +			compatible = "qcom,ipq9574-tlmm";
>>> +			reg = <0x01000000 0x300000>;
>>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>> +			gpio-controller;
>>> +			#gpio-cells = <2>;
>>> +			gpio-ranges = <&tlmm 0 0 65>;
>>> +			gpio-reserved-ranges = <59 1>;
>>
>> Hm, why reserved ranges are in SoC?
> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC

Why it is forbidden on all boards? I guess it depends on the firmware
and this can differ, can't it?

Best regards,
Krzysztof


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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 13/01/2023 14:29, Devi Priya wrote:
>>> +
>>> +	soc: soc@0 {
>>> +		#address-cells = <1>;
>>> +		#size-cells = <1>;
>>> +		ranges = <0 0 0 0xffffffff>;
>>> +		compatible = "simple-bus";
>>> +
>>> +		tlmm: pinctrl@1000000 {
>>> +			compatible = "qcom,ipq9574-tlmm";
>>> +			reg = <0x01000000 0x300000>;
>>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>> +			gpio-controller;
>>> +			#gpio-cells = <2>;
>>> +			gpio-ranges = <&tlmm 0 0 65>;
>>> +			gpio-reserved-ranges = <59 1>;
>>
>> Hm, why reserved ranges are in SoC?
> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC

Why it is forbidden on all boards? I guess it depends on the firmware
and this can differ, can't it?

Best regards,
Krzysztof

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/13/2023 7:50 PM, Krzysztof Kozlowski wrote:
> On 13/01/2023 14:29, Devi Priya wrote:
>>>> +
>>>> +	soc: soc@0 {
>>>> +		#address-cells = <1>;
>>>> +		#size-cells = <1>;
>>>> +		ranges = <0 0 0 0xffffffff>;
>>>> +		compatible = "simple-bus";
>>>> +
>>>> +		tlmm: pinctrl@1000000 {
>>>> +			compatible = "qcom,ipq9574-tlmm";
>>>> +			reg = <0x01000000 0x300000>;
>>>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>> +			gpio-controller;
>>>> +			#gpio-cells = <2>;
>>>> +			gpio-ranges = <&tlmm 0 0 65>;
>>>> +			gpio-reserved-ranges = <59 1>;
>>>
>>> Hm, why reserved ranges are in SoC?
>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
> 
> Why it is forbidden on all boards? I guess it depends on the firmware
> and this can differ, can't it?
> 
This GPIO is protected and used by the TZ firmware and is forbidden on 
all the boards & firmware
> Best regards,
> Krzysztof
> 
Regards,
Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/13/2023 7:50 PM, Krzysztof Kozlowski wrote:
> On 13/01/2023 14:29, Devi Priya wrote:
>>>> +
>>>> +	soc: soc@0 {
>>>> +		#address-cells = <1>;
>>>> +		#size-cells = <1>;
>>>> +		ranges = <0 0 0 0xffffffff>;
>>>> +		compatible = "simple-bus";
>>>> +
>>>> +		tlmm: pinctrl@1000000 {
>>>> +			compatible = "qcom,ipq9574-tlmm";
>>>> +			reg = <0x01000000 0x300000>;
>>>> +			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>> +			gpio-controller;
>>>> +			#gpio-cells = <2>;
>>>> +			gpio-ranges = <&tlmm 0 0 65>;
>>>> +			gpio-reserved-ranges = <59 1>;
>>>
>>> Hm, why reserved ranges are in SoC?
>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
> 
> Why it is forbidden on all boards? I guess it depends on the firmware
> and this can differ, can't it?
> 
This GPIO is protected and used by the TZ firmware and is forbidden on 
all the boards & firmware
> Best regards,
> Krzysztof
> 
Regards,
Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 24/01/2023 08:19, Devi Priya wrote:
>>>>> +			gpio-ranges = <&tlmm 0 0 65>;
>>>>> +			gpio-reserved-ranges = <59 1>;
>>>>
>>>> Hm, why reserved ranges are in SoC?
>>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
>>
>> Why it is forbidden on all boards? I guess it depends on the firmware
>> and this can differ, can't it?
>>
> This GPIO is protected and used by the TZ firmware and is forbidden on 
> all the boards & firmware

OK

Best regards,
Krzysztof

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 24/01/2023 08:19, Devi Priya wrote:
>>>>> +			gpio-ranges = <&tlmm 0 0 65>;
>>>>> +			gpio-reserved-ranges = <59 1>;
>>>>
>>>> Hm, why reserved ranges are in SoC?
>>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
>>
>> Why it is forbidden on all boards? I guess it depends on the firmware
>> and this can differ, can't it?
>>
> This GPIO is protected and used by the TZ firmware and is forbidden on 
> all the boards & firmware

OK

Best regards,
Krzysztof


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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Konrad Dybcio]

On 24.01.2023 08:19, Devi Priya wrote:
> 
> 
> On 1/13/2023 7:50 PM, Krzysztof Kozlowski wrote:
>> On 13/01/2023 14:29, Devi Priya wrote:
>>>>> +
>>>>> +    soc: soc@0 {
>>>>> +        #address-cells = <1>;
>>>>> +        #size-cells = <1>;
>>>>> +        ranges = <0 0 0 0xffffffff>;
>>>>> +        compatible = "simple-bus";
>>>>> +
>>>>> +        tlmm: pinctrl@1000000 {
>>>>> +            compatible = "qcom,ipq9574-tlmm";
>>>>> +            reg = <0x01000000 0x300000>;
>>>>> +            interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +            gpio-controller;
>>>>> +            #gpio-cells = <2>;
>>>>> +            gpio-ranges = <&tlmm 0 0 65>;
>>>>> +            gpio-reserved-ranges = <59 1>;
>>>>
>>>> Hm, why reserved ranges are in SoC?
>>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
>>
>> Why it is forbidden on all boards? I guess it depends on the firmware
>> and this can differ, can't it?
>>
> This GPIO is protected and used by the TZ firmware and is forbidden on all the boards & firmware
If it's protected on *all* boards and *all* firmwares (for any
good reason that you probably have internally), perhaps it
would be better to describe it in the .c driver.. wdyt?

Konrad
>> Best regards,
>> Krzysztof
>>
> Regards,
> Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Konrad Dybcio]

On 24.01.2023 08:19, Devi Priya wrote:
> 
> 
> On 1/13/2023 7:50 PM, Krzysztof Kozlowski wrote:
>> On 13/01/2023 14:29, Devi Priya wrote:
>>>>> +
>>>>> +    soc: soc@0 {
>>>>> +        #address-cells = <1>;
>>>>> +        #size-cells = <1>;
>>>>> +        ranges = <0 0 0 0xffffffff>;
>>>>> +        compatible = "simple-bus";
>>>>> +
>>>>> +        tlmm: pinctrl@1000000 {
>>>>> +            compatible = "qcom,ipq9574-tlmm";
>>>>> +            reg = <0x01000000 0x300000>;
>>>>> +            interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>> +            gpio-controller;
>>>>> +            #gpio-cells = <2>;
>>>>> +            gpio-ranges = <&tlmm 0 0 65>;
>>>>> +            gpio-reserved-ranges = <59 1>;
>>>>
>>>> Hm, why reserved ranges are in SoC?
>>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
>>
>> Why it is forbidden on all boards? I guess it depends on the firmware
>> and this can differ, can't it?
>>
> This GPIO is protected and used by the TZ firmware and is forbidden on all the boards & firmware
If it's protected on *all* boards and *all* firmwares (for any
good reason that you probably have internally), perhaps it
would be better to describe it in the .c driver.. wdyt?

Konrad
>> Best regards,
>> Krzysztof
>>
> Regards,
> Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/24/2023 3:16 PM, Konrad Dybcio wrote:
> 
> 
> On 24.01.2023 08:19, Devi Priya wrote:
>>
>>
>> On 1/13/2023 7:50 PM, Krzysztof Kozlowski wrote:
>>> On 13/01/2023 14:29, Devi Priya wrote:
>>>>>> +
>>>>>> +    soc: soc@0 {
>>>>>> +        #address-cells = <1>;
>>>>>> +        #size-cells = <1>;
>>>>>> +        ranges = <0 0 0 0xffffffff>;
>>>>>> +        compatible = "simple-bus";
>>>>>> +
>>>>>> +        tlmm: pinctrl@1000000 {
>>>>>> +            compatible = "qcom,ipq9574-tlmm";
>>>>>> +            reg = <0x01000000 0x300000>;
>>>>>> +            interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +            gpio-controller;
>>>>>> +            #gpio-cells = <2>;
>>>>>> +            gpio-ranges = <&tlmm 0 0 65>;
>>>>>> +            gpio-reserved-ranges = <59 1>;
>>>>>
>>>>> Hm, why reserved ranges are in SoC?
>>>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
>>>
>>> Why it is forbidden on all boards? I guess it depends on the firmware
>>> and this can differ, can't it?
>>>
>> This GPIO is protected and used by the TZ firmware and is forbidden on all the boards & firmware
> If it's protected on *all* boards and *all* firmwares (for any
> good reason that you probably have internally), perhaps it
> would be better to describe it in the .c driver.. wdyt?
> 
Sure, okay. Will add the gpio to reserved_gpios entry in the pinctrl driver
> Konrad
>>> Best regards,
>>> Krzysztof
>>>
>> Regards,
>> Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/24/2023 3:16 PM, Konrad Dybcio wrote:
> 
> 
> On 24.01.2023 08:19, Devi Priya wrote:
>>
>>
>> On 1/13/2023 7:50 PM, Krzysztof Kozlowski wrote:
>>> On 13/01/2023 14:29, Devi Priya wrote:
>>>>>> +
>>>>>> +    soc: soc@0 {
>>>>>> +        #address-cells = <1>;
>>>>>> +        #size-cells = <1>;
>>>>>> +        ranges = <0 0 0 0xffffffff>;
>>>>>> +        compatible = "simple-bus";
>>>>>> +
>>>>>> +        tlmm: pinctrl@1000000 {
>>>>>> +            compatible = "qcom,ipq9574-tlmm";
>>>>>> +            reg = <0x01000000 0x300000>;
>>>>>> +            interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
>>>>>> +            gpio-controller;
>>>>>> +            #gpio-cells = <2>;
>>>>>> +            gpio-ranges = <&tlmm 0 0 65>;
>>>>>> +            gpio-reserved-ranges = <59 1>;
>>>>>
>>>>> Hm, why reserved ranges are in SoC?
>>>> As the gpio is forbidden on all ipq9574 boards, we have added it in SoC
>>>
>>> Why it is forbidden on all boards? I guess it depends on the firmware
>>> and this can differ, can't it?
>>>
>> This GPIO is protected and used by the TZ firmware and is forbidden on all the boards & firmware
> If it's protected on *all* boards and *all* firmwares (for any
> good reason that you probably have internally), perhaps it
> would be better to describe it in the .c driver.. wdyt?
> 
Sure, okay. Will add the gpio to reserved_gpios entry in the pinctrl driver
> Konrad
>>> Best regards,
>>> Krzysztof
>>>
>> Regards,
>> Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>

Don't use CAPITAL CASE FOR NAMES BUT Camel Case. Although different
languages might have different rules, but most cases when transliterated
to English (or Latin alphabet), the name Start with capital letter. The
same in your case.

> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++

One more:

Use subject prefixes matching the subsystem (which you can get for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching).

Best regards,
Krzysztof


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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Krzysztof Kozlowski]

On 10/01/2023 13:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>

Don't use CAPITAL CASE FOR NAMES BUT Camel Case. Although different
languages might have different rules, but most cases when transliterated
to English (or Latin alphabet), the name Start with capital letter. The
same in your case.

> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++

One more:

Use subject prefixes matching the subsystem (which you can get for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching).

Best regards,
Krzysztof

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 3:15 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Don't use CAPITAL CASE FOR NAMES BUT Camel Case. Although different
> languages might have different rules, but most cases when transliterated
> to English (or Latin alphabet), the name Start with capital letter. The
> same in your case.
Sure, okay
> 
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
> 
> One more:
> 
> Use subject prefixes matching the subsystem (which you can get for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching).
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/11/2023 3:15 PM, Krzysztof Kozlowski wrote:
> On 10/01/2023 13:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Don't use CAPITAL CASE FOR NAMES BUT Camel Case. Although different
> languages might have different rules, but most cases when transliterated
> to English (or Latin alphabet), the name Start with capital letter. The
> same in your case.
Sure, okay
> 
>> ---
>>   arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>   arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
> 
> One more:
> 
> Use subject prefixes matching the subsystem (which you can get for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
> your patch is touching).
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Marc Zyngier]

On 2023-01-10 12:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>  3 files changed, 388 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile
> b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..872c62028a0b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> new file mode 100644
> index 000000000000..ae3c32f3e16a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts

[...]

> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | 
> IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

Interesting choice for the PPIs...

> +		clock-frequency = <24000000>;

Please drop this and fix the firmware. No system built within
past 10 years should need it.

         M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Marc Zyngier]

On 2023-01-10 12:13, devi priya wrote:
> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> 
> Add initial device tree support for Qualcomm IPQ9574 SoC
> and AL02 board
> 
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>  3 files changed, 388 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/Makefile
> b/arch/arm64/boot/dts/qcom/Makefile
> index 3e79496292e7..872c62028a0b 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c1.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk10-c2.dtb
> +dtb-$(CONFIG_ARCH_QCOM)	+= ipq9574-al02-c7.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-alcatel-idol347.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-asus-z00l.dtb
>  dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-huawei-g7.dtb
> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> new file mode 100644
> index 000000000000..ae3c32f3e16a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts

[...]

> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | 
> IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

Interesting choice for the PPIs...

> +		clock-frequency = <24000000>;

Please drop this and fix the firmware. No system built within
past 10 years should need it.

         M.
-- 
Jazz is not dead. It just smells funny...

Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/13/2023 7:19 PM, Marc Zyngier wrote:
> On 2023-01-10 12:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>  3 files changed, 388 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)    += ipq6018-cp01-c1.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk01.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c1.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)    += ipq9574-al02-c7.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += msm8916-alcatel-idol347.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += msm8916-asus-z00l.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> 
> [...]
> 
>> +    timer {
>> +        compatible = "arm,armv8-timer";
>> +        interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>;
> 
> Interesting choice for the PPIs...
> 
>> +        clock-frequency = <24000000>;
> 
> Please drop this and fix the firmware. No system built within
> past 10 years should need it.
Sure, will drop!
> 
>          M.
Best Regards,
Devi Priya

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Re: [PATCH 6/7] arm64: dts: Add ipq9574 SoC and AL02 board support

[Devi Priya]

On 1/13/2023 7:19 PM, Marc Zyngier wrote:
> On 2023-01-10 12:13, devi priya wrote:
>> From: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>>
>> Add initial device tree support for Qualcomm IPQ9574 SoC
>> and AL02 board
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Co-developed-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> Signed-off-by: POOVENDHAN SELVARAJ <quic_poovendh@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/Makefile            |   1 +
>>  arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts |  69 ++++
>>  arch/arm64/boot/dts/qcom/ipq9574.dtsi        | 318 +++++++++++++++++++
>>  3 files changed, 388 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>>  create mode 100644 arch/arm64/boot/dts/qcom/ipq9574.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/Makefile
>> b/arch/arm64/boot/dts/qcom/Makefile
>> index 3e79496292e7..872c62028a0b 100644
>> --- a/arch/arm64/boot/dts/qcom/Makefile
>> +++ b/arch/arm64/boot/dts/qcom/Makefile
>> @@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM)    += ipq6018-cp01-c1.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk01.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c1.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += ipq8074-hk10-c2.dtb
>> +dtb-$(CONFIG_ARCH_QCOM)    += ipq9574-al02-c7.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += msm8916-alcatel-idol347.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += msm8916-asus-z00l.dtb
>>  dtb-$(CONFIG_ARCH_QCOM)    += msm8916-huawei-g7.dtb
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
>> new file mode 100644
>> index 000000000000..ae3c32f3e16a
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574-al02-c7.dts
> 
> [...]
> 
>> +    timer {
>> +        compatible = "arm,armv8-timer";
>> +        interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>,
>> +                 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | 
>> IRQ_TYPE_LEVEL_LOW)>;
> 
> Interesting choice for the PPIs...
> 
>> +        clock-frequency = <24000000>;
> 
> Please drop this and fix the firmware. No system built within
> past 10 years should need it.
Sure, will drop!
> 
>          M.
Best Regards,
Devi Priya

[PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[devi priya]

Enables clk & pinctrl related configs

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 851e8f9be06d..e0ae0996d5ad 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
 CONFIG_PINCTRL_MSM=y
 CONFIG_PINCTRL_IPQ8074=y
 CONFIG_PINCTRL_IPQ6018=y
+CONFIG_PINCTRL_IPQ9574=y
 CONFIG_PINCTRL_MSM8916=y
 CONFIG_PINCTRL_MSM8953=y
 CONFIG_PINCTRL_MSM8976=y
@@ -1093,6 +1094,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_QCOM_CLK_RPMH=y
 CONFIG_IPQ_GCC_6018=y
 CONFIG_IPQ_GCC_8074=y
+CONFIG_IPQ_GCC_9574=y
 CONFIG_MSM_GCC_8916=y
 CONFIG_MSM_GCC_8994=y
 CONFIG_MSM_MMCC_8996=y
-- 
2.17.1


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[PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[devi priya]

Enables clk & pinctrl related configs

Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
Signed-off-by: devi priya <quic_devipriy@quicinc.com>
---
 arch/arm64/configs/defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 851e8f9be06d..e0ae0996d5ad 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
 CONFIG_PINCTRL_MSM=y
 CONFIG_PINCTRL_IPQ8074=y
 CONFIG_PINCTRL_IPQ6018=y
+CONFIG_PINCTRL_IPQ9574=y
 CONFIG_PINCTRL_MSM8916=y
 CONFIG_PINCTRL_MSM8953=y
 CONFIG_PINCTRL_MSM8976=y
@@ -1093,6 +1094,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_QCOM_CLK_RPMH=y
 CONFIG_IPQ_GCC_6018=y
 CONFIG_IPQ_GCC_8074=y
+CONFIG_IPQ_GCC_9574=y
 CONFIG_MSM_GCC_8916=y
 CONFIG_MSM_GCC_8994=y
 CONFIG_MSM_MMCC_8996=y
-- 
2.17.1

Re: [PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[Kathiravan Thirumoorthy]

On 1/10/2023 5:43 PM, devi priya wrote:
> Enables clk & pinctrl related configs
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>   arch/arm64/configs/defconfig | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 851e8f9be06d..e0ae0996d5ad 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
>   CONFIG_PINCTRL_MSM=y
>   CONFIG_PINCTRL_IPQ8074=y
>   CONFIG_PINCTRL_IPQ6018=y
> +CONFIG_PINCTRL_IPQ9574=y
Please move this after IPQ8074, to keep it in ascending order. We can 
move the IPQ6018 config before IPQ8074.
>   CONFIG_PINCTRL_MSM8916=y
>   CONFIG_PINCTRL_MSM8953=y
>   CONFIG_PINCTRL_MSM8976=y
> @@ -1093,6 +1094,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
>   CONFIG_QCOM_CLK_RPMH=y
>   CONFIG_IPQ_GCC_6018=y
>   CONFIG_IPQ_GCC_8074=y
> +CONFIG_IPQ_GCC_9574=y
>   CONFIG_MSM_GCC_8916=y
>   CONFIG_MSM_GCC_8994=y
>   CONFIG_MSM_MMCC_8996=y

Re: [PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[Kathiravan Thirumoorthy]

On 1/10/2023 5:43 PM, devi priya wrote:
> Enables clk & pinctrl related configs
>
> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
> ---
>   arch/arm64/configs/defconfig | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 851e8f9be06d..e0ae0996d5ad 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
>   CONFIG_PINCTRL_MSM=y
>   CONFIG_PINCTRL_IPQ8074=y
>   CONFIG_PINCTRL_IPQ6018=y
> +CONFIG_PINCTRL_IPQ9574=y
Please move this after IPQ8074, to keep it in ascending order. We can 
move the IPQ6018 config before IPQ8074.
>   CONFIG_PINCTRL_MSM8916=y
>   CONFIG_PINCTRL_MSM8953=y
>   CONFIG_PINCTRL_MSM8976=y
> @@ -1093,6 +1094,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y
>   CONFIG_QCOM_CLK_RPMH=y
>   CONFIG_IPQ_GCC_6018=y
>   CONFIG_IPQ_GCC_8074=y
> +CONFIG_IPQ_GCC_9574=y
>   CONFIG_MSM_GCC_8916=y
>   CONFIG_MSM_GCC_8994=y
>   CONFIG_MSM_MMCC_8996=y

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Re: [PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[Krzysztof Kozlowski]

On 11/01/2023 15:48, Kathiravan Thirumoorthy wrote:
> 
> On 1/10/2023 5:43 PM, devi priya wrote:
>> Enables clk & pinctrl related configs
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   arch/arm64/configs/defconfig | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index 851e8f9be06d..e0ae0996d5ad 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
>>   CONFIG_PINCTRL_MSM=y
>>   CONFIG_PINCTRL_IPQ8074=y
>>   CONFIG_PINCTRL_IPQ6018=y
>> +CONFIG_PINCTRL_IPQ9574=y
> Please move this after IPQ8074, to keep it in ascending order. We can 
> move the IPQ6018 config before IPQ8074.

This must match savedefconfig order, not alphabetical.

Best regards,
Krzysztof

Re: [PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[Krzysztof Kozlowski]

On 11/01/2023 15:48, Kathiravan Thirumoorthy wrote:
> 
> On 1/10/2023 5:43 PM, devi priya wrote:
>> Enables clk & pinctrl related configs
>>
>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>> ---
>>   arch/arm64/configs/defconfig | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index 851e8f9be06d..e0ae0996d5ad 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
>>   CONFIG_PINCTRL_MSM=y
>>   CONFIG_PINCTRL_IPQ8074=y
>>   CONFIG_PINCTRL_IPQ6018=y
>> +CONFIG_PINCTRL_IPQ9574=y
> Please move this after IPQ8074, to keep it in ascending order. We can 
> move the IPQ6018 config before IPQ8074.

This must match savedefconfig order, not alphabetical.

Best regards,
Krzysztof


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Re: [PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[Devi Priya]

On 1/11/2023 8:33 PM, Krzysztof Kozlowski wrote:
> On 11/01/2023 15:48, Kathiravan Thirumoorthy wrote:
>>
>> On 1/10/2023 5:43 PM, devi priya wrote:
>>> Enables clk & pinctrl related configs
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>> ---
>>>    arch/arm64/configs/defconfig | 2 ++
>>>    1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>> index 851e8f9be06d..e0ae0996d5ad 100644
>>> --- a/arch/arm64/configs/defconfig
>>> +++ b/arch/arm64/configs/defconfig
>>> @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
>>>    CONFIG_PINCTRL_MSM=y
>>>    CONFIG_PINCTRL_IPQ8074=y
>>>    CONFIG_PINCTRL_IPQ6018=y
>>> +CONFIG_PINCTRL_IPQ9574=y
>> Please move this after IPQ8074, to keep it in ascending order. We can
>> move the IPQ6018 config before IPQ8074.
> 
> This must match savedefconfig order, not alphabetical.
Understood!
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya

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Re: [PATCH 7/7] arm64: defconfig: Enable IPQ9574 SoC base configs

[Devi Priya]

On 1/11/2023 8:33 PM, Krzysztof Kozlowski wrote:
> On 11/01/2023 15:48, Kathiravan Thirumoorthy wrote:
>>
>> On 1/10/2023 5:43 PM, devi priya wrote:
>>> Enables clk & pinctrl related configs
>>>
>>> Co-developed-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com>
>>> Signed-off-by: devi priya <quic_devipriy@quicinc.com>
>>> ---
>>>    arch/arm64/configs/defconfig | 2 ++
>>>    1 file changed, 2 insertions(+)
>>>
>>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>>> index 851e8f9be06d..e0ae0996d5ad 100644
>>> --- a/arch/arm64/configs/defconfig
>>> +++ b/arch/arm64/configs/defconfig
>>> @@ -545,6 +545,7 @@ CONFIG_PINCTRL_IMX93=y
>>>    CONFIG_PINCTRL_MSM=y
>>>    CONFIG_PINCTRL_IPQ8074=y
>>>    CONFIG_PINCTRL_IPQ6018=y
>>> +CONFIG_PINCTRL_IPQ9574=y
>> Please move this after IPQ8074, to keep it in ascending order. We can
>> move the IPQ6018 config before IPQ8074.
> 
> This must match savedefconfig order, not alphabetical.
Understood!
> 
> Best regards,
> Krzysztof
> 
Best Regards,
Devi Priya