[PATCH v2 1/3] xen/riscv: read/save hart_id and dtb_base passed by bootloader

[Oleksii Kurochko <oleksii.kurochko@gmail.com>]

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes since v1:
 * read/save/pass of hart_id and  dtb_base passed by a bootloader
   were moved to head.S. 
 * Update start_xen() to recieve hard_id & dtb_base
---
 xen/arch/riscv/riscv64/head.S | 24 ++++++++++++++++++++++++
 xen/arch/riscv/setup.c        |  3 ++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
index ffd95f9f89..851b4691a5 100644
--- a/xen/arch/riscv/riscv64/head.S
+++ b/xen/arch/riscv/riscv64/head.S
@@ -1,3 +1,4 @@
+#include <asm/asm.h>
 #include <asm/riscv_encoding.h>
 
         .section .text.header, "ax", %progbits
@@ -6,8 +7,31 @@ ENTRY(start)
         /* Mask all interrupts */
         csrw    CSR_SIE, zero
 
+        /* Save HART ID and DTB base */
+        lla     a6, _bootcpu_id
+        REG_S   a0, (a6)
+        lla     a6, _dtb_base
+        REG_S   a1, (a6)
+
         la      sp, cpu0_boot_stack
         li      t0, STACK_SIZE
         add     sp, sp, t0
 
+        lla     a6, _bootcpu_id
+        REG_L   a0, (a6)
+        lla     a6, _dtb_base
+        REG_L   a1, (a6)
+
         tail    start_xen
+
+        /*
+         * Boot cpu id is passed by a bootloader
+         */
+_bootcpu_id:
+        RISCV_PTR 0x0
+
+        /*
+         * DTB base is passed by a bootloader
+         */
+_dtb_base:
+        RISCV_PTR 0x0
diff --git a/xen/arch/riscv/setup.c b/xen/arch/riscv/setup.c
index 1c87899e8e..d9723fe1c0 100644
--- a/xen/arch/riscv/setup.c
+++ b/xen/arch/riscv/setup.c
@@ -7,7 +7,8 @@
 unsigned char __initdata cpu0_boot_stack[STACK_SIZE]
     __aligned(STACK_SIZE);
 
-void __init noreturn start_xen(void)
+void __init noreturn start_xen(unsigned long bootcpu_id,
+                               unsigned long dtb_base)
 {
     early_printk("Hello from C env\n");
 
-- 
2.39.0