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From: Oleksii Kurochko <oleksii.kurochko@gmail.com>
To: xen-devel@lists.xenproject.org
Cc: Jan Beulich <jbeulich@suse.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>,
	Stefano Stabellini <sstabellini@kernel.org>,
	Gianluca Guida <gianluca@rivosinc.com>,
	Oleksii Kurochko <oleksii.kurochko@gmail.com>,
	Bob Eshleman <bobbyeshleman@gmail.com>,
	Alistair Francis <alistair.francis@wdc.com>,
	Connor Davis <connojdavis@gmail.com>
Subject: [PATCH v2 2/3] xen/riscv: initialize .bss section
Date: Thu,  2 Mar 2023 15:23:19 +0200	[thread overview]
Message-ID: <495bd1d7fc2becdd48bd00253c079971e2231e99.1677762812.git.oleksii.kurochko@gmail.com> (raw)
In-Reply-To: <cover.1677762812.git.oleksii.kurochko@gmail.com>

Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
---
Changes since v1:
 * initialization of .bss was moved to head.S
---
 xen/arch/riscv/include/asm/asm.h | 4 ++++
 xen/arch/riscv/riscv64/head.S    | 9 +++++++++
 2 files changed, 13 insertions(+)

diff --git a/xen/arch/riscv/include/asm/asm.h b/xen/arch/riscv/include/asm/asm.h
index 6d426ecea7..5208529cb4 100644
--- a/xen/arch/riscv/include/asm/asm.h
+++ b/xen/arch/riscv/include/asm/asm.h
@@ -26,14 +26,18 @@
 #if __SIZEOF_POINTER__ == 8
 #ifdef __ASSEMBLY__
 #define RISCV_PTR		.dword
+#define RISCV_SZPTR		8
 #else
 #define RISCV_PTR		".dword"
+#define RISCV_SZPTR		8
 #endif
 #elif __SIZEOF_POINTER__ == 4
 #ifdef __ASSEMBLY__
 #define RISCV_PTR		.word
+#define RISCV_SZPTR		4
 #else
 #define RISCV_PTR		".word"
+#define RISCV_SZPTR		4
 #endif
 #else
 #error "Unexpected __SIZEOF_POINTER__"
diff --git a/xen/arch/riscv/riscv64/head.S b/xen/arch/riscv/riscv64/head.S
index 851b4691a5..b139976b7a 100644
--- a/xen/arch/riscv/riscv64/head.S
+++ b/xen/arch/riscv/riscv64/head.S
@@ -13,6 +13,15 @@ ENTRY(start)
         lla     a6, _dtb_base
         REG_S   a1, (a6)
 
+        la      a3, __bss_start
+        la      a4, __bss_end
+        ble     a4, a3, clear_bss_done
+clear_bss:
+        REG_S   zero, (a3)
+        add     a3, a3, RISCV_SZPTR
+        blt     a3, a4, clear_bss
+clear_bss_done:
+
         la      sp, cpu0_boot_stack
         li      t0, STACK_SIZE
         add     sp, sp, t0
-- 
2.39.0



  parent reply	other threads:[~2023-03-02 13:23 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-02 13:23 [PATCH v2 0/3] Do basic initialization things Oleksii Kurochko
2023-03-02 13:23 ` [PATCH v2 1/3] xen/riscv: read/save hart_id and dtb_base passed by bootloader Oleksii Kurochko
2023-03-02 14:02   ` Andrew Cooper
2023-03-02 14:53     ` Oleksii
2023-03-02 18:58       ` Andrew Cooper
2023-03-03  8:48         ` Oleksii
2023-03-02 13:23 ` Oleksii Kurochko [this message]
2023-03-02 14:12   ` [PATCH v2 2/3] xen/riscv: initialize .bss section Andrew Cooper
2023-03-02 14:55     ` Oleksii
2023-03-02 14:22   ` Jan Beulich
2023-03-02 15:55     ` Oleksii
2023-03-02 16:01       ` Jan Beulich
2023-03-02 20:34       ` Andrew Cooper
2023-03-02 13:23 ` [PATCH v2 3/3] xen/riscv: disable fpu Oleksii Kurochko
2023-03-02 14:20   ` Andrew Cooper
2023-03-02 17:11     ` Oleksii

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