From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: Allen-KH Cheng <allen-kh.cheng@mediatek.com>, Lee Jones <lee@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, hsinyi@chromium.org Subject: Re: [PATCH 2/5] arm64: dts: mt8186: Add power domains controller Date: Tue, 27 Sep 2022 15:47:38 +0200 [thread overview] Message-ID: <4576f195-b390-2083-300c-bb31ad09a7ed@collabora.com> (raw) In-Reply-To: <20220923131148.6678-3-allen-kh.cheng@mediatek.com> Il 23/09/22 15:11, Allen-KH Cheng ha scritto: > Add power domains controller for mt8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++ > 1 file changed, 188 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index 64693c17af9e..833e7037fe22 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -329,6 +329,194 @@ > #interrupt-cells = <2>; > }; > > + scpsys: syscon@10006000 { > + compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; > + reg = <0 0x10006000 0 0x1000>; > + > + /* System Power Manager */ > + spm: power-controller { > + compatible = "mediatek,mt8186-power-controller"; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + ..snip.. > + power-domain@MT8186_POWER_DOMAIN_DIS { > + reg = <MT8186_POWER_DOMAIN_DIS>; > + clocks = <&topckgen CLK_TOP_DISP>, > + <&topckgen CLK_TOP_MDP>, > + <&mmsys CLK_MM_SMI_INFRA>, > + <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_GALS>, > + <&mmsys CLK_MM_SMI_IOMMU>; > + clock-names = "dis0", "dis1", "dis-0", "dis-1", > + "dis-2", "dis-3"; What about using more descriptive names for clock-names? disp, mdp, smi_infra, smi_common, smi_gals, smi_iommu > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_VDEC { > + reg = <MT8186_POWER_DOMAIN_VDEC>; > + clocks = <&topckgen CLK_TOP_VDEC>, > + <&vdecsys CLK_VDEC_LARB1_CKEN>; > + clock-names = "vdec0", "vdec-0"; vdec0, larb > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM { > + reg = <MT8186_POWER_DOMAIN_CAM>; > + clocks = <&topckgen CLK_TOP_CAM>, > + <&topckgen CLK_TOP_SENINF>, > + <&topckgen CLK_TOP_SENINF1>, > + <&topckgen CLK_TOP_SENINF2>, > + <&topckgen CLK_TOP_SENINF3>, > + <&topckgen CLK_TOP_CAMTM>, > + <&camsys CLK_CAM2MM_GALS>; > + clock-names = "cam0", "cam1", "cam2", "cam3", > + "cam4", "cam5", "cam-0"; cam-top, cam0, cam1, cam2, cam3, cam-tm, gals > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { > + reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { > + reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IMG { > + reg = <MT8186_POWER_DOMAIN_IMG>; > + clocks = <&topckgen CLK_TOP_IMG1>, > + <&imgsys1 CLK_IMG1_GALS_IMG1>; > + clock-names = "img0", "img-0"; img-top, gals > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_IMG2 { > + reg = <MT8186_POWER_DOMAIN_IMG2>; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IPE { > + reg = <MT8186_POWER_DOMAIN_IPE>; > + clocks = <&topckgen CLK_TOP_IPE>, > + <&ipesys CLK_IPE_LARB19>, > + <&ipesys CLK_IPE_LARB20>, > + <&ipesys CLK_IPE_SMI_SUBCOM>, > + <&ipesys CLK_IPE_GALS_IPE>; > + clock-names = "ipe0", "ipe-0", "ipe-1", "ipe-2", > + "ipe-3"; ipe-top, ipe-larb0, ipe-larb1, ipe-smi, ipe-gals > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_VENC { > + reg = <MT8186_POWER_DOMAIN_VENC>; > + clocks = <&topckgen CLK_TOP_VENC>, > + <&vencsys CLK_VENC_CKE1_VENC>; > + clock-names = "venc0", "venc-0"; venc0, larb > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_WPE { > + reg = <MT8186_POWER_DOMAIN_WPE>; > + clocks = <&topckgen CLK_TOP_WPE>, > + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, > + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; > + clock-names = "wpe0", "wpe-0", "wpe-1"; wpe0, larb-ck, larb-pclk Regards, Angelo
WARNING: multiple messages have this Message-ID (diff)
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> To: Allen-KH Cheng <allen-kh.cheng@mediatek.com>, Lee Jones <lee@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>, Rob Herring <robh+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Cc: Project_Global_Chrome_Upstream_Group@mediatek.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, hsinyi@chromium.org Subject: Re: [PATCH 2/5] arm64: dts: mt8186: Add power domains controller Date: Tue, 27 Sep 2022 15:47:38 +0200 [thread overview] Message-ID: <4576f195-b390-2083-300c-bb31ad09a7ed@collabora.com> (raw) In-Reply-To: <20220923131148.6678-3-allen-kh.cheng@mediatek.com> Il 23/09/22 15:11, Allen-KH Cheng ha scritto: > Add power domains controller for mt8186 SoC. > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com> > --- > arch/arm64/boot/dts/mediatek/mt8186.dtsi | 188 +++++++++++++++++++++++ > 1 file changed, 188 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > index 64693c17af9e..833e7037fe22 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi > @@ -329,6 +329,194 @@ > #interrupt-cells = <2>; > }; > > + scpsys: syscon@10006000 { > + compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd"; > + reg = <0 0x10006000 0 0x1000>; > + > + /* System Power Manager */ > + spm: power-controller { > + compatible = "mediatek,mt8186-power-controller"; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + ..snip.. > + power-domain@MT8186_POWER_DOMAIN_DIS { > + reg = <MT8186_POWER_DOMAIN_DIS>; > + clocks = <&topckgen CLK_TOP_DISP>, > + <&topckgen CLK_TOP_MDP>, > + <&mmsys CLK_MM_SMI_INFRA>, > + <&mmsys CLK_MM_SMI_COMMON>, > + <&mmsys CLK_MM_SMI_GALS>, > + <&mmsys CLK_MM_SMI_IOMMU>; > + clock-names = "dis0", "dis1", "dis-0", "dis-1", > + "dis-2", "dis-3"; What about using more descriptive names for clock-names? disp, mdp, smi_infra, smi_common, smi_gals, smi_iommu > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_VDEC { > + reg = <MT8186_POWER_DOMAIN_VDEC>; > + clocks = <&topckgen CLK_TOP_VDEC>, > + <&vdecsys CLK_VDEC_LARB1_CKEN>; > + clock-names = "vdec0", "vdec-0"; vdec0, larb > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM { > + reg = <MT8186_POWER_DOMAIN_CAM>; > + clocks = <&topckgen CLK_TOP_CAM>, > + <&topckgen CLK_TOP_SENINF>, > + <&topckgen CLK_TOP_SENINF1>, > + <&topckgen CLK_TOP_SENINF2>, > + <&topckgen CLK_TOP_SENINF3>, > + <&topckgen CLK_TOP_CAMTM>, > + <&camsys CLK_CAM2MM_GALS>; > + clock-names = "cam0", "cam1", "cam2", "cam3", > + "cam4", "cam5", "cam-0"; cam-top, cam0, cam1, cam2, cam3, cam-tm, gals > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWB { > + reg = <MT8186_POWER_DOMAIN_CAM_RAWB>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_CAM_RAWA { > + reg = <MT8186_POWER_DOMAIN_CAM_RAWA>; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IMG { > + reg = <MT8186_POWER_DOMAIN_IMG>; > + clocks = <&topckgen CLK_TOP_IMG1>, > + <&imgsys1 CLK_IMG1_GALS_IMG1>; > + clock-names = "img0", "img-0"; img-top, gals > + mediatek,infracfg = <&infracfg_ao>; > + #address-cells = <1>; > + #size-cells = <0>; > + #power-domain-cells = <1>; > + > + power-domain@MT8186_POWER_DOMAIN_IMG2 { > + reg = <MT8186_POWER_DOMAIN_IMG2>; > + #power-domain-cells = <0>; > + }; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_IPE { > + reg = <MT8186_POWER_DOMAIN_IPE>; > + clocks = <&topckgen CLK_TOP_IPE>, > + <&ipesys CLK_IPE_LARB19>, > + <&ipesys CLK_IPE_LARB20>, > + <&ipesys CLK_IPE_SMI_SUBCOM>, > + <&ipesys CLK_IPE_GALS_IPE>; > + clock-names = "ipe0", "ipe-0", "ipe-1", "ipe-2", > + "ipe-3"; ipe-top, ipe-larb0, ipe-larb1, ipe-smi, ipe-gals > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_VENC { > + reg = <MT8186_POWER_DOMAIN_VENC>; > + clocks = <&topckgen CLK_TOP_VENC>, > + <&vencsys CLK_VENC_CKE1_VENC>; > + clock-names = "venc0", "venc-0"; venc0, larb > + mediatek,infracfg = <&infracfg_ao>; > + #power-domain-cells = <0>; > + }; > + > + power-domain@MT8186_POWER_DOMAIN_WPE { > + reg = <MT8186_POWER_DOMAIN_WPE>; > + clocks = <&topckgen CLK_TOP_WPE>, > + <&wpesys CLK_WPE_SMI_LARB8_CK_EN>, > + <&wpesys CLK_WPE_SMI_LARB8_PCLK_EN>; > + clock-names = "wpe0", "wpe-0", "wpe-1"; wpe0, larb-ck, larb-pclk Regards, Angelo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-27 13:47 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-09-23 13:11 [PATCH 0/5] Add some driver nodes for MT8186 SoC Allen-KH Cheng 2022-09-23 13:11 ` Allen-KH Cheng 2022-09-23 13:11 ` [PATCH 1/5] dt-bindings: mfd: mediatek: Add scpsys compatible for mt8186 Allen-KH Cheng 2022-09-23 13:11 ` Allen-KH Cheng 2022-09-23 17:47 ` Krzysztof Kozlowski 2022-09-23 17:47 ` Krzysztof Kozlowski 2022-09-26 7:48 ` Lee Jones 2022-09-26 7:48 ` Lee Jones 2022-09-23 13:11 ` [PATCH 2/5] arm64: dts: mt8186: Add power domains controller Allen-KH Cheng 2022-09-23 13:11 ` Allen-KH Cheng 2022-09-27 13:47 ` AngeloGioacchino Del Regno [this message] 2022-09-27 13:47 ` AngeloGioacchino Del Regno 2022-09-23 13:11 ` [PATCH 3/5] arm64: dts: mt8186: Add IOMMU and SMI nodes Allen-KH Cheng 2022-09-23 13:11 ` Allen-KH Cheng 2022-09-27 13:40 ` AngeloGioacchino Del Regno 2022-09-27 13:40 ` AngeloGioacchino Del Regno 2022-09-27 13:53 ` Allen-KH Cheng (程冠勳) 2022-09-27 13:53 ` Allen-KH Cheng (程冠勳) 2022-09-23 13:11 ` [PATCH 4/5] arm64: dts: mt8186: Add dpi node Allen-KH Cheng 2022-09-23 13:11 ` Allen-KH Cheng 2022-09-23 13:11 ` [PATCH 5/5] arm64: dts: mt8186: Add xhci nodes Allen-KH Cheng 2022-09-23 13:11 ` Allen-KH Cheng 2022-09-27 13:48 ` AngeloGioacchino Del Regno 2022-09-27 13:48 ` AngeloGioacchino Del Regno
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