* [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-15 10:09 ` Heinrich Schuchardt 0 siblings, 0 replies; 16+ messages in thread From: Heinrich Schuchardt @ 2021-10-15 10:09 UTC (permalink / raw) To: Daniel Lezcano, Thomas Gleixner Cc: Guo Ren, Bin Meng, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, opensbi, Heinrich Schuchardt The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to the MTIMER device. The current schema does not allow to specify this. OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the restriction. Samuael Holland suggested in lib: utils/timer: Use standard property to specify 32-bit I/O https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e to use "reg-io-width = <4>;" as the reg-io-width property is generally used in the devicetree schema for such a condition. A release candidate of the ACLINT specification is available at https://github.com/riscv/riscv-aclint/releases Add reg-io-width as optional property to the SiFive Core Local Interruptor. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index a35952f48742..266012d887b5 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -41,6 +41,13 @@ properties: reg: maxItems: 1 + reg-io-width: + description: | + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support + 32bit access for MTIMER. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 4 + interrupts-extended: minItems: 1 -- 2.32.0 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-15 10:09 ` Heinrich Schuchardt 0 siblings, 0 replies; 16+ messages in thread From: Heinrich Schuchardt @ 2021-10-15 10:09 UTC (permalink / raw) To: Daniel Lezcano, Thomas Gleixner Cc: Guo Ren, Bin Meng, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, opensbi, Heinrich Schuchardt The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to the MTIMER device. The current schema does not allow to specify this. OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the restriction. Samuael Holland suggested in lib: utils/timer: Use standard property to specify 32-bit I/O https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e to use "reg-io-width = <4>;" as the reg-io-width property is generally used in the devicetree schema for such a condition. A release candidate of the ACLINT specification is available at https://github.com/riscv/riscv-aclint/releases Add reg-io-width as optional property to the SiFive Core Local Interruptor. Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index a35952f48742..266012d887b5 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -41,6 +41,13 @@ properties: reg: maxItems: 1 + reg-io-width: + description: | + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support + 32bit access for MTIMER. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 4 + interrupts-extended: minItems: 1 -- 2.32.0 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT 2021-10-15 10:09 ` Heinrich Schuchardt @ 2021-10-15 10:14 ` Bin Meng -1 siblings, 0 replies; 16+ messages in thread From: Bin Meng @ 2021-10-15 10:14 UTC (permalink / raw) To: Heinrich Schuchardt Cc: Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local Interruptor. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..266012d887b5 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -41,6 +41,13 @@ properties: > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 But this is not a "sifive,clint" anyway. Should there be a new dt-bindings for T-Head clint variant? > + > interrupts-extended: > minItems: 1 Regards, Bin ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-15 10:14 ` Bin Meng 0 siblings, 0 replies; 16+ messages in thread From: Bin Meng @ 2021-10-15 10:14 UTC (permalink / raw) To: Heinrich Schuchardt Cc: Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local Interruptor. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..266012d887b5 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -41,6 +41,13 @@ properties: > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 But this is not a "sifive,clint" anyway. Should there be a new dt-bindings for T-Head clint variant? > + > interrupts-extended: > minItems: 1 Regards, Bin _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT 2021-10-15 10:14 ` Bin Meng @ 2021-10-15 11:54 ` Heinrich Schuchardt -1 siblings, 0 replies; 16+ messages in thread From: Heinrich Schuchardt @ 2021-10-15 11:54 UTC (permalink / raw) To: Bin Meng Cc: Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On 10/15/21 12:14, Bin Meng wrote: > On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt > <heinrich.schuchardt@canonical.com> wrote: >> >> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to >> the MTIMER device. The current schema does not allow to specify this. >> >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >> restriction. Samuael Holland suggested in >> lib: utils/timer: Use standard property to specify 32-bit I/O >> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e >> to use "reg-io-width = <4>;" as the reg-io-width property is generally used >> in the devicetree schema for such a condition. >> >> A release candidate of the ACLINT specification is available at >> https://github.com/riscv/riscv-aclint/releases >> >> Add reg-io-width as optional property to the SiFive Core Local Interruptor. >> >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >> --- >> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >> index a35952f48742..266012d887b5 100644 >> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml >> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >> @@ -41,6 +41,13 @@ properties: >> reg: >> maxItems: 1 >> >> + reg-io-width: >> + description: | >> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support >> + 32bit access for MTIMER. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + const: 4 > > But this is not a "sifive,clint" anyway. Should there be a new > dt-bindings for T-Head clint variant? I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. The vendor Debian image uses: compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0"}; We could add this diff in a future version of the patch: --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -26,6 +26,7 @@ properties: - enum: - sifive,fu540-c000-clint - canaan,k210-clint + - allwinner,sun20i-d1-clint - const: sifive,clint0 description: @@ -33,10 +34,10 @@ properties: Supported compatible strings are - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive - CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and + CLINT v0 as integrated onto the Canaan Kendryte K210 chip, "sifive,clint0" for the SiFive CLINT v0 IP block with no chip - integration tweaks. - Please refer to sifive-blocks-ip-versioning.txt for details + integration tweaks, and "allwinner,sun20i-d1-clint" for the Allwinner + D1. Please refer to sifive-blocks-ip-versioning.txt for details reg: maxItems: 1 Best regards Heinrich > >> + >> interrupts-extended: >> minItems: 1 > > Regards, > Bin > ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-15 11:54 ` Heinrich Schuchardt 0 siblings, 0 replies; 16+ messages in thread From: Heinrich Schuchardt @ 2021-10-15 11:54 UTC (permalink / raw) To: Bin Meng Cc: Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On 10/15/21 12:14, Bin Meng wrote: > On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt > <heinrich.schuchardt@canonical.com> wrote: >> >> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to >> the MTIMER device. The current schema does not allow to specify this. >> >> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >> restriction. Samuael Holland suggested in >> lib: utils/timer: Use standard property to specify 32-bit I/O >> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e >> to use "reg-io-width = <4>;" as the reg-io-width property is generally used >> in the devicetree schema for such a condition. >> >> A release candidate of the ACLINT specification is available at >> https://github.com/riscv/riscv-aclint/releases >> >> Add reg-io-width as optional property to the SiFive Core Local Interruptor. >> >> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >> --- >> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >> index a35952f48742..266012d887b5 100644 >> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml >> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >> @@ -41,6 +41,13 @@ properties: >> reg: >> maxItems: 1 >> >> + reg-io-width: >> + description: | >> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support >> + 32bit access for MTIMER. >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + const: 4 > > But this is not a "sifive,clint" anyway. Should there be a new > dt-bindings for T-Head clint variant? I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. The vendor Debian image uses: compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0"}; We could add this diff in a future version of the patch: --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -26,6 +26,7 @@ properties: - enum: - sifive,fu540-c000-clint - canaan,k210-clint + - allwinner,sun20i-d1-clint - const: sifive,clint0 description: @@ -33,10 +34,10 @@ properties: Supported compatible strings are - "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive - CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and + CLINT v0 as integrated onto the Canaan Kendryte K210 chip, "sifive,clint0" for the SiFive CLINT v0 IP block with no chip - integration tweaks. - Please refer to sifive-blocks-ip-versioning.txt for details + integration tweaks, and "allwinner,sun20i-d1-clint" for the Allwinner + D1. Please refer to sifive-blocks-ip-versioning.txt for details reg: maxItems: 1 Best regards Heinrich > >> + >> interrupts-extended: >> minItems: 1 > > Regards, > Bin > _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT 2021-10-15 11:54 ` Heinrich Schuchardt @ 2021-10-15 12:15 ` Jessica Clarke -1 siblings, 0 replies; 16+ messages in thread From: Jessica Clarke @ 2021-10-15 12:15 UTC (permalink / raw) To: Heinrich Schuchardt Cc: Bin Meng, Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On 15 Oct 2021, at 12:54, Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > On 10/15/21 12:14, Bin Meng wrote: >> On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt >> <heinrich.schuchardt@canonical.com> wrote: >>> >>> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to >>> the MTIMER device. The current schema does not allow to specify this. >>> >>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >>> restriction. Samuael Holland suggested in >>> lib: utils/timer: Use standard property to specify 32-bit I/O >>> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e >>> to use "reg-io-width = <4>;" as the reg-io-width property is generally used >>> in the devicetree schema for such a condition. >>> >>> A release candidate of the ACLINT specification is available at >>> https://github.com/riscv/riscv-aclint/releases >>> >>> Add reg-io-width as optional property to the SiFive Core Local Interruptor. >>> >>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >>> --- >>> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ >>> 1 file changed, 7 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> index a35952f48742..266012d887b5 100644 >>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> @@ -41,6 +41,13 @@ properties: >>> reg: >>> maxItems: 1 >>> >>> + reg-io-width: >>> + description: | >>> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support >>> + 32bit access for MTIMER. >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + const: 4 >> But this is not a "sifive,clint" anyway. Should there be a new >> dt-bindings for T-Head clint variant? > > I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. > > The vendor Debian image uses: > compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0”}; I assume Bin means to stop calling it a sifive,clint0 and instead have something like "allwinner,sun20i-d1-clint", "thead,clint0" as is being done for their non-conforming PLIC. It’s worth pointing out that the same is true here; the SiFive CLINT supports 64-bit accesses on RV64, so this is not compatible with a SiFive CLINT. Moreover, the RISC-V spec was clearly written in a way that intended 64-bit accesses to be supported for RV64, though was not completely explicit about that, which has now been resolved (see https://github.com/riscv/riscv-isa-manual/issues/639), so this CLINT violates the obvious intent of the pre-1.12 privileged specs (see Andrew’s message in the issue, which agrees with my reading). Jess ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-15 12:15 ` Jessica Clarke 0 siblings, 0 replies; 16+ messages in thread From: Jessica Clarke @ 2021-10-15 12:15 UTC (permalink / raw) To: Heinrich Schuchardt Cc: Bin Meng, Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On 15 Oct 2021, at 12:54, Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > On 10/15/21 12:14, Bin Meng wrote: >> On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt >> <heinrich.schuchardt@canonical.com> wrote: >>> >>> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to >>> the MTIMER device. The current schema does not allow to specify this. >>> >>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >>> restriction. Samuael Holland suggested in >>> lib: utils/timer: Use standard property to specify 32-bit I/O >>> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e >>> to use "reg-io-width = <4>;" as the reg-io-width property is generally used >>> in the devicetree schema for such a condition. >>> >>> A release candidate of the ACLINT specification is available at >>> https://github.com/riscv/riscv-aclint/releases >>> >>> Add reg-io-width as optional property to the SiFive Core Local Interruptor. >>> >>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >>> --- >>> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ >>> 1 file changed, 7 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> index a35952f48742..266012d887b5 100644 >>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>> @@ -41,6 +41,13 @@ properties: >>> reg: >>> maxItems: 1 >>> >>> + reg-io-width: >>> + description: | >>> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support >>> + 32bit access for MTIMER. >>> + $ref: /schemas/types.yaml#/definitions/uint32 >>> + const: 4 >> But this is not a "sifive,clint" anyway. Should there be a new >> dt-bindings for T-Head clint variant? > > I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. > > The vendor Debian image uses: > compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0”}; I assume Bin means to stop calling it a sifive,clint0 and instead have something like "allwinner,sun20i-d1-clint", "thead,clint0" as is being done for their non-conforming PLIC. It’s worth pointing out that the same is true here; the SiFive CLINT supports 64-bit accesses on RV64, so this is not compatible with a SiFive CLINT. Moreover, the RISC-V spec was clearly written in a way that intended 64-bit accesses to be supported for RV64, though was not completely explicit about that, which has now been resolved (see https://github.com/riscv/riscv-isa-manual/issues/639), so this CLINT violates the obvious intent of the pre-1.12 privileged specs (see Andrew’s message in the issue, which agrees with my reading). Jess _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT 2021-10-15 12:15 ` Jessica Clarke @ 2021-10-15 12:42 ` Heinrich Schuchardt -1 siblings, 0 replies; 16+ messages in thread From: Heinrich Schuchardt @ 2021-10-15 12:42 UTC (permalink / raw) To: Jessica Clarke Cc: Bin Meng, Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On 10/15/21 14:15, Jessica Clarke wrote: > On 15 Oct 2021, at 12:54, Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: >> >> On 10/15/21 12:14, Bin Meng wrote: >>> On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt >>> <heinrich.schuchardt@canonical.com> wrote: >>>> >>>> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to >>>> the MTIMER device. The current schema does not allow to specify this. >>>> >>>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >>>> restriction. Samuael Holland suggested in >>>> lib: utils/timer: Use standard property to specify 32-bit I/O >>>> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e >>>> to use "reg-io-width = <4>;" as the reg-io-width property is generally used >>>> in the devicetree schema for such a condition. >>>> >>>> A release candidate of the ACLINT specification is available at >>>> https://github.com/riscv/riscv-aclint/releases >>>> >>>> Add reg-io-width as optional property to the SiFive Core Local Interruptor. >>>> >>>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >>>> --- >>>> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ >>>> 1 file changed, 7 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>>> index a35952f48742..266012d887b5 100644 >>>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>>> @@ -41,6 +41,13 @@ properties: >>>> reg: >>>> maxItems: 1 >>>> >>>> + reg-io-width: >>>> + description: | >>>> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support >>>> + 32bit access for MTIMER. >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + const: 4 >>> But this is not a "sifive,clint" anyway. Should there be a new >>> dt-bindings for T-Head clint variant? >> >> I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. >> >> The vendor Debian image uses: >> compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0”}; > > I assume Bin means to stop calling it a sifive,clint0 and instead have > something like > > "allwinner,sun20i-d1-clint", "thead,clint0" > > as is being done for their non-conforming PLIC. It’s worth pointing out > that the same is true here; the SiFive CLINT supports 64-bit accesses > on RV64, so this is not compatible with a SiFive CLINT. Moreover, the > RISC-V spec was clearly written in a way that intended 64-bit accesses > to be supported for RV64, though was not completely explicit about > that, which has now been resolved (see > https://github.com/riscv/riscv-isa-manual/issues/639), so this CLINT > violates the obvious intent of the pre-1.12 privileged specs (see > Andrew’s message in the issue, which agrees with my reading). > > Jess > This comment is referring to the discussion in https://lore.kernel.org/lkml/693a609c-4278-84ab-8a9b-448936bb13d0@sholland.org/ ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-15 12:42 ` Heinrich Schuchardt 0 siblings, 0 replies; 16+ messages in thread From: Heinrich Schuchardt @ 2021-10-15 12:42 UTC (permalink / raw) To: Jessica Clarke Cc: Bin Meng, Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On 10/15/21 14:15, Jessica Clarke wrote: > On 15 Oct 2021, at 12:54, Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: >> >> On 10/15/21 12:14, Bin Meng wrote: >>> On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt >>> <heinrich.schuchardt@canonical.com> wrote: >>>> >>>> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to >>>> the MTIMER device. The current schema does not allow to specify this. >>>> >>>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the >>>> restriction. Samuael Holland suggested in >>>> lib: utils/timer: Use standard property to specify 32-bit I/O >>>> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e >>>> to use "reg-io-width = <4>;" as the reg-io-width property is generally used >>>> in the devicetree schema for such a condition. >>>> >>>> A release candidate of the ACLINT specification is available at >>>> https://github.com/riscv/riscv-aclint/releases >>>> >>>> Add reg-io-width as optional property to the SiFive Core Local Interruptor. >>>> >>>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> >>>> --- >>>> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ >>>> 1 file changed, 7 insertions(+) >>>> >>>> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>>> index a35952f48742..266012d887b5 100644 >>>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml >>>> @@ -41,6 +41,13 @@ properties: >>>> reg: >>>> maxItems: 1 >>>> >>>> + reg-io-width: >>>> + description: | >>>> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support >>>> + 32bit access for MTIMER. >>>> + $ref: /schemas/types.yaml#/definitions/uint32 >>>> + const: 4 >>> But this is not a "sifive,clint" anyway. Should there be a new >>> dt-bindings for T-Head clint variant? >> >> I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. >> >> The vendor Debian image uses: >> compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0”}; > > I assume Bin means to stop calling it a sifive,clint0 and instead have > something like > > "allwinner,sun20i-d1-clint", "thead,clint0" > > as is being done for their non-conforming PLIC. It’s worth pointing out > that the same is true here; the SiFive CLINT supports 64-bit accesses > on RV64, so this is not compatible with a SiFive CLINT. Moreover, the > RISC-V spec was clearly written in a way that intended 64-bit accesses > to be supported for RV64, though was not completely explicit about > that, which has now been resolved (see > https://github.com/riscv/riscv-isa-manual/issues/639), so this CLINT > violates the obvious intent of the pre-1.12 privileged specs (see > Andrew’s message in the issue, which agrees with my reading). > > Jess > This comment is referring to the discussion in https://lore.kernel.org/lkml/693a609c-4278-84ab-8a9b-448936bb13d0@sholland.org/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT 2021-10-15 12:15 ` Jessica Clarke @ 2021-10-15 13:46 ` Bin Meng -1 siblings, 0 replies; 16+ messages in thread From: Bin Meng @ 2021-10-15 13:46 UTC (permalink / raw) To: Jessica Clarke Cc: Heinrich Schuchardt, Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On Fri, Oct 15, 2021 at 8:15 PM Jessica Clarke <jrtc27@jrtc27.com> wrote: > > On 15 Oct 2021, at 12:54, Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > > > On 10/15/21 12:14, Bin Meng wrote: > >> On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt > >> <heinrich.schuchardt@canonical.com> wrote: > >>> > >>> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > >>> the MTIMER device. The current schema does not allow to specify this. > >>> > >>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > >>> restriction. Samuael Holland suggested in > >>> lib: utils/timer: Use standard property to specify 32-bit I/O > >>> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > >>> to use "reg-io-width = <4>;" as the reg-io-width property is generally used > >>> in the devicetree schema for such a condition. > >>> > >>> A release candidate of the ACLINT specification is available at > >>> https://github.com/riscv/riscv-aclint/releases > >>> > >>> Add reg-io-width as optional property to the SiFive Core Local Interruptor. > >>> > >>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > >>> --- > >>> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ > >>> 1 file changed, 7 insertions(+) > >>> > >>> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > >>> index a35952f48742..266012d887b5 100644 > >>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > >>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > >>> @@ -41,6 +41,13 @@ properties: > >>> reg: > >>> maxItems: 1 > >>> > >>> + reg-io-width: > >>> + description: | > >>> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support > >>> + 32bit access for MTIMER. > >>> + $ref: /schemas/types.yaml#/definitions/uint32 > >>> + const: 4 > >> But this is not a "sifive,clint" anyway. Should there be a new > >> dt-bindings for T-Head clint variant? > > > > I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. > > > > The vendor Debian image uses: > > compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0”}; > > I assume Bin means to stop calling it a sifive,clint0 and instead have > something like > > "allwinner,sun20i-d1-clint", "thead,clint0" Yep, that's what I wanted to see. Sorry for not being clear. The T-Head CLINT is definitely not compatible with "sifive,clint0". > as is being done for their non-conforming PLIC. It’s worth pointing out > that the same is true here; the SiFive CLINT supports 64-bit accesses > on RV64, so this is not compatible with a SiFive CLINT. Moreover, the > RISC-V spec was clearly written in a way that intended 64-bit accesses > to be supported for RV64, though was not completely explicit about > that, which has now been resolved (see > https://github.com/riscv/riscv-isa-manual/issues/639), so this CLINT > violates the obvious intent of the pre-1.12 privileged specs (see > Andrew’s message in the issue, which agrees with my reading). Regards, Bin ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-15 13:46 ` Bin Meng 0 siblings, 0 replies; 16+ messages in thread From: Bin Meng @ 2021-10-15 13:46 UTC (permalink / raw) To: Jessica Clarke Cc: Heinrich Schuchardt, Daniel Lezcano, Thomas Gleixner, Guo Ren, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, OpenSBI On Fri, Oct 15, 2021 at 8:15 PM Jessica Clarke <jrtc27@jrtc27.com> wrote: > > On 15 Oct 2021, at 12:54, Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > > > On 10/15/21 12:14, Bin Meng wrote: > >> On Fri, Oct 15, 2021 at 6:09 PM Heinrich Schuchardt > >> <heinrich.schuchardt@canonical.com> wrote: > >>> > >>> The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > >>> the MTIMER device. The current schema does not allow to specify this. > >>> > >>> OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > >>> restriction. Samuael Holland suggested in > >>> lib: utils/timer: Use standard property to specify 32-bit I/O > >>> https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > >>> to use "reg-io-width = <4>;" as the reg-io-width property is generally used > >>> in the devicetree schema for such a condition. > >>> > >>> A release candidate of the ACLINT specification is available at > >>> https://github.com/riscv/riscv-aclint/releases > >>> > >>> Add reg-io-width as optional property to the SiFive Core Local Interruptor. > >>> > >>> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > >>> --- > >>> Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ > >>> 1 file changed, 7 insertions(+) > >>> > >>> diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > >>> index a35952f48742..266012d887b5 100644 > >>> --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > >>> +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > >>> @@ -41,6 +41,13 @@ properties: > >>> reg: > >>> maxItems: 1 > >>> > >>> + reg-io-width: > >>> + description: | > >>> + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support > >>> + 32bit access for MTIMER. > >>> + $ref: /schemas/types.yaml#/definitions/uint32 > >>> + const: 4 > >> But this is not a "sifive,clint" anyway. Should there be a new > >> dt-bindings for T-Head clint variant? > > > > I assume by new dt-bindings variant you mean: Add a new compatible string in Documentation/devicetree/bindings/timer/sifive,clint.yaml. > > > > The vendor Debian image uses: > > compatible = "{allwinner,sun20i-d1-clint", "sifive,clint0”}; > > I assume Bin means to stop calling it a sifive,clint0 and instead have > something like > > "allwinner,sun20i-d1-clint", "thead,clint0" Yep, that's what I wanted to see. Sorry for not being clear. The T-Head CLINT is definitely not compatible with "sifive,clint0". > as is being done for their non-conforming PLIC. It’s worth pointing out > that the same is true here; the SiFive CLINT supports 64-bit accesses > on RV64, so this is not compatible with a SiFive CLINT. Moreover, the > RISC-V spec was clearly written in a way that intended 64-bit accesses > to be supported for RV64, though was not completely explicit about > that, which has now been resolved (see > https://github.com/riscv/riscv-isa-manual/issues/639), so this CLINT > violates the obvious intent of the pre-1.12 privileged specs (see > Andrew’s message in the issue, which agrees with my reading). Regards, Bin _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT 2021-10-15 10:09 ` Heinrich Schuchardt @ 2021-10-17 7:54 ` Xiang W -1 siblings, 0 replies; 16+ messages in thread From: Xiang W @ 2021-10-17 7:54 UTC (permalink / raw) To: Heinrich Schuchardt, Daniel Lezcano, Thomas Gleixner Cc: Guo Ren, Bin Meng, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, opensbi 在 2021-10-15星期五的 12:09 +0200，Heinrich Schuchardt写道： > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio > access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to > indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is > generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local > Interruptor. > > Signed-off-by: Heinrich Schuchardt > <heinrich.schuchardt@canonical.com> > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 > +++++++ > 1 file changed, 7 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..266012d887b5 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -41,6 +41,13 @@ properties: > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only > support > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 > + > interrupts-extended: > minItems: 1 > I think we can move has_64bit_mmio to fdt_match->data.This way we no longer rely on 'clint, has-no-64bit-mmio' or 'reg-io-width' Regards, Xiang W _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-17 7:54 ` Xiang W 0 siblings, 0 replies; 16+ messages in thread From: Xiang W @ 2021-10-17 7:54 UTC (permalink / raw) To: Heinrich Schuchardt, Daniel Lezcano, Thomas Gleixner Cc: Guo Ren, Bin Meng, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, linux-kernel, devicetree, linux-riscv, opensbi 在 2021-10-15星期五的 12:09 +0200，Heinrich Schuchardt写道： > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio > access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to > indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is > generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local > Interruptor. > > Signed-off-by: Heinrich Schuchardt > <heinrich.schuchardt@canonical.com> > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 > +++++++ > 1 file changed, 7 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..266012d887b5 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -41,6 +41,13 @@ properties: > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only > support > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 > + > interrupts-extended: > minItems: 1 > I think we can move has_64bit_mmio to fdt_match->data.This way we no longer rely on 'clint, has-no-64bit-mmio' or 'reg-io-width' Regards, Xiang W ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT 2021-10-15 10:09 ` Heinrich Schuchardt @ 2021-10-19 6:10 ` Guo Ren -1 siblings, 0 replies; 16+ messages in thread From: Guo Ren @ 2021-10-19 6:10 UTC (permalink / raw) To: Heinrich Schuchardt Cc: Daniel Lezcano, Thomas Gleixner, Guo Ren, Bin Meng, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, Linux Kernel Mailing List, devicetree, linux-riscv, OpenSBI On Fri, Oct 15, 2021 at 6:10 PM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local Interruptor. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..266012d887b5 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -41,6 +41,13 @@ properties: > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support ^^^^^^^^^^^ -> allwinner d1, new version of our processors would support 64bit access > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 > + > interrupts-extended: > minItems: 1 > > -- > 2.32.0 > > > -- > opensbi mailing list > opensbi@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/opensbi -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT @ 2021-10-19 6:10 ` Guo Ren 0 siblings, 0 replies; 16+ messages in thread From: Guo Ren @ 2021-10-19 6:10 UTC (permalink / raw) To: Heinrich Schuchardt Cc: Daniel Lezcano, Thomas Gleixner, Guo Ren, Bin Meng, Xiang W, Samuel Holland, Atish Patra, Rob Herring, Palmer Dabbelt, Paul Walmsley, Anup Patel, Linux Kernel Mailing List, devicetree, linux-riscv, OpenSBI On Fri, Oct 15, 2021 at 6:10 PM Heinrich Schuchardt <heinrich.schuchardt@canonical.com> wrote: > > The CLINT in the T-HEAD 9xx processors do not support 64bit mmio access to > the MTIMER device. The current schema does not allow to specify this. > > OpenSBI currently uses a property 'clint,has-no-64bit-mmio' to indicate the > restriction. Samuael Holland suggested in > lib: utils/timer: Use standard property to specify 32-bit I/O > https://github.com/smaeul/opensbi/commit/b95e9cf7cf93b0af16fc89204378bc59ff30008e > to use "reg-io-width = <4>;" as the reg-io-width property is generally used > in the devicetree schema for such a condition. > > A release candidate of the ACLINT specification is available at > https://github.com/riscv/riscv-aclint/releases > > Add reg-io-width as optional property to the SiFive Core Local Interruptor. > > Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> > --- > Documentation/devicetree/bindings/timer/sifive,clint.yaml | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > index a35952f48742..266012d887b5 100644 > --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml > +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml > @@ -41,6 +41,13 @@ properties: > reg: > maxItems: 1 > > + reg-io-width: > + description: | > + Some CLINT implementations, e.g. on the T-HEAD 9xx, only support ^^^^^^^^^^^ -> allwinner d1, new version of our processors would support 64bit access > + 32bit access for MTIMER. > + $ref: /schemas/types.yaml#/definitions/uint32 > + const: 4 > + > interrupts-extended: > minItems: 1 > > -- > 2.32.0 > > > -- > opensbi mailing list > opensbi@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/opensbi -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2021-10-19 6:10 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-10-15 10:09 [PATCH 1/1] dt-bindings: reg-io-width for SiFive CLINT Heinrich Schuchardt 2021-10-15 10:09 ` Heinrich Schuchardt 2021-10-15 10:14 ` Bin Meng 2021-10-15 10:14 ` Bin Meng 2021-10-15 11:54 ` Heinrich Schuchardt 2021-10-15 11:54 ` Heinrich Schuchardt 2021-10-15 12:15 ` Jessica Clarke 2021-10-15 12:15 ` Jessica Clarke 2021-10-15 12:42 ` Heinrich Schuchardt 2021-10-15 12:42 ` Heinrich Schuchardt 2021-10-15 13:46 ` Bin Meng 2021-10-15 13:46 ` Bin Meng 2021-10-17 7:54 ` Xiang W 2021-10-17 7:54 ` Xiang W 2021-10-19 6:10 ` Guo Ren 2021-10-19 6:10 ` Guo Ren
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