Re: [XEN v3 08/12] xen/Arm: GICv3: Define ICH_AP0R<n> and ICH_AP1R<n> for AArch32

[Michal Orzel <michal.orzel@amd.com>]

Hi Ayan,

On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> Adapt save_aprn_regs()/restore_aprn_regs() for AArch32.
> 
> For which we have defined the following registers:-
> 1. Interrupt Controller Hyp Active Priorities Group0 Registers 0-3
> 2. Interrupt Controller Hyp Active Priorities Group1 Registers 0-3
> 
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
> ---
> 
> Changes from :-
> v1 - 1. Moved coproc register definition to asm/cpregs.h.
> 
> v2 - 1. Defined register alias.
> 2. Style issues.
> 3. Dropped R-b and Ack.
> 
>  xen/arch/arm/include/asm/cpregs.h | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 
> diff --git a/xen/arch/arm/include/asm/cpregs.h b/xen/arch/arm/include/asm/cpregs.h
> index 242dabaea8..5331ec3448 100644
> --- a/xen/arch/arm/include/asm/cpregs.h
> +++ b/xen/arch/arm/include/asm/cpregs.h
> @@ -259,6 +259,26 @@
>  #define VBAR            p15,0,c12,c0,0  /* Vector Base Address Register */
>  #define HVBAR           p15,4,c12,c0,0  /* Hyp. Vector Base Address Register */
>  
> +/*
> + * CP15 CR12: Interrupt Controller Hyp Active Priorities Group 0 Registers,
> + * n = 0 - 3
> + */
> +#define __AP0Rx(x)      ___CP32(p15, 4, c12, c8, x)
You are using a macro ___CP32 here but it is defined somewhere down the file.
So I think you need to make a change so that the definition appears before use.

> +#define ICH_AP0R0       __AP0Rx(0)
> +#define ICH_AP0R1       __AP0Rx(1)
> +#define ICH_AP0R2       __AP0Rx(2)
> +#define ICH_AP0R3       __AP0Rx(3)
> +
> +/*
> + * CP15 CR12: Interrupt Controller Hyp Active Priorities Group 1 Registers,
> + * n = 0 - 3
> + */
> +#define __AP1Rx(x)      ___CP32(p15, 4, c12, c9, x)
> +#define ICH_AP1R0       __AP1Rx(0)
> +#define ICH_AP1R1       __AP1Rx(1)
> +#define ICH_AP1R2       __AP1Rx(2)
> +#define ICH_AP1R3       __AP1Rx(3)
> +
>  /* CP15 CR12: Interrupt Controller List Registers, n = 0 - 15 */
>  #define ___CP32(coproc, opc1, crn, crm, opc2) coproc, opc1, crn, crm, opc2
>  #define __LR0(x)                  ___CP32(p15, 4, c12, c12, x)
> @@ -360,6 +380,14 @@
>  #define HCR_EL2                 HCR
>  #define HPFAR_EL2               HPFAR
>  #define HSTR_EL2                HSTR
> +#define ICH_AP0R0_EL2           ICH_AP0R0
> +#define ICH_AP0R1_EL2           ICH_AP0R1
> +#define ICH_AP0R2_EL2           ICH_AP0R2
> +#define ICH_AP0R3_EL2           ICH_AP0R3
> +#define ICH_AP1R0_EL2           ICH_AP1R0
> +#define ICH_AP1R1_EL2           ICH_AP1R1
> +#define ICH_AP1R2_EL2           ICH_AP1R2
> +#define ICH_AP1R3_EL2           ICH_AP1R3
>  #define ICH_LR0_EL2             ICH_LR0
>  #define ICH_LR1_EL2             ICH_LR1
>  #define ICH_LR2_EL2             ICH_LR2

~Michal