All of lore.kernel.org
 help / color / mirror / Atom feed
From: Michal Orzel <michal.orzel@amd.com>
To: Ayan Kumar Halder <ayan.kumar.halder@amd.com>,
	<xen-devel@lists.xenproject.org>
Cc: <sstabellini@kernel.org>, <stefanos@xilinx.com>, <julien@xen.org>,
	<Volodymyr_Babchuk@epam.com>, <bertrand.marquis@arm.com>,
	<jgrall@amazon.com>, <burzalodowa@gmail.com>
Subject: Re: [XEN v3 12/12] xen/Arm: GICv3: Enable GICv3 for AArch32
Date: Wed, 23 Nov 2022 10:51:20 +0100	[thread overview]
Message-ID: <e2345a5b-451c-15f9-46b0-270aeddd5d5f@amd.com> (raw)
In-Reply-To: <20221111141739.2872-13-ayan.kumar.halder@amd.com>

Hi Ayan,

On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> One can now use GICv3 on AArch32 systems. However, ITS is not supported.
> The reason being currently we are trying to validate GICv3 on an AArch32_v8R
> system. Refer ARM DDI 0568A.c ID110520, B1.3.1,
> "A Generic Interrupt Controller (GIC) implemented with an Armv8-R PE must not
> implement LPI support."
> 
> By default GICv3 is disabled on AArch32 and enabled on AArch64.
> 
> Updated SUPPORT.md to state that GICv3 on Arm32 is not security supported.
> 
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>

with one remark...

> ---
> 
> Changed from :-
> v1 - 1. Remove "ARM_64 || ARM_32" as it is always true.
> 2. Updated SUPPORT.md.
> 
> v2 - 1. GICv3 is enabled by default only on ARM_64.
> 2. Updated SUPPORT.md.
> 
>  SUPPORT.md                            | 7 +++++++
>  xen/arch/arm/Kconfig                  | 9 +++++----
>  xen/arch/arm/include/asm/cpufeature.h | 1 +
>  3 files changed, 13 insertions(+), 4 deletions(-)
> 
> diff --git a/SUPPORT.md b/SUPPORT.md
> index ab71464cf6..3f16d83191 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -82,6 +82,13 @@ Extension to the GICv3 interrupt controller to support MSI.
>  
>      Status: Experimental
>  
> +### ARM/GICv3
... For me this section should go before the section ARM/GICv3 ITS.
The reason being ITS is an extension and your section being generic
should be listed before listing extension.

~Michal


  reply	other threads:[~2022-11-23  9:51 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-11 14:17 [XEN v3 00/12] Arm: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 01/12] xen/Arm: vGICv3: Sysreg emulation is applicable for AArch64 only Ayan Kumar Halder
2022-11-17 13:05   ` Michal Orzel
2022-11-22 20:30     ` Julien Grall
2022-11-11 14:17 ` [XEN v3 02/12] xen/Arm: GICv3: Adapt access to VMPIDR register for AArch32 Ayan Kumar Halder
2022-11-17 13:39   ` Michal Orzel
2022-11-22 20:31     ` Julien Grall
2022-11-23  9:35       ` Michal Orzel
2022-11-24 18:50         ` Julien Grall
2022-11-27 13:32     ` Ayan Kumar Halder
2022-11-28  9:21       ` Julien Grall
2022-11-11 14:17 ` [XEN v3 03/12] xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32 Ayan Kumar Halder
2022-11-17 13:11   ` Michal Orzel
2022-11-22 20:34     ` Julien Grall
2022-11-11 14:17 ` [XEN v3 04/12] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32 Ayan Kumar Halder
2022-11-17 13:45   ` Michal Orzel
2022-11-22 20:37   ` Julien Grall
2022-11-28  9:56     ` Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 05/12] xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 06/12] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 07/12] xen/Arm: GICv3: Define ICH_LR<n>_EL2 " Ayan Kumar Halder
2022-11-18 10:13   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 08/12] xen/Arm: GICv3: Define ICH_AP0R<n> and ICH_AP1R<n> for AArch32 Ayan Kumar Halder
2022-11-18 12:26   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 09/12] xen/Arm: GICv3: Define remaining GIC registers " Ayan Kumar Halder
2022-11-18 12:43   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 10/12] xen/Arm: GICv3: Use ULL instead of UL for 64bits Ayan Kumar Halder
2022-11-18 12:58   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 11/12] xen/Arm: GICv3: Define macros to read/write 64 bit Ayan Kumar Halder
2022-11-11 16:17   ` Xenia Ragiadakou
2022-11-11 17:37     ` Ayan Kumar Halder
2022-11-11 17:53       ` Julien Grall
2022-11-28 12:32         ` Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 12/12] xen/Arm: GICv3: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-11-23  9:51   ` Michal Orzel [this message]
2022-11-25  8:42   ` Julien Grall

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=e2345a5b-451c-15f9-46b0-270aeddd5d5f@amd.com \
    --to=michal.orzel@amd.com \
    --cc=Volodymyr_Babchuk@epam.com \
    --cc=ayan.kumar.halder@amd.com \
    --cc=bertrand.marquis@arm.com \
    --cc=burzalodowa@gmail.com \
    --cc=jgrall@amazon.com \
    --cc=julien@xen.org \
    --cc=sstabellini@kernel.org \
    --cc=stefanos@xilinx.com \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.