Re: [XEN v3 02/12] xen/Arm: GICv3: Adapt access to VMPIDR register for AArch32

[Julien Grall <julien@xen.org>]

On 27/11/2022 14:32, Ayan Kumar Halder wrote:
> 
> On 17/11/2022 13:39, Michal Orzel wrote:
>> Hi Ayan,
> Hi Michal,
>>
>> On 11/11/2022 15:17, Ayan Kumar Halder wrote:
>>> Refer ARM DDI 0487I.a ID081822, G8-9817, G8.2.169
>>> Affinity level 3 is not present in AArch32.
>>> Also, refer ARM DDI 0406C.d ID040418, B4-1644, B4.1.106,
>>> Affinity level 3 is not present in Armv7 (ie arm32).
>>> Thus, any access to affinity level 3 needs to be guarded within
>>> "ifdef CONFIG_ARM_64".
>>>
>>> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
>> Reviewed-by: Michal Orzel <michal.orzel@amd.com>
>>
>> although, IMO the commit msg does not reflect the change (i.e. you do 
>> nothing
>> related to accessing MPIDR, but instead you are just not taking the 
>> Aff3 into account for AArch32).
>> Also, I'm not sure why you used VMPIDR and not MPIDR.
> 
> Actually MPIDR in EL2 is known as VMPIDR. So I used this name.

Quoting the Arm Arm: The VMPIDR, holds the value of the Virtualization 
Multiprocessor ID. This is the value returned by Non-secure EL1 reads of 
MPIDR.

The code you are touching is looking a the pCPU information. Therefore, 
the correct name of the register is MPIDR.

Cheers,

-- 
Julien Grall