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From: Michal Orzel <michal.orzel@amd.com>
To: Ayan Kumar Halder <ayan.kumar.halder@amd.com>,
	<xen-devel@lists.xenproject.org>
Cc: <sstabellini@kernel.org>, <stefanos@xilinx.com>, <julien@xen.org>,
	<Volodymyr_Babchuk@epam.com>, <bertrand.marquis@arm.com>,
	<jgrall@amazon.com>, <burzalodowa@gmail.com>
Subject: Re: [XEN v3 03/12] xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32
Date: Thu, 17 Nov 2022 14:11:30 +0100	[thread overview]
Message-ID: <a2a471dc-f757-940b-c0bb-2eba696e5a70@amd.com> (raw)
In-Reply-To: <20221111141739.2872-4-ayan.kumar.halder@amd.com>

Hi Ayan,

On 11/11/2022 15:17, Ayan Kumar Halder wrote:
> In some situations (e.g. GICR_TYPER), the hypervior may need to emulate
> 64bit registers in AArch32 mode. In such situations, the hypervisor may
> need to read/modify the lower or upper 32 bits of the 64 bit register.
> 
> In AArch32, 'unsigned long' is 32 bits. Thus, we cannot use it for 64 bit
> registers.
> 
> While we could replace 'unsigned long' by 'uint64_t', it is not entirely clear
> whether a 32-bit compiler would not allocate register for the upper 32-bit.
> Therefore fold vreg_reg_* helper in the size specific one and use the
> appropriate type based on the size requested.
> 
> Signed-off-by: Ayan Kumar Halder <ayan.kumar.halder@amd.com>
Reviewed-by: Michal Orzel <michal.orzel@amd.com>

~Michal


  reply	other threads:[~2022-11-17 13:12 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-11 14:17 [XEN v3 00/12] Arm: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 01/12] xen/Arm: vGICv3: Sysreg emulation is applicable for AArch64 only Ayan Kumar Halder
2022-11-17 13:05   ` Michal Orzel
2022-11-22 20:30     ` Julien Grall
2022-11-11 14:17 ` [XEN v3 02/12] xen/Arm: GICv3: Adapt access to VMPIDR register for AArch32 Ayan Kumar Halder
2022-11-17 13:39   ` Michal Orzel
2022-11-22 20:31     ` Julien Grall
2022-11-23  9:35       ` Michal Orzel
2022-11-24 18:50         ` Julien Grall
2022-11-27 13:32     ` Ayan Kumar Halder
2022-11-28  9:21       ` Julien Grall
2022-11-11 14:17 ` [XEN v3 03/12] xen/Arm: vreg: Support vreg_reg64_* helpers on AArch32 Ayan Kumar Halder
2022-11-17 13:11   ` Michal Orzel [this message]
2022-11-22 20:34     ` Julien Grall
2022-11-11 14:17 ` [XEN v3 04/12] xen/Arm: vGICv3: Adapt emulation of GICR_TYPER for AArch32 Ayan Kumar Halder
2022-11-17 13:45   ` Michal Orzel
2022-11-22 20:37   ` Julien Grall
2022-11-28  9:56     ` Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 05/12] xen/Arm: GICv3: Fix GICR_{PENDBASER, PROPBASER} emulation on 32-bit host Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 06/12] xen/Arm: vGICv3: Fix emulation of ICC_SGI1R on AArch32 Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 07/12] xen/Arm: GICv3: Define ICH_LR<n>_EL2 " Ayan Kumar Halder
2022-11-18 10:13   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 08/12] xen/Arm: GICv3: Define ICH_AP0R<n> and ICH_AP1R<n> for AArch32 Ayan Kumar Halder
2022-11-18 12:26   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 09/12] xen/Arm: GICv3: Define remaining GIC registers " Ayan Kumar Halder
2022-11-18 12:43   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 10/12] xen/Arm: GICv3: Use ULL instead of UL for 64bits Ayan Kumar Halder
2022-11-18 12:58   ` Michal Orzel
2022-11-11 14:17 ` [XEN v3 11/12] xen/Arm: GICv3: Define macros to read/write 64 bit Ayan Kumar Halder
2022-11-11 16:17   ` Xenia Ragiadakou
2022-11-11 17:37     ` Ayan Kumar Halder
2022-11-11 17:53       ` Julien Grall
2022-11-28 12:32         ` Ayan Kumar Halder
2022-11-11 14:17 ` [XEN v3 12/12] xen/Arm: GICv3: Enable GICv3 for AArch32 Ayan Kumar Halder
2022-11-23  9:51   ` Michal Orzel
2022-11-25  8:42   ` Julien Grall

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