From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <jbeulich@suse.com>,
"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Cc: Wei Liu <wl@xen.org>, Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH v8 03/12] x86emul: support ENQCMD insns
Date: Thu, 7 May 2020 19:59:33 +0100 [thread overview]
Message-ID: <4fdaeefb-9593-789d-9f73-510e89d6df43@citrix.com> (raw)
In-Reply-To: <099d03d0-2846-2a3d-93ec-2d10dab12655@suse.com>
On 05/05/2020 09:13, Jan Beulich wrote:
> Note that the ISA extensions document revision 038 doesn't specify
> exception behavior for ModRM.mod == 0b11; assuming #UD here.
Stale.
> --- a/xen/arch/x86/x86_emulate/x86_emulate.c
> +++ b/xen/arch/x86/x86_emulate/x86_emulate.c
> @@ -11480,11 +11513,36 @@ int x86_emul_blk(
> {
> switch ( state->blk )
> {
> + bool zf;
> +
> /*
> * Throughout this switch(), memory clobbers are used to compensate
> * that other operands may not properly express the (full) memory
> * ranges covered.
> */
> + case blk_enqcmd:
> + ASSERT(bytes == 64);
> + if ( ((unsigned long)ptr & 0x3f) )
> + {
> + ASSERT_UNREACHABLE();
> + return X86EMUL_UNHANDLEABLE;
> + }
> + *eflags &= ~EFLAGS_MASK;
> +#ifdef HAVE_AS_ENQCMD
> + asm ( "enqcmds (%[src]), %[dst]" ASM_FLAG_OUT(, "; setz %0")
%[zf]
> + : [zf] ASM_FLAG_OUT("=@ccz", "=qm") (zf)
> + : [src] "r" (data), [dst] "r" (ptr) : "memory" );
Can't src get away with being "m" (*data)? There is no need to force it
into a single register, even if it is overwhelmingly likely to end up
with %rsi scheduled here.
> +#else
> + /* enqcmds (%rsi), %rdi */
> + asm ( ".byte 0xf3, 0x0f, 0x38, 0xf8, 0x3e"
> + ASM_FLAG_OUT(, "; setz %[zf]")
> + : [zf] ASM_FLAG_OUT("=@ccz", "=qm") (zf)
> + : "S" (data), "D" (ptr) : "memory" );
> +#endif
> + if ( zf )
> + *eflags |= X86_EFLAGS_ZF;
> + break;
> +
> case blk_movdir:
> switch ( bytes )
> {
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -420,6 +420,10 @@
> #define MSR_IA32_TSC_DEADLINE 0x000006E0
> #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0
>
> +#define MSR_IA32_PASID 0x00000d93
> +#define PASID_PASID_MASK 0x000fffff
> +#define PASID_VALID 0x80000000
> +
Above the legacy line please as this is using the newer style, and drop
_IA32. Intel's ideal of architectural-ness isn't interesting or worth
the added code volume.
PASSID_PASSID_MASK isn't great, but I can't suggest anything better, and
MSR_PASSID_MAS doesn't work either.
Otherwise, Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
next prev parent reply other threads:[~2020-05-07 19:00 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 8:10 [PATCH v8 00/12] x86emul: further work Jan Beulich
2020-05-05 8:12 ` [PATCH v8 01/12] x86emul: disable FPU/MMX/SIMD insn emulation when !HVM Jan Beulich
2020-05-07 18:11 ` Andrew Cooper
2020-05-08 8:10 ` Jan Beulich
2020-05-05 8:13 ` [PATCH v8 02/12] x86emul: support MOVDIR{I,64B} insns Jan Beulich
2020-05-07 18:30 ` Andrew Cooper
2020-05-08 7:19 ` Jan Beulich
2020-05-05 8:13 ` [PATCH v8 03/12] x86emul: support ENQCMD insns Jan Beulich
2020-05-07 18:59 ` Andrew Cooper [this message]
2020-05-08 7:32 ` Jan Beulich
2020-05-05 8:14 ` [PATCH v8 04/12] x86emul: support SERIALIZE Jan Beulich
2020-05-07 19:32 ` Andrew Cooper
2020-05-08 7:34 ` Jan Beulich
2020-05-08 13:00 ` Andrew Cooper
2020-05-08 13:59 ` Jan Beulich
2020-05-08 15:05 ` Andrew Cooper
2020-05-05 8:14 ` [PATCH v8 05/12] x86emul: support X{SUS,RES}LDTRK Jan Beulich
2020-05-07 20:13 ` Andrew Cooper
2020-05-08 7:38 ` Jan Beulich
2020-05-08 13:15 ` Andrew Cooper
2020-05-08 14:42 ` Jan Beulich
2020-05-05 8:15 ` [PATCH v8 06/12] x86/HVM: make hvmemul_blk() capable of handling r/o operations Jan Beulich
2020-05-05 14:20 ` Paul Durrant
2020-05-07 20:34 ` Andrew Cooper
2020-05-08 7:13 ` Jan Beulich
2020-05-05 8:15 ` [PATCH v8 07/12] x86emul: support FNSTENV and FNSAVE Jan Beulich
2020-05-05 12:36 ` Jan Beulich
2020-05-08 17:58 ` Andrew Cooper
2020-05-13 12:07 ` Jan Beulich
2020-05-05 8:16 ` [PATCH v8 08/12] x86emul: support FLDENV and FRSTOR Jan Beulich
2020-05-08 13:37 ` Roger Pau Monné
2020-05-08 15:04 ` Jan Beulich
2020-05-08 16:21 ` Roger Pau Monné
2020-05-11 7:29 ` Jan Beulich
2020-05-11 9:22 ` Roger Pau Monné
2020-05-08 18:29 ` Andrew Cooper
2020-05-11 7:25 ` Jan Beulich
2020-05-11 8:02 ` Roger Pau Monné
2020-05-08 18:19 ` Andrew Cooper
2020-05-05 8:16 ` [PATCH v8 09/12] x86emul: support FXSAVE/FXRSTOR Jan Beulich
2020-05-08 19:31 ` Andrew Cooper
2020-05-13 13:24 ` Jan Beulich
2020-05-05 8:17 ` [PATCH v8 09/12] x86/HVM: scale MPERF values reported to guests (on AMD) Jan Beulich
2020-05-05 8:19 ` Jan Beulich
2020-05-05 8:18 ` [PATCH v8 10/12] " Jan Beulich
2020-05-08 20:32 ` Andrew Cooper
2020-05-05 8:19 ` [PATCH v8 11/12] x86emul: support RDPRU Jan Beulich
2020-05-05 8:20 ` [PATCH v8 12/12] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads Jan Beulich
2020-05-08 21:04 ` Andrew Cooper
2020-05-13 13:35 ` Jan Beulich
2020-05-14 8:52 ` Jan Beulich
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