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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Wei Liu <wl@xen.org>, Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH v8 05/12] x86emul: support X{SUS,RES}LDTRK
Date: Fri, 8 May 2020 14:15:08 +0100	[thread overview]
Message-ID: <9fa8ceb3-fd4b-e754-2c82-92f134603e34@citrix.com> (raw)
In-Reply-To: <b5f9438b-471d-bf32-3f4c-11287060938c@suse.com>

On 08/05/2020 08:38, Jan Beulich wrote:
> [CAUTION - EXTERNAL EMAIL] DO NOT reply, click links, or open attachments unless you have verified the sender and know the content is safe.
>
> On 07.05.2020 22:13, Andrew Cooper wrote:
>> On 05/05/2020 09:14, Jan Beulich wrote:
>>> --- a/xen/tools/gen-cpuid.py
>>> +++ b/xen/tools/gen-cpuid.py
>>> @@ -284,6 +284,9 @@ def crunch_numbers(state):
>>>          # as dependent features simplifies Xen's logic, and prevents the guest
>>>          # from seeing implausible configurations.
>>>          IBRSB: [STIBP, SSBD],
>>> +
>>> +        # In principle the TSXLDTRK insns could also be considered independent.
>>> +        RTM: [TSXLDTRK],
>> Why the link?  There is no relevant interaction AFAICT.
> Do the insns make any sense without TSX? Anyway - hence the
> comment, and if you're convinced the connection does not
> need making, I'd be okay dropping it. I would assume though
> that we'd better hide TSXLDTRK whenever we hide RTM, which
> is most easily achieved by having a connection here.

Actually - that is a very good point.  I expect there will (or should)
be an interaction with MSR_TSX_CTRL, as it has CPUID-hiding functionality.

For now, could I ask you to not expose this to guests in this patch?

For the emulator side of things alone I think this is ok (although
looking over it a second time, we could really do with a comment in the
code explaining that we're never in an RTM region, hence the nop behaviour).

I'll follow up with Intel, and we can figure out the CPUID derivation
details at a later point.

If you're happy with this plan, then A-by to save a round trip.

~Andrew


  reply	other threads:[~2020-05-08 13:15 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-05  8:10 [PATCH v8 00/12] x86emul: further work Jan Beulich
2020-05-05  8:12 ` [PATCH v8 01/12] x86emul: disable FPU/MMX/SIMD insn emulation when !HVM Jan Beulich
2020-05-07 18:11   ` Andrew Cooper
2020-05-08  8:10     ` Jan Beulich
2020-05-05  8:13 ` [PATCH v8 02/12] x86emul: support MOVDIR{I,64B} insns Jan Beulich
2020-05-07 18:30   ` Andrew Cooper
2020-05-08  7:19     ` Jan Beulich
2020-05-05  8:13 ` [PATCH v8 03/12] x86emul: support ENQCMD insns Jan Beulich
2020-05-07 18:59   ` Andrew Cooper
2020-05-08  7:32     ` Jan Beulich
2020-05-05  8:14 ` [PATCH v8 04/12] x86emul: support SERIALIZE Jan Beulich
2020-05-07 19:32   ` Andrew Cooper
2020-05-08  7:34     ` Jan Beulich
2020-05-08 13:00       ` Andrew Cooper
2020-05-08 13:59         ` Jan Beulich
2020-05-08 15:05           ` Andrew Cooper
2020-05-05  8:14 ` [PATCH v8 05/12] x86emul: support X{SUS,RES}LDTRK Jan Beulich
2020-05-07 20:13   ` Andrew Cooper
2020-05-08  7:38     ` Jan Beulich
2020-05-08 13:15       ` Andrew Cooper [this message]
2020-05-08 14:42         ` Jan Beulich
2020-05-05  8:15 ` [PATCH v8 06/12] x86/HVM: make hvmemul_blk() capable of handling r/o operations Jan Beulich
2020-05-05 14:20   ` Paul Durrant
2020-05-07 20:34   ` Andrew Cooper
2020-05-08  7:13     ` Jan Beulich
2020-05-05  8:15 ` [PATCH v8 07/12] x86emul: support FNSTENV and FNSAVE Jan Beulich
2020-05-05 12:36   ` Jan Beulich
2020-05-08 17:58   ` Andrew Cooper
2020-05-13 12:07     ` Jan Beulich
2020-05-05  8:16 ` [PATCH v8 08/12] x86emul: support FLDENV and FRSTOR Jan Beulich
2020-05-08 13:37   ` Roger Pau Monné
2020-05-08 15:04     ` Jan Beulich
2020-05-08 16:21       ` Roger Pau Monné
2020-05-11  7:29         ` Jan Beulich
2020-05-11  9:22           ` Roger Pau Monné
2020-05-08 18:29       ` Andrew Cooper
2020-05-11  7:25         ` Jan Beulich
2020-05-11  8:02           ` Roger Pau Monné
2020-05-08 18:19   ` Andrew Cooper
2020-05-05  8:16 ` [PATCH v8 09/12] x86emul: support FXSAVE/FXRSTOR Jan Beulich
2020-05-08 19:31   ` Andrew Cooper
2020-05-13 13:24     ` Jan Beulich
2020-05-05  8:17 ` [PATCH v8 09/12] x86/HVM: scale MPERF values reported to guests (on AMD) Jan Beulich
2020-05-05  8:19   ` Jan Beulich
2020-05-05  8:18 ` [PATCH v8 10/12] " Jan Beulich
2020-05-08 20:32   ` Andrew Cooper
2020-05-05  8:19 ` [PATCH v8 11/12] x86emul: support RDPRU Jan Beulich
2020-05-05  8:20 ` [PATCH v8 12/12] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads Jan Beulich
2020-05-08 21:04   ` Andrew Cooper
2020-05-13 13:35     ` Jan Beulich
2020-05-14  8:52       ` Jan Beulich

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