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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Wei Liu <wl@xen.org>, Roger Pau Monne <roger.pau@citrix.com>
Subject: Re: [PATCH v8 04/12] x86emul: support SERIALIZE
Date: Fri, 8 May 2020 14:00:24 +0100	[thread overview]
Message-ID: <fe12bd3d-37f6-111c-e738-dde0b42d2d3d@citrix.com> (raw)
In-Reply-To: <0c5a03c6-6c4f-c6ec-e474-71a2badd1c9c@suse.com>

On 08/05/2020 08:34, Jan Beulich wrote:
>>> @@ -5660,6 +5661,18 @@ x86_emulate(
>>>                  goto done;
>>>              break;
>>>  
>>> +        case 0xe8:
>>> +            switch ( vex.pfx )
>>> +            {
>>> +            case vex_none: /* serialize */
>>> +                host_and_vcpu_must_have(serialize);
>>> +                asm volatile ( ".byte 0x0f, 0x01, 0xe8" );
>> There is very little need for an actual implementation here.  The VMExit
>> to get here is good enough.
>>
>> The only question is whether pre-unrestricted_guest Intel boxes are
>> liable to find this in real mode code.
> Apart from this we also shouldn't assume HVM in the core emulator,
> I think.

It's not assuming HVM.  Its just that there is no way we can end up
emulating this instruction from PV context.

If we could end up here in PV context, the exception causing us to
emulate to begin with would be good enough as well.

~Andrew


  reply	other threads:[~2020-05-08 13:00 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-05  8:10 [PATCH v8 00/12] x86emul: further work Jan Beulich
2020-05-05  8:12 ` [PATCH v8 01/12] x86emul: disable FPU/MMX/SIMD insn emulation when !HVM Jan Beulich
2020-05-07 18:11   ` Andrew Cooper
2020-05-08  8:10     ` Jan Beulich
2020-05-05  8:13 ` [PATCH v8 02/12] x86emul: support MOVDIR{I,64B} insns Jan Beulich
2020-05-07 18:30   ` Andrew Cooper
2020-05-08  7:19     ` Jan Beulich
2020-05-05  8:13 ` [PATCH v8 03/12] x86emul: support ENQCMD insns Jan Beulich
2020-05-07 18:59   ` Andrew Cooper
2020-05-08  7:32     ` Jan Beulich
2020-05-05  8:14 ` [PATCH v8 04/12] x86emul: support SERIALIZE Jan Beulich
2020-05-07 19:32   ` Andrew Cooper
2020-05-08  7:34     ` Jan Beulich
2020-05-08 13:00       ` Andrew Cooper [this message]
2020-05-08 13:59         ` Jan Beulich
2020-05-08 15:05           ` Andrew Cooper
2020-05-05  8:14 ` [PATCH v8 05/12] x86emul: support X{SUS,RES}LDTRK Jan Beulich
2020-05-07 20:13   ` Andrew Cooper
2020-05-08  7:38     ` Jan Beulich
2020-05-08 13:15       ` Andrew Cooper
2020-05-08 14:42         ` Jan Beulich
2020-05-05  8:15 ` [PATCH v8 06/12] x86/HVM: make hvmemul_blk() capable of handling r/o operations Jan Beulich
2020-05-05 14:20   ` Paul Durrant
2020-05-07 20:34   ` Andrew Cooper
2020-05-08  7:13     ` Jan Beulich
2020-05-05  8:15 ` [PATCH v8 07/12] x86emul: support FNSTENV and FNSAVE Jan Beulich
2020-05-05 12:36   ` Jan Beulich
2020-05-08 17:58   ` Andrew Cooper
2020-05-13 12:07     ` Jan Beulich
2020-05-05  8:16 ` [PATCH v8 08/12] x86emul: support FLDENV and FRSTOR Jan Beulich
2020-05-08 13:37   ` Roger Pau Monné
2020-05-08 15:04     ` Jan Beulich
2020-05-08 16:21       ` Roger Pau Monné
2020-05-11  7:29         ` Jan Beulich
2020-05-11  9:22           ` Roger Pau Monné
2020-05-08 18:29       ` Andrew Cooper
2020-05-11  7:25         ` Jan Beulich
2020-05-11  8:02           ` Roger Pau Monné
2020-05-08 18:19   ` Andrew Cooper
2020-05-05  8:16 ` [PATCH v8 09/12] x86emul: support FXSAVE/FXRSTOR Jan Beulich
2020-05-08 19:31   ` Andrew Cooper
2020-05-13 13:24     ` Jan Beulich
2020-05-05  8:17 ` [PATCH v8 09/12] x86/HVM: scale MPERF values reported to guests (on AMD) Jan Beulich
2020-05-05  8:19   ` Jan Beulich
2020-05-05  8:18 ` [PATCH v8 10/12] " Jan Beulich
2020-05-08 20:32   ` Andrew Cooper
2020-05-05  8:19 ` [PATCH v8 11/12] x86emul: support RDPRU Jan Beulich
2020-05-05  8:20 ` [PATCH v8 12/12] x86/HVM: don't needlessly intercept APERF/MPERF/TSC MSR reads Jan Beulich
2020-05-08 21:04   ` Andrew Cooper
2020-05-13 13:35     ` Jan Beulich
2020-05-14  8:52       ` Jan Beulich

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