* [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup
@ 2012-10-28 15:03 Blue Swirl
2012-10-28 15:03 ` [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env Blue Swirl
` (5 more replies)
0 siblings, 6 replies; 19+ messages in thread
From: Blue Swirl @ 2012-10-28 15:03 UTC (permalink / raw)
To: qemu-devel; +Cc: blauwirbel
In some cases it's pretty easy to avoid using global
cpu_single_env since a local version is available.
Blue Swirl (5):
disas: avoid using cpu_single_env
kvm: avoid using cpu_single_env
target-unicore32: avoid using cpu_single_env
target-xtensa: avoid using cpu_single_env
target-i386: avoid using cpu_single_env
disas.c | 149 ++++++++-------
disas.h | 3 +-
qemu-log.h | 6 +-
target-alpha/translate.c | 2 +-
target-arm/translate.c | 2 +-
target-cris/translate.c | 2 +-
target-i386/kvm.c | 21 +-
target-i386/translate.c | 442 +++++++++++++++++++++--------------------
target-lm32/translate.c | 2 +-
target-m68k/translate.c | 2 +-
target-microblaze/translate.c | 2 +-
target-mips/translate.c | 2 +-
target-openrisc/translate.c | 2 +-
target-ppc/translate.c | 2 +-
target-s390x/translate.c | 2 +-
target-sh4/translate.c | 2 +-
target-sparc/translate.c | 2 +-
target-unicore32/softmmu.c | 8 +-
target-unicore32/translate.c | 2 +-
target-xtensa/translate.c | 10 +-
20 files changed, 342 insertions(+), 323 deletions(-)
--
1.7.2.5
^ permalink raw reply [flat|nested] 19+ messages in thread* [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env 2012-10-28 15:03 [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Blue Swirl @ 2012-10-28 15:03 ` Blue Swirl 2012-10-29 4:45 ` Richard Henderson ` (3 more replies) 2012-10-28 15:03 ` [Qemu-devel] " Blue Swirl ` (4 subsequent siblings) 5 siblings, 4 replies; 19+ messages in thread From: Blue Swirl @ 2012-10-28 15:03 UTC (permalink / raw) To: qemu-devel Cc: Peter Maydell, Alexander Graf, blauwirbel, Michael Walle, qemu-ppc, Paul Brook, Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno, Richard Henderson Pass around CPUState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> --- disas.c | 149 ++++++++++++++++++++++------------------- disas.h | 3 +- qemu-log.h | 6 +- target-alpha/translate.c | 2 +- target-arm/translate.c | 2 +- target-cris/translate.c | 2 +- target-i386/translate.c | 2 +- target-lm32/translate.c | 2 +- target-m68k/translate.c | 2 +- target-microblaze/translate.c | 2 +- target-mips/translate.c | 2 +- target-openrisc/translate.c | 2 +- target-ppc/translate.c | 2 +- target-s390x/translate.c | 2 +- target-sh4/translate.c | 2 +- target-sparc/translate.c | 2 +- target-unicore32/translate.c | 2 +- 17 files changed, 100 insertions(+), 86 deletions(-) diff --git a/disas.c b/disas.c index b801c8f..6da1dd0 100644 --- a/disas.c +++ b/disas.c @@ -7,6 +7,11 @@ #include "cpu.h" #include "disas.h" +typedef struct CPUDebug { + struct disassemble_info info; + CPUArchState *env; +} CPUDebug; + /* Filled in by elfload.c. Simplistic, but will do for now. */ struct syminfo *syminfos = NULL; @@ -32,7 +37,9 @@ target_read_memory (bfd_vma memaddr, int length, struct disassemble_info *info) { - cpu_memory_rw_debug(cpu_single_env, memaddr, myaddr, length, 0); + CPUDebug *s = container_of(info, CPUDebug, info); + + cpu_memory_rw_debug(s->env, memaddr, myaddr, length, 0); return 0; } @@ -158,32 +165,35 @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info) ppc - nonzero means little endian other targets - unused */ -void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) +void target_disas(FILE *out, CPUArchState *env, target_ulong code, + target_ulong size, int flags) { target_ulong pc; int count; - struct disassemble_info disasm_info; + CPUDebug s; int (*print_insn)(bfd_vma pc, disassemble_info *info); - INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); + INIT_DISASSEMBLE_INFO(s.info, out, fprintf); - disasm_info.read_memory_func = target_read_memory; - disasm_info.buffer_vma = code; - disasm_info.buffer_length = size; - disasm_info.print_address_func = generic_print_target_address; + s.env = env; + s.info.read_memory_func = target_read_memory; + s.info.buffer_vma = code; + s.info.buffer_length = size; + s.info.print_address_func = generic_print_target_address; #ifdef TARGET_WORDS_BIGENDIAN - disasm_info.endian = BFD_ENDIAN_BIG; + s.info.endian = BFD_ENDIAN_BIG; #else - disasm_info.endian = BFD_ENDIAN_LITTLE; + s.info.endian = BFD_ENDIAN_LITTLE; #endif #if defined(TARGET_I386) - if (flags == 2) - disasm_info.mach = bfd_mach_x86_64; - else if (flags == 1) - disasm_info.mach = bfd_mach_i386_i8086; - else - disasm_info.mach = bfd_mach_i386_i386; + if (flags == 2) { + s.info.mach = bfd_mach_x86_64; + } else if (flags == 1) { + s.info.mach = bfd_mach_i386_i8086; + } else { + s.info.mach = bfd_mach_i386_i386; + } print_insn = print_insn_i386; #elif defined(TARGET_ARM) if (flags & 1) { @@ -193,27 +203,28 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) } if (flags & 2) { #ifdef TARGET_WORDS_BIGENDIAN - disasm_info.endian = BFD_ENDIAN_LITTLE; + s.info.endian = BFD_ENDIAN_LITTLE; #else - disasm_info.endian = BFD_ENDIAN_BIG; + s.info.endian = BFD_ENDIAN_BIG; #endif } #elif defined(TARGET_SPARC) print_insn = print_insn_sparc; #ifdef TARGET_SPARC64 - disasm_info.mach = bfd_mach_sparc_v9b; + s.info.mach = bfd_mach_sparc_v9b; #endif #elif defined(TARGET_PPC) - if (flags >> 16) - disasm_info.endian = BFD_ENDIAN_LITTLE; + if (flags >> 16) { + s.info.endian = BFD_ENDIAN_LITTLE; + } if (flags & 0xFFFF) { /* If we have a precise definitions of the instructions set, use it */ - disasm_info.mach = flags & 0xFFFF; + s.info.mach = flags & 0xFFFF; } else { #ifdef TARGET_PPC64 - disasm_info.mach = bfd_mach_ppc64; + s.info.mach = bfd_mach_ppc64; #else - disasm_info.mach = bfd_mach_ppc; + s.info.mach = bfd_mach_ppc; #endif } print_insn = print_insn_ppc; @@ -226,27 +237,27 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) print_insn = print_insn_little_mips; #endif #elif defined(TARGET_SH4) - disasm_info.mach = bfd_mach_sh4; + s.info.mach = bfd_mach_sh4; print_insn = print_insn_sh; #elif defined(TARGET_ALPHA) - disasm_info.mach = bfd_mach_alpha_ev6; + s.info.mach = bfd_mach_alpha_ev6; print_insn = print_insn_alpha; #elif defined(TARGET_CRIS) if (flags != 32) { - disasm_info.mach = bfd_mach_cris_v0_v10; + s.info.mach = bfd_mach_cris_v0_v10; print_insn = print_insn_crisv10; } else { - disasm_info.mach = bfd_mach_cris_v32; + s.info.mach = bfd_mach_cris_v32; print_insn = print_insn_crisv32; } #elif defined(TARGET_S390X) - disasm_info.mach = bfd_mach_s390_64; + s.info.mach = bfd_mach_s390_64; print_insn = print_insn_s390; #elif defined(TARGET_MICROBLAZE) - disasm_info.mach = bfd_arch_microblaze; + s.info.mach = bfd_arch_microblaze; print_insn = print_insn_microblaze; #elif defined(TARGET_LM32) - disasm_info.mach = bfd_mach_lm32; + s.info.mach = bfd_mach_lm32; print_insn = print_insn_lm32; #else fprintf(out, "0x" TARGET_FMT_lx @@ -256,14 +267,14 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) for (pc = code; size > 0; pc += count, size -= count) { fprintf(out, "0x" TARGET_FMT_lx ": ", pc); - count = print_insn(pc, &disasm_info); + count = print_insn(pc, &s.info); #if 0 { int i; uint8_t b; fprintf(out, " {"); for(i = 0; i < count; i++) { - target_read_memory(pc + i, &b, 1, &disasm_info); + target_read_memory(pc + i, &b, 1, &s.info); fprintf(out, " %02x", b); } fprintf(out, " }"); @@ -287,28 +298,28 @@ void disas(FILE *out, void *code, unsigned long size) { uintptr_t pc; int count; - struct disassemble_info disasm_info; + CPUDebug s; int (*print_insn)(bfd_vma pc, disassemble_info *info); - INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); - disasm_info.print_address_func = generic_print_host_address; + INIT_DISASSEMBLE_INFO(s.info, out, fprintf); + s.info.print_address_func = generic_print_host_address; - disasm_info.buffer = code; - disasm_info.buffer_vma = (uintptr_t)code; - disasm_info.buffer_length = size; + s.info.buffer = code; + s.info.buffer_vma = (uintptr_t)code; + s.info.buffer_length = size; #ifdef HOST_WORDS_BIGENDIAN - disasm_info.endian = BFD_ENDIAN_BIG; + s.info.endian = BFD_ENDIAN_BIG; #else - disasm_info.endian = BFD_ENDIAN_LITTLE; + s.info.endian = BFD_ENDIAN_LITTLE; #endif #if defined(CONFIG_TCG_INTERPRETER) print_insn = print_insn_tci; #elif defined(__i386__) - disasm_info.mach = bfd_mach_i386_i386; + s.info.mach = bfd_mach_i386_i386; print_insn = print_insn_i386; #elif defined(__x86_64__) - disasm_info.mach = bfd_mach_x86_64; + s.info.mach = bfd_mach_x86_64; print_insn = print_insn_i386; #elif defined(_ARCH_PPC) print_insn = print_insn_ppc; @@ -316,7 +327,7 @@ void disas(FILE *out, void *code, unsigned long size) print_insn = print_insn_alpha; #elif defined(__sparc__) print_insn = print_insn_sparc; - disasm_info.mach = bfd_mach_sparc_v9b; + s.info.mach = bfd_mach_sparc_v9b; #elif defined(__arm__) print_insn = print_insn_arm; #elif defined(__MIPSEB__) @@ -338,7 +349,7 @@ void disas(FILE *out, void *code, unsigned long size) #endif for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) { fprintf(out, "0x%08" PRIxPTR ": ", pc); - count = print_insn(pc, &disasm_info); + count = print_insn(pc, &s.info); fprintf(out, "\n"); if (count < 0) break; @@ -366,16 +377,17 @@ const char *lookup_symbol(target_ulong orig_addr) #include "monitor.h" static int monitor_disas_is_physical; -static CPUArchState *monitor_disas_env; static int monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length, struct disassemble_info *info) { + CPUDebug *s = container_of(info, CPUDebug, info); + if (monitor_disas_is_physical) { cpu_physical_memory_read(memaddr, myaddr, length); } else { - cpu_memory_rw_debug(monitor_disas_env, memaddr,myaddr, length, 0); + cpu_memory_rw_debug(s->env, memaddr,myaddr, length, 0); } return 0; } @@ -394,30 +406,31 @@ void monitor_disas(Monitor *mon, CPUArchState *env, target_ulong pc, int nb_insn, int is_physical, int flags) { int count, i; - struct disassemble_info disasm_info; + CPUDebug s; int (*print_insn)(bfd_vma pc, disassemble_info *info); - INIT_DISASSEMBLE_INFO(disasm_info, (FILE *)mon, monitor_fprintf); + INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf); - monitor_disas_env = env; + s.env = env; monitor_disas_is_physical = is_physical; - disasm_info.read_memory_func = monitor_read_memory; - disasm_info.print_address_func = generic_print_target_address; + s.info.read_memory_func = monitor_read_memory; + s.info.print_address_func = generic_print_target_address; - disasm_info.buffer_vma = pc; + s.info.buffer_vma = pc; #ifdef TARGET_WORDS_BIGENDIAN - disasm_info.endian = BFD_ENDIAN_BIG; + s.info.endian = BFD_ENDIAN_BIG; #else - disasm_info.endian = BFD_ENDIAN_LITTLE; + s.info.endian = BFD_ENDIAN_LITTLE; #endif #if defined(TARGET_I386) - if (flags == 2) - disasm_info.mach = bfd_mach_x86_64; - else if (flags == 1) - disasm_info.mach = bfd_mach_i386_i8086; - else - disasm_info.mach = bfd_mach_i386_i386; + if (flags == 2) { + s.info.mach = bfd_mach_x86_64; + } else if (flags == 1) { + s.info.mach = bfd_mach_i386_i8086; + } else { + s.info.mach = bfd_mach_i386_i386; + } print_insn = print_insn_i386; #elif defined(TARGET_ARM) print_insn = print_insn_arm; @@ -426,13 +439,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env, #elif defined(TARGET_SPARC) print_insn = print_insn_sparc; #ifdef TARGET_SPARC64 - disasm_info.mach = bfd_mach_sparc_v9b; + s.info.mach = bfd_mach_sparc_v9b; #endif #elif defined(TARGET_PPC) #ifdef TARGET_PPC64 - disasm_info.mach = bfd_mach_ppc64; + s.info.mach = bfd_mach_ppc64; #else - disasm_info.mach = bfd_mach_ppc; + s.info.mach = bfd_mach_ppc; #endif print_insn = print_insn_ppc; #elif defined(TARGET_M68K) @@ -444,13 +457,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env, print_insn = print_insn_little_mips; #endif #elif defined(TARGET_SH4) - disasm_info.mach = bfd_mach_sh4; + s.info.mach = bfd_mach_sh4; print_insn = print_insn_sh; #elif defined(TARGET_S390X) - disasm_info.mach = bfd_mach_s390_64; + s.info.mach = bfd_mach_s390_64; print_insn = print_insn_s390; #elif defined(TARGET_LM32) - disasm_info.mach = bfd_mach_lm32; + s.info.mach = bfd_mach_lm32; print_insn = print_insn_lm32; #else monitor_printf(mon, "0x" TARGET_FMT_lx @@ -460,7 +473,7 @@ void monitor_disas(Monitor *mon, CPUArchState *env, for(i = 0; i < nb_insn; i++) { monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc); - count = print_insn(pc, &disasm_info); + count = print_insn(pc, &s.info); monitor_printf(mon, "\n"); if (count < 0) break; diff --git a/disas.h b/disas.h index a8a0974..c13ca9a 100644 --- a/disas.h +++ b/disas.h @@ -6,7 +6,8 @@ #ifdef NEED_CPU_H /* Disassemble this for me please... (debugging). */ void disas(FILE *out, void *code, unsigned long size); -void target_disas(FILE *out, target_ulong code, target_ulong size, int flags); +void target_disas(FILE *out, CPUArchState *env, target_ulong code, + target_ulong size, int flags); void monitor_disas(Monitor *mon, CPUArchState *env, target_ulong pc, int nb_insn, int is_physical, int flags); diff --git a/qemu-log.h b/qemu-log.h index ce6bb09..344eca3 100644 --- a/qemu-log.h +++ b/qemu-log.h @@ -84,10 +84,10 @@ static inline void log_cpu_state_mask(int mask, CPUArchState *env1, int flags) } /* disas() and target_disas() to qemu_logfile: */ -static inline void log_target_disas(target_ulong start, target_ulong len, - int flags) +static inline void log_target_disas(CPUArchState *env, target_ulong start, + target_ulong len, int flags) { - target_disas(qemu_logfile, start, len, flags); + target_disas(qemu_logfile, env, start, len, flags); } static inline void log_disas(void *code, unsigned long size) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index f707d8d..8c4dd02 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3477,7 +3477,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, ctx.pc - pc_start, 1); + log_target_disas(env, pc_start, ctx.pc - pc_start, 1); qemu_log("\n"); } #endif diff --git a/target-arm/translate.c b/target-arm/translate.c index 25433da..7d8f8e5 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9968,7 +9968,7 @@ done_generating: if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, dc->pc - pc_start, + log_target_disas(env, pc_start, dc->pc - pc_start, dc->thumb | (dc->bswap_code << 1)); qemu_log("\n"); } diff --git a/target-cris/translate.c b/target-cris/translate.c index 755de65..f8ebc43a 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3413,7 +3413,7 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb, #ifdef DEBUG_DISAS #if !DISAS_CRIS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { - log_target_disas(pc_start, dc->pc - pc_start, + log_target_disas(env, pc_start, dc->pc - pc_start, dc->env->pregs[PR_VR]); qemu_log("\nisize=%d osize=%td\n", dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); diff --git a/target-i386/translate.c b/target-i386/translate.c index ee75850..bf52eef 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -8047,7 +8047,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, else #endif disas_flags = !dc->code32; - log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); + log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); qemu_log("\n"); } #endif diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 77c2866..3307daa 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1120,7 +1120,7 @@ static void gen_intermediate_code_internal(CPULM32State *env, #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("\n"); - log_target_disas(pc_start, dc->pc - pc_start, 0); + log_target_disas(env, pc_start, dc->pc - pc_start, 0); qemu_log("\nisize=%d osize=%td\n", dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); } diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 451ef74..1430d4c 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3070,7 +3070,7 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb, if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, dc->pc - pc_start, 0); + log_target_disas(env, pc_start, dc->pc - pc_start, 0); qemu_log("\n"); } #endif diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 7d864b1..5eaf975 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1913,7 +1913,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("\n"); #if DISAS_GNU - log_target_disas(pc_start, dc->pc - pc_start, 0); + log_target_disas(env, pc_start, dc->pc - pc_start, 0); #endif qemu_log("\nisize=%d osize=%td\n", dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); diff --git a/target-mips/translate.c b/target-mips/translate.c index 454e5cc..e00323a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12939,7 +12939,7 @@ done_generating: LOG_DISAS("\n"); if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, ctx.pc - pc_start, 0); + log_target_disas(env, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); } #endif diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index e2cad3a..ff2feb4 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1797,7 +1797,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("\n"); - log_target_disas(pc_start, dc->pc - pc_start, 0); + log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0); qemu_log("\nisize=%d osize=%td\n", dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1042268..06c58c2 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9783,7 +9783,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, flags = env->bfd_mach; flags |= ctx.le_mode << 16; qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, ctx.nip - pc_start, flags); + log_target_disas(env, pc_start, ctx.nip - pc_start, flags); qemu_log("\n"); } #endif diff --git a/target-s390x/translate.c b/target-s390x/translate.c index db464cc..c6267a8 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5220,7 +5220,7 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env, #if defined(S390X_DEBUG_DISAS) if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, dc.pc - pc_start, 1); + log_target_disas(env, pc_start, dc.pc - pc_start, 1); qemu_log("\n"); } #endif diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 9d955eb..2ae7f03 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -2070,7 +2070,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ - log_target_disas(pc_start, ctx.pc - pc_start, 0); + log_target_disas(env, pc_start, ctx.pc - pc_start, 0); qemu_log("\n"); } #endif diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 4321393..f410efc 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5353,7 +5353,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("--------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, last_pc + 4 - pc_start, 0); + log_target_disas(env, pc_start, last_pc + 4 - pc_start, 0); qemu_log("\n"); } #endif diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index c3cdafa..57b18ac 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -2109,7 +2109,7 @@ done_generating: if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); - log_target_disas(pc_start, dc->pc - pc_start, 0); + log_target_disas(env, pc_start, dc->pc - pc_start, 0); qemu_log("\n"); } #endif -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env Blue Swirl @ 2012-10-29 4:45 ` Richard Henderson 2012-10-29 9:06 ` Andreas Färber ` (2 subsequent siblings) 3 siblings, 0 replies; 19+ messages in thread From: Richard Henderson @ 2012-10-29 4:45 UTC (permalink / raw) To: Blue Swirl Cc: Peter Maydell, qemu-devel, Alexander Graf, Michael Walle, qemu-ppc, Paul Brook, Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno On 2012-10-29 02:03, Blue Swirl wrote: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > disas.c | 149 ++++++++++++++++++++++------------------- > disas.h | 3 +- > qemu-log.h | 6 +- > target-alpha/translate.c | 2 +- > target-arm/translate.c | 2 +- > target-cris/translate.c | 2 +- > target-i386/translate.c | 2 +- > target-lm32/translate.c | 2 +- > target-m68k/translate.c | 2 +- > target-microblaze/translate.c | 2 +- > target-mips/translate.c | 2 +- > target-openrisc/translate.c | 2 +- > target-ppc/translate.c | 2 +- > target-s390x/translate.c | 2 +- > target-sh4/translate.c | 2 +- > target-sparc/translate.c | 2 +- > target-unicore32/translate.c | 2 +- > 17 files changed, 100 insertions(+), 86 deletions(-) Acked-by: Richard Henderson <rth@twiddle.net> r~ ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env Blue Swirl 2012-10-29 4:45 ` Richard Henderson @ 2012-10-29 9:06 ` Andreas Färber 2012-10-29 14:36 ` Aurelien Jarno [not found] ` <92f1e4fe1bf16c76d53eef0dcf9389865a66e0dd.1351436501.git.blauwirbel@gm ail.com> 3 siblings, 0 replies; 19+ messages in thread From: Andreas Färber @ 2012-10-29 9:06 UTC (permalink / raw) To: Blue Swirl Cc: Peter Maydell, qemu-devel, Alexander Graf, Michael Walle, qemu-ppc, Paul Brook, Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno, Richard Henderson Am 28.10.2012 16:03, schrieb Blue Swirl: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> CPUState would be really nice, you seem to mean CPUArchState though as intermediate step. Please adjust the commit message, looks fine as far as reviewed otherwise. Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env Blue Swirl 2012-10-29 4:45 ` Richard Henderson 2012-10-29 9:06 ` Andreas Färber @ 2012-10-29 14:36 ` Aurelien Jarno [not found] ` <92f1e4fe1bf16c76d53eef0dcf9389865a66e0dd.1351436501.git.blauwirbel@gm ail.com> 3 siblings, 0 replies; 19+ messages in thread From: Aurelien Jarno @ 2012-10-29 14:36 UTC (permalink / raw) To: Blue Swirl Cc: Peter Maydell, qemu-devel, Alexander Graf, Michael Walle, qemu-ppc, Paul Brook, Edgar E. Iglesias, Guan Xuetao, Richard Henderson On Sun, Oct 28, 2012 at 03:03:48PM +0000, Blue Swirl wrote: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > disas.c | 149 ++++++++++++++++++++++------------------- > disas.h | 3 +- > qemu-log.h | 6 +- > target-alpha/translate.c | 2 +- > target-arm/translate.c | 2 +- > target-cris/translate.c | 2 +- > target-i386/translate.c | 2 +- > target-lm32/translate.c | 2 +- > target-m68k/translate.c | 2 +- > target-microblaze/translate.c | 2 +- > target-mips/translate.c | 2 +- > target-openrisc/translate.c | 2 +- > target-ppc/translate.c | 2 +- > target-s390x/translate.c | 2 +- > target-sh4/translate.c | 2 +- > target-sparc/translate.c | 2 +- > target-unicore32/translate.c | 2 +- > 17 files changed, 100 insertions(+), 86 deletions(-) > > diff --git a/disas.c b/disas.c > index b801c8f..6da1dd0 100644 > --- a/disas.c > +++ b/disas.c > @@ -7,6 +7,11 @@ > #include "cpu.h" > #include "disas.h" > > +typedef struct CPUDebug { > + struct disassemble_info info; > + CPUArchState *env; > +} CPUDebug; > + > /* Filled in by elfload.c. Simplistic, but will do for now. */ > struct syminfo *syminfos = NULL; > > @@ -32,7 +37,9 @@ target_read_memory (bfd_vma memaddr, > int length, > struct disassemble_info *info) > { > - cpu_memory_rw_debug(cpu_single_env, memaddr, myaddr, length, 0); > + CPUDebug *s = container_of(info, CPUDebug, info); > + > + cpu_memory_rw_debug(s->env, memaddr, myaddr, length, 0); > return 0; > } > > @@ -158,32 +165,35 @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info) > ppc - nonzero means little endian > other targets - unused > */ > -void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) > +void target_disas(FILE *out, CPUArchState *env, target_ulong code, > + target_ulong size, int flags) > { > target_ulong pc; > int count; > - struct disassemble_info disasm_info; > + CPUDebug s; > int (*print_insn)(bfd_vma pc, disassemble_info *info); > > - INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); > + INIT_DISASSEMBLE_INFO(s.info, out, fprintf); > > - disasm_info.read_memory_func = target_read_memory; > - disasm_info.buffer_vma = code; > - disasm_info.buffer_length = size; > - disasm_info.print_address_func = generic_print_target_address; > + s.env = env; > + s.info.read_memory_func = target_read_memory; > + s.info.buffer_vma = code; > + s.info.buffer_length = size; > + s.info.print_address_func = generic_print_target_address; > > #ifdef TARGET_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #else > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #endif > #if defined(TARGET_I386) > - if (flags == 2) > - disasm_info.mach = bfd_mach_x86_64; > - else if (flags == 1) > - disasm_info.mach = bfd_mach_i386_i8086; > - else > - disasm_info.mach = bfd_mach_i386_i386; > + if (flags == 2) { > + s.info.mach = bfd_mach_x86_64; > + } else if (flags == 1) { > + s.info.mach = bfd_mach_i386_i8086; > + } else { > + s.info.mach = bfd_mach_i386_i386; > + } > print_insn = print_insn_i386; > #elif defined(TARGET_ARM) > if (flags & 1) { > @@ -193,27 +203,28 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) > } > if (flags & 2) { > #ifdef TARGET_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #else > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #endif > } > #elif defined(TARGET_SPARC) > print_insn = print_insn_sparc; > #ifdef TARGET_SPARC64 > - disasm_info.mach = bfd_mach_sparc_v9b; > + s.info.mach = bfd_mach_sparc_v9b; > #endif > #elif defined(TARGET_PPC) > - if (flags >> 16) > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + if (flags >> 16) { > + s.info.endian = BFD_ENDIAN_LITTLE; > + } > if (flags & 0xFFFF) { > /* If we have a precise definitions of the instructions set, use it */ > - disasm_info.mach = flags & 0xFFFF; > + s.info.mach = flags & 0xFFFF; > } else { > #ifdef TARGET_PPC64 > - disasm_info.mach = bfd_mach_ppc64; > + s.info.mach = bfd_mach_ppc64; > #else > - disasm_info.mach = bfd_mach_ppc; > + s.info.mach = bfd_mach_ppc; > #endif > } > print_insn = print_insn_ppc; > @@ -226,27 +237,27 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) > print_insn = print_insn_little_mips; > #endif > #elif defined(TARGET_SH4) > - disasm_info.mach = bfd_mach_sh4; > + s.info.mach = bfd_mach_sh4; > print_insn = print_insn_sh; > #elif defined(TARGET_ALPHA) > - disasm_info.mach = bfd_mach_alpha_ev6; > + s.info.mach = bfd_mach_alpha_ev6; > print_insn = print_insn_alpha; > #elif defined(TARGET_CRIS) > if (flags != 32) { > - disasm_info.mach = bfd_mach_cris_v0_v10; > + s.info.mach = bfd_mach_cris_v0_v10; > print_insn = print_insn_crisv10; > } else { > - disasm_info.mach = bfd_mach_cris_v32; > + s.info.mach = bfd_mach_cris_v32; > print_insn = print_insn_crisv32; > } > #elif defined(TARGET_S390X) > - disasm_info.mach = bfd_mach_s390_64; > + s.info.mach = bfd_mach_s390_64; > print_insn = print_insn_s390; > #elif defined(TARGET_MICROBLAZE) > - disasm_info.mach = bfd_arch_microblaze; > + s.info.mach = bfd_arch_microblaze; > print_insn = print_insn_microblaze; > #elif defined(TARGET_LM32) > - disasm_info.mach = bfd_mach_lm32; > + s.info.mach = bfd_mach_lm32; > print_insn = print_insn_lm32; > #else > fprintf(out, "0x" TARGET_FMT_lx > @@ -256,14 +267,14 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags) > > for (pc = code; size > 0; pc += count, size -= count) { > fprintf(out, "0x" TARGET_FMT_lx ": ", pc); > - count = print_insn(pc, &disasm_info); > + count = print_insn(pc, &s.info); > #if 0 > { > int i; > uint8_t b; > fprintf(out, " {"); > for(i = 0; i < count; i++) { > - target_read_memory(pc + i, &b, 1, &disasm_info); > + target_read_memory(pc + i, &b, 1, &s.info); > fprintf(out, " %02x", b); > } > fprintf(out, " }"); > @@ -287,28 +298,28 @@ void disas(FILE *out, void *code, unsigned long size) > { > uintptr_t pc; > int count; > - struct disassemble_info disasm_info; > + CPUDebug s; > int (*print_insn)(bfd_vma pc, disassemble_info *info); > > - INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); > - disasm_info.print_address_func = generic_print_host_address; > + INIT_DISASSEMBLE_INFO(s.info, out, fprintf); > + s.info.print_address_func = generic_print_host_address; > > - disasm_info.buffer = code; > - disasm_info.buffer_vma = (uintptr_t)code; > - disasm_info.buffer_length = size; > + s.info.buffer = code; > + s.info.buffer_vma = (uintptr_t)code; > + s.info.buffer_length = size; > > #ifdef HOST_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #else > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #endif > #if defined(CONFIG_TCG_INTERPRETER) > print_insn = print_insn_tci; > #elif defined(__i386__) > - disasm_info.mach = bfd_mach_i386_i386; > + s.info.mach = bfd_mach_i386_i386; > print_insn = print_insn_i386; > #elif defined(__x86_64__) > - disasm_info.mach = bfd_mach_x86_64; > + s.info.mach = bfd_mach_x86_64; > print_insn = print_insn_i386; > #elif defined(_ARCH_PPC) > print_insn = print_insn_ppc; > @@ -316,7 +327,7 @@ void disas(FILE *out, void *code, unsigned long size) > print_insn = print_insn_alpha; > #elif defined(__sparc__) > print_insn = print_insn_sparc; > - disasm_info.mach = bfd_mach_sparc_v9b; > + s.info.mach = bfd_mach_sparc_v9b; > #elif defined(__arm__) > print_insn = print_insn_arm; > #elif defined(__MIPSEB__) > @@ -338,7 +349,7 @@ void disas(FILE *out, void *code, unsigned long size) > #endif > for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) { > fprintf(out, "0x%08" PRIxPTR ": ", pc); > - count = print_insn(pc, &disasm_info); > + count = print_insn(pc, &s.info); > fprintf(out, "\n"); > if (count < 0) > break; > @@ -366,16 +377,17 @@ const char *lookup_symbol(target_ulong orig_addr) > #include "monitor.h" > > static int monitor_disas_is_physical; > -static CPUArchState *monitor_disas_env; > > static int > monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length, > struct disassemble_info *info) > { > + CPUDebug *s = container_of(info, CPUDebug, info); > + > if (monitor_disas_is_physical) { > cpu_physical_memory_read(memaddr, myaddr, length); > } else { > - cpu_memory_rw_debug(monitor_disas_env, memaddr,myaddr, length, 0); > + cpu_memory_rw_debug(s->env, memaddr,myaddr, length, 0); > } > return 0; > } > @@ -394,30 +406,31 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > target_ulong pc, int nb_insn, int is_physical, int flags) > { > int count, i; > - struct disassemble_info disasm_info; > + CPUDebug s; > int (*print_insn)(bfd_vma pc, disassemble_info *info); > > - INIT_DISASSEMBLE_INFO(disasm_info, (FILE *)mon, monitor_fprintf); > + INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf); > > - monitor_disas_env = env; > + s.env = env; > monitor_disas_is_physical = is_physical; > - disasm_info.read_memory_func = monitor_read_memory; > - disasm_info.print_address_func = generic_print_target_address; > + s.info.read_memory_func = monitor_read_memory; > + s.info.print_address_func = generic_print_target_address; > > - disasm_info.buffer_vma = pc; > + s.info.buffer_vma = pc; > > #ifdef TARGET_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #else > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #endif > #if defined(TARGET_I386) > - if (flags == 2) > - disasm_info.mach = bfd_mach_x86_64; > - else if (flags == 1) > - disasm_info.mach = bfd_mach_i386_i8086; > - else > - disasm_info.mach = bfd_mach_i386_i386; > + if (flags == 2) { > + s.info.mach = bfd_mach_x86_64; > + } else if (flags == 1) { > + s.info.mach = bfd_mach_i386_i8086; > + } else { > + s.info.mach = bfd_mach_i386_i386; > + } > print_insn = print_insn_i386; > #elif defined(TARGET_ARM) > print_insn = print_insn_arm; > @@ -426,13 +439,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > #elif defined(TARGET_SPARC) > print_insn = print_insn_sparc; > #ifdef TARGET_SPARC64 > - disasm_info.mach = bfd_mach_sparc_v9b; > + s.info.mach = bfd_mach_sparc_v9b; > #endif > #elif defined(TARGET_PPC) > #ifdef TARGET_PPC64 > - disasm_info.mach = bfd_mach_ppc64; > + s.info.mach = bfd_mach_ppc64; > #else > - disasm_info.mach = bfd_mach_ppc; > + s.info.mach = bfd_mach_ppc; > #endif > print_insn = print_insn_ppc; > #elif defined(TARGET_M68K) > @@ -444,13 +457,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > print_insn = print_insn_little_mips; > #endif > #elif defined(TARGET_SH4) > - disasm_info.mach = bfd_mach_sh4; > + s.info.mach = bfd_mach_sh4; > print_insn = print_insn_sh; > #elif defined(TARGET_S390X) > - disasm_info.mach = bfd_mach_s390_64; > + s.info.mach = bfd_mach_s390_64; > print_insn = print_insn_s390; > #elif defined(TARGET_LM32) > - disasm_info.mach = bfd_mach_lm32; > + s.info.mach = bfd_mach_lm32; > print_insn = print_insn_lm32; > #else > monitor_printf(mon, "0x" TARGET_FMT_lx > @@ -460,7 +473,7 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > > for(i = 0; i < nb_insn; i++) { > monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc); > - count = print_insn(pc, &disasm_info); > + count = print_insn(pc, &s.info); > monitor_printf(mon, "\n"); > if (count < 0) > break; > diff --git a/disas.h b/disas.h > index a8a0974..c13ca9a 100644 > --- a/disas.h > +++ b/disas.h > @@ -6,7 +6,8 @@ > #ifdef NEED_CPU_H > /* Disassemble this for me please... (debugging). */ > void disas(FILE *out, void *code, unsigned long size); > -void target_disas(FILE *out, target_ulong code, target_ulong size, int flags); > +void target_disas(FILE *out, CPUArchState *env, target_ulong code, > + target_ulong size, int flags); > > void monitor_disas(Monitor *mon, CPUArchState *env, > target_ulong pc, int nb_insn, int is_physical, int flags); > diff --git a/qemu-log.h b/qemu-log.h > index ce6bb09..344eca3 100644 > --- a/qemu-log.h > +++ b/qemu-log.h > @@ -84,10 +84,10 @@ static inline void log_cpu_state_mask(int mask, CPUArchState *env1, int flags) > } > > /* disas() and target_disas() to qemu_logfile: */ > -static inline void log_target_disas(target_ulong start, target_ulong len, > - int flags) > +static inline void log_target_disas(CPUArchState *env, target_ulong start, > + target_ulong len, int flags) > { > - target_disas(qemu_logfile, start, len, flags); > + target_disas(qemu_logfile, env, start, len, flags); > } > > static inline void log_disas(void *code, unsigned long size) > diff --git a/target-alpha/translate.c b/target-alpha/translate.c > index f707d8d..8c4dd02 100644 > --- a/target-alpha/translate.c > +++ b/target-alpha/translate.c > @@ -3477,7 +3477,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, ctx.pc - pc_start, 1); > + log_target_disas(env, pc_start, ctx.pc - pc_start, 1); > qemu_log("\n"); > } > #endif > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 25433da..7d8f8e5 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -9968,7 +9968,7 @@ done_generating: > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc->pc - pc_start, > + log_target_disas(env, pc_start, dc->pc - pc_start, > dc->thumb | (dc->bswap_code << 1)); > qemu_log("\n"); > } > diff --git a/target-cris/translate.c b/target-cris/translate.c > index 755de65..f8ebc43a 100644 > --- a/target-cris/translate.c > +++ b/target-cris/translate.c > @@ -3413,7 +3413,7 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb, > #ifdef DEBUG_DISAS > #if !DISAS_CRIS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > - log_target_disas(pc_start, dc->pc - pc_start, > + log_target_disas(env, pc_start, dc->pc - pc_start, > dc->env->pregs[PR_VR]); > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > diff --git a/target-i386/translate.c b/target-i386/translate.c > index ee75850..bf52eef 100644 > --- a/target-i386/translate.c > +++ b/target-i386/translate.c > @@ -8047,7 +8047,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, > else > #endif > disas_flags = !dc->code32; > - log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); > + log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); > qemu_log("\n"); > } > #endif > diff --git a/target-lm32/translate.c b/target-lm32/translate.c > index 77c2866..3307daa 100644 > --- a/target-lm32/translate.c > +++ b/target-lm32/translate.c > @@ -1120,7 +1120,7 @@ static void gen_intermediate_code_internal(CPULM32State *env, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("\n"); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > } > diff --git a/target-m68k/translate.c b/target-m68k/translate.c > index 451ef74..1430d4c 100644 > --- a/target-m68k/translate.c > +++ b/target-m68k/translate.c > @@ -3070,7 +3070,7 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb, > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c > index 7d864b1..5eaf975 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -1913,7 +1913,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("\n"); > #if DISAS_GNU > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > #endif > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 454e5cc..e00323a 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -12939,7 +12939,7 @@ done_generating: > LOG_DISAS("\n"); > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, ctx.pc - pc_start, 0); > + log_target_disas(env, pc_start, ctx.pc - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c > index e2cad3a..ff2feb4 100644 > --- a/target-openrisc/translate.c > +++ b/target-openrisc/translate.c > @@ -1797,7 +1797,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("\n"); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0); > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > } > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 1042268..06c58c2 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -9783,7 +9783,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, > flags = env->bfd_mach; > flags |= ctx.le_mode << 16; > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, ctx.nip - pc_start, flags); > + log_target_disas(env, pc_start, ctx.nip - pc_start, flags); > qemu_log("\n"); > } > #endif > diff --git a/target-s390x/translate.c b/target-s390x/translate.c > index db464cc..c6267a8 100644 > --- a/target-s390x/translate.c > +++ b/target-s390x/translate.c > @@ -5220,7 +5220,7 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env, > #if defined(S390X_DEBUG_DISAS) > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc.pc - pc_start, 1); > + log_target_disas(env, pc_start, dc.pc - pc_start, 1); > qemu_log("\n"); > } > #endif > diff --git a/target-sh4/translate.c b/target-sh4/translate.c > index 9d955eb..2ae7f03 100644 > --- a/target-sh4/translate.c > +++ b/target-sh4/translate.c > @@ -2070,7 +2070,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ > - log_target_disas(pc_start, ctx.pc - pc_start, 0); > + log_target_disas(env, pc_start, ctx.pc - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 4321393..f410efc 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -5353,7 +5353,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("--------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, last_pc + 4 - pc_start, 0); > + log_target_disas(env, pc_start, last_pc + 4 - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c > index c3cdafa..57b18ac 100644 > --- a/target-unicore32/translate.c > +++ b/target-unicore32/translate.c > @@ -2109,7 +2109,7 @@ done_generating: > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > qemu_log("\n"); > } > #endif MIPS part: Acked-by: Aurelien Jarno <aurelien@aurel32.net> -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net ^ permalink raw reply [flat|nested] 19+ messages in thread
[parent not found: <92f1e4fe1bf16c76d53eef0dcf9389865a66e0dd.1351436501.git.blauwirbel@gm ail.com>]
* Re: [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env [not found] ` <92f1e4fe1bf16c76d53eef0dcf9389865a66e0dd.1351436501.git.blauwirbel@gm ail.com> @ 2012-10-31 4:20 ` guanxuetao 0 siblings, 0 replies; 19+ messages in thread From: guanxuetao @ 2012-10-31 4:20 UTC (permalink / raw) To: Blue Swirl Cc: Peter Maydell, qemu-devel, Alexander Graf, Michael Walle, qemu-ppc, Paul Brook, Edgar E. Iglesias, Guan Xuetao, Aurelien Jarno, Richard Henderson > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> For unicore32 part: Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> > --- > disas.c | 149 > ++++++++++++++++++++++------------------- > disas.h | 3 +- > qemu-log.h | 6 +- > target-alpha/translate.c | 2 +- > target-arm/translate.c | 2 +- > target-cris/translate.c | 2 +- > target-i386/translate.c | 2 +- > target-lm32/translate.c | 2 +- > target-m68k/translate.c | 2 +- > target-microblaze/translate.c | 2 +- > target-mips/translate.c | 2 +- > target-openrisc/translate.c | 2 +- > target-ppc/translate.c | 2 +- > target-s390x/translate.c | 2 +- > target-sh4/translate.c | 2 +- > target-sparc/translate.c | 2 +- > target-unicore32/translate.c | 2 +- > 17 files changed, 100 insertions(+), 86 deletions(-) > > diff --git a/disas.c b/disas.c > index b801c8f..6da1dd0 100644 > --- a/disas.c > +++ b/disas.c > @@ -7,6 +7,11 @@ > #include "cpu.h" > #include "disas.h" > > +typedef struct CPUDebug { > + struct disassemble_info info; > + CPUArchState *env; > +} CPUDebug; > + > /* Filled in by elfload.c. Simplistic, but will do for now. */ > struct syminfo *syminfos = NULL; > > @@ -32,7 +37,9 @@ target_read_memory (bfd_vma memaddr, > int length, > struct disassemble_info *info) > { > - cpu_memory_rw_debug(cpu_single_env, memaddr, myaddr, length, 0); > + CPUDebug *s = container_of(info, CPUDebug, info); > + > + cpu_memory_rw_debug(s->env, memaddr, myaddr, length, 0); > return 0; > } > > @@ -158,32 +165,35 @@ print_insn_thumb1(bfd_vma pc, disassemble_info > *info) > ppc - nonzero means little endian > other targets - unused > */ > -void target_disas(FILE *out, target_ulong code, target_ulong size, int > flags) > +void target_disas(FILE *out, CPUArchState *env, target_ulong code, > + target_ulong size, int flags) > { > target_ulong pc; > int count; > - struct disassemble_info disasm_info; > + CPUDebug s; > int (*print_insn)(bfd_vma pc, disassemble_info *info); > > - INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); > + INIT_DISASSEMBLE_INFO(s.info, out, fprintf); > > - disasm_info.read_memory_func = target_read_memory; > - disasm_info.buffer_vma = code; > - disasm_info.buffer_length = size; > - disasm_info.print_address_func = generic_print_target_address; > + s.env = env; > + s.info.read_memory_func = target_read_memory; > + s.info.buffer_vma = code; > + s.info.buffer_length = size; > + s.info.print_address_func = generic_print_target_address; > > #ifdef TARGET_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #else > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #endif > #if defined(TARGET_I386) > - if (flags == 2) > - disasm_info.mach = bfd_mach_x86_64; > - else if (flags == 1) > - disasm_info.mach = bfd_mach_i386_i8086; > - else > - disasm_info.mach = bfd_mach_i386_i386; > + if (flags == 2) { > + s.info.mach = bfd_mach_x86_64; > + } else if (flags == 1) { > + s.info.mach = bfd_mach_i386_i8086; > + } else { > + s.info.mach = bfd_mach_i386_i386; > + } > print_insn = print_insn_i386; > #elif defined(TARGET_ARM) > if (flags & 1) { > @@ -193,27 +203,28 @@ void target_disas(FILE *out, target_ulong code, > target_ulong size, int flags) > } > if (flags & 2) { > #ifdef TARGET_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #else > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #endif > } > #elif defined(TARGET_SPARC) > print_insn = print_insn_sparc; > #ifdef TARGET_SPARC64 > - disasm_info.mach = bfd_mach_sparc_v9b; > + s.info.mach = bfd_mach_sparc_v9b; > #endif > #elif defined(TARGET_PPC) > - if (flags >> 16) > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + if (flags >> 16) { > + s.info.endian = BFD_ENDIAN_LITTLE; > + } > if (flags & 0xFFFF) { > /* If we have a precise definitions of the instructions set, use > it */ > - disasm_info.mach = flags & 0xFFFF; > + s.info.mach = flags & 0xFFFF; > } else { > #ifdef TARGET_PPC64 > - disasm_info.mach = bfd_mach_ppc64; > + s.info.mach = bfd_mach_ppc64; > #else > - disasm_info.mach = bfd_mach_ppc; > + s.info.mach = bfd_mach_ppc; > #endif > } > print_insn = print_insn_ppc; > @@ -226,27 +237,27 @@ void target_disas(FILE *out, target_ulong code, > target_ulong size, int flags) > print_insn = print_insn_little_mips; > #endif > #elif defined(TARGET_SH4) > - disasm_info.mach = bfd_mach_sh4; > + s.info.mach = bfd_mach_sh4; > print_insn = print_insn_sh; > #elif defined(TARGET_ALPHA) > - disasm_info.mach = bfd_mach_alpha_ev6; > + s.info.mach = bfd_mach_alpha_ev6; > print_insn = print_insn_alpha; > #elif defined(TARGET_CRIS) > if (flags != 32) { > - disasm_info.mach = bfd_mach_cris_v0_v10; > + s.info.mach = bfd_mach_cris_v0_v10; > print_insn = print_insn_crisv10; > } else { > - disasm_info.mach = bfd_mach_cris_v32; > + s.info.mach = bfd_mach_cris_v32; > print_insn = print_insn_crisv32; > } > #elif defined(TARGET_S390X) > - disasm_info.mach = bfd_mach_s390_64; > + s.info.mach = bfd_mach_s390_64; > print_insn = print_insn_s390; > #elif defined(TARGET_MICROBLAZE) > - disasm_info.mach = bfd_arch_microblaze; > + s.info.mach = bfd_arch_microblaze; > print_insn = print_insn_microblaze; > #elif defined(TARGET_LM32) > - disasm_info.mach = bfd_mach_lm32; > + s.info.mach = bfd_mach_lm32; > print_insn = print_insn_lm32; > #else > fprintf(out, "0x" TARGET_FMT_lx > @@ -256,14 +267,14 @@ void target_disas(FILE *out, target_ulong code, > target_ulong size, int flags) > > for (pc = code; size > 0; pc += count, size -= count) { > fprintf(out, "0x" TARGET_FMT_lx ": ", pc); > - count = print_insn(pc, &disasm_info); > + count = print_insn(pc, &s.info); > #if 0 > { > int i; > uint8_t b; > fprintf(out, " {"); > for(i = 0; i < count; i++) { > - target_read_memory(pc + i, &b, 1, &disasm_info); > + target_read_memory(pc + i, &b, 1, &s.info); > fprintf(out, " %02x", b); > } > fprintf(out, " }"); > @@ -287,28 +298,28 @@ void disas(FILE *out, void *code, unsigned long > size) > { > uintptr_t pc; > int count; > - struct disassemble_info disasm_info; > + CPUDebug s; > int (*print_insn)(bfd_vma pc, disassemble_info *info); > > - INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf); > - disasm_info.print_address_func = generic_print_host_address; > + INIT_DISASSEMBLE_INFO(s.info, out, fprintf); > + s.info.print_address_func = generic_print_host_address; > > - disasm_info.buffer = code; > - disasm_info.buffer_vma = (uintptr_t)code; > - disasm_info.buffer_length = size; > + s.info.buffer = code; > + s.info.buffer_vma = (uintptr_t)code; > + s.info.buffer_length = size; > > #ifdef HOST_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #else > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #endif > #if defined(CONFIG_TCG_INTERPRETER) > print_insn = print_insn_tci; > #elif defined(__i386__) > - disasm_info.mach = bfd_mach_i386_i386; > + s.info.mach = bfd_mach_i386_i386; > print_insn = print_insn_i386; > #elif defined(__x86_64__) > - disasm_info.mach = bfd_mach_x86_64; > + s.info.mach = bfd_mach_x86_64; > print_insn = print_insn_i386; > #elif defined(_ARCH_PPC) > print_insn = print_insn_ppc; > @@ -316,7 +327,7 @@ void disas(FILE *out, void *code, unsigned long size) > print_insn = print_insn_alpha; > #elif defined(__sparc__) > print_insn = print_insn_sparc; > - disasm_info.mach = bfd_mach_sparc_v9b; > + s.info.mach = bfd_mach_sparc_v9b; > #elif defined(__arm__) > print_insn = print_insn_arm; > #elif defined(__MIPSEB__) > @@ -338,7 +349,7 @@ void disas(FILE *out, void *code, unsigned long size) > #endif > for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) { > fprintf(out, "0x%08" PRIxPTR ": ", pc); > - count = print_insn(pc, &disasm_info); > + count = print_insn(pc, &s.info); > fprintf(out, "\n"); > if (count < 0) > break; > @@ -366,16 +377,17 @@ const char *lookup_symbol(target_ulong orig_addr) > #include "monitor.h" > > static int monitor_disas_is_physical; > -static CPUArchState *monitor_disas_env; > > static int > monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length, > struct disassemble_info *info) > { > + CPUDebug *s = container_of(info, CPUDebug, info); > + > if (monitor_disas_is_physical) { > cpu_physical_memory_read(memaddr, myaddr, length); > } else { > - cpu_memory_rw_debug(monitor_disas_env, memaddr,myaddr, length, > 0); > + cpu_memory_rw_debug(s->env, memaddr,myaddr, length, 0); > } > return 0; > } > @@ -394,30 +406,31 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > target_ulong pc, int nb_insn, int is_physical, int > flags) > { > int count, i; > - struct disassemble_info disasm_info; > + CPUDebug s; > int (*print_insn)(bfd_vma pc, disassemble_info *info); > > - INIT_DISASSEMBLE_INFO(disasm_info, (FILE *)mon, monitor_fprintf); > + INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf); > > - monitor_disas_env = env; > + s.env = env; > monitor_disas_is_physical = is_physical; > - disasm_info.read_memory_func = monitor_read_memory; > - disasm_info.print_address_func = generic_print_target_address; > + s.info.read_memory_func = monitor_read_memory; > + s.info.print_address_func = generic_print_target_address; > > - disasm_info.buffer_vma = pc; > + s.info.buffer_vma = pc; > > #ifdef TARGET_WORDS_BIGENDIAN > - disasm_info.endian = BFD_ENDIAN_BIG; > + s.info.endian = BFD_ENDIAN_BIG; > #else > - disasm_info.endian = BFD_ENDIAN_LITTLE; > + s.info.endian = BFD_ENDIAN_LITTLE; > #endif > #if defined(TARGET_I386) > - if (flags == 2) > - disasm_info.mach = bfd_mach_x86_64; > - else if (flags == 1) > - disasm_info.mach = bfd_mach_i386_i8086; > - else > - disasm_info.mach = bfd_mach_i386_i386; > + if (flags == 2) { > + s.info.mach = bfd_mach_x86_64; > + } else if (flags == 1) { > + s.info.mach = bfd_mach_i386_i8086; > + } else { > + s.info.mach = bfd_mach_i386_i386; > + } > print_insn = print_insn_i386; > #elif defined(TARGET_ARM) > print_insn = print_insn_arm; > @@ -426,13 +439,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > #elif defined(TARGET_SPARC) > print_insn = print_insn_sparc; > #ifdef TARGET_SPARC64 > - disasm_info.mach = bfd_mach_sparc_v9b; > + s.info.mach = bfd_mach_sparc_v9b; > #endif > #elif defined(TARGET_PPC) > #ifdef TARGET_PPC64 > - disasm_info.mach = bfd_mach_ppc64; > + s.info.mach = bfd_mach_ppc64; > #else > - disasm_info.mach = bfd_mach_ppc; > + s.info.mach = bfd_mach_ppc; > #endif > print_insn = print_insn_ppc; > #elif defined(TARGET_M68K) > @@ -444,13 +457,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > print_insn = print_insn_little_mips; > #endif > #elif defined(TARGET_SH4) > - disasm_info.mach = bfd_mach_sh4; > + s.info.mach = bfd_mach_sh4; > print_insn = print_insn_sh; > #elif defined(TARGET_S390X) > - disasm_info.mach = bfd_mach_s390_64; > + s.info.mach = bfd_mach_s390_64; > print_insn = print_insn_s390; > #elif defined(TARGET_LM32) > - disasm_info.mach = bfd_mach_lm32; > + s.info.mach = bfd_mach_lm32; > print_insn = print_insn_lm32; > #else > monitor_printf(mon, "0x" TARGET_FMT_lx > @@ -460,7 +473,7 @@ void monitor_disas(Monitor *mon, CPUArchState *env, > > for(i = 0; i < nb_insn; i++) { > monitor_printf(mon, "0x" TARGET_FMT_lx ": ", pc); > - count = print_insn(pc, &disasm_info); > + count = print_insn(pc, &s.info); > monitor_printf(mon, "\n"); > if (count < 0) > break; > diff --git a/disas.h b/disas.h > index a8a0974..c13ca9a 100644 > --- a/disas.h > +++ b/disas.h > @@ -6,7 +6,8 @@ > #ifdef NEED_CPU_H > /* Disassemble this for me please... (debugging). */ > void disas(FILE *out, void *code, unsigned long size); > -void target_disas(FILE *out, target_ulong code, target_ulong size, int > flags); > +void target_disas(FILE *out, CPUArchState *env, target_ulong code, > + target_ulong size, int flags); > > void monitor_disas(Monitor *mon, CPUArchState *env, > target_ulong pc, int nb_insn, int is_physical, int > flags); > diff --git a/qemu-log.h b/qemu-log.h > index ce6bb09..344eca3 100644 > --- a/qemu-log.h > +++ b/qemu-log.h > @@ -84,10 +84,10 @@ static inline void log_cpu_state_mask(int mask, > CPUArchState *env1, int flags) > } > > /* disas() and target_disas() to qemu_logfile: */ > -static inline void log_target_disas(target_ulong start, target_ulong len, > - int flags) > +static inline void log_target_disas(CPUArchState *env, target_ulong > start, > + target_ulong len, int flags) > { > - target_disas(qemu_logfile, start, len, flags); > + target_disas(qemu_logfile, env, start, len, flags); > } > > static inline void log_disas(void *code, unsigned long size) > diff --git a/target-alpha/translate.c b/target-alpha/translate.c > index f707d8d..8c4dd02 100644 > --- a/target-alpha/translate.c > +++ b/target-alpha/translate.c > @@ -3477,7 +3477,7 @@ static inline void > gen_intermediate_code_internal(CPUAlphaState *env, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, ctx.pc - pc_start, 1); > + log_target_disas(env, pc_start, ctx.pc - pc_start, 1); > qemu_log("\n"); > } > #endif > diff --git a/target-arm/translate.c b/target-arm/translate.c > index 25433da..7d8f8e5 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -9968,7 +9968,7 @@ done_generating: > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc->pc - pc_start, > + log_target_disas(env, pc_start, dc->pc - pc_start, > dc->thumb | (dc->bswap_code << 1)); > qemu_log("\n"); > } > diff --git a/target-cris/translate.c b/target-cris/translate.c > index 755de65..f8ebc43a 100644 > --- a/target-cris/translate.c > +++ b/target-cris/translate.c > @@ -3413,7 +3413,7 @@ gen_intermediate_code_internal(CPUCRISState *env, > TranslationBlock *tb, > #ifdef DEBUG_DISAS > #if !DISAS_CRIS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > - log_target_disas(pc_start, dc->pc - pc_start, > + log_target_disas(env, pc_start, dc->pc - pc_start, > dc->env->pregs[PR_VR]); > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > diff --git a/target-i386/translate.c b/target-i386/translate.c > index ee75850..bf52eef 100644 > --- a/target-i386/translate.c > +++ b/target-i386/translate.c > @@ -8047,7 +8047,7 @@ static inline void > gen_intermediate_code_internal(CPUX86State *env, > else > #endif > disas_flags = !dc->code32; > - log_target_disas(pc_start, pc_ptr - pc_start, disas_flags); > + log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags); > qemu_log("\n"); > } > #endif > diff --git a/target-lm32/translate.c b/target-lm32/translate.c > index 77c2866..3307daa 100644 > --- a/target-lm32/translate.c > +++ b/target-lm32/translate.c > @@ -1120,7 +1120,7 @@ static void > gen_intermediate_code_internal(CPULM32State *env, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("\n"); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > } > diff --git a/target-m68k/translate.c b/target-m68k/translate.c > index 451ef74..1430d4c 100644 > --- a/target-m68k/translate.c > +++ b/target-m68k/translate.c > @@ -3070,7 +3070,7 @@ gen_intermediate_code_internal(CPUM68KState *env, > TranslationBlock *tb, > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c > index 7d864b1..5eaf975 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -1913,7 +1913,7 @@ gen_intermediate_code_internal(CPUMBState *env, > TranslationBlock *tb, > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("\n"); > #if DISAS_GNU > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > #endif > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 454e5cc..e00323a 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -12939,7 +12939,7 @@ done_generating: > LOG_DISAS("\n"); > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, ctx.pc - pc_start, 0); > + log_target_disas(env, pc_start, ctx.pc - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c > index e2cad3a..ff2feb4 100644 > --- a/target-openrisc/translate.c > +++ b/target-openrisc/translate.c > @@ -1797,7 +1797,7 @@ static inline void > gen_intermediate_code_internal(OpenRISCCPU *cpu, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("\n"); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0); > qemu_log("\nisize=%d osize=%td\n", > dc->pc - pc_start, gen_opc_ptr - gen_opc_buf); > } > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 1042268..06c58c2 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -9783,7 +9783,7 @@ static inline void > gen_intermediate_code_internal(CPUPPCState *env, > flags = env->bfd_mach; > flags |= ctx.le_mode << 16; > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, ctx.nip - pc_start, flags); > + log_target_disas(env, pc_start, ctx.nip - pc_start, flags); > qemu_log("\n"); > } > #endif > diff --git a/target-s390x/translate.c b/target-s390x/translate.c > index db464cc..c6267a8 100644 > --- a/target-s390x/translate.c > +++ b/target-s390x/translate.c > @@ -5220,7 +5220,7 @@ static inline void > gen_intermediate_code_internal(CPUS390XState *env, > #if defined(S390X_DEBUG_DISAS) > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc.pc - pc_start, 1); > + log_target_disas(env, pc_start, dc.pc - pc_start, 1); > qemu_log("\n"); > } > #endif > diff --git a/target-sh4/translate.c b/target-sh4/translate.c > index 9d955eb..2ae7f03 100644 > --- a/target-sh4/translate.c > +++ b/target-sh4/translate.c > @@ -2070,7 +2070,7 @@ gen_intermediate_code_internal(CPUSH4State * env, > TranslationBlock * tb, > #ifdef DEBUG_DISAS > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ > - log_target_disas(pc_start, ctx.pc - pc_start, 0); > + log_target_disas(env, pc_start, ctx.pc - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 4321393..f410efc 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -5353,7 +5353,7 @@ static inline void > gen_intermediate_code_internal(TranslationBlock * tb, > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("--------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, last_pc + 4 - pc_start, 0); > + log_target_disas(env, pc_start, last_pc + 4 - pc_start, 0); > qemu_log("\n"); > } > #endif > diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c > index c3cdafa..57b18ac 100644 > --- a/target-unicore32/translate.c > +++ b/target-unicore32/translate.c > @@ -2109,7 +2109,7 @@ done_generating: > if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { > qemu_log("----------------\n"); > qemu_log("IN: %s\n", lookup_symbol(pc_start)); > - log_target_disas(pc_start, dc->pc - pc_start, 0); > + log_target_disas(env, pc_start, dc->pc - pc_start, 0); > qemu_log("\n"); > } > #endif > -- > 1.7.2.5 > ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/5] kvm: avoid using cpu_single_env 2012-10-28 15:03 [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Blue Swirl @ 2012-10-28 15:03 ` Blue Swirl 2012-10-28 15:03 ` [Qemu-devel] " Blue Swirl ` (4 subsequent siblings) 5 siblings, 0 replies; 19+ messages in thread From: Blue Swirl @ 2012-10-28 15:03 UTC (permalink / raw) To: qemu-devel; +Cc: blauwirbel, Avi Kivity, Marcelo Tosatti, kvm Pass around CPUState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> --- target-i386/kvm.c | 21 +++++++++++---------- 1 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 3aa62b2..3329d5e 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1909,14 +1909,15 @@ void kvm_arch_remove_all_hw_breakpoints(void) static CPUWatchpoint hw_watchpoint; -static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) +static int kvm_handle_debug(CPUX86State *env, + struct kvm_debug_exit_arch *arch_info) { int ret = 0; int n; if (arch_info->exception == 1) { if (arch_info->dr6 & (1 << 14)) { - if (cpu_single_env->singlestep_enabled) { + if (env->singlestep_enabled) { ret = EXCP_DEBUG; } } else { @@ -1928,13 +1929,13 @@ static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) break; case 0x1: ret = EXCP_DEBUG; - cpu_single_env->watchpoint_hit = &hw_watchpoint; + env->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_WRITE; break; case 0x3: ret = EXCP_DEBUG; - cpu_single_env->watchpoint_hit = &hw_watchpoint; + env->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_ACCESS; break; @@ -1942,16 +1943,16 @@ static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) } } } - } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { + } else if (kvm_find_sw_breakpoint(env, arch_info->pc)) { ret = EXCP_DEBUG; } if (ret == 0) { - cpu_synchronize_state(cpu_single_env); - assert(cpu_single_env->exception_injected == -1); + cpu_synchronize_state(env); + assert(env->exception_injected == -1); /* pass to guest */ - cpu_single_env->exception_injected = arch_info->exception; - cpu_single_env->has_error_code = 0; + env->exception_injected = arch_info->exception; + env->has_error_code = 0; } return ret; @@ -2034,7 +2035,7 @@ int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run) break; case KVM_EXIT_DEBUG: DPRINTF("kvm_exit_debug\n"); - ret = kvm_handle_debug(&run->debug.arch); + ret = kvm_handle_debug(env, &run->debug.arch); break; default: fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH 2/5] kvm: avoid using cpu_single_env @ 2012-10-28 15:03 ` Blue Swirl 0 siblings, 0 replies; 19+ messages in thread From: Blue Swirl @ 2012-10-28 15:03 UTC (permalink / raw) To: qemu-devel; +Cc: blauwirbel, Marcelo Tosatti, Avi Kivity, kvm Pass around CPUState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> --- target-i386/kvm.c | 21 +++++++++++---------- 1 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 3aa62b2..3329d5e 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1909,14 +1909,15 @@ void kvm_arch_remove_all_hw_breakpoints(void) static CPUWatchpoint hw_watchpoint; -static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) +static int kvm_handle_debug(CPUX86State *env, + struct kvm_debug_exit_arch *arch_info) { int ret = 0; int n; if (arch_info->exception == 1) { if (arch_info->dr6 & (1 << 14)) { - if (cpu_single_env->singlestep_enabled) { + if (env->singlestep_enabled) { ret = EXCP_DEBUG; } } else { @@ -1928,13 +1929,13 @@ static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) break; case 0x1: ret = EXCP_DEBUG; - cpu_single_env->watchpoint_hit = &hw_watchpoint; + env->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_WRITE; break; case 0x3: ret = EXCP_DEBUG; - cpu_single_env->watchpoint_hit = &hw_watchpoint; + env->watchpoint_hit = &hw_watchpoint; hw_watchpoint.vaddr = hw_breakpoint[n].addr; hw_watchpoint.flags = BP_MEM_ACCESS; break; @@ -1942,16 +1943,16 @@ static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info) } } } - } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) { + } else if (kvm_find_sw_breakpoint(env, arch_info->pc)) { ret = EXCP_DEBUG; } if (ret == 0) { - cpu_synchronize_state(cpu_single_env); - assert(cpu_single_env->exception_injected == -1); + cpu_synchronize_state(env); + assert(env->exception_injected == -1); /* pass to guest */ - cpu_single_env->exception_injected = arch_info->exception; - cpu_single_env->has_error_code = 0; + env->exception_injected = arch_info->exception; + env->has_error_code = 0; } return ret; @@ -2034,7 +2035,7 @@ int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run) break; case KVM_EXIT_DEBUG: DPRINTF("kvm_exit_debug\n"); - ret = kvm_handle_debug(&run->debug.arch); + ret = kvm_handle_debug(env, &run->debug.arch); break; default: fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason); -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 2/5] kvm: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] " Blue Swirl @ 2012-10-31 3:25 ` Andreas Färber -1 siblings, 0 replies; 19+ messages in thread From: Andreas Färber @ 2012-10-31 3:25 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel, Marcelo Tosatti, Avi Kivity, kvm Am 28.10.2012 16:03, schrieb Blue Swirl: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > target-i386/kvm.c | 21 +++++++++++---------- > 1 files changed, 11 insertions(+), 10 deletions(-) If you fix CPUState -> CPU*State or CPUArchState above, Reviewed-by: Andreas Färber <afaerber@suse.de> Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 2/5] kvm: avoid using cpu_single_env @ 2012-10-31 3:25 ` Andreas Färber 0 siblings, 0 replies; 19+ messages in thread From: Andreas Färber @ 2012-10-31 3:25 UTC (permalink / raw) To: Blue Swirl; +Cc: Marcelo Tosatti, qemu-devel, kvm, Avi Kivity Am 28.10.2012 16:03, schrieb Blue Swirl: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > target-i386/kvm.c | 21 +++++++++++---------- > 1 files changed, 11 insertions(+), 10 deletions(-) If you fix CPUState -> CPU*State or CPUArchState above, Reviewed-by: Andreas Färber <afaerber@suse.de> Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH 3/5] target-unicore32: avoid using cpu_single_env 2012-10-28 15:03 [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Blue Swirl 2012-10-28 15:03 ` [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env Blue Swirl 2012-10-28 15:03 ` [Qemu-devel] " Blue Swirl @ 2012-10-28 15:03 ` Blue Swirl [not found] ` <5cd15b325c56b2b7fe0b315c52a9b5094ce73633.1351436501.git.blauwirbel@gm ail.com> 2012-10-31 3:26 ` Andreas Färber 2012-10-28 15:03 ` [Qemu-devel] [PATCH 4/5] target-xtensa: " Blue Swirl ` (2 subsequent siblings) 5 siblings, 2 replies; 19+ messages in thread From: Blue Swirl @ 2012-10-28 15:03 UTC (permalink / raw) To: qemu-devel; +Cc: blauwirbel, Guan Xuetao Pass around CPUState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> --- target-unicore32/softmmu.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c index 9c2c54c..fc27100 100644 --- a/target-unicore32/softmmu.c +++ b/target-unicore32/softmmu.c @@ -31,7 +31,7 @@ /* Map CPU modes onto saved register banks. */ -static inline int bank_number(int mode) +static inline int bank_number(CPUUniCore32State *env, int mode) { switch (mode) { case ASR_MODE_USER: @@ -46,7 +46,7 @@ static inline int bank_number(int mode) case ASR_MODE_INTR: return 4; } - cpu_abort(cpu_single_env, "Bad mode %x\n", mode); + cpu_abort(env, "Bad mode %x\n", mode); return -1; } @@ -60,12 +60,12 @@ void switch_mode(CPUUniCore32State *env, int mode) return; } - i = bank_number(old_mode); + i = bank_number(env, old_mode); env->banked_r29[i] = env->regs[29]; env->banked_r30[i] = env->regs[30]; env->banked_bsr[i] = env->bsr; - i = bank_number(mode); + i = bank_number(env, mode); env->regs[29] = env->banked_r29[i]; env->regs[30] = env->banked_r30[i]; env->bsr = env->banked_bsr[i]; -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 19+ messages in thread
[parent not found: <5cd15b325c56b2b7fe0b315c52a9b5094ce73633.1351436501.git.blauwirbel@gm ail.com>]
* Re: [Qemu-devel] [PATCH 3/5] target-unicore32: avoid using cpu_single_env [not found] ` <5cd15b325c56b2b7fe0b315c52a9b5094ce73633.1351436501.git.blauwirbel@gm ail.com> @ 2012-10-31 2:55 ` guanxuetao 0 siblings, 0 replies; 19+ messages in thread From: guanxuetao @ 2012-10-31 2:55 UTC (permalink / raw) To: Blue Swirl; +Cc: Guan Xuetao, qemu-devel > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Guan Xuetao <gxt@mprc.pku.edu.cn> > --- > target-unicore32/softmmu.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c > index 9c2c54c..fc27100 100644 > --- a/target-unicore32/softmmu.c > +++ b/target-unicore32/softmmu.c > @@ -31,7 +31,7 @@ > > > /* Map CPU modes onto saved register banks. */ > -static inline int bank_number(int mode) > +static inline int bank_number(CPUUniCore32State *env, int mode) > { > switch (mode) { > case ASR_MODE_USER: > @@ -46,7 +46,7 @@ static inline int bank_number(int mode) > case ASR_MODE_INTR: > return 4; > } > - cpu_abort(cpu_single_env, "Bad mode %x\n", mode); > + cpu_abort(env, "Bad mode %x\n", mode); > return -1; > } > > @@ -60,12 +60,12 @@ void switch_mode(CPUUniCore32State *env, int mode) > return; > } > > - i = bank_number(old_mode); > + i = bank_number(env, old_mode); > env->banked_r29[i] = env->regs[29]; > env->banked_r30[i] = env->regs[30]; > env->banked_bsr[i] = env->bsr; > > - i = bank_number(mode); > + i = bank_number(env, mode); > env->regs[29] = env->banked_r29[i]; > env->regs[30] = env->banked_r30[i]; > env->bsr = env->banked_bsr[i]; > -- > 1.7.2.5 > ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 3/5] target-unicore32: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] [PATCH 3/5] target-unicore32: " Blue Swirl [not found] ` <5cd15b325c56b2b7fe0b315c52a9b5094ce73633.1351436501.git.blauwirbel@gm ail.com> @ 2012-10-31 3:26 ` Andreas Färber 1 sibling, 0 replies; 19+ messages in thread From: Andreas Färber @ 2012-10-31 3:26 UTC (permalink / raw) To: Blue Swirl; +Cc: Guan Xuetao, qemu-devel Am 28.10.2012 16:03, schrieb Blue Swirl: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > target-unicore32/softmmu.c | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) Reviewed-by: Andreas Färber <afaerber@suse.de> with the usual remark on "CPUState". Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH 4/5] target-xtensa: avoid using cpu_single_env 2012-10-28 15:03 [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Blue Swirl ` (2 preceding siblings ...) 2012-10-28 15:03 ` [Qemu-devel] [PATCH 3/5] target-unicore32: " Blue Swirl @ 2012-10-28 15:03 ` Blue Swirl 2012-10-29 5:58 ` Max Filippov 2012-10-31 3:28 ` Andreas Färber 2012-10-28 15:03 ` [Qemu-devel] [PATCH 5/5] target-i386: " Blue Swirl 2012-10-31 3:59 ` [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Andreas Färber 5 siblings, 2 replies; 19+ messages in thread From: Blue Swirl @ 2012-10-28 15:03 UTC (permalink / raw) To: qemu-devel; +Cc: blauwirbel, Max Filippov Pass around CPUState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> --- target-xtensa/translate.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 82e8ccc..3c03775 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -810,7 +810,7 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned) return m; } -static void disas_xtensa_insn(DisasContext *dc) +static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc) { #define HAS_OPTION_BITS(opt) do { \ if (!option_bits_enabled(dc, opt)) { \ @@ -900,8 +900,8 @@ static void disas_xtensa_insn(DisasContext *dc) #define RSR_SR (b1) - uint8_t b0 = cpu_ldub_code(cpu_single_env, dc->pc); - uint8_t b1 = cpu_ldub_code(cpu_single_env, dc->pc + 1); + uint8_t b0 = cpu_ldub_code(env, dc->pc); + uint8_t b1 = cpu_ldub_code(env, dc->pc + 1); uint8_t b2 = 0; static const uint32_t B4CONST[] = { @@ -917,7 +917,7 @@ static void disas_xtensa_insn(DisasContext *dc) HAS_OPTION(XTENSA_OPTION_CODE_DENSITY); } else { dc->next_pc = dc->pc + 3; - b2 = cpu_ldub_code(cpu_single_env, dc->pc + 2); + b2 = cpu_ldub_code(env, dc->pc + 2); } switch (OP0) { @@ -2931,7 +2931,7 @@ static void gen_intermediate_code_internal( gen_ibreak_check(env, &dc); } - disas_xtensa_insn(&dc); + disas_xtensa_insn(env, &dc); ++insn_count; if (dc.icount) { tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount); -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] target-xtensa: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] [PATCH 4/5] target-xtensa: " Blue Swirl @ 2012-10-29 5:58 ` Max Filippov 2012-10-31 3:28 ` Andreas Färber 1 sibling, 0 replies; 19+ messages in thread From: Max Filippov @ 2012-10-29 5:58 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel On Sun, Oct 28, 2012 at 7:03 PM, Blue Swirl <blauwirbel@gmail.com> wrote: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > target-xtensa/translate.c | 10 +++++----- > 1 files changed, 5 insertions(+), 5 deletions(-) Acked-by: Max Filippov <jcmvbkbc@gmail.com> -- Thanks. -- Max ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 4/5] target-xtensa: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] [PATCH 4/5] target-xtensa: " Blue Swirl 2012-10-29 5:58 ` Max Filippov @ 2012-10-31 3:28 ` Andreas Färber 1 sibling, 0 replies; 19+ messages in thread From: Andreas Färber @ 2012-10-31 3:28 UTC (permalink / raw) To: Blue Swirl; +Cc: Max Filippov, qemu-devel Am 28.10.2012 16:03, schrieb Blue Swirl: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > target-xtensa/translate.c | 10 +++++----- > 1 files changed, 5 insertions(+), 5 deletions(-) Reviewed-by: Andreas Färber <afaerber@suse.de> ditto about "CPUState". Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg ^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH 5/5] target-i386: avoid using cpu_single_env 2012-10-28 15:03 [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Blue Swirl ` (3 preceding siblings ...) 2012-10-28 15:03 ` [Qemu-devel] [PATCH 4/5] target-xtensa: " Blue Swirl @ 2012-10-28 15:03 ` Blue Swirl 2012-10-31 3:41 ` Andreas Färber 2012-10-31 3:59 ` [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Andreas Färber 5 siblings, 1 reply; 19+ messages in thread From: Blue Swirl @ 2012-10-28 15:03 UTC (permalink / raw) To: qemu-devel; +Cc: blauwirbel Pass around CPUState instead of using global cpu_single_env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> --- target-i386/translate.c | 440 ++++++++++++++++++++++++----------------------- 1 files changed, 222 insertions(+), 218 deletions(-) diff --git a/target-i386/translate.c b/target-i386/translate.c index bf52eef..7fdb8bc 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -2018,7 +2018,8 @@ static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c) } } -static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr) +static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm, + int *reg_ptr, int *offset_ptr) { target_long disp; int havesib; @@ -2044,7 +2045,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ if (base == 4) { havesib = 1; - code = cpu_ldub_code(cpu_single_env, s->pc++); + code = cpu_ldub_code(env, s->pc++); scale = (code >> 6) & 3; index = ((code >> 3) & 7) | REX_X(s); base = (code & 7); @@ -2055,7 +2056,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ case 0: if ((base & 7) == 5) { base = -1; - disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc); + disp = (int32_t)cpu_ldl_code(env, s->pc); s->pc += 4; if (CODE64(s) && !havesib) { disp += s->pc + s->rip_offset; @@ -2065,11 +2066,11 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ } break; case 1: - disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++); + disp = (int8_t)cpu_ldub_code(env, s->pc++); break; default: case 2: - disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc); + disp = (int32_t)cpu_ldl_code(env, s->pc); s->pc += 4; break; } @@ -2132,7 +2133,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ switch (mod) { case 0: if (rm == 6) { - disp = cpu_lduw_code(cpu_single_env, s->pc); + disp = cpu_lduw_code(env, s->pc); s->pc += 2; gen_op_movl_A0_im(disp); rm = 0; /* avoid SS override */ @@ -2142,11 +2143,11 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ } break; case 1: - disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++); + disp = (int8_t)cpu_ldub_code(env, s->pc++); break; default: case 2: - disp = cpu_lduw_code(cpu_single_env, s->pc); + disp = cpu_lduw_code(env, s->pc); s->pc += 2; break; } @@ -2202,7 +2203,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ *offset_ptr = disp; } -static void gen_nop_modrm(DisasContext *s, int modrm) +static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm) { int mod, rm, base, code; @@ -2216,7 +2217,7 @@ static void gen_nop_modrm(DisasContext *s, int modrm) base = rm; if (base == 4) { - code = cpu_ldub_code(cpu_single_env, s->pc++); + code = cpu_ldub_code(env, s->pc++); base = (code & 7); } @@ -2276,7 +2277,8 @@ static void gen_add_A0_ds_seg(DisasContext *s) /* generate modrm memory load or store of 'reg'. TMP0 is used if reg == OR_TMP0 */ -static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store) +static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm, + int ot, int reg, int is_store) { int mod, rm, opreg, disp; @@ -2293,7 +2295,7 @@ static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_s gen_op_mov_reg_T0(ot, reg); } } else { - gen_lea_modrm(s, modrm, &opreg, &disp); + gen_lea_modrm(env, s, modrm, &opreg, &disp); if (is_store) { if (reg != OR_TMP0) gen_op_mov_TN_reg(ot, 0, reg); @@ -2306,22 +2308,22 @@ static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_s } } -static inline uint32_t insn_get(DisasContext *s, int ot) +static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot) { uint32_t ret; switch(ot) { case OT_BYTE: - ret = cpu_ldub_code(cpu_single_env, s->pc); + ret = cpu_ldub_code(env, s->pc); s->pc++; break; case OT_WORD: - ret = cpu_lduw_code(cpu_single_env, s->pc); + ret = cpu_lduw_code(env, s->pc); s->pc += 2; break; default: case OT_LONG: - ret = cpu_ldl_code(cpu_single_env, s->pc); + ret = cpu_ldl_code(env, s->pc); s->pc += 4; break; } @@ -3167,7 +3169,8 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = { [0x63] = SSE42_OP(pcmpistri), }; -static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) +static void gen_sse(CPUX86State *env, DisasContext *s, int b, + target_ulong pc_start, int rex_r) { int b1, op1_offset, op2_offset, is_xmm, val, ot; int modrm, mod, rm, reg, reg_addr, offset_addr; @@ -3230,7 +3233,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) gen_helper_enter_mmx(cpu_env); } - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7); if (is_xmm) reg |= rex_r; @@ -3241,7 +3244,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x0e7: /* movntq */ if (mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); break; case 0x1e7: /* movntdq */ @@ -3249,20 +3252,20 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x12b: /* movntps */ if (mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); break; case 0x3f0: /* lddqu */ if (mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); break; case 0x22b: /* movntss */ case 0x32b: /* movntsd */ if (mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (b1 & 1) { gen_stq_env_A0(s->mem_index, offsetof(CPUX86State, xmm_regs[reg])); @@ -3275,12 +3278,12 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x6e: /* movd mm, ea */ #ifdef TARGET_X86_64 if (s->dflag == 2) { - gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); } else #endif { - gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); @@ -3290,14 +3293,14 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x16e: /* movd xmm, ea */ #ifdef TARGET_X86_64 if (s->dflag == 2) { - gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[reg])); gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]); } else #endif { - gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[reg])); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); @@ -3306,7 +3309,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x6f: /* movq mm, ea */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); } else { rm = (modrm & 7); @@ -3323,7 +3326,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x16f: /* movdqa xmm, ea */ case 0x26f: /* movdqu xmm, ea */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); @@ -3333,7 +3336,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x210: /* movss xmm, ea */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_T0_A0(OT_LONG + s->mem_index); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_movl_T0_0(); @@ -3348,7 +3351,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x310: /* movsd xmm, ea */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); gen_op_movl_T0_0(); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2))); @@ -3362,7 +3365,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x012: /* movlps */ case 0x112: /* movlpd */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { /* movhlps */ @@ -3373,7 +3376,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x212: /* movsldup */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); @@ -3389,7 +3392,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x312: /* movddup */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); @@ -3402,7 +3405,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x016: /* movhps */ case 0x116: /* movhpd */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); } else { /* movlhps */ @@ -3413,7 +3416,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x216: /* movshdup */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); @@ -3434,8 +3437,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (b1 == 1 && reg != 0) goto illegal_op; - field_length = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F; - bit_index = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F; + field_length = cpu_ldub_code(env, s->pc++) & 0x3F; + bit_index = cpu_ldub_code(env, s->pc++) & 0x3F; tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[reg])); if (b1 == 1) @@ -3453,13 +3456,13 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (s->dflag == 2) { tcg_gen_ld_i64(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx)); - gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); } else #endif { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0))); - gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); } break; case 0x17e: /* movd ea, xmm */ @@ -3467,18 +3470,18 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (s->dflag == 2) { tcg_gen_ld_i64(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); - gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1); } else #endif { tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); - gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1); } break; case 0x27e: /* movq xmm, ea */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); @@ -3489,7 +3492,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x7f: /* movq ea, mm */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx)); } else { rm = (modrm & 7); @@ -3504,7 +3507,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x17f: /* movdqa ea, xmm */ case 0x27f: /* movdqu ea, xmm */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg])); } else { rm = (modrm & 7) | REX_B(s); @@ -3514,7 +3517,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x211: /* movss ea, xmm */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0))); gen_op_st_T0_A0(OT_LONG + s->mem_index); } else { @@ -3525,7 +3528,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x311: /* movsd ea, xmm */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); @@ -3536,7 +3539,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x013: /* movlps */ case 0x113: /* movlpd */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { goto illegal_op; @@ -3545,7 +3548,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x017: /* movhps */ case 0x117: /* movhpd */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1))); } else { goto illegal_op; @@ -3560,7 +3563,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (b1 >= 2) { goto illegal_op; } - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); if (is_xmm) { gen_op_movl_T0_im(val); tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0))); @@ -3610,7 +3613,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x12a: /* cvtpi2pd */ gen_helper_enter_mmx(cpu_env); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,mmx_t0); gen_ldq_env_A0(s->mem_index, op2_offset); } else { @@ -3633,7 +3636,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x22a: /* cvtsi2ss */ case 0x32a: /* cvtsi2sd */ ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); op1_offset = offsetof(CPUX86State,xmm_regs[reg]); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); if (ot == OT_LONG) { @@ -3655,7 +3658,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x12d: /* cvtpd2pi */ gen_helper_enter_mmx(cpu_env); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,xmm_t0); gen_ldo_env_A0(s->mem_index, op2_offset); } else { @@ -3686,7 +3689,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x32d: /* cvtsd2si */ ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if ((b >> 8) & 1) { gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0))); } else { @@ -3718,8 +3721,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0xc4: /* pinsrw */ case 0x1c4: s->rip_offset = 1; - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); - val = cpu_ldub_code(cpu_single_env, s->pc++); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); + val = cpu_ldub_code(env, s->pc++); if (b1) { val &= 7; tcg_gen_st16_tl(cpu_T[0], cpu_env, @@ -3735,7 +3738,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (mod != 3) goto illegal_op; ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); if (b1) { val &= 7; rm = (modrm & 7) | REX_B(s); @@ -3752,7 +3755,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x1d6: /* movq ea, xmm */ if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0))); } else { rm = (modrm & 7) | REX_B(s); @@ -3796,7 +3799,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) goto crc32; case 0x038: b = modrm; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); rm = modrm & 7; reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; @@ -3817,7 +3820,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); } else { op2_offset = offsetof(CPUX86State,xmm_t0); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); switch (b) { case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */ case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */ @@ -3852,7 +3855,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); } else { op2_offset = offsetof(CPUX86State,mmx_t0); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, op2_offset); } } @@ -3870,7 +3873,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x338: /* crc32 */ crc32: b = modrm; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; if (b != 0xf0 && b != 0xf1) @@ -3890,7 +3893,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) gen_op_mov_TN_reg(OT_LONG, 0, reg); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_helper_crc32(cpu_T[0], cpu_tmp2_i32, cpu_T[0], tcg_const_i32(8 << ot)); @@ -3900,7 +3903,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x03a: case 0x13a: b = modrm; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); rm = modrm & 7; reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; @@ -3919,9 +3922,9 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) ot = (s->dflag == 2) ? OT_QUAD : OT_LONG; rm = (modrm & 7) | REX_B(s); if (mod != 3) - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); reg = ((modrm >> 3) & 7) | rex_r; - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); switch (b) { case 0x14: /* pextrb */ tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, @@ -4051,7 +4054,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]); } else { op2_offset = offsetof(CPUX86State,xmm_t0); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldo_env_A0(s->mem_index, op2_offset); } } else { @@ -4060,11 +4063,11 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) op2_offset = offsetof(CPUX86State,fpregs[rm].mmx); } else { op2_offset = offsetof(CPUX86State,mmx_t0); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_ldq_env_A0(s->mem_index, op2_offset); } } - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); if ((b & 0xfc) == 0x60) { /* pcmpXstrX */ s->cc_op = CC_OP_EFLAGS; @@ -4095,7 +4098,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) if (is_xmm) { op1_offset = offsetof(CPUX86State,xmm_regs[reg]); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,xmm_t0); if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) || b == 0xc2)) { @@ -4118,7 +4121,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) } else { op1_offset = offsetof(CPUX86State,fpregs[reg].mmx); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); op2_offset = offsetof(CPUX86State,mmx_t0); gen_ldq_env_A0(s->mem_index, op2_offset); } else { @@ -4130,7 +4133,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) case 0x0f: /* 3DNow! data insns */ if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) goto illegal_op; - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); sse_fn_epp = sse_op_table5[val]; if (!sse_fn_epp) { goto illegal_op; @@ -4141,7 +4144,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0x70: /* pshufx insn */ case 0xc6: /* pshufx insn */ - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset); tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset); /* XXX: introduce a new table? */ @@ -4150,7 +4153,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) break; case 0xc2: /* compare insns */ - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); if (val >= 8) goto illegal_op; sse_fn_epp = sse_op_table4[val][b1]; @@ -4195,7 +4198,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r) /* convert one instruction. s->is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) +static target_ulong disas_insn(CPUX86State *env, DisasContext *s, + target_ulong pc_start) { int b, prefixes, aflag, dflag; int shift, ot; @@ -4220,7 +4224,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) #endif s->rip_offset = 0; /* for relative ip address */ next_byte: - b = cpu_ldub_code(cpu_single_env, s->pc); + b = cpu_ldub_code(env, s->pc); s->pc++; /* check prefixes */ #ifdef TARGET_X86_64 @@ -4335,7 +4339,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x0f: /**************************/ /* extended op code */ - b = cpu_ldub_code(cpu_single_env, s->pc++) | 0x100; + b = cpu_ldub_code(env, s->pc++) | 0x100; goto reswitch; /**************************/ @@ -4360,12 +4364,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) switch(f) { case 0: /* OP Ev, Gv */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); opreg = OR_TMP0; } else if (op == OP_XORL && rm == reg) { xor_zero: @@ -4382,12 +4386,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op(s, op, ot, opreg); break; case 1: /* OP Gv, Ev */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; reg = ((modrm >> 3) & 7) | rex_r; rm = (modrm & 7) | REX_B(s); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_T1_A0(ot + s->mem_index); } else if (op == OP_XORL && rm == reg) { goto xor_zero; @@ -4397,7 +4401,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op(s, op, ot, reg); break; case 2: /* OP A, Iv */ - val = insn_get(s, ot); + val = insn_get(env, s, ot); gen_op_movl_T1_im(val); gen_op(s, op, ot, OR_EAX); break; @@ -4419,7 +4423,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); op = (modrm >> 3) & 7; @@ -4429,7 +4433,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) s->rip_offset = 1; else s->rip_offset = insn_const_size(ot); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); opreg = OR_TMP0; } else { opreg = rm; @@ -4440,10 +4444,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x80: case 0x81: case 0x82: - val = insn_get(s, ot); + val = insn_get(env, s, ot); break; case 0x83: - val = (int8_t)insn_get(s, OT_BYTE); + val = (int8_t)insn_get(env, s, OT_BYTE); break; } gen_op_movl_T1_im(val); @@ -4468,14 +4472,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); op = (modrm >> 3) & 7; if (mod != 3) { if (op == 0) s->rip_offset = insn_const_size(ot); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_T0_A0(ot + s->mem_index); } else { gen_op_mov_TN_reg(ot, 0, rm); @@ -4483,7 +4487,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) switch(op) { case 0: /* test */ - val = insn_get(s, ot); + val = insn_get(env, s, ot); gen_op_movl_T1_im(val); gen_op_testl_T0_T1_cc(); s->cc_op = CC_OP_LOGICB + ot; @@ -4700,7 +4704,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); op = (modrm >> 3) & 7; @@ -4719,7 +4723,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } } if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (op >= 2 && op != 3 && op != 5) gen_op_ld_T0_A0(ot + s->mem_index); } else { @@ -4812,10 +4816,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_TN_reg(ot, 1, reg); gen_op_testl_T0_T1_cc(); s->cc_op = CC_OP_LOGICB + ot; @@ -4827,7 +4831,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag + OT_WORD; - val = insn_get(s, ot); + val = insn_get(env, s, ot); gen_op_mov_TN_reg(ot, 0, OR_EAX); gen_op_movl_T1_im(val); @@ -4877,18 +4881,18 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x69: /* imul Gv, Ev, I */ case 0x6b: ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; if (b == 0x69) s->rip_offset = insn_const_size(ot); else if (b == 0x6b) s->rip_offset = 1; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); if (b == 0x69) { - val = insn_get(s, ot); + val = insn_get(env, s, ot); gen_op_movl_T1_im(val); } else if (b == 0x6b) { - val = (int8_t)insn_get(s, OT_BYTE); + val = (int8_t)insn_get(env, s, OT_BYTE); gen_op_movl_T1_im(val); } else { gen_op_mov_TN_reg(ot, 1, reg); @@ -4941,7 +4945,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; if (mod == 3) { @@ -4952,7 +4956,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_mov_reg_T1(ot, reg); gen_op_mov_reg_T0(ot, rm); } else { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_mov_TN_reg(ot, 0, reg); gen_op_ld_T1_A0(ot + s->mem_index); gen_op_addl_T0_T1(); @@ -4972,7 +4976,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; t0 = tcg_temp_local_new(); @@ -4984,7 +4988,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) rm = (modrm & 7) | REX_B(s); gen_op_mov_v_reg(ot, t0, rm); } else { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_mov_tl(a0, cpu_A0); gen_op_ld_v(ot + s->mem_index, t0, a0); rm = 0; /* avoid warning */ @@ -5020,7 +5024,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; case 0x1c7: /* cmpxchg8b */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; if ((mod == 3) || ((modrm & 0x38) != 0x8)) goto illegal_op; @@ -5031,7 +5035,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_helper_cmpxchg16b(cpu_env, cpu_A0); } else #endif @@ -5041,7 +5045,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_jmp_im(pc_start - s->cs_base); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_helper_cmpxchg8b(cpu_env, cpu_A0); } s->cc_op = CC_OP_EFLAGS; @@ -5082,9 +5086,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = dflag + OT_WORD; } if (b == 0x68) - val = insn_get(s, ot); + val = insn_get(env, s, ot); else - val = (int8_t)insn_get(s, OT_BYTE); + val = (int8_t)insn_get(env, s, OT_BYTE); gen_op_movl_T0_im(val); gen_push_T0(s); break; @@ -5094,7 +5098,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } else { ot = dflag + OT_WORD; } - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; gen_pop_T0(s); if (mod == 3) { @@ -5105,7 +5109,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } else { /* NOTE: order is important too for MMU exceptions */ s->popl_esp_hack = 1 << ot; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); s->popl_esp_hack = 0; gen_pop_update(s); } @@ -5113,9 +5117,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0xc8: /* enter */ { int level; - val = cpu_lduw_code(cpu_single_env, s->pc); + val = cpu_lduw_code(env, s->pc); s->pc += 2; - level = cpu_ldub_code(cpu_single_env, s->pc++); + level = cpu_ldub_code(env, s->pc++); gen_enter(s, val, level); } break; @@ -5195,11 +5199,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; /* generate a generic store */ - gen_ldst_modrm(s, modrm, ot, reg, 1); + gen_ldst_modrm(env, s, modrm, ot, reg, 1); break; case 0xc6: case 0xc7: /* mov Ev, Iv */ @@ -5207,13 +5211,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; if (mod != 3) { s->rip_offset = insn_const_size(ot); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); } - val = insn_get(s, ot); + val = insn_get(env, s, ot); gen_op_movl_T0_im(val); if (mod != 3) gen_op_st_T0_A0(ot + s->mem_index); @@ -5226,18 +5230,18 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = OT_WORD + dflag; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_op_mov_reg_T0(ot, reg); break; case 0x8e: /* mov seg, Gv */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = (modrm >> 3) & 7; if (reg >= 6 || reg == R_CS) goto illegal_op; - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); gen_movl_seg_T0(s, reg, pc_start - s->cs_base); if (reg == R_SS) { /* if reg == SS, inhibit interrupts/trace */ @@ -5253,7 +5257,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; case 0x8c: /* mov Gv, seg */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = (modrm >> 3) & 7; mod = (modrm >> 6) & 3; if (reg >= 6) @@ -5263,7 +5267,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_WORD + dflag; else ot = OT_WORD; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 0x1b6: /* movzbS Gv, Eb */ @@ -5276,7 +5280,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) d_ot = dflag + OT_WORD; /* ot is the size of source */ ot = (b & 1) + OT_BYTE; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); @@ -5300,7 +5304,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } gen_op_mov_reg_T0(d_ot, reg); } else { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (b & 8) { gen_op_lds_T0_A0(ot + s->mem_index); } else { @@ -5313,7 +5317,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x8d: /* lea */ ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; @@ -5322,7 +5326,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) s->override = -1; val = s->addseg; s->addseg = 0; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); s->addseg = val; gen_op_mov_reg_A0(ot - OT_WORD, reg); break; @@ -5340,16 +5344,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = dflag + OT_WORD; #ifdef TARGET_X86_64 if (s->aflag == 2) { - offset_addr = cpu_ldq_code(cpu_single_env, s->pc); + offset_addr = cpu_ldq_code(env, s->pc); s->pc += 8; gen_op_movq_A0_im(offset_addr); } else #endif { if (s->aflag) { - offset_addr = insn_get(s, OT_LONG); + offset_addr = insn_get(env, s, OT_LONG); } else { - offset_addr = insn_get(s, OT_WORD); + offset_addr = insn_get(env, s, OT_WORD); } gen_op_movl_A0_im(offset_addr); } @@ -5387,7 +5391,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_mov_reg_T0(OT_BYTE, R_EAX); break; case 0xb0 ... 0xb7: /* mov R, Ib */ - val = insn_get(s, OT_BYTE); + val = insn_get(env, s, OT_BYTE); gen_op_movl_T0_im(val); gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s)); break; @@ -5396,7 +5400,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (dflag == 2) { uint64_t tmp; /* 64 bit case */ - tmp = cpu_ldq_code(cpu_single_env, s->pc); + tmp = cpu_ldq_code(env, s->pc); s->pc += 8; reg = (b & 7) | REX_B(s); gen_movtl_T0_im(tmp); @@ -5405,7 +5409,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) #endif { ot = dflag ? OT_LONG : OT_WORD; - val = insn_get(s, ot); + val = insn_get(env, s, ot); reg = (b & 7) | REX_B(s); gen_op_movl_T0_im(val); gen_op_mov_reg_T0(ot, reg); @@ -5424,7 +5428,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; if (mod == 3) { @@ -5435,7 +5439,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_mov_reg_T0(ot, rm); gen_op_mov_reg_T1(ot, reg); } else { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_mov_TN_reg(ot, 0, reg); /* for xchg, lock is implicit */ if (!(prefixes & PREFIX_LOCK)) @@ -5467,12 +5471,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) op = R_GS; do_lxx: ot = dflag ? OT_LONG : OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_T1_A0(ot + s->mem_index); gen_add_A0_im(s, 1 << (ot - OT_WORD + 1)); /* load the segment first to handle exceptions properly */ @@ -5499,7 +5503,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) else ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; op = (modrm >> 3) & 7; @@ -5507,7 +5511,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (shift == 2) { s->rip_offset = 1; } - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); opreg = OR_TMP0; } else { opreg = (modrm & 7) | REX_B(s); @@ -5518,7 +5522,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_shift(s, op, ot, opreg, OR_ECX); } else { if (shift == 2) { - shift = cpu_ldub_code(cpu_single_env, s->pc++); + shift = cpu_ldub_code(env, s->pc++); } gen_shifti(s, op, ot, opreg, shift); } @@ -5552,12 +5556,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) shift = 0; do_shiftd: ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); reg = ((modrm >> 3) & 7) | rex_r; if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); opreg = OR_TMP0; } else { opreg = rm; @@ -5565,7 +5569,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_op_mov_TN_reg(ot, 1, reg); if (shift) { - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); tcg_gen_movi_tl(cpu_T3, val); } else { tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]); @@ -5582,13 +5586,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); break; } - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; rm = modrm & 7; op = ((b & 7) << 3) | ((modrm >> 3) & 7); if (mod != 3) { /* memory op */ - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); switch(op) { case 0x00 ... 0x07: /* fxxxs */ case 0x10 ... 0x17: /* fixxxl */ @@ -6213,7 +6217,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag ? OT_LONG : OT_WORD; - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); gen_op_movl_T0_im(val); gen_check_io(s, ot, pc_start - s->cs_base, SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes)); @@ -6233,7 +6237,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_BYTE; else ot = dflag ? OT_LONG : OT_WORD; - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); gen_op_movl_T0_im(val); gen_check_io(s, ot, pc_start - s->cs_base, svm_is_rep(prefixes)); @@ -6295,7 +6299,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /************************/ /* control */ case 0xc2: /* ret im */ - val = cpu_ldsw_code(cpu_single_env, s->pc); + val = cpu_ldsw_code(env, s->pc); s->pc += 2; gen_pop_T0(s); if (CODE64(s) && s->dflag) @@ -6315,7 +6319,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_eob(s); break; case 0xca: /* lret im */ - val = cpu_ldsw_code(cpu_single_env, s->pc); + val = cpu_ldsw_code(env, s->pc); s->pc += 2; do_lret: if (s->pe && !s->vm86) { @@ -6371,9 +6375,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0xe8: /* call im */ { if (dflag) - tval = (int32_t)insn_get(s, OT_LONG); + tval = (int32_t)insn_get(env, s, OT_LONG); else - tval = (int16_t)insn_get(s, OT_WORD); + tval = (int16_t)insn_get(env, s, OT_WORD); next_eip = s->pc - s->cs_base; tval += next_eip; if (s->dflag == 0) @@ -6392,8 +6396,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (CODE64(s)) goto illegal_op; ot = dflag ? OT_LONG : OT_WORD; - offset = insn_get(s, ot); - selector = insn_get(s, OT_WORD); + offset = insn_get(env, s, ot); + selector = insn_get(env, s, OT_WORD); gen_op_movl_T0_im(selector); gen_op_movl_T1_imu(offset); @@ -6401,9 +6405,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) goto do_lcall; case 0xe9: /* jmp im */ if (dflag) - tval = (int32_t)insn_get(s, OT_LONG); + tval = (int32_t)insn_get(env, s, OT_LONG); else - tval = (int16_t)insn_get(s, OT_WORD); + tval = (int16_t)insn_get(env, s, OT_WORD); tval += s->pc - s->cs_base; if (s->dflag == 0) tval &= 0xffff; @@ -6418,28 +6422,28 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (CODE64(s)) goto illegal_op; ot = dflag ? OT_LONG : OT_WORD; - offset = insn_get(s, ot); - selector = insn_get(s, OT_WORD); + offset = insn_get(env, s, ot); + selector = insn_get(env, s, OT_WORD); gen_op_movl_T0_im(selector); gen_op_movl_T1_imu(offset); } goto do_ljmp; case 0xeb: /* jmp Jb */ - tval = (int8_t)insn_get(s, OT_BYTE); + tval = (int8_t)insn_get(env, s, OT_BYTE); tval += s->pc - s->cs_base; if (s->dflag == 0) tval &= 0xffff; gen_jmp(s, tval); break; case 0x70 ... 0x7f: /* jcc Jb */ - tval = (int8_t)insn_get(s, OT_BYTE); + tval = (int8_t)insn_get(env, s, OT_BYTE); goto do_jcc; case 0x180 ... 0x18f: /* jcc Jv */ if (dflag) { - tval = (int32_t)insn_get(s, OT_LONG); + tval = (int32_t)insn_get(env, s, OT_LONG); } else { - tval = (int16_t)insn_get(s, OT_WORD); + tval = (int16_t)insn_get(env, s, OT_WORD); } do_jcc: next_eip = s->pc - s->cs_base; @@ -6450,9 +6454,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) break; case 0x190 ... 0x19f: /* setcc Gv */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); gen_setcc(s, b); - gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1); break; case 0x140 ... 0x14f: /* cmov Gv, Ev */ { @@ -6460,12 +6464,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) TCGv t0; ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; t0 = tcg_temp_local_new(); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); } else { rm = (modrm & 7) | REX_B(s); @@ -6618,19 +6622,19 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* bit operations */ case 0x1ba: /* bt/bts/btr/btc Gv, im */ ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); op = (modrm >> 3) & 7; mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); if (mod != 3) { s->rip_offset = 1; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_T0_A0(ot + s->mem_index); } else { gen_op_mov_TN_reg(ot, 0, rm); } /* load shift */ - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); gen_op_movl_T1_im(val); if (op < 4) goto illegal_op; @@ -6649,13 +6653,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) op = 3; do_btx: ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); gen_op_mov_TN_reg(OT_LONG, 1, reg); if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); /* specific case: we need to add a displacement */ gen_exts(ot, cpu_T[1]); tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot); @@ -6710,9 +6714,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) TCGv t0; ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; - gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s,modrm, ot, OR_TMP0, 0); gen_extu(ot, cpu_T[0]); t0 = tcg_temp_local_new(); tcg_gen_mov_tl(t0, cpu_T[0]); @@ -6782,7 +6786,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0xd4: /* aam */ if (CODE64(s)) goto illegal_op; - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); if (val == 0) { gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); } else { @@ -6793,7 +6797,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0xd5: /* aad */ if (CODE64(s)) goto illegal_op; - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); gen_helper_aad(cpu_env, tcg_const_i32(val)); s->cc_op = CC_OP_LOGICB; break; @@ -6827,7 +6831,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); break; case 0xcd: /* int N */ - val = cpu_ldub_code(cpu_single_env, s->pc++); + val = cpu_ldub_code(env, s->pc++); if (s->vm86 && s->iopl != 3) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { @@ -6849,7 +6853,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_debug(s, pc_start - s->cs_base); #else /* start debug */ - tb_flush(cpu_single_env); + tb_flush(env); cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM); #endif break; @@ -6897,13 +6901,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (CODE64(s)) goto illegal_op; ot = dflag ? OT_LONG : OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = (modrm >> 3) & 7; mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; gen_op_mov_TN_reg(ot, 0, reg); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); if (ot == OT_WORD) { @@ -6944,7 +6948,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) { int l1, l2, l3; - tval = (int8_t)insn_get(s, OT_BYTE); + tval = (int8_t)insn_get(env, s, OT_BYTE); next_eip = s->pc - s->cs_base; tval += next_eip; if (s->dflag == 0) @@ -7024,7 +7028,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) break; case 0x134: /* sysenter */ /* For Intel SYSENTER is valid on 64-bit */ - if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) + if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); @@ -7037,7 +7041,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) break; case 0x135: /* sysexit */ /* For Intel SYSEXIT is valid on 64-bit */ - if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) + if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1) goto illegal_op; if (!s->pe) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); @@ -7088,7 +7092,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; case 0x100: - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; op = (modrm >> 3) & 7; switch(op) { @@ -7100,7 +7104,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_WORD; if (mod == 3) ot += s->dflag; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 2: /* lldt */ if (!s->pe || s->vm86) @@ -7109,7 +7113,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE); - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_lldt(cpu_env, cpu_tmp2_i32); @@ -7123,7 +7127,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) ot = OT_WORD; if (mod == 3) ot += s->dflag; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1); break; case 3: /* ltr */ if (!s->pe || s->vm86) @@ -7132,7 +7136,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE); - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); gen_jmp_im(pc_start - s->cs_base); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); gen_helper_ltr(cpu_env, cpu_tmp2_i32); @@ -7142,7 +7146,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 5: /* verw */ if (!s->pe || s->vm86) goto illegal_op; - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); if (op == 4) { @@ -7157,7 +7161,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; case 0x101: - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; op = (modrm >> 3) & 7; rm = modrm & 7; @@ -7166,7 +7170,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (mod == 3) goto illegal_op; gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit)); gen_op_st_T0_A0(OT_WORD + s->mem_index); gen_add_A0_im(s, 2); @@ -7230,7 +7234,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } } else { /* sidt */ gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit)); gen_op_st_T0_A0(OT_WORD + s->mem_index); gen_add_A0_im(s, 2); @@ -7332,7 +7336,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } else { gen_svm_check_intercept(s, pc_start, op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_T1_A0(OT_WORD + s->mem_index); gen_add_A0_im(s, 2); gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index); @@ -7354,14 +7358,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) #else tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0])); #endif - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1); break; case 6: /* lmsw */ if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0); - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); gen_helper_lmsw(cpu_env, cpu_T[0]); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); @@ -7375,7 +7379,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_helper_invlpg(cpu_env, cpu_A0); gen_jmp_im(s->pc - s->cs_base); gen_eob(s); @@ -7442,7 +7446,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* d_ot is the size of destination */ d_ot = dflag + OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; mod = (modrm >> 6) & 3; rm = (modrm & 7) | REX_B(s); @@ -7454,7 +7458,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]); gen_op_mov_reg_T0(d_ot, reg); } else { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (d_ot == OT_QUAD) { gen_op_lds_T0_A0(OT_LONG + s->mem_index); } else { @@ -7474,12 +7478,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) t1 = tcg_temp_local_new(); t2 = tcg_temp_local_new(); ot = OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = (modrm >> 3) & 7; mod = (modrm >> 6) & 3; rm = modrm & 7; if (mod != 3) { - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); gen_op_ld_v(ot + s->mem_index, t0, cpu_A0); a0 = tcg_temp_local_new(); tcg_gen_mov_tl(a0, cpu_A0); @@ -7522,9 +7526,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (!s->pe || s->vm86) goto illegal_op; ot = dflag ? OT_LONG : OT_WORD; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; - gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0); t0 = tcg_temp_local_new(); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); @@ -7543,7 +7547,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; case 0x118: - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; op = (modrm >> 3) & 7; switch(op) { @@ -7553,24 +7557,24 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 3: /* prefetchnt0 */ if (mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); /* nothing more to do */ break; default: /* nop (multi byte) */ - gen_nop_modrm(s, modrm); + gen_nop_modrm(env, s, modrm); break; } break; case 0x119 ... 0x11f: /* nop (multi byte) */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); - gen_nop_modrm(s, modrm); + modrm = cpu_ldub_code(env, s->pc++); + gen_nop_modrm(env, s, modrm); break; case 0x120: /* mov reg, crN */ case 0x122: /* mov crN, reg */ if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). * AMD documentation (24594.pdf) and testing of * intel 386 and 486 processors all show that the mod bits @@ -7616,7 +7620,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (s->cpl != 0) { gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); } else { - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); /* Ignore the mod bits (assume (modrm&0xc0)==0xc0). * AMD documentation (24594.pdf) and testing of * intel 386 and 486 processors all show that the mod bits @@ -7660,16 +7664,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (!(s->cpuid_features & CPUID_SSE2)) goto illegal_op; ot = s->dflag == 2 ? OT_QUAD : OT_LONG; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; reg = ((modrm >> 3) & 7) | rex_r; /* generate a generic store */ - gen_ldst_modrm(s, modrm, ot, reg, 1); + gen_ldst_modrm(env, s, modrm, ot, reg, 1); break; case 0x1ae: - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; op = (modrm >> 3) & 7; switch(op) { @@ -7681,7 +7685,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); break; } - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); @@ -7695,7 +7699,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); break; } - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (s->cc_op != CC_OP_DYNAMIC) gen_op_set_cc_op(s->cc_op); gen_jmp_im(pc_start - s->cs_base); @@ -7711,7 +7715,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) || mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); if (op == 2) { gen_op_ld_T0_A0(OT_LONG + s->mem_index); tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]); @@ -7736,7 +7740,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) /* clflush */ if (!(s->cpuid_features & CPUID_CLFLUSH)) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); } break; default: @@ -7744,11 +7748,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) } break; case 0x10d: /* 3DNow! prefetch(w) */ - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); mod = (modrm >> 6) & 3; if (mod == 3) goto illegal_op; - gen_lea_modrm(s, modrm, ®_addr, &offset_addr); + gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr); /* ignore for now */ break; case 0x1aa: /* rsm */ @@ -7767,7 +7771,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT)) goto illegal_op; - modrm = cpu_ldub_code(cpu_single_env, s->pc++); + modrm = cpu_ldub_code(env, s->pc++); reg = ((modrm >> 3) & 7) | rex_r; if (s->prefix & PREFIX_DATA) @@ -7777,7 +7781,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) else ot = OT_QUAD; - gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0); + gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0); gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot)); gen_op_mov_reg_T0(ot, reg); @@ -7794,7 +7798,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start) case 0x1c2: case 0x1c4 ... 0x1c6: case 0x1d0 ... 0x1fe: - gen_sse(s, b, pc_start, rex_r); + gen_sse(env, s, b, pc_start, rex_r); break; default: goto illegal_op; @@ -7994,7 +7998,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); - pc_ptr = disas_insn(dc, pc_ptr); + pc_ptr = disas_insn(env, dc, pc_ptr); num_insns++; /* stop translation if indicated */ if (dc->is_jmp) -- 1.7.2.5 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 5/5] target-i386: avoid using cpu_single_env 2012-10-28 15:03 ` [Qemu-devel] [PATCH 5/5] target-i386: " Blue Swirl @ 2012-10-31 3:41 ` Andreas Färber 0 siblings, 0 replies; 19+ messages in thread From: Andreas Färber @ 2012-10-31 3:41 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel Am 28.10.2012 16:03, schrieb Blue Swirl: > Pass around CPUState instead of using global cpu_single_env. > > Signed-off-by: Blue Swirl <blauwirbel@gmail.com> > --- > target-i386/translate.c | 440 ++++++++++++++++++++++++----------------------- > 1 files changed, 222 insertions(+), 218 deletions(-) Reviewed-by: Andreas Färber <afaerber@suse.de> with the repetitive remark on "CPUState". Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup 2012-10-28 15:03 [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Blue Swirl ` (4 preceding siblings ...) 2012-10-28 15:03 ` [Qemu-devel] [PATCH 5/5] target-i386: " Blue Swirl @ 2012-10-31 3:59 ` Andreas Färber 5 siblings, 0 replies; 19+ messages in thread From: Andreas Färber @ 2012-10-31 3:59 UTC (permalink / raw) To: Blue Swirl; +Cc: qemu-devel Am 28.10.2012 16:03, schrieb Blue Swirl: > In some cases it's pretty easy to avoid using global > cpu_single_env since a local version is available. > > Blue Swirl (5): > disas: avoid using cpu_single_env > kvm: avoid using cpu_single_env > target-unicore32: avoid using cpu_single_env > target-xtensa: avoid using cpu_single_env > target-i386: avoid using cpu_single_env Each of these has been reviewed by at least a second pair of eyes now. I recently stumbled over cpu_single_env as an obstacle to actually using CPUState somewhere, so I'm happy about removing some occurrences. Have you considered using FooCPU arguments in target-specific code (e.g., last three) and decided against it? I checked that they build bisectably and still apply on top of my PULL; you being a committer, are you planning to apply these directly, or should I queue them for the next CPU pull and fix the messages myself? Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2012-10-31 4:03 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
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2012-10-28 15:03 [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Blue Swirl
2012-10-28 15:03 ` [Qemu-devel] [PATCH 1/5] disas: avoid using cpu_single_env Blue Swirl
2012-10-29 4:45 ` Richard Henderson
2012-10-29 9:06 ` Andreas Färber
2012-10-29 14:36 ` Aurelien Jarno
[not found] ` <92f1e4fe1bf16c76d53eef0dcf9389865a66e0dd.1351436501.git.blauwirbel@gm ail.com>
2012-10-31 4:20 ` guanxuetao
2012-10-28 15:03 ` [PATCH 2/5] kvm: " Blue Swirl
2012-10-28 15:03 ` [Qemu-devel] " Blue Swirl
2012-10-31 3:25 ` Andreas Färber
2012-10-31 3:25 ` Andreas Färber
2012-10-28 15:03 ` [Qemu-devel] [PATCH 3/5] target-unicore32: " Blue Swirl
[not found] ` <5cd15b325c56b2b7fe0b315c52a9b5094ce73633.1351436501.git.blauwirbel@gm ail.com>
2012-10-31 2:55 ` guanxuetao
2012-10-31 3:26 ` Andreas Färber
2012-10-28 15:03 ` [Qemu-devel] [PATCH 4/5] target-xtensa: " Blue Swirl
2012-10-29 5:58 ` Max Filippov
2012-10-31 3:28 ` Andreas Färber
2012-10-28 15:03 ` [Qemu-devel] [PATCH 5/5] target-i386: " Blue Swirl
2012-10-31 3:41 ` Andreas Färber
2012-10-31 3:59 ` [Qemu-devel] [PATCH 0/5] cpu_single_env cleanup Andreas Färber
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