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* [PATCH] drm/radeon: Fix num_banks calculation for SI
@ 2014-04-22  7:53 Michel Dänzer
  2014-04-22 12:51 ` Alex Deucher
  0 siblings, 1 reply; 4+ messages in thread
From: Michel Dänzer @ 2014-04-22  7:53 UTC (permalink / raw)
  To: dri-devel

From: Michel Dänzer <michel.daenzer@amd.com>

The way the tile mode array index was calculated only makes sense for
the CIK specific macrotile mode array. For SI, we need to use one of the
tile mode array indices reserved for displayable surfaces.

This happened to result in correct display most if not all of the time
because most of the SI tiling modes use the same number of banks.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---
 drivers/gpu/drm/radeon/atombios_crtc.c | 46 +++++++++++++++++++++++-----------
 1 file changed, 31 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index fb187c7..2b8039b 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1177,27 +1177,43 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
 
 		/* Set NUM_BANKS. */
 		if (rdev->family >= CHIP_TAHITI) {
-			unsigned tileb, index, num_banks, tile_split_bytes;
+			unsigned index, num_banks;
 
-			/* Calculate the macrotile mode index. */
-			tile_split_bytes = 64 << tile_split;
-			tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
-			tileb = min(tile_split_bytes, tileb);
+			if (rdev->family >= CHIP_BONAIRE) {
+				unsigned tileb, tile_split_bytes;
 
-			for (index = 0; tileb > 64; index++) {
-				tileb >>= 1;
-			}
+				/* Calculate the macrotile mode index. */
+				tile_split_bytes = 64 << tile_split;
+				tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
+				tileb = min(tile_split_bytes, tileb);
 
-			if (index >= 16) {
-				DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
-					  target_fb->bits_per_pixel, tile_split);
-				return -EINVAL;
-			}
+				for (index = 0; tileb > 64; index++)
+					tileb >>= 1;
+
+				if (index >= 16) {
+					DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
+						  target_fb->bits_per_pixel, tile_split);
+					return -EINVAL;
+				}
 
-			if (rdev->family >= CHIP_BONAIRE)
 				num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
-			else
+			} else {
+			  	switch (target_fb->bits_per_pixel) {
+				case 8:
+					index = 10;
+					break;
+				case 16:
+					index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
+					break;
+				default:
+				case 32:
+					index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
+					break;
+				}
+
 				num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
+			}
+
 			fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
 		} else {
 			/* NI and older. */
-- 
1.9.2

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^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/radeon: Fix num_banks calculation for SI
  2014-04-22  7:53 [PATCH] drm/radeon: Fix num_banks calculation for SI Michel Dänzer
@ 2014-04-22 12:51 ` Alex Deucher
  2014-05-02  2:20   ` Michel Dänzer
  0 siblings, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2014-04-22 12:51 UTC (permalink / raw)
  To: Michel Dänzer; +Cc: Maling list - DRI developers

On Tue, Apr 22, 2014 at 3:53 AM, Michel Dänzer <michel@daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
>
> The way the tile mode array index was calculated only makes sense for
> the CIK specific macrotile mode array. For SI, we need to use one of the
> tile mode array indices reserved for displayable surfaces.
>
> This happened to result in correct display most if not all of the time
> because most of the SI tiling modes use the same number of banks.
>
> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

Thanks for doing this.

Reviewed-by:  Alex Deucher <alexander.deucher@amd.com>

Christian, can you cc stable when you pick this up?

Alex

> ---
>  drivers/gpu/drm/radeon/atombios_crtc.c | 46 +++++++++++++++++++++++-----------
>  1 file changed, 31 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
> index fb187c7..2b8039b 100644
> --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> @@ -1177,27 +1177,43 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
>
>                 /* Set NUM_BANKS. */
>                 if (rdev->family >= CHIP_TAHITI) {
> -                       unsigned tileb, index, num_banks, tile_split_bytes;
> +                       unsigned index, num_banks;
>
> -                       /* Calculate the macrotile mode index. */
> -                       tile_split_bytes = 64 << tile_split;
> -                       tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
> -                       tileb = min(tile_split_bytes, tileb);
> +                       if (rdev->family >= CHIP_BONAIRE) {
> +                               unsigned tileb, tile_split_bytes;
>
> -                       for (index = 0; tileb > 64; index++) {
> -                               tileb >>= 1;
> -                       }
> +                               /* Calculate the macrotile mode index. */
> +                               tile_split_bytes = 64 << tile_split;
> +                               tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
> +                               tileb = min(tile_split_bytes, tileb);
>
> -                       if (index >= 16) {
> -                               DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
> -                                         target_fb->bits_per_pixel, tile_split);
> -                               return -EINVAL;
> -                       }
> +                               for (index = 0; tileb > 64; index++)
> +                                       tileb >>= 1;
> +
> +                               if (index >= 16) {
> +                                       DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
> +                                                 target_fb->bits_per_pixel, tile_split);
> +                                       return -EINVAL;
> +                               }
>
> -                       if (rdev->family >= CHIP_BONAIRE)
>                                 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
> -                       else
> +                       } else {
> +                               switch (target_fb->bits_per_pixel) {
> +                               case 8:
> +                                       index = 10;
> +                                       break;
> +                               case 16:
> +                                       index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
> +                                       break;
> +                               default:
> +                               case 32:
> +                                       index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
> +                                       break;
> +                               }
> +
>                                 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
> +                       }
> +
>                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
>                 } else {
>                         /* NI and older. */
> --
> 1.9.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/radeon: Fix num_banks calculation for SI
  2014-04-22 12:51 ` Alex Deucher
@ 2014-05-02  2:20   ` Michel Dänzer
  2014-05-02 10:16     ` Christian König
  0 siblings, 1 reply; 4+ messages in thread
From: Michel Dänzer @ 2014-05-02  2:20 UTC (permalink / raw)
  To: Alex Deucher; +Cc: Maling list - DRI developers

On 22.04.2014 21:51, Alex Deucher wrote:
> On Tue, Apr 22, 2014 at 3:53 AM, Michel Dänzer <michel@daenzer.net> wrote:
>> From: Michel Dänzer <michel.daenzer@amd.com>
>>
>> The way the tile mode array index was calculated only makes sense for
>> the CIK specific macrotile mode array. For SI, we need to use one of the
>> tile mode array indices reserved for displayable surfaces.
>>
>> This happened to result in correct display most if not all of the time
>> because most of the SI tiling modes use the same number of banks.
>>
>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
> 
> Thanks for doing this.
> 
> Reviewed-by:  Alex Deucher <alexander.deucher@amd.com>

Thanks Alex.

> Christian, can you cc stable when you pick this up?

Actually, I deliberately left that out, as the previous code mostly
seems to calculate the same result in practice, just not in the correct
way. So I'm not sure it's worth taking any risk for stable, however
small it may be. We can still nominate it for stable later if it turns
out to fix an actual problem in practice.


Anyway, I can't seem to find this patch in any DRM tree yet. Christian,
did you see it?


-- 
Earthling Michel Dänzer            |                  http://www.amd.com
Libre software enthusiast          |                Mesa and X developer
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^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH] drm/radeon: Fix num_banks calculation for SI
  2014-05-02  2:20   ` Michel Dänzer
@ 2014-05-02 10:16     ` Christian König
  0 siblings, 0 replies; 4+ messages in thread
From: Christian König @ 2014-05-02 10:16 UTC (permalink / raw)
  To: Michel Dänzer, Alex Deucher; +Cc: Maling list - DRI developers

Am 02.05.2014 04:20, schrieb Michel Dänzer:
> On 22.04.2014 21:51, Alex Deucher wrote:
>> On Tue, Apr 22, 2014 at 3:53 AM, Michel Dänzer <michel@daenzer.net> wrote:
>>> From: Michel Dänzer <michel.daenzer@amd.com>
>>>
>>> The way the tile mode array index was calculated only makes sense for
>>> the CIK specific macrotile mode array. For SI, we need to use one of the
>>> tile mode array indices reserved for displayable surfaces.
>>>
>>> This happened to result in correct display most if not all of the time
>>> because most of the SI tiling modes use the same number of banks.
>>>
>>> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
>> Thanks for doing this.
>>
>> Reviewed-by:  Alex Deucher <alexander.deucher@amd.com>
> Thanks Alex.
>
>> Christian, can you cc stable when you pick this up?
> Actually, I deliberately left that out, as the previous code mostly
> seems to calculate the same result in practice, just not in the correct
> way. So I'm not sure it's worth taking any risk for stable, however
> small it may be. We can still nominate it for stable later if it turns
> out to fix an actual problem in practice.
>
>
> Anyway, I can't seem to find this patch in any DRM tree yet. Christian,
> did you see it?
I've seen this patch, but somehow thought that it was for libdrm and not 
the kernel module.

Nevermind I'm going to push it with the next drm-fixes.

Christian.
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^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2014-05-02 10:16 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2014-04-22  7:53 [PATCH] drm/radeon: Fix num_banks calculation for SI Michel Dänzer
2014-04-22 12:51 ` Alex Deucher
2014-05-02  2:20   ` Michel Dänzer
2014-05-02 10:16     ` Christian König

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