[PATCHv2 00/15] ARM: mvebu: Armada 39x basic support, and preparatory cleanups

[PATCHv2 00/15] ARM: mvebu: Armada 39x basic support, and preparatory cleanups

[Thomas Petazzoni]

Hello,

This is the second version of the patch series adding Armada 39x basic
support.

This set of patches add basic support for a new family of Marvell EBU
processors: the Armada 39x. They are based on Cortex-A9 (like Armada
375 and 38x) and the most important new feature is probably the
addition of 10 GbE support.

See http://www.marvell.com/embedded-processors/armada-39x/ for a basic
introduction.

Note that this web page talks about an Armada 395 and Armada 398, but
so far the technical documentation we have been given access to only
describes Armada 390 and Armada 398, so this series supports only
Armada 390 and Armada 398 so far. Support for Armada 395 might be
added in the future, once we get access to the appropriate technical
details.

Compared to the previous version of this patch series, this version
brings a number of changes:

 - At the SoC level, add the description of SPI controller 0 and 1,
   NAND flash controller, SDHCI controller, Core Divider Clock (needed
   by the NAND flash controller), the main PLL clock (needed by the
   Core Divider Clock) and the XOR engines.

 - At the board level, add the description of the SPI flash connected
   to SPI bus 1, which contains the bootloader, and the description of
   the NAND flash.

 - Fix space vs. tab.

 - Use __initconst when defining the dt_compat table for Armada
   39x. Suggested by Stephen Boyd.

 - Fix typo in commit log of "ARM: mvebu: add core support for Armada
   39x", noticed by Maxime Ripard.

 - Remove earlyprintk from /chosen/bootargs. Suggested by Andrew Lunn.

 - Add aliases for uart[0-3]. Suggested by Andrew Lunn.

 - Add /chosen/stdout-path to Armada 398 DB DT. Suggested by Andrew
   Lunn.

 - Move pinctrl configurations at the SoC level. Suggested by Andrew
   Lunn.

 - Add several preparation/cleanup patches not related to Armada 39x
   directly, but whose topics were found while working on Armada 39x
   support:

     - Add __initconst to all dt_compat table in mach-mvebu.
     - Fixup usb@ unit address on Armada 38x
     - Add stdout-path to all armada-*.dts
     - Use GIC and IRQ macros in SDHCI definition of Armada 38x
     - Add missing UART alias on Armada 38x

This branch is based on mvebu/for-next, and is obviously 3.21
material. Such an early posting is done to gather early review and
feedback. I'll repost an updated version when 3.20-rc1 / 4.0-rc1
lands.

Best regards,

Thomas

Thomas Petazzoni (15):
  ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat
    tables
  ARM: mvebu: fix usb@ unit address on Armada 38x to match register
    address
  ARM: mvebu: add missing UART alias on Armada 38x
  ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x
  ARM: mvebu: add stdout-path to all armada-*.dts
  devicetree: bindings: add DT binding for the Marvell Armada 39x SoC
    family
  devicetree: bindings: update DT bindings for Marvell EBU clock support
  devicetree: bindings: add Device Tree bindings for Armada 39x
    pin-muxing controller
  devicetree: bindings: add new SMP enable method for Marvell Armada 39x
  clk: mvebu: extend common code to allow an optional refclk
  clk: mvebu: add Marvell Armada 39x driver
  pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x
  ARM: mvebu: add core support for Armada 39x
  ARM: mvebu: add Device Tree files for Armada 39x SoC and board
  Documentation: arm: update supported Marvell EBU processors

 Documentation/arm/Marvell/README                   |   5 +
 .../devicetree/bindings/arm/armada-39x.txt         |  20 +
 Documentation/devicetree/bindings/arm/cpus.txt     |   1 +
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   9 +
 .../bindings/clock/mvebu-gated-clock.txt           |  15 +-
 .../pinctrl/marvell,armada-39x-pinctrl.txt         |  78 ++++
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/armada-370-db.dts                |   1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |   1 +
 arch/arm/boot/dts/armada-370-netgear-rn102.dts     |   1 +
 arch/arm/boot/dts/armada-370-netgear-rn104.dts     |   1 +
 arch/arm/boot/dts/armada-370-rd.dts                |   1 +
 arch/arm/boot/dts/armada-375-db.dts                |   1 +
 arch/arm/boot/dts/armada-388-db.dts                |   3 +-
 arch/arm/boot/dts/armada-388-gp.dts                |   2 +-
 arch/arm/boot/dts/armada-388-rd.dts                |   1 +
 arch/arm/boot/dts/armada-38x.dtsi                  |   6 +-
 .../dts/{armada-xp-matrix.dts => armada-390.dtsi}  |  71 +---
 .../dts/{armada-388-db.dts => armada-398-db.dts}   | 112 ++---
 .../dts/{armada-xp-matrix.dts => armada-398.dtsi}  |  70 +--
 .../boot/dts/{armada-38x.dtsi => armada-39x.dtsi}  | 472 +++++++++------------
 arch/arm/boot/dts/armada-xp-axpwifiap.dts          |   1 +
 arch/arm/boot/dts/armada-xp-db.dts                 |   1 +
 arch/arm/boot/dts/armada-xp-gp.dts                 |   1 +
 arch/arm/boot/dts/armada-xp-matrix.dts             |   1 +
 arch/arm/boot/dts/armada-xp-netgear-rn2120.dts     |   1 +
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   |   1 +
 arch/arm/mach-mvebu/Kconfig                        |  14 +
 arch/arm/mach-mvebu/board-v7.c                     |  20 +-
 arch/arm/mach-mvebu/dove.c                         |   2 +-
 arch/arm/mach-mvebu/kirkwood.c                     |   2 +-
 arch/arm/mach-mvebu/platsmp-a9.c                   |   2 +
 drivers/clk/mvebu/Kconfig                          |   4 +
 drivers/clk/mvebu/Makefile                         |   1 +
 drivers/clk/mvebu/armada-39x.c                     | 156 +++++++
 drivers/clk/mvebu/common.c                         |  17 +
 drivers/clk/mvebu/common.h                         |   1 +
 drivers/pinctrl/mvebu/Kconfig                      |   4 +
 drivers/pinctrl/mvebu/Makefile                     |   1 +
 drivers/pinctrl/mvebu/pinctrl-armada-39x.c         | 432 +++++++++++++++++++
 40 files changed, 1045 insertions(+), 490 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-39x.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
 copy arch/arm/boot/dts/{armada-xp-matrix.dts => armada-390.dtsi} (61%)
 copy arch/arm/boot/dts/{armada-388-db.dts => armada-398-db.dts} (70%)
 copy arch/arm/boot/dts/{armada-xp-matrix.dts => armada-398.dtsi} (61%)
 copy arch/arm/boot/dts/{armada-38x.dtsi => armada-39x.dtsi} (53%)
 create mode 100644 drivers/clk/mvebu/armada-39x.c
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-39x.c

-- 
2.1.0

[PATCHv2 00/15] ARM: mvebu: Armada 39x basic support, and preparatory cleanups

[Thomas Petazzoni]

Hello,

This is the second version of the patch series adding Armada 39x basic
support.

This set of patches add basic support for a new family of Marvell EBU
processors: the Armada 39x. They are based on Cortex-A9 (like Armada
375 and 38x) and the most important new feature is probably the
addition of 10 GbE support.

See http://www.marvell.com/embedded-processors/armada-39x/ for a basic
introduction.

Note that this web page talks about an Armada 395 and Armada 398, but
so far the technical documentation we have been given access to only
describes Armada 390 and Armada 398, so this series supports only
Armada 390 and Armada 398 so far. Support for Armada 395 might be
added in the future, once we get access to the appropriate technical
details.

Compared to the previous version of this patch series, this version
brings a number of changes:

 - At the SoC level, add the description of SPI controller 0 and 1,
   NAND flash controller, SDHCI controller, Core Divider Clock (needed
   by the NAND flash controller), the main PLL clock (needed by the
   Core Divider Clock) and the XOR engines.

 - At the board level, add the description of the SPI flash connected
   to SPI bus 1, which contains the bootloader, and the description of
   the NAND flash.

 - Fix space vs. tab.

 - Use __initconst when defining the dt_compat table for Armada
   39x. Suggested by Stephen Boyd.

 - Fix typo in commit log of "ARM: mvebu: add core support for Armada
   39x", noticed by Maxime Ripard.

 - Remove earlyprintk from /chosen/bootargs. Suggested by Andrew Lunn.

 - Add aliases for uart[0-3]. Suggested by Andrew Lunn.

 - Add /chosen/stdout-path to Armada 398 DB DT. Suggested by Andrew
   Lunn.

 - Move pinctrl configurations at the SoC level. Suggested by Andrew
   Lunn.

 - Add several preparation/cleanup patches not related to Armada 39x
   directly, but whose topics were found while working on Armada 39x
   support:

     - Add __initconst to all dt_compat table in mach-mvebu.
     - Fixup usb@ unit address on Armada 38x
     - Add stdout-path to all armada-*.dts
     - Use GIC and IRQ macros in SDHCI definition of Armada 38x
     - Add missing UART alias on Armada 38x

This branch is based on mvebu/for-next, and is obviously 3.21
material. Such an early posting is done to gather early review and
feedback. I'll repost an updated version when 3.20-rc1 / 4.0-rc1
lands.

Best regards,

Thomas

Thomas Petazzoni (15):
  ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat
    tables
  ARM: mvebu: fix usb@ unit address on Armada 38x to match register
    address
  ARM: mvebu: add missing UART alias on Armada 38x
  ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x
  ARM: mvebu: add stdout-path to all armada-*.dts
  devicetree: bindings: add DT binding for the Marvell Armada 39x SoC
    family
  devicetree: bindings: update DT bindings for Marvell EBU clock support
  devicetree: bindings: add Device Tree bindings for Armada 39x
    pin-muxing controller
  devicetree: bindings: add new SMP enable method for Marvell Armada 39x
  clk: mvebu: extend common code to allow an optional refclk
  clk: mvebu: add Marvell Armada 39x driver
  pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x
  ARM: mvebu: add core support for Armada 39x
  ARM: mvebu: add Device Tree files for Armada 39x SoC and board
  Documentation: arm: update supported Marvell EBU processors

 Documentation/arm/Marvell/README                   |   5 +
 .../devicetree/bindings/arm/armada-39x.txt         |  20 +
 Documentation/devicetree/bindings/arm/cpus.txt     |   1 +
 .../devicetree/bindings/clock/mvebu-core-clock.txt |   9 +
 .../bindings/clock/mvebu-gated-clock.txt           |  15 +-
 .../pinctrl/marvell,armada-39x-pinctrl.txt         |  78 ++++
 arch/arm/boot/dts/Makefile                         |   2 +
 arch/arm/boot/dts/armada-370-db.dts                |   1 +
 arch/arm/boot/dts/armada-370-mirabox.dts           |   1 +
 arch/arm/boot/dts/armada-370-netgear-rn102.dts     |   1 +
 arch/arm/boot/dts/armada-370-netgear-rn104.dts     |   1 +
 arch/arm/boot/dts/armada-370-rd.dts                |   1 +
 arch/arm/boot/dts/armada-375-db.dts                |   1 +
 arch/arm/boot/dts/armada-388-db.dts                |   3 +-
 arch/arm/boot/dts/armada-388-gp.dts                |   2 +-
 arch/arm/boot/dts/armada-388-rd.dts                |   1 +
 arch/arm/boot/dts/armada-38x.dtsi                  |   6 +-
 .../dts/{armada-xp-matrix.dts => armada-390.dtsi}  |  71 +---
 .../dts/{armada-388-db.dts => armada-398-db.dts}   | 112 ++---
 .../dts/{armada-xp-matrix.dts => armada-398.dtsi}  |  70 +--
 .../boot/dts/{armada-38x.dtsi => armada-39x.dtsi}  | 472 +++++++++------------
 arch/arm/boot/dts/armada-xp-axpwifiap.dts          |   1 +
 arch/arm/boot/dts/armada-xp-db.dts                 |   1 +
 arch/arm/boot/dts/armada-xp-gp.dts                 |   1 +
 arch/arm/boot/dts/armada-xp-matrix.dts             |   1 +
 arch/arm/boot/dts/armada-xp-netgear-rn2120.dts     |   1 +
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   |   1 +
 arch/arm/mach-mvebu/Kconfig                        |  14 +
 arch/arm/mach-mvebu/board-v7.c                     |  20 +-
 arch/arm/mach-mvebu/dove.c                         |   2 +-
 arch/arm/mach-mvebu/kirkwood.c                     |   2 +-
 arch/arm/mach-mvebu/platsmp-a9.c                   |   2 +
 drivers/clk/mvebu/Kconfig                          |   4 +
 drivers/clk/mvebu/Makefile                         |   1 +
 drivers/clk/mvebu/armada-39x.c                     | 156 +++++++
 drivers/clk/mvebu/common.c                         |  17 +
 drivers/clk/mvebu/common.h                         |   1 +
 drivers/pinctrl/mvebu/Kconfig                      |   4 +
 drivers/pinctrl/mvebu/Makefile                     |   1 +
 drivers/pinctrl/mvebu/pinctrl-armada-39x.c         | 432 +++++++++++++++++++
 40 files changed, 1045 insertions(+), 490 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-39x.txt
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
 copy arch/arm/boot/dts/{armada-xp-matrix.dts => armada-390.dtsi} (61%)
 copy arch/arm/boot/dts/{armada-388-db.dts => armada-398-db.dts} (70%)
 copy arch/arm/boot/dts/{armada-xp-matrix.dts => armada-398.dtsi} (61%)
 copy arch/arm/boot/dts/{armada-38x.dtsi => armada-39x.dtsi} (53%)
 create mode 100644 drivers/clk/mvebu/armada-39x.c
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-39x.c

-- 
2.1.0

[PATCHv2 01/15] ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat tables

[Thomas Petazzoni]

As suggested by Stephen Boyd, this commit adds the __initconst
specifier to the dt_compat table declarations used by the
DT_MACHINE_START structures in mach-mvebu land.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 arch/arm/mach-mvebu/board-v7.c | 6 +++---
 arch/arm/mach-mvebu/dove.c     | 2 +-
 arch/arm/mach-mvebu/kirkwood.c | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 89a139e..31b66f2 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -184,7 +184,7 @@ static void __init mvebu_dt_init(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char * const armada_370_xp_dt_compat[] = {
+static const char * const armada_370_xp_dt_compat[] __initconst = {
 	"marvell,armada-370-xp",
 	NULL,
 };
@@ -205,7 +205,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
 	.dt_compat	= armada_370_xp_dt_compat,
 MACHINE_END
 
-static const char * const armada_375_dt_compat[] = {
+static const char * const armada_375_dt_compat[] __initconst = {
 	"marvell,armada375",
 	NULL,
 };
@@ -219,7 +219,7 @@ DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
 	.dt_compat	= armada_375_dt_compat,
 MACHINE_END
 
-static const char * const armada_38x_dt_compat[] = {
+static const char * const armada_38x_dt_compat[] __initconst = {
 	"marvell,armada380",
 	"marvell,armada385",
 	NULL,
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index b50464e..5a17415 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -27,7 +27,7 @@ static void __init dove_init(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char * const dove_dt_compat[] = {
+static const char * const dove_dt_compat[] __initconst = {
 	"marvell,dove",
 	NULL
 };
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 6b53108..925f75f 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -186,7 +186,7 @@ static void __init kirkwood_dt_init(void)
 	of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
 }
 
-static const char * const kirkwood_dt_board_compat[] = {
+static const char * const kirkwood_dt_board_compat[] __initconst = {
 	"marvell,kirkwood",
 	NULL
 };
-- 
2.1.0

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[PATCHv2 01/15] ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat tables

[Thomas Petazzoni]

As suggested by Stephen Boyd, this commit adds the __initconst
specifier to the dt_compat table declarations used by the
DT_MACHINE_START structures in mach-mvebu land.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/board-v7.c | 6 +++---
 arch/arm/mach-mvebu/dove.c     | 2 +-
 arch/arm/mach-mvebu/kirkwood.c | 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 89a139e..31b66f2 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -184,7 +184,7 @@ static void __init mvebu_dt_init(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char * const armada_370_xp_dt_compat[] = {
+static const char * const armada_370_xp_dt_compat[] __initconst = {
 	"marvell,armada-370-xp",
 	NULL,
 };
@@ -205,7 +205,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
 	.dt_compat	= armada_370_xp_dt_compat,
 MACHINE_END
 
-static const char * const armada_375_dt_compat[] = {
+static const char * const armada_375_dt_compat[] __initconst = {
 	"marvell,armada375",
 	NULL,
 };
@@ -219,7 +219,7 @@ DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
 	.dt_compat	= armada_375_dt_compat,
 MACHINE_END
 
-static const char * const armada_38x_dt_compat[] = {
+static const char * const armada_38x_dt_compat[] __initconst = {
 	"marvell,armada380",
 	"marvell,armada385",
 	NULL,
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index b50464e..5a17415 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -27,7 +27,7 @@ static void __init dove_init(void)
 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 
-static const char * const dove_dt_compat[] = {
+static const char * const dove_dt_compat[] __initconst = {
 	"marvell,dove",
 	NULL
 };
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 6b53108..925f75f 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -186,7 +186,7 @@ static void __init kirkwood_dt_init(void)
 	of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
 }
 
-static const char * const kirkwood_dt_board_compat[] = {
+static const char * const kirkwood_dt_board_compat[] __initconst = {
 	"marvell,kirkwood",
 	NULL
 };
-- 
2.1.0

[PATCHv2 02/15] ARM: mvebu: fix usb@ unit address on Armada 38x to match register address

[Thomas Petazzoni]

On Marvell Armada 38x, the USB2 controller registers are at 0x58000,
so the corresponding Device Tree node should have a unit address of
58000, and not 50000. We were using 50000 due to an incorrect
copy/pastebin of Armada 370/XP code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-388-db.dts | 2 +-
 arch/arm/boot/dts/armada-388-gp.dts | 2 +-
 arch/arm/boot/dts/armada-38x.dtsi   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index 16512ef..af6c74e 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -99,7 +99,7 @@
 				phy-mode = "rgmii-id";
 			};
 
-			usb@50000 {
+			usb@58000 {
 				status = "ok";
 			};
 
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 590b383..3ff0573 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -135,7 +135,7 @@
 			};
 
 			/* CON4 */
-			usb@50000 {
+			usb@58000 {
 				vcc-supply = <&reg_usb2_0_vbus>;
 				status = "okay";
 			};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 54ebce7..96d7cf0 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -435,7 +435,7 @@
 				status = "disabled";
 			};
 
-			usb@50000 {
+			usb@58000 {
 				compatible = "marvell,orion-ehci";
 				reg = <0x58000 0x500>;
 				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.1.0

[PATCHv2 02/15] ARM: mvebu: fix usb@ unit address on Armada 38x to match register address

[Thomas Petazzoni]

On Marvell Armada 38x, the USB2 controller registers are at 0x58000,
so the corresponding Device Tree node should have a unit address of
58000, and not 50000. We were using 50000 due to an incorrect
copy/pastebin of Armada 370/XP code.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-388-db.dts | 2 +-
 arch/arm/boot/dts/armada-388-gp.dts | 2 +-
 arch/arm/boot/dts/armada-38x.dtsi   | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index 16512ef..af6c74e 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -99,7 +99,7 @@
 				phy-mode = "rgmii-id";
 			};
 
-			usb at 50000 {
+			usb at 58000 {
 				status = "ok";
 			};
 
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 590b383..3ff0573 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -135,7 +135,7 @@
 			};
 
 			/* CON4 */
-			usb at 50000 {
+			usb at 58000 {
 				vcc-supply = <&reg_usb2_0_vbus>;
 				status = "okay";
 			};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 54ebce7..96d7cf0 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -435,7 +435,7 @@
 				status = "disabled";
 			};
 
-			usb at 50000 {
+			usb at 58000 {
 				compatible = "marvell,orion-ehci";
 				reg = <0x58000 0x500>;
 				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
-- 
2.1.0

[PATCHv2 03/15] ARM: mvebu: add missing UART alias on Armada 38x

[Thomas Petazzoni]

The Armada 38x had an alias for UART0, but not UART1. This commit
fixes that.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 96d7cf0..8c76a8d 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -216,7 +216,7 @@
 				status = "disabled";
 			};
 
-			serial@12100 {
+			uart1: serial@12100 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0x12100 0x100>;
 				reg-shift = <2>;
-- 
2.1.0

[PATCHv2 03/15] ARM: mvebu: add missing UART alias on Armada 38x

[Thomas Petazzoni]

The Armada 38x had an alias for UART0, but not UART1. This commit
fixes that.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 96d7cf0..8c76a8d 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -216,7 +216,7 @@
 				status = "disabled";
 			};
 
-			serial at 12100 {
+			uart1: serial at 12100 {
 				compatible = "snps,dw-apb-uart";
 				reg = <0x12100 0x100>;
 				reg-shift = <2>;
-- 
2.1.0

[PATCHv2 04/15] ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x

[Thomas Petazzoni]

The Armada 38x SDHCI controller definition in the SoC Device Tree file
is using hardcoded values instead of the nice GIC and IRQ macros
provided by DT header files. This commit fixes that, which allows the
SDHCI interrupt definition to be consistent with was is done in the
rest of the file.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 8c76a8d..0f0cc41 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -542,7 +542,7 @@
 			sdhci@d8000 {
 				compatible = "marvell,armada-380-sdhci";
 				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
-				interrupts = <0 25 0x4>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&gateclk 17>;
 				mrvl,clk-delay-cycles = <0x1F>;
 				status = "disabled";
-- 
2.1.0

[PATCHv2 04/15] ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x

[Thomas Petazzoni]

The Armada 38x SDHCI controller definition in the SoC Device Tree file
is using hardcoded values instead of the nice GIC and IRQ macros
provided by DT header files. This commit fixes that, which allows the
SDHCI interrupt definition to be consistent with was is done in the
rest of the file.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 8c76a8d..0f0cc41 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -542,7 +542,7 @@
 			sdhci at d8000 {
 				compatible = "marvell,armada-380-sdhci";
 				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
-				interrupts = <0 25 0x4>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&gateclk 17>;
 				mrvl,clk-delay-cycles = <0x1F>;
 				status = "disabled";
-- 
2.1.0

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

This commit adds the stdout-path property in /chosen for all Armada
boards that were not yet carrying this property.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-370-db.dts              | 1 +
 arch/arm/boot/dts/armada-370-mirabox.dts         | 1 +
 arch/arm/boot/dts/armada-370-netgear-rn102.dts   | 1 +
 arch/arm/boot/dts/armada-370-netgear-rn104.dts   | 1 +
 arch/arm/boot/dts/armada-370-rd.dts              | 1 +
 arch/arm/boot/dts/armada-375-db.dts              | 1 +
 arch/arm/boot/dts/armada-388-db.dts              | 1 +
 arch/arm/boot/dts/armada-388-rd.dts              | 1 +
 arch/arm/boot/dts/armada-xp-axpwifiap.dts        | 1 +
 arch/arm/boot/dts/armada-xp-db.dts               | 1 +
 arch/arm/boot/dts/armada-xp-gp.dts               | 1 +
 arch/arm/boot/dts/armada-xp-matrix.dts           | 1 +
 arch/arm/boot/dts/armada-xp-netgear-rn2120.dts   | 1 +
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 1 +
 14 files changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e993c46..286bedd 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -56,6 +56,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index b10ceb4..ec77b86 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -52,6 +52,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 7c5c4ff..8c786cf 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -54,6 +54,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 1de53b5..1d64532 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -54,6 +54,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 6ae36a3..f40d35b 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -65,6 +65,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 0440891..033665c 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -56,6 +56,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index af6c74e..c56ccd74 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -55,6 +55,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index d99baac..e17edbb 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -56,6 +56,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index c1fbab2..a7fd474 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -60,6 +60,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 48bdafe..a12e159 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -65,6 +65,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 206aebb..8a2e49e 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -66,6 +66,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 56f958e..3e81f22 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -53,6 +53,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index a7ceafd..508a395 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -54,6 +54,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 0c76d9f..7b2ea2060 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -55,6 +55,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
-- 
2.1.0

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

This commit adds the stdout-path property in /chosen for all Armada
boards that were not yet carrying this property.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/armada-370-db.dts              | 1 +
 arch/arm/boot/dts/armada-370-mirabox.dts         | 1 +
 arch/arm/boot/dts/armada-370-netgear-rn102.dts   | 1 +
 arch/arm/boot/dts/armada-370-netgear-rn104.dts   | 1 +
 arch/arm/boot/dts/armada-370-rd.dts              | 1 +
 arch/arm/boot/dts/armada-375-db.dts              | 1 +
 arch/arm/boot/dts/armada-388-db.dts              | 1 +
 arch/arm/boot/dts/armada-388-rd.dts              | 1 +
 arch/arm/boot/dts/armada-xp-axpwifiap.dts        | 1 +
 arch/arm/boot/dts/armada-xp-db.dts               | 1 +
 arch/arm/boot/dts/armada-xp-gp.dts               | 1 +
 arch/arm/boot/dts/armada-xp-matrix.dts           | 1 +
 arch/arm/boot/dts/armada-xp-netgear-rn2120.dts   | 1 +
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 1 +
 14 files changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index e993c46..286bedd 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -56,6 +56,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index b10ceb4..ec77b86 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -52,6 +52,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 7c5c4ff..8c786cf 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -54,6 +54,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 1de53b5..1d64532 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -54,6 +54,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 6ae36a3..f40d35b 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -65,6 +65,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 0440891..033665c 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -56,6 +56,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index af6c74e..c56ccd74 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -55,6 +55,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index d99baac..e17edbb 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -56,6 +56,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index c1fbab2..a7fd474 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -60,6 +60,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 48bdafe..a12e159 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -65,6 +65,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 206aebb..8a2e49e 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -66,6 +66,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index 56f958e..3e81f22 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -53,6 +53,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index a7ceafd..508a395 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -54,6 +54,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 0c76d9f..7b2ea2060 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -55,6 +55,7 @@
 
 	chosen {
 		bootargs = "console=ttyS0,115200 earlyprintk";
+		stdout-path = &uart0;
 	};
 
 	memory {
-- 
2.1.0

[PATCHv2 06/15] devicetree: bindings: add DT binding for the Marvell Armada 39x SoC family

[Thomas Petazzoni]

The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the
Armada 398, with a slightly different number of interfaces. This
commit introduces the Device Tree binding that documents the top-level
compatible strings for Armada 39x based platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 Documentation/devicetree/bindings/arm/armada-39x.txt | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-39x.txt

diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt b/Documentation/devicetree/bindings/arm/armada-39x.txt
new file mode 100644
index 0000000..53d4ff9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-39x.txt
@@ -0,0 +1,20 @@
+Marvell Armada 39x Platforms Device Tree Bindings
+-------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 39x family shall have the
+following property:
+
+Required root node property:
+
+ - compatible: must contain "marvell,armada390"
+
+In addition, boards using the Marvell Armada 398 SoC shall have the
+following property before the previous one:
+
+Required root node property:
+
+compatible: must contain "marvell,armada398"
+
+Example:
+
+compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
-- 
2.1.0

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[PATCHv2 06/15] devicetree: bindings: add DT binding for the Marvell Armada 39x SoC family

[Thomas Petazzoni]

The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the
Armada 398, with a slightly different number of interfaces. This
commit introduces the Device Tree binding that documents the top-level
compatible strings for Armada 39x based platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 Documentation/devicetree/bindings/arm/armada-39x.txt | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/arm/armada-39x.txt

diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt b/Documentation/devicetree/bindings/arm/armada-39x.txt
new file mode 100644
index 0000000..53d4ff9
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/armada-39x.txt
@@ -0,0 +1,20 @@
+Marvell Armada 39x Platforms Device Tree Bindings
+-------------------------------------------------
+
+Boards with a SoC of the Marvell Armada 39x family shall have the
+following property:
+
+Required root node property:
+
+ - compatible: must contain "marvell,armada390"
+
+In addition, boards using the Marvell Armada 398 SoC shall have the
+following property before the previous one:
+
+Required root node property:
+
+compatible: must contain "marvell,armada398"
+
+Example:
+
+compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
-- 
2.1.0

[PATCHv2 07/15] devicetree: bindings: update DT bindings for Marvell EBU clock support

[Thomas Petazzoni]

With the introduction of the Marvell Armada 39x SoC, the DT bindings
for Marvell EBU clocks need to be extended. This commit include the
corresponding update to the Device Tree bindings documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt        |  9 +++++++++
 .../devicetree/bindings/clock/mvebu-gated-clock.txt       | 15 ++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index dc5ea5b..670c2af 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -23,6 +23,14 @@ The following is a list of provided IDs and clock names on Armada 380/385:
  2 = l2clk   (L2 Cache clock)
  3 = ddrclk  (DDR clock)
 
+The following is a list of provided IDs and clock names on Armada 39x:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = nbclk   (Coherent Fabric clock)
+ 3 = hclk    (SDRAM Controller Internal Clock)
+ 4 = dclk    (SDRAM Interface Clock)
+ 5 = refclk  (Reference Clock)
+
 The following is a list of provided IDs and clock names on Kirkwood and Dove:
  0 = tclk   (Internal Bus clock)
  1 = cpuclk (CPU0 clock)
@@ -39,6 +47,7 @@ Required properties:
 	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
 	"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
 	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
+	"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
 	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 76477be..31c7c0c 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -1,6 +1,6 @@
 * Gated Clock bindings for Marvell EBU SoCs
 
-Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
+Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
 peripheral clocks to be gated to save some power. The clock consumer
 should specify the desired clock by having the clock ID in its
 "clocks" phandle cell. The clock ID is directly mapped to the
@@ -77,6 +77,18 @@ ID	Clock		Peripheral
 28	xor1		XOR 1
 30	sata1		SATA 1
 
+The following is a list of provided IDs for Armada 39x:
+ID	Clock		Peripheral
+-----------------------------------
+5	pex1		PCIe 1
+6	pex2		PCIe 2
+7	pex3		PCIe 3
+8	pex0		PCIe 0
+9	usb3h0		USB3 Host 0
+17	sdio		SDIO
+22	xor0		XOR 0
+28	xor1		XOR 1
+
 The following is a list of provided IDs for Armada XP:
 ID	Clock	Peripheral
 -----------------------------------
@@ -152,6 +164,7 @@ Required properties:
 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
+	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
 	"marvell,dove-gating-clock" - for Dove SoC clock gating
 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
-- 
2.1.0

[PATCHv2 07/15] devicetree: bindings: update DT bindings for Marvell EBU clock support

[Thomas Petazzoni]

With the introduction of the Marvell Armada 39x SoC, the DT bindings
for Marvell EBU clocks need to be extended. This commit include the
corresponding update to the Device Tree bindings documentation.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../devicetree/bindings/clock/mvebu-core-clock.txt        |  9 +++++++++
 .../devicetree/bindings/clock/mvebu-gated-clock.txt       | 15 ++++++++++++++-
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
index dc5ea5b..670c2af 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt
@@ -23,6 +23,14 @@ The following is a list of provided IDs and clock names on Armada 380/385:
  2 = l2clk   (L2 Cache clock)
  3 = ddrclk  (DDR clock)
 
+The following is a list of provided IDs and clock names on Armada 39x:
+ 0 = tclk    (Internal Bus clock)
+ 1 = cpuclk  (CPU clock)
+ 2 = nbclk   (Coherent Fabric clock)
+ 3 = hclk    (SDRAM Controller Internal Clock)
+ 4 = dclk    (SDRAM Interface Clock)
+ 5 = refclk  (Reference Clock)
+
 The following is a list of provided IDs and clock names on Kirkwood and Dove:
  0 = tclk   (Internal Bus clock)
  1 = cpuclk (CPU0 clock)
@@ -39,6 +47,7 @@ Required properties:
 	"marvell,armada-370-core-clock" - For Armada 370 SoC core clocks
 	"marvell,armada-375-core-clock" - For Armada 375 SoC core clocks
 	"marvell,armada-380-core-clock" - For Armada 380/385 SoC core clocks
+	"marvell,armada-390-core-clock" - For Armada 39x SoC core clocks
 	"marvell,armada-xp-core-clock" - For Armada XP SoC core clocks
 	"marvell,dove-core-clock" - for Dove SoC core clocks
 	"marvell,kirkwood-core-clock" - for Kirkwood SoC (except mv88f6180)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 76477be..31c7c0c 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -1,6 +1,6 @@
 * Gated Clock bindings for Marvell EBU SoCs
 
-Marvell Armada 370/375/380/385/XP, Dove and Kirkwood allow some
+Marvell Armada 370/375/380/385/39x/XP, Dove and Kirkwood allow some
 peripheral clocks to be gated to save some power. The clock consumer
 should specify the desired clock by having the clock ID in its
 "clocks" phandle cell. The clock ID is directly mapped to the
@@ -77,6 +77,18 @@ ID	Clock		Peripheral
 28	xor1		XOR 1
 30	sata1		SATA 1
 
+The following is a list of provided IDs for Armada 39x:
+ID	Clock		Peripheral
+-----------------------------------
+5	pex1		PCIe 1
+6	pex2		PCIe 2
+7	pex3		PCIe 3
+8	pex0		PCIe 0
+9	usb3h0		USB3 Host 0
+17	sdio		SDIO
+22	xor0		XOR 0
+28	xor1		XOR 1
+
 The following is a list of provided IDs for Armada XP:
 ID	Clock	Peripheral
 -----------------------------------
@@ -152,6 +164,7 @@ Required properties:
 	"marvell,armada-370-gating-clock" - for Armada 370 SoC clock gating
 	"marvell,armada-375-gating-clock" - for Armada 375 SoC clock gating
 	"marvell,armada-380-gating-clock" - for Armada 380/385 SoC clock gating
+	"marvell,armada-390-gating-clock" - for Armada 39x SoC clock gating
 	"marvell,armada-xp-gating-clock" - for Armada XP SoC clock gating
 	"marvell,dove-gating-clock" - for Dove SoC clock gating
 	"marvell,kirkwood-gating-clock" - for Kirkwood SoC clock gating
-- 
2.1.0

[PATCHv2 08/15] devicetree: bindings: add Device Tree bindings for Armada 39x pin-muxing controller

[Thomas Petazzoni]

This commit adds the Device Tree binding documentation to describe the
pin-muxing controller of the Marvell Armada 39x processors. Two
variants are supported for the moment: the 88F6920 (Armada 390) and
88F6928 (Armada 398).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../pinctrl/marvell,armada-39x-pinctrl.txt         | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
new file mode 100644
index 0000000..5b1a9dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
@@ -0,0 +1,78 @@
+* Marvell Armada 39x SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl"
+  depending on the specific variant of the SoC being used.
+- reg: register specifier of MPP registers
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name    pins    functions
+================================================================================
+mpp0	0	gpio, ua0(rxd)
+mpp1	1	gpio, ua0(txd)
+mpp2	2	gpio, i2c0(sck)
+mpp3	3	gpio, i2c0(sda)
+mpp4	4	gpio, ua1(txd), ua0(rts), smi(mdc)
+mpp5	5	gpio, ua1(rxd), ua0(cts), smi(mdio)
+mpp6	6	gpio, dev(cs3), xsmi(mdio)
+mpp7	7	gpio, dev(ad9), xsmi(mdc)
+mpp8	8	gpio, dev(ad10), ptp(trig)
+mpp9	9	gpio, dev(ad11), ptp(clk)
+mpp10	10	gpio, dev(ad12), ptp(event)
+mpp11	11	gpio, dev(ad13), led(clk)
+mpp12	12	gpio, pcie0(rstout), dev(ad14), led(stb)
+mpp13	13	gpio, dev(ad15), led(data)
+mpp14	14	gpio, m(vtt), dev(wen1), ua1(txd)
+mpp15	15	gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
+mpp16	16	gpio, m(decc), spi0(miso), i2c1(sda)
+mpp17	17	gpio, ua1(rxd), spi0(sck), smi(mdio)
+mpp18	18	gpio, ua1(txd), spi0(cs0), i2c2(sck)
+mpp19	19	gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda)
+mpp20	20	gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc)
+mpp21	21	gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0)
+mpp22	22	gpio, spi0(mosi), dev(ad0)
+mpp23	23	gpio, spi0(sck), dev(ad2)
+mpp24	24	gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn)
+mpp25	25	gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0)
+mpp26	26	gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1)
+mpp27	27	gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout)
+mpp28	28	gpio, sd(clk), dev(ad5), ge(txd0)
+mpp29	29	gpio, dev(ale0), ge(txd1)
+mpp30	30	gpio, dev(oen), ge(txd2)
+mpp31	31	gpio, dev(ale1), ge(txd3)
+mpp32	32	gpio, dev(wen0), ge(txctl)
+mpp33	33	gpio, m(decc), dev(ad3)
+mpp34	34	gpio, dev(ad1)
+mpp35	35	gpio, ref(clk), dev(a1)
+mpp36	36	gpio, dev(a0)
+mpp37	37	gpio, sd(d3), dev(ad8), ge(rxclk)
+mpp38	38	gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1)
+mpp39	39	gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2)
+mpp40	40	gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3)
+mpp41	41	gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl)
+mpp42	42	gpio, ua1(txd), ua0(rts), dev(ad7)
+mpp43	43	gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1)
+mpp44	44	gpio, sata0(present) [1], sata1(present) [1], led(clk)
+mpp45	45	gpio, ref(clk), pcie0(rstout), ua1(rxd)
+mpp46	46	gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)
+mpp47	47	gpio, sata0(present) [1], sata1(present) [1], led(data)
+mpp48	48	gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd)
+mpp49	49	gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd)
+mpp50	50	gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd)
+mpp51	51	gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd)
+mpp52	52	gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck)
+mpp53	53	gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda)
+mpp54	54	gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd)
+mpp55	55	gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd)
+mpp56	56	gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd)
+mpp57	57	gpio, spi1(sck), sd(clk), ua1(txd)
+mpp58	58	gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd)
+mpp59	59	gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2)
+
+[1]: only available on 88F6928
-- 
2.1.0

[PATCHv2 08/15] devicetree: bindings: add Device Tree bindings for Armada 39x pin-muxing controller

[Thomas Petazzoni]

This commit adds the Device Tree binding documentation to describe the
pin-muxing controller of the Marvell Armada 39x processors. Two
variants are supported for the moment: the 88F6920 (Armada 390) and
88F6928 (Armada 398).

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 .../pinctrl/marvell,armada-39x-pinctrl.txt         | 78 ++++++++++++++++++++++
 1 file changed, 78 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt

diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
new file mode 100644
index 0000000..5b1a9dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-39x-pinctrl.txt
@@ -0,0 +1,78 @@
+* Marvell Armada 39x SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6920-pinctrl", "marvell,88f6928-pinctrl"
+  depending on the specific variant of the SoC being used.
+- reg: register specifier of MPP registers
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name    pins    functions
+================================================================================
+mpp0	0	gpio, ua0(rxd)
+mpp1	1	gpio, ua0(txd)
+mpp2	2	gpio, i2c0(sck)
+mpp3	3	gpio, i2c0(sda)
+mpp4	4	gpio, ua1(txd), ua0(rts), smi(mdc)
+mpp5	5	gpio, ua1(rxd), ua0(cts), smi(mdio)
+mpp6	6	gpio, dev(cs3), xsmi(mdio)
+mpp7	7	gpio, dev(ad9), xsmi(mdc)
+mpp8	8	gpio, dev(ad10), ptp(trig)
+mpp9	9	gpio, dev(ad11), ptp(clk)
+mpp10	10	gpio, dev(ad12), ptp(event)
+mpp11	11	gpio, dev(ad13), led(clk)
+mpp12	12	gpio, pcie0(rstout), dev(ad14), led(stb)
+mpp13	13	gpio, dev(ad15), led(data)
+mpp14	14	gpio, m(vtt), dev(wen1), ua1(txd)
+mpp15	15	gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
+mpp16	16	gpio, m(decc), spi0(miso), i2c1(sda)
+mpp17	17	gpio, ua1(rxd), spi0(sck), smi(mdio)
+mpp18	18	gpio, ua1(txd), spi0(cs0), i2c2(sck)
+mpp19	19	gpio, sata1(present) [1], ua0(cts), ua1(rxd), i2c2(sda)
+mpp20	20	gpio, sata0(present) [1], ua0(rts), ua1(txd), smi(mdc)
+mpp21	21	gpio, spi0(cs1), sata0(present) [1], sd(cmd), dev(bootcs), ge(rxd0)
+mpp22	22	gpio, spi0(mosi), dev(ad0)
+mpp23	23	gpio, spi0(sck), dev(ad2)
+mpp24	24	gpio, spi0(miso), ua0(cts), ua1(rxd), sd(d4), dev(readyn)
+mpp25	25	gpio, spi0(cs0), ua0(rts), ua1(txd), sd(d5), dev(cs0)
+mpp26	26	gpio, spi0(cs2), i2c1(sck), sd(d6), dev(cs1)
+mpp27	27	gpio, spi0(cs3), i2c1(sda), sd(d7), dev(cs2), ge(txclkout)
+mpp28	28	gpio, sd(clk), dev(ad5), ge(txd0)
+mpp29	29	gpio, dev(ale0), ge(txd1)
+mpp30	30	gpio, dev(oen), ge(txd2)
+mpp31	31	gpio, dev(ale1), ge(txd3)
+mpp32	32	gpio, dev(wen0), ge(txctl)
+mpp33	33	gpio, m(decc), dev(ad3)
+mpp34	34	gpio, dev(ad1)
+mpp35	35	gpio, ref(clk), dev(a1)
+mpp36	36	gpio, dev(a0)
+mpp37	37	gpio, sd(d3), dev(ad8), ge(rxclk)
+mpp38	38	gpio, ref(clk), sd(d0), dev(ad4), ge(rxd1)
+mpp39	39	gpio, i2c1(sck), ua0(cts), sd(d1), dev(a2), ge(rxd2)
+mpp40	40	gpio, i2c1(sda), ua0(rts), sd(d2), dev(ad6), ge(rxd3)
+mpp41	41	gpio, ua1(rxd), ua0(cts), spi1(cs3), dev(burstn), nd(rbn0), ge(rxctl)
+mpp42	42	gpio, ua1(txd), ua0(rts), dev(ad7)
+mpp43	43	gpio, pcie0(clkreq), m(vtt), m(decc), spi1(cs2), dev(clkout), nd(rbn1)
+mpp44	44	gpio, sata0(present) [1], sata1(present) [1], led(clk)
+mpp45	45	gpio, ref(clk), pcie0(rstout), ua1(rxd)
+mpp46	46	gpio, ref(clk), pcie0(rstout), ua1(txd), led(stb)
+mpp47	47	gpio, sata0(present) [1], sata1(present) [1], led(data)
+mpp48	48	gpio, sata0(present) [1], m(vtt), tdm(pclk) [1], audio(mclk) [1], sd(d4), pcie0(clkreq), ua1(txd)
+mpp49	49	gpio, tdm(fsync) [1], audio(lrclk) [1], sd(d5), ua2(rxd)
+mpp50	50	gpio, pcie0(rstout), tdm(drx) [1], audio(extclk) [1], sd(cmd), ua2(rxd)
+mpp51	51	gpio, tdm(dtx) [1], audio(sdo) [1], m(decc), ua2(txd)
+mpp52	52	gpio, pcie0(rstout), tdm(intn) [1], audio(sdi) [1], sd(d6), i2c3(sck)
+mpp53	53	gpio, sata1(present) [1], sata0(present) [1], tdm(rstn) [1], audio(bclk) [1], sd(d7), i2c3(sda)
+mpp54	54	gpio, sata0(present) [1], sata1(present) [1], pcie0(rstout), sd(d3), ua3(txd)
+mpp55	55	gpio, ua1(cts), spi1(cs1), sd(d0), ua1(rxd), ua3(rxd)
+mpp56	56	gpio, ua1(rts), m(decc), spi1(mosi), ua1(txd)
+mpp57	57	gpio, spi1(sck), sd(clk), ua1(txd)
+mpp58	58	gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd(d1), ua1(rxd)
+mpp59	59	gpio, pcie0(rstout), i2c1(sda), spi1(cs0), sd(d2)
+
+[1]: only available on 88F6928
-- 
2.1.0

[PATCHv2 09/15] devicetree: bindings: add new SMP enable method for Marvell Armada 39x

[Thomas Petazzoni]

This commit updates the ARM CPUs Device Tree binding to document a new
enable method of Marvell Armada 39x processors.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index b2aacbe..eb13d2e 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
 			    "brcm,brahma-b15"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
+			    "marvell,armada-390-smp"
 			    "marvell,armada-xp-smp"
 			    "qcom,gcc-msm8660"
 			    "qcom,kpss-acc-v1"
-- 
2.1.0

[PATCHv2 09/15] devicetree: bindings: add new SMP enable method for Marvell Armada 39x

[Thomas Petazzoni]

This commit updates the ARM CPUs Device Tree binding to document a new
enable method of Marvell Armada 39x processors.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 Documentation/devicetree/bindings/arm/cpus.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index b2aacbe..eb13d2e 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,7 @@ nodes to be present and contain the properties described below.
 			    "brcm,brahma-b15"
 			    "marvell,armada-375-smp"
 			    "marvell,armada-380-smp"
+			    "marvell,armada-390-smp"
 			    "marvell,armada-xp-smp"
 			    "qcom,gcc-msm8660"
 			    "qcom,kpss-acc-v1"
-- 
2.1.0

[PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Thomas Petazzoni]

The Armada 39x, contrary to its predecessor, has a configurable
reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
previous SoCs, it was fixed to 25 Mhz and described directly as such
in the Device Tree.

For Armada 39x, we need to read certain registers to know whether the
frequency is 25 or 40 Mhz. Therefore, this commit extends the common
mvebu clock code to allow the SoC-specific code to say it wants to
register a reference clock, by giving a non-NULL ->get_refclk_freq()
function pointer in its coreclk_soc_desc structure.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/clk/mvebu/common.c | 17 +++++++++++++++++
 drivers/clk/mvebu/common.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 0d4d121..15b370f 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 
 	/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
 	clk_data.clk_num = 2 + desc->num_ratios;
+
+	/* One more clock for the optional refclk */
+	if (desc->get_refclk_freq)
+		clk_data.clk_num += 1;
+
 	clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
 				GFP_KERNEL);
 	if (WARN_ON(!clk_data.clks)) {
@@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 		WARN_ON(IS_ERR(clk_data.clks[2+n]));
 	};
 
+	/* Register optional refclk */
+	if (desc->get_refclk_freq) {
+		const char *name = "refclk";
+		of_property_read_string_index(np, "clock-output-names",
+					      2 + desc->num_ratios, &name);
+		rate = desc->get_refclk_freq(base);
+		clk_data.clks[2 + desc->num_ratios] =
+			clk_register_fixed_rate(NULL, name, NULL,
+						CLK_IS_ROOT, rate);
+		WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
+	}
+
 	/* SAR register isn't needed anymore */
 	iounmap(base);
 
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index 783b563..f0de6c8 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -30,6 +30,7 @@ struct coreclk_soc_desc {
 	u32 (*get_tclk_freq)(void __iomem *sar);
 	u32 (*get_cpu_freq)(void __iomem *sar);
 	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+	u32 (*get_refclk_freq)(void __iomem *sar);
 	bool (*is_sscg_enabled)(void __iomem *sar);
 	u32 (*fix_sscg_deviation)(u32 system_clk);
 	const struct coreclk_ratio *ratios;
-- 
2.1.0

[PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Thomas Petazzoni]

The Armada 39x, contrary to its predecessor, has a configurable
reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
previous SoCs, it was fixed to 25 Mhz and described directly as such
in the Device Tree.

For Armada 39x, we need to read certain registers to know whether the
frequency is 25 or 40 Mhz. Therefore, this commit extends the common
mvebu clock code to allow the SoC-specific code to say it wants to
register a reference clock, by giving a non-NULL ->get_refclk_freq()
function pointer in its coreclk_soc_desc structure.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/clk/mvebu/common.c | 17 +++++++++++++++++
 drivers/clk/mvebu/common.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 0d4d121..15b370f 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 
 	/* Allocate struct for TCLK, cpu clk, and core ratio clocks */
 	clk_data.clk_num = 2 + desc->num_ratios;
+
+	/* One more clock for the optional refclk */
+	if (desc->get_refclk_freq)
+		clk_data.clk_num += 1;
+
 	clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
 				GFP_KERNEL);
 	if (WARN_ON(!clk_data.clks)) {
@@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
 		WARN_ON(IS_ERR(clk_data.clks[2+n]));
 	};
 
+	/* Register optional refclk */
+	if (desc->get_refclk_freq) {
+		const char *name = "refclk";
+		of_property_read_string_index(np, "clock-output-names",
+					      2 + desc->num_ratios, &name);
+		rate = desc->get_refclk_freq(base);
+		clk_data.clks[2 + desc->num_ratios] =
+			clk_register_fixed_rate(NULL, name, NULL,
+						CLK_IS_ROOT, rate);
+		WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
+	}
+
 	/* SAR register isn't needed anymore */
 	iounmap(base);
 
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index 783b563..f0de6c8 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -30,6 +30,7 @@ struct coreclk_soc_desc {
 	u32 (*get_tclk_freq)(void __iomem *sar);
 	u32 (*get_cpu_freq)(void __iomem *sar);
 	void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+	u32 (*get_refclk_freq)(void __iomem *sar);
 	bool (*is_sscg_enabled)(void __iomem *sar);
 	u32 (*fix_sscg_deviation)(u32 system_clk);
 	const struct coreclk_ratio *ratios;
-- 
2.1.0

[PATCHv2 11/15] clk: mvebu: add Marvell Armada 39x driver

[Thomas Petazzoni]

This commit adds a new clock driver for the Marvell Armada 39x family
of processors. This driver is fairly similar to the ones already used
on other Marvell EBU processors, with the following main differences:

 * Different set of ratios
 * Different set of core clocks
 * Configurable reference clock in frequency

Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
 drivers/clk/mvebu/Kconfig      |   4 ++
 drivers/clk/mvebu/Makefile     |   1 +
 drivers/clk/mvebu/armada-39x.c | 156 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 161 insertions(+)
 create mode 100644 drivers/clk/mvebu/armada-39x.c

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 3b34dba..2769625 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -21,6 +21,10 @@ config ARMADA_38X_CLK
 	bool
 	select MVEBU_CLK_COMMON
 
+config ARMADA_39X_CLK
+	bool
+	select MVEBU_CLK_COMMON
+
 config ARMADA_XP_CLK
 	bool
 	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index a9a56fc..645ac7e 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_MVEBU_CLK_COREDIV)	+= clk-corediv.o
 obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o
 obj-$(CONFIG_ARMADA_375_CLK)	+= armada-375.o
 obj-$(CONFIG_ARMADA_38X_CLK)	+= armada-38x.o
+obj-$(CONFIG_ARMADA_39X_CLK)	+= armada-39x.o
 obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
diff --git a/drivers/clk/mvebu/armada-39x.c b/drivers/clk/mvebu/armada-39x.c
new file mode 100644
index 0000000..efb974d
--- /dev/null
+++ b/drivers/clk/mvebu/armada-39x.c
@@ -0,0 +1,156 @@
+/*
+ * Marvell Armada 39x SoC clocks
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ * Sebastian Hesselbarth <sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ * Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
+ * Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
+ *
+ * SARL[15]    : TCLK frequency
+ *		 0 = 250 MHz
+ *		 1 = 200 MHz
+ *
+ * SARH[0]     : Reference clock frequency
+ *               0 = 25 Mhz
+ *               1 = 40 Mhz
+ */
+
+#define SARL 					0
+#define  SARL_A390_TCLK_FREQ_OPT		15
+#define  SARL_A390_TCLK_FREQ_OPT_MASK		0x1
+#define  SARL_A390_CPU_DDR_L2_FREQ_OPT		10
+#define  SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK	0x1F
+#define SARH					4
+#define  SARH_A390_REFCLK_FREQ			BIT(0)
+
+static const u32 armada_39x_tclk_frequencies[] __initconst = {
+	250000000,
+	200000000,
+};
+
+static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
+{
+	u8 tclk_freq_select;
+
+	tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
+			    SARL_A390_TCLK_FREQ_OPT_MASK);
+	return armada_39x_tclk_frequencies[tclk_freq_select];
+}
+
+static const u32 armada_39x_cpu_frequencies[] __initconst = {
+	[0x0] = 666 * 1000 * 1000,
+	[0x2] = 800 * 1000 * 1000,
+	[0x3] = 800 * 1000 * 1000,
+	[0x4] = 1066 * 1000 * 1000,
+	[0x5] = 1066 * 1000 * 1000,
+	[0x6] = 1200 * 1000 * 1000,
+	[0x8] = 1332 * 1000 * 1000,
+	[0xB] = 1600 * 1000 * 1000,
+	[0xC] = 1600 * 1000 * 1000,
+	[0x12] = 1800 * 1000 * 1000,
+	[0x1E] = 1800 * 1000 * 1000,
+};
+
+static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
+{
+	u8 cpu_freq_select;
+
+	cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
+			   SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
+	if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
+		pr_err("Selected CPU frequency (%d) unsupported\n",
+			cpu_freq_select);
+		return 0;
+	}
+
+	return armada_39x_cpu_frequencies[cpu_freq_select];
+}
+
+enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
+
+static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
+	{ .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
+	{ .id = A390_CPU_TO_HCLK, .name = "hclk" },
+	{ .id = A390_CPU_TO_DCLK, .name = "dclk" },
+};
+
+static void __init armada_39x_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	switch (id) {
+	case A390_CPU_TO_NBCLK:
+		*mult = 1;
+		*div = 2;
+		break;
+	case A390_CPU_TO_HCLK:
+		*mult = 1;
+		*div = 4;
+		break;
+	case A390_CPU_TO_DCLK:
+		*mult = 1;
+		*div = 2;
+		break;
+	}
+}
+
+static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
+{
+	if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
+		return 40 * 1000 * 1000;
+	else
+		return 25 * 1000 * 1000;
+}
+
+static const struct coreclk_soc_desc armada_39x_coreclks = {
+	.get_tclk_freq = armada_39x_get_tclk_freq,
+	.get_cpu_freq = armada_39x_get_cpu_freq,
+	.get_clk_ratio = armada_39x_get_clk_ratio,
+	.get_refclk_freq = armada_39x_refclk_ratio,
+	.ratios = armada_39x_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
+};
+
+static void __init armada_39x_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &armada_39x_coreclks);
+}
+CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
+	       armada_39x_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
+	{ "pex1", NULL, 5 },
+	{ "pex2", NULL, 6 },
+	{ "pex3", NULL, 7 },
+	{ "pex0", NULL, 8 },
+	{ "usb3h0", NULL, 9 },
+	{ "sdio", NULL, 17 },
+	{ "xor0", NULL, 22 },
+	{ "xor1", NULL, 28 },
+	{ }
+};
+
+static void __init armada_39x_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, armada_39x_gating_desc);
+}
+CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
+	       armada_39x_clk_gating_init);
-- 
2.1.0

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[PATCHv2 11/15] clk: mvebu: add Marvell Armada 39x driver

[Thomas Petazzoni]

This commit adds a new clock driver for the Marvell Armada 39x family
of processors. This driver is fairly similar to the ones already used
on other Marvell EBU processors, with the following main differences:

 * Different set of ratios
 * Different set of core clocks
 * Configurable reference clock in frequency

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/clk/mvebu/Kconfig      |   4 ++
 drivers/clk/mvebu/Makefile     |   1 +
 drivers/clk/mvebu/armada-39x.c | 156 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 161 insertions(+)
 create mode 100644 drivers/clk/mvebu/armada-39x.c

diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 3b34dba..2769625 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -21,6 +21,10 @@ config ARMADA_38X_CLK
 	bool
 	select MVEBU_CLK_COMMON
 
+config ARMADA_39X_CLK
+	bool
+	select MVEBU_CLK_COMMON
+
 config ARMADA_XP_CLK
 	bool
 	select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index a9a56fc..645ac7e 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_MVEBU_CLK_COREDIV)	+= clk-corediv.o
 obj-$(CONFIG_ARMADA_370_CLK)	+= armada-370.o
 obj-$(CONFIG_ARMADA_375_CLK)	+= armada-375.o
 obj-$(CONFIG_ARMADA_38X_CLK)	+= armada-38x.o
+obj-$(CONFIG_ARMADA_39X_CLK)	+= armada-39x.o
 obj-$(CONFIG_ARMADA_XP_CLK)	+= armada-xp.o
 obj-$(CONFIG_DOVE_CLK)		+= dove.o
 obj-$(CONFIG_KIRKWOOD_CLK)	+= kirkwood.o
diff --git a/drivers/clk/mvebu/armada-39x.c b/drivers/clk/mvebu/armada-39x.c
new file mode 100644
index 0000000..efb974d
--- /dev/null
+++ b/drivers/clk/mvebu/armada-39x.c
@@ -0,0 +1,156 @@
+/*
+ * Marvell Armada 39x SoC clocks
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * SARL[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
+ *
+ * SARL[15]    : TCLK frequency
+ *		 0 = 250 MHz
+ *		 1 = 200 MHz
+ *
+ * SARH[0]     : Reference clock frequency
+ *               0 = 25 Mhz
+ *               1 = 40 Mhz
+ */
+
+#define SARL 					0
+#define  SARL_A390_TCLK_FREQ_OPT		15
+#define  SARL_A390_TCLK_FREQ_OPT_MASK		0x1
+#define  SARL_A390_CPU_DDR_L2_FREQ_OPT		10
+#define  SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK	0x1F
+#define SARH					4
+#define  SARH_A390_REFCLK_FREQ			BIT(0)
+
+static const u32 armada_39x_tclk_frequencies[] __initconst = {
+	250000000,
+	200000000,
+};
+
+static u32 __init armada_39x_get_tclk_freq(void __iomem *sar)
+{
+	u8 tclk_freq_select;
+
+	tclk_freq_select = ((readl(sar + SARL) >> SARL_A390_TCLK_FREQ_OPT) &
+			    SARL_A390_TCLK_FREQ_OPT_MASK);
+	return armada_39x_tclk_frequencies[tclk_freq_select];
+}
+
+static const u32 armada_39x_cpu_frequencies[] __initconst = {
+	[0x0] = 666 * 1000 * 1000,
+	[0x2] = 800 * 1000 * 1000,
+	[0x3] = 800 * 1000 * 1000,
+	[0x4] = 1066 * 1000 * 1000,
+	[0x5] = 1066 * 1000 * 1000,
+	[0x6] = 1200 * 1000 * 1000,
+	[0x8] = 1332 * 1000 * 1000,
+	[0xB] = 1600 * 1000 * 1000,
+	[0xC] = 1600 * 1000 * 1000,
+	[0x12] = 1800 * 1000 * 1000,
+	[0x1E] = 1800 * 1000 * 1000,
+};
+
+static u32 __init armada_39x_get_cpu_freq(void __iomem *sar)
+{
+	u8 cpu_freq_select;
+
+	cpu_freq_select = ((readl(sar + SARL) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
+			   SARL_A390_CPU_DDR_L2_FREQ_OPT_MASK);
+	if (cpu_freq_select >= ARRAY_SIZE(armada_39x_cpu_frequencies)) {
+		pr_err("Selected CPU frequency (%d) unsupported\n",
+			cpu_freq_select);
+		return 0;
+	}
+
+	return armada_39x_cpu_frequencies[cpu_freq_select];
+}
+
+enum { A390_CPU_TO_NBCLK, A390_CPU_TO_HCLK, A390_CPU_TO_DCLK };
+
+static const struct coreclk_ratio armada_39x_coreclk_ratios[] __initconst = {
+	{ .id = A390_CPU_TO_NBCLK, .name = "nbclk" },
+	{ .id = A390_CPU_TO_HCLK, .name = "hclk" },
+	{ .id = A390_CPU_TO_DCLK, .name = "dclk" },
+};
+
+static void __init armada_39x_get_clk_ratio(
+	void __iomem *sar, int id, int *mult, int *div)
+{
+	switch (id) {
+	case A390_CPU_TO_NBCLK:
+		*mult = 1;
+		*div = 2;
+		break;
+	case A390_CPU_TO_HCLK:
+		*mult = 1;
+		*div = 4;
+		break;
+	case A390_CPU_TO_DCLK:
+		*mult = 1;
+		*div = 2;
+		break;
+	}
+}
+
+static u32 __init armada_39x_refclk_ratio(void __iomem *sar)
+{
+	if (readl(sar + SARH) & SARH_A390_REFCLK_FREQ)
+		return 40 * 1000 * 1000;
+	else
+		return 25 * 1000 * 1000;
+}
+
+static const struct coreclk_soc_desc armada_39x_coreclks = {
+	.get_tclk_freq = armada_39x_get_tclk_freq,
+	.get_cpu_freq = armada_39x_get_cpu_freq,
+	.get_clk_ratio = armada_39x_get_clk_ratio,
+	.get_refclk_freq = armada_39x_refclk_ratio,
+	.ratios = armada_39x_coreclk_ratios,
+	.num_ratios = ARRAY_SIZE(armada_39x_coreclk_ratios),
+};
+
+static void __init armada_39x_coreclk_init(struct device_node *np)
+{
+	mvebu_coreclk_setup(np, &armada_39x_coreclks);
+}
+CLK_OF_DECLARE(armada_39x_core_clk, "marvell,armada-390-core-clock",
+	       armada_39x_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+static const struct clk_gating_soc_desc armada_39x_gating_desc[] __initconst = {
+	{ "pex1", NULL, 5 },
+	{ "pex2", NULL, 6 },
+	{ "pex3", NULL, 7 },
+	{ "pex0", NULL, 8 },
+	{ "usb3h0", NULL, 9 },
+	{ "sdio", NULL, 17 },
+	{ "xor0", NULL, 22 },
+	{ "xor1", NULL, 28 },
+	{ }
+};
+
+static void __init armada_39x_clk_gating_init(struct device_node *np)
+{
+	mvebu_clk_gating_setup(np, armada_39x_gating_desc);
+}
+CLK_OF_DECLARE(armada_39x_clk_gating, "marvell,armada-390-gating-clock",
+	       armada_39x_clk_gating_init);
-- 
2.1.0

[PATCHv2 12/15] pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x

[Thomas Petazzoni]

This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing infrastructure to
support pin-muxing on Marvell EBU processors. Two variants of the
Armada 39x are supported: 88F6920 (Armada 390) and 88F6928 (Armada
398), which have a few differences in the available functions for
certain pins.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/pinctrl/mvebu/Kconfig              |   4 +
 drivers/pinctrl/mvebu/Makefile             |   1 +
 drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 432 +++++++++++++++++++++++++++++
 3 files changed, 437 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-39x.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index d6dd835..1706024 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -26,6 +26,10 @@ config PINCTRL_ARMADA_38X
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_39X
+	bool
+	select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
 	bool
 	select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index a0818e9..554d8af 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
+obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
new file mode 100644
index 0000000..5963411
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
@@ -0,0 +1,432 @@
+/*
+ * Marvell Armada 39x pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static void __iomem *mpp_base;
+
+static int armada_39x_mpp_ctrl_get(unsigned pid, unsigned long *config)
+{
+	return default_mpp_ctrl_get(mpp_base, pid, config);
+}
+
+static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config)
+{
+	return default_mpp_ctrl_set(mpp_base, pid, config);
+}
+
+enum {
+	V_88F6920 = BIT(0),
+	V_88F6928 = BIT(1),
+	V_88F6920_PLUS = (V_88F6920 | V_88F6928),
+};
+
+static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua0",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(1,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua0",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(2,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c0",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(3,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c0",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(4,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdc",      V_88F6920_PLUS)),
+	MPP_MODE(5,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdio",     V_88F6920_PLUS)),
+	MPP_MODE(6,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs3",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "xsmi",    "mdio",     V_88F6920_PLUS)),
+	MPP_MODE(7,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad9",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "xsmi",    "mdc",      V_88F6920_PLUS)),
+	MPP_MODE(8,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad10",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ptp",     "trig",     V_88F6920_PLUS)),
+	MPP_MODE(9,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad11",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ptp",     "clk",      V_88F6920_PLUS)),
+	MPP_MODE(10,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad12",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ptp",     "event",    V_88F6920_PLUS)),
+	MPP_MODE(11,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad13",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "clk",      V_88F6920_PLUS)),
+	MPP_MODE(12,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad14",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "stb",      V_88F6920_PLUS)),
+	MPP_MODE(13,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad15",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "data",     V_88F6920_PLUS)),
+	MPP_MODE(14,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "vtt",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "wen1",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(15,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "mosi",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c1",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(16,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "miso",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c1",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(17,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdio",     V_88F6920_PLUS)),
+	MPP_MODE(18,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "cs0",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c2",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(19,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(5, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c2",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(20,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(5, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdc",      V_88F6920_PLUS)),
+	MPP_MODE(21,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs1",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(4, "sd",      "cmd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "bootcs",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd0",     V_88F6920_PLUS)),
+	MPP_MODE(22,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "mosi",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad0",      V_88F6920_PLUS)),
+	MPP_MODE(23,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad2",      V_88F6920_PLUS)),
+	MPP_MODE(24,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "miso",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d4",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "readyn",   V_88F6920_PLUS)),
+	MPP_MODE(25,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs0",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d5",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs0",      V_88F6920_PLUS)),
+	MPP_MODE(26,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs2",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "i2c1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d6",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs1",      V_88F6920_PLUS)),
+	MPP_MODE(27,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs3",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "i2c1",    "sda",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d7",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs2",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txclkout", V_88F6920_PLUS)),
+	MPP_MODE(28,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad5",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd0",     V_88F6920_PLUS)),
+	MPP_MODE(29,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ale0",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd1",     V_88F6920_PLUS)),
+	MPP_MODE(30,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "oen",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd2",     V_88F6920_PLUS)),
+	MPP_MODE(31,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ale1",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd3",     V_88F6920_PLUS)),
+	MPP_MODE(32,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "wen0",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txctl",    V_88F6920_PLUS)),
+	MPP_MODE(33,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad3",      V_88F6920_PLUS)),
+	MPP_MODE(34,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad1",      V_88F6920_PLUS)),
+	MPP_MODE(35,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "a1",       V_88F6920_PLUS)),
+	MPP_MODE(36,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "a0",       V_88F6920_PLUS)),
+	MPP_MODE(37,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d3",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad8",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxclk",    V_88F6920_PLUS)),
+	MPP_MODE(38,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d0",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad4",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd1",     V_88F6920_PLUS)),
+	MPP_MODE(39,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d1",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "a2",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd2",     V_88F6920_PLUS)),
+	MPP_MODE(40,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c1",    "sda",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d2",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad6",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd3",     V_88F6920_PLUS)),
+	MPP_MODE(41,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs3",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "burstn",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "nd",      "rbn0",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxctl",    V_88F6920_PLUS)),
+	MPP_MODE(42,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad7",      V_88F6920_PLUS)),
+	MPP_MODE(43,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "clkreq",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "m",       "vtt",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs2",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "clkout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "nd",      "rbn1",     V_88F6920_PLUS)),
+	MPP_MODE(44,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(7, "led",     "clk",      V_88F6920_PLUS)),
+	MPP_MODE(45,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(46,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "stb",      V_88F6920_PLUS)),
+	MPP_MODE(47,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(7, "led",     "data",     V_88F6920_PLUS)),
+	MPP_MODE(48,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "m",       "vtt",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "pclk",     V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "mclk",     V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d4",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "pcie0",   "clkreq",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(49,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "fsync",    V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "lrclk",    V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d5",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua2",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(50,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "drx",      V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "extclk",   V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "cmd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua2",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(51,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "dtx",      V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "sdo",      V_88F6928),
+		 MPP_VAR_FUNCTION(5, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua2",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(52,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "intn",     V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "sdi",      V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d6",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c3",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(53,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(3, "tdm",     "rstn",     V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "bclk",     V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d7",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c3",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(54,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(3, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d3",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua3",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(55,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs1",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d0",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua3",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(56,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "mosi",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(57,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(58,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "i2c1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "pcie2",   "clkreq",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "miso",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d1",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(59,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "i2c1",    "sda",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs0",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d2",       V_88F6920_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info;
+
+static struct of_device_id armada_39x_pinctrl_of_match[] = {
+	{
+		.compatible = "marvell,mv88f6920-pinctrl",
+		.data       = (void *) V_88F6920,
+	},
+	{
+		.compatible = "marvell,mv88f6928-pinctrl",
+		.data       = (void *) V_88F6928,
+	},
+	{ },
+};
+
+static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 59, NULL, armada_39x_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 27),
+};
+
+static int armada_39x_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &armada_39x_pinctrl_info;
+	const struct of_device_id *match =
+		of_match_device(armada_39x_pinctrl_of_match, &pdev->dev);
+	struct resource *res;
+
+	if (!match)
+		return -ENODEV;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mpp_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mpp_base))
+		return PTR_ERR(mpp_base);
+
+	soc->variant = (unsigned) match->data & 0xff;
+	soc->controls = armada_39x_mpp_controls;
+	soc->ncontrols = ARRAY_SIZE(armada_39x_mpp_controls);
+	soc->gpioranges = armada_39x_mpp_gpio_ranges;
+	soc->ngpioranges = ARRAY_SIZE(armada_39x_mpp_gpio_ranges);
+	soc->modes = armada_39x_mpp_modes;
+	soc->nmodes = armada_39x_mpp_controls[0].npins;
+
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int armada_39x_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_39x_pinctrl_driver = {
+	.driver = {
+		.name = "armada-39x-pinctrl",
+		.of_match_table = of_match_ptr(armada_39x_pinctrl_of_match),
+	},
+	.probe = armada_39x_pinctrl_probe,
+	.remove = armada_39x_pinctrl_remove,
+};
+
+module_platform_driver(armada_39x_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada 39x pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.0

[PATCHv2 12/15] pinctrl: mvebu: add pinctrl driver for Marvell Armada 39x

[Thomas Petazzoni]

This commit adds a new pinctrl driver for the Marvell Armada 39x
family of processors, which hooks into the existing infrastructure to
support pin-muxing on Marvell EBU processors. Two variants of the
Armada 39x are supported: 88F6920 (Armada 390) and 88F6928 (Armada
398), which have a few differences in the available functions for
certain pins.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 drivers/pinctrl/mvebu/Kconfig              |   4 +
 drivers/pinctrl/mvebu/Makefile             |   1 +
 drivers/pinctrl/mvebu/pinctrl-armada-39x.c | 432 +++++++++++++++++++++++++++++
 3 files changed, 437 insertions(+)
 create mode 100644 drivers/pinctrl/mvebu/pinctrl-armada-39x.c

diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index d6dd835..1706024 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -26,6 +26,10 @@ config PINCTRL_ARMADA_38X
 	bool
 	select PINCTRL_MVEBU
 
+config PINCTRL_ARMADA_39X
+	bool
+	select PINCTRL_MVEBU
+
 config PINCTRL_ARMADA_XP
 	bool
 	select PINCTRL_MVEBU
diff --git a/drivers/pinctrl/mvebu/Makefile b/drivers/pinctrl/mvebu/Makefile
index a0818e9..554d8af 100644
--- a/drivers/pinctrl/mvebu/Makefile
+++ b/drivers/pinctrl/mvebu/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_PINCTRL_KIRKWOOD)	+= pinctrl-kirkwood.o
 obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
 obj-$(CONFIG_PINCTRL_ARMADA_375) += pinctrl-armada-375.o
 obj-$(CONFIG_PINCTRL_ARMADA_38X) += pinctrl-armada-38x.o
+obj-$(CONFIG_PINCTRL_ARMADA_39X) += pinctrl-armada-39x.o
 obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 obj-$(CONFIG_PINCTRL_ORION)  += pinctrl-orion.o
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-39x.c b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
new file mode 100644
index 0000000..5963411
--- /dev/null
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-39x.c
@@ -0,0 +1,432 @@
+/*
+ * Marvell Armada 39x pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static void __iomem *mpp_base;
+
+static int armada_39x_mpp_ctrl_get(unsigned pid, unsigned long *config)
+{
+	return default_mpp_ctrl_get(mpp_base, pid, config);
+}
+
+static int armada_39x_mpp_ctrl_set(unsigned pid, unsigned long config)
+{
+	return default_mpp_ctrl_set(mpp_base, pid, config);
+}
+
+enum {
+	V_88F6920 = BIT(0),
+	V_88F6928 = BIT(1),
+	V_88F6920_PLUS = (V_88F6920 | V_88F6928),
+};
+
+static struct mvebu_mpp_mode armada_39x_mpp_modes[] = {
+	MPP_MODE(0,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua0",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(1,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua0",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(2,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c0",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(3,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c0",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(4,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdc",      V_88F6920_PLUS)),
+	MPP_MODE(5,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdio",     V_88F6920_PLUS)),
+	MPP_MODE(6,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs3",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "xsmi",    "mdio",     V_88F6920_PLUS)),
+	MPP_MODE(7,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad9",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "xsmi",    "mdc",      V_88F6920_PLUS)),
+	MPP_MODE(8,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad10",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ptp",     "trig",     V_88F6920_PLUS)),
+	MPP_MODE(9,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad11",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ptp",     "clk",      V_88F6920_PLUS)),
+	MPP_MODE(10,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad12",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ptp",     "event",    V_88F6920_PLUS)),
+	MPP_MODE(11,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad13",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "clk",      V_88F6920_PLUS)),
+	MPP_MODE(12,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad14",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "stb",      V_88F6920_PLUS)),
+	MPP_MODE(13,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad15",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "data",     V_88F6920_PLUS)),
+	MPP_MODE(14,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "vtt",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "wen1",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(15,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "mosi",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c1",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(16,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "miso",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c1",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(17,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdio",     V_88F6920_PLUS)),
+	MPP_MODE(18,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi0",    "cs0",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c2",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(19,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(5, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c2",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(20,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(5, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "smi",     "mdc",      V_88F6920_PLUS)),
+	MPP_MODE(21,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs1",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(4, "sd",      "cmd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "bootcs",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd0",     V_88F6920_PLUS)),
+	MPP_MODE(22,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "mosi",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad0",      V_88F6920_PLUS)),
+	MPP_MODE(23,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad2",      V_88F6920_PLUS)),
+	MPP_MODE(24,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "miso",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d4",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "readyn",   V_88F6920_PLUS)),
+	MPP_MODE(25,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs0",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d5",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs0",      V_88F6920_PLUS)),
+	MPP_MODE(26,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs2",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "i2c1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d6",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs1",      V_88F6920_PLUS)),
+	MPP_MODE(27,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "spi0",    "cs3",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "i2c1",    "sda",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d7",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "cs2",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txclkout", V_88F6920_PLUS)),
+	MPP_MODE(28,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad5",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd0",     V_88F6920_PLUS)),
+	MPP_MODE(29,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ale0",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd1",     V_88F6920_PLUS)),
+	MPP_MODE(30,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "oen",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd2",     V_88F6920_PLUS)),
+	MPP_MODE(31,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ale1",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txd3",     V_88F6920_PLUS)),
+	MPP_MODE(32,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "wen0",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "txctl",    V_88F6920_PLUS)),
+	MPP_MODE(33,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad3",      V_88F6920_PLUS)),
+	MPP_MODE(34,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad1",      V_88F6920_PLUS)),
+	MPP_MODE(35,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "a1",       V_88F6920_PLUS)),
+	MPP_MODE(36,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "a0",       V_88F6920_PLUS)),
+	MPP_MODE(37,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d3",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad8",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxclk",    V_88F6920_PLUS)),
+	MPP_MODE(38,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d0",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad4",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd1",     V_88F6920_PLUS)),
+	MPP_MODE(39,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d1",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "a2",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd2",     V_88F6920_PLUS)),
+	MPP_MODE(40,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "i2c1",    "sda",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "sd",      "d2",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad6",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxd3",     V_88F6920_PLUS)),
+	MPP_MODE(41,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs3",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "burstn",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "nd",      "rbn0",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(8, "ge",      "rxctl",    V_88F6920_PLUS)),
+	MPP_MODE(42,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "ua0",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "ad7",      V_88F6920_PLUS)),
+	MPP_MODE(43,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "clkreq",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "m",       "vtt",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs2",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "dev",     "clkout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "nd",      "rbn1",     V_88F6920_PLUS)),
+	MPP_MODE(44,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(7, "led",     "clk",      V_88F6920_PLUS)),
+	MPP_MODE(45,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(46,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ref",     "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "led",     "stb",      V_88F6920_PLUS)),
+	MPP_MODE(47,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(7, "led",     "data",     V_88F6920_PLUS)),
+	MPP_MODE(48,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "m",       "vtt",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "pclk",     V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "mclk",     V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d4",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "pcie0",   "clkreq",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(49,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "fsync",    V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "lrclk",    V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d5",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua2",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(50,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "drx",      V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "extclk",   V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "cmd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua2",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(51,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "dtx",      V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "sdo",      V_88F6928),
+		 MPP_VAR_FUNCTION(5, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua2",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(52,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "tdm",     "intn",     V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "sdi",      V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d6",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c3",    "sck",      V_88F6920_PLUS)),
+	MPP_MODE(53,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(3, "tdm",     "rstn",     V_88F6928),
+		 MPP_VAR_FUNCTION(4, "audio",   "bclk",     V_88F6928),
+		 MPP_VAR_FUNCTION(5, "sd",      "d7",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "i2c3",    "sda",      V_88F6920_PLUS)),
+	MPP_MODE(54,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "sata0",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(2, "sata1",   "present",  V_88F6928),
+		 MPP_VAR_FUNCTION(3, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d3",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua3",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(55,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "cts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs1",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d0",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(7, "ua3",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(56,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "ua1",     "rts",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "m",       "decc",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "mosi",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(57,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "clk",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "txd",      V_88F6920_PLUS)),
+	MPP_MODE(58,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "i2c1",    "sck",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(3, "pcie2",   "clkreq",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "miso",     V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d1",       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(6, "ua1",     "rxd",      V_88F6920_PLUS)),
+	MPP_MODE(59,
+		 MPP_VAR_FUNCTION(0, "gpio",    NULL,       V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(1, "pcie0",   "rstout",   V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(2, "i2c1",    "sda",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(4, "spi1",    "cs0",      V_88F6920_PLUS),
+		 MPP_VAR_FUNCTION(5, "sd",      "d2",       V_88F6920_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_39x_pinctrl_info;
+
+static struct of_device_id armada_39x_pinctrl_of_match[] = {
+	{
+		.compatible = "marvell,mv88f6920-pinctrl",
+		.data       = (void *) V_88F6920,
+	},
+	{
+		.compatible = "marvell,mv88f6928-pinctrl",
+		.data       = (void *) V_88F6928,
+	},
+	{ },
+};
+
+static struct mvebu_mpp_ctrl armada_39x_mpp_controls[] = {
+	MPP_FUNC_CTRL(0, 59, NULL, armada_39x_mpp_ctrl),
+};
+
+static struct pinctrl_gpio_range armada_39x_mpp_gpio_ranges[] = {
+	MPP_GPIO_RANGE(0,   0,  0, 32),
+	MPP_GPIO_RANGE(1,  32, 32, 27),
+};
+
+static int armada_39x_pinctrl_probe(struct platform_device *pdev)
+{
+	struct mvebu_pinctrl_soc_info *soc = &armada_39x_pinctrl_info;
+	const struct of_device_id *match =
+		of_match_device(armada_39x_pinctrl_of_match, &pdev->dev);
+	struct resource *res;
+
+	if (!match)
+		return -ENODEV;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mpp_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(mpp_base))
+		return PTR_ERR(mpp_base);
+
+	soc->variant = (unsigned) match->data & 0xff;
+	soc->controls = armada_39x_mpp_controls;
+	soc->ncontrols = ARRAY_SIZE(armada_39x_mpp_controls);
+	soc->gpioranges = armada_39x_mpp_gpio_ranges;
+	soc->ngpioranges = ARRAY_SIZE(armada_39x_mpp_gpio_ranges);
+	soc->modes = armada_39x_mpp_modes;
+	soc->nmodes = armada_39x_mpp_controls[0].npins;
+
+	pdev->dev.platform_data = soc;
+
+	return mvebu_pinctrl_probe(pdev);
+}
+
+static int armada_39x_pinctrl_remove(struct platform_device *pdev)
+{
+	return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_39x_pinctrl_driver = {
+	.driver = {
+		.name = "armada-39x-pinctrl",
+		.of_match_table = of_match_ptr(armada_39x_pinctrl_of_match),
+	},
+	.probe = armada_39x_pinctrl_probe,
+	.remove = armada_39x_pinctrl_remove,
+};
+
+module_platform_driver(armada_39x_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada 39x pinctrl driver");
+MODULE_LICENSE("GPL v2");
-- 
2.1.0

[PATCHv2 13/15] ARM: mvebu: add core support for Armada 39x

[Thomas Petazzoni]

This commit adds the core support for Armada 39x, which is quite
simple:

 - a new Kconfig option which selects the appropriate clock and
   pinctrl drivers as well as other common features (GIC, L2 cache,
   SMP, etc.)

 - a new DT_MACHINE_START which references the top-level compatible
   strings supported for the Marvell Armada 39x.

 - a new SMP enable-method. The mechanism to enable CPUs for Armada
   39x appears to be the same as Armada 38x. However, we do not want
   to use marvell,armada-380-smp in the Device Tree, in the case of
   the discovery of a subtle difference in the future, which would
   require changing the Device Tree. And the enable-method isn't a
   compatible string: you can't specify several values and expect a
   fallback on the second string if the first one isn't
   supported. Therefore, we simply declare the SMP enable method
   "marvell,armada-390-smp" as doing the same thing as the
   "marvell,armada-380-smp" one.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/Kconfig      | 14 ++++++++++++++
 arch/arm/mach-mvebu/board-v7.c   | 14 ++++++++++++++
 arch/arm/mach-mvebu/platsmp-a9.c |  2 ++
 3 files changed, 30 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index c1e4567..9747316 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -64,6 +64,20 @@ config MACH_ARMADA_38X
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada 380/385 SoC with device tree.
 
+config MACH_ARMADA_39X
+	bool "Marvell Armada 39x boards" if ARCH_MULTI_V7
+	select ARM_GIC
+	select ARMADA_39X_CLK
+	select CACHE_L2X0
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD if SMP
+	select HAVE_SMP
+	select MACH_MVEBU_V7
+	select PINCTRL_ARMADA_39X
+	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada 39x SoC with device tree.
+
 config MACH_ARMADA_XP
 	bool "Marvell Armada XP boards" if ARCH_MULTI_V7
 	select ARMADA_XP_CLK
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 31b66f2..afee908 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -232,3 +232,17 @@ DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_38x_dt_compat,
 MACHINE_END
+
+static const char * const armada_39x_dt_compat[] __initconst = {
+	"marvell,armada390",
+	"marvell,armada398",
+	NULL,
+};
+
+DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.init_irq       = mvebu_init_irq,
+	.restart	= mvebu_restart,
+	.dt_compat	= armada_39x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 2ec1a42..df0a9cc 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -110,3 +110,5 @@ CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
 		      &mvebu_cortex_a9_smp_ops);
 CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
 		      &armada_38x_smp_ops);
+CPU_METHOD_OF_DECLARE(mvebu_armada_390_smp, "marvell,armada-390-smp",
+		      &armada_38x_smp_ops);
-- 
2.1.0

[PATCHv2 13/15] ARM: mvebu: add core support for Armada 39x

[Thomas Petazzoni]

This commit adds the core support for Armada 39x, which is quite
simple:

 - a new Kconfig option which selects the appropriate clock and
   pinctrl drivers as well as other common features (GIC, L2 cache,
   SMP, etc.)

 - a new DT_MACHINE_START which references the top-level compatible
   strings supported for the Marvell Armada 39x.

 - a new SMP enable-method. The mechanism to enable CPUs for Armada
   39x appears to be the same as Armada 38x. However, we do not want
   to use marvell,armada-380-smp in the Device Tree, in the case of
   the discovery of a subtle difference in the future, which would
   require changing the Device Tree. And the enable-method isn't a
   compatible string: you can't specify several values and expect a
   fallback on the second string if the first one isn't
   supported. Therefore, we simply declare the SMP enable method
   "marvell,armada-390-smp" as doing the same thing as the
   "marvell,armada-380-smp" one.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/mach-mvebu/Kconfig      | 14 ++++++++++++++
 arch/arm/mach-mvebu/board-v7.c   | 14 ++++++++++++++
 arch/arm/mach-mvebu/platsmp-a9.c |  2 ++
 3 files changed, 30 insertions(+)

diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index c1e4567..9747316 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -64,6 +64,20 @@ config MACH_ARMADA_38X
 	  Say 'Y' here if you want your kernel to support boards based
 	  on the Marvell Armada 380/385 SoC with device tree.
 
+config MACH_ARMADA_39X
+	bool "Marvell Armada 39x boards" if ARCH_MULTI_V7
+	select ARM_GIC
+	select ARMADA_39X_CLK
+	select CACHE_L2X0
+	select HAVE_ARM_SCU
+	select HAVE_ARM_TWD if SMP
+	select HAVE_SMP
+	select MACH_MVEBU_V7
+	select PINCTRL_ARMADA_39X
+	help
+	  Say 'Y' here if you want your kernel to support boards based
+	  on the Marvell Armada 39x SoC with device tree.
+
 config MACH_ARMADA_XP
 	bool "Marvell Armada XP boards" if ARCH_MULTI_V7
 	select ARMADA_XP_CLK
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 31b66f2..afee908 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -232,3 +232,17 @@ DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
 	.restart	= mvebu_restart,
 	.dt_compat	= armada_38x_dt_compat,
 MACHINE_END
+
+static const char * const armada_39x_dt_compat[] __initconst = {
+	"marvell,armada390",
+	"marvell,armada398",
+	NULL,
+};
+
+DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
+	.l2c_aux_val	= 0,
+	.l2c_aux_mask	= ~0,
+	.init_irq       = mvebu_init_irq,
+	.restart	= mvebu_restart,
+	.dt_compat	= armada_39x_dt_compat,
+MACHINE_END
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
index 2ec1a42..df0a9cc 100644
--- a/arch/arm/mach-mvebu/platsmp-a9.c
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -110,3 +110,5 @@ CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
 		      &mvebu_cortex_a9_smp_ops);
 CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
 		      &armada_38x_smp_ops);
+CPU_METHOD_OF_DECLARE(mvebu_armada_390_smp, "marvell,armada-390-smp",
+		      &armada_38x_smp_ops);
-- 
2.1.0

[PATCHv2 14/15] ARM: mvebu: add Device Tree files for Armada 39x SoC and board

[Thomas Petazzoni]

This commit adds the Device Tree files for the Armada 39x family of
processors, as well as one Armada 398 Development Board.

Like for other Marvell EBU families, a common armada-39x.dtsi contains
the description of the common features of all Armada 39x SoCs, while
armada-390.dtsi and armada-398.dtsi respectively describe the
specificities of those SoCs.

Finally, an armada-398-db.dts file is added to describe the Armada 398
Development Board itself.

So far, the following features are supported:

 * SMP: dual Cortex-A9
 * Basic ARM IPs: SCU, timer, GIC
 * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus
   controller, MPIC interrupt controller, timer, CPU reset for SMP,
   PMSU.
 * I2C
 * UART
 * PCIe

Additional features will be supported in the future.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/Makefile          |   2 +
 arch/arm/boot/dts/armada-390.dtsi   |  57 +++++
 arch/arm/boot/dts/armada-398-db.dts | 154 +++++++++++
 arch/arm/boot/dts/armada-398.dtsi   |  60 +++++
 arch/arm/boot/dts/armada-39x.dtsi   | 494 ++++++++++++++++++++++++++++++++++++
 5 files changed, 767 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-390.dtsi
 create mode 100644 arch/arm/boot/dts/armada-398-db.dts
 create mode 100644 arch/arm/boot/dts/armada-398.dtsi
 create mode 100644 arch/arm/boot/dts/armada-39x.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 968bc7a..64886fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -540,6 +540,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
 	armada-388-db.dtb \
 	armada-388-gp.dtb \
 	armada-388-rd.dtb
+dtb-$(CONFIG_MACH_ARMADA_39X) += \
+	armada-398-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_XP) += \
 	armada-xp-axpwifiap.dtb \
 	armada-xp-db.dtb \
diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi
new file mode 100644
index 0000000..094e39c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-390.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada 390 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-39x.dtsi"
+
+/ {
+	soc {
+		internal-regs {
+			pinctrl@18000 {
+				compatible = "marvell,mv88f6920-pinctrl";
+				reg = <0x18000 0x20>;
+			};
+		};
+};
diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
new file mode 100644
index 0000000..15dac29
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398-db.dts
@@ -0,0 +1,154 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 Development Board
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-398.dtsi"
+
+/ {
+	model = "Marvell Armada 398 Development Board";
+	compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2 GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi@10680 {
+				status = "okay";
+				pinctrl-0 = <&spi1_pins>;
+				pinctrl-names = "default";
+
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "n25q128a13";
+					reg = <0>;
+					spi-max-frequency = <108000000>;
+
+					partition@0 {
+						label = "U-Boot";
+						reg = <0 0x400000>;
+					};
+
+					partition@400000 {
+						label = "Filesystem";
+						reg = <0x400000 0x1000000>;
+					};
+				};
+			};
+
+			i2c@11000 {
+				pinctrl-0 = <&i2c0_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+			serial@12000 {
+				pinctrl-0 = <&uart0_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+			};
+
+			serial@12100 {
+				pinctrl-0 = <&uart1_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+			};
+
+			flash@d0000 {
+				status = "okay";
+				pinctrl-0 = <&nand_pins>;
+				pinctrl-names = "default";
+				num-cs = <1>;
+				marvell,nand-keep-config;
+				marvell,nand-enable-arbiter;
+				nand-on-flash-bbt;
+				nand-ecc-strength = <8>;
+				nand-ecc-step-size = <512>;
+
+				partition@0 {
+					label = "U-Boot";
+					reg = <0 0x800000>;
+				};
+				partition@800000 {
+					label = "Linux";
+					reg = <0x800000 0x800000>;
+				};
+				partition@1000000 {
+					label = "Filesystem";
+					reg = <0x1000000 0x3f000000>;
+				};
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie@1,0 {
+				status = "okay";
+			};
+
+			pcie@2,0 {
+				status = "okay";
+			};
+
+			pcie@3,0 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi
new file mode 100644
index 0000000..fdc2591
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-39x.dtsi"
+
+/ {
+	compatible = "marvell,armada398", "marvell,armada390";
+
+	soc {
+		internal-regs {
+			pinctrl@18000 {
+				compatible = "marvell,mv88f6928-pinctrl";
+				reg = <0x18000 0x20>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
new file mode 100644
index 0000000..fe43cd7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -0,0 +1,494 @@
+/*
+ * Device Tree Include file for Marvell Armada 39x family of SoCs.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+/ {
+	model = "Marvell Armada 39x family SoC";
+	compatible = "marvell,armada390";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "marvell,armada-390-smp";
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
+			     "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		controller = <&mbusc>;
+		interrupt-parent = <&gic>;
+		pcie-mem-aperture = <0xe0000000 0x8000000>;
+		pcie-io-aperture  = <0xe8000000 0x100000>;
+
+		bootrom {
+			compatible = "marvell,bootrom";
+			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
+		};
+
+		internal-regs {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+			scu@c000 {
+				compatible = "arm,cortex-a9-scu";
+				reg = <0xc000 0x100>;
+			};
+
+			timer@c600 {
+				compatible = "arm,cortex-a9-twd-timer";
+				reg = <0xc600 0x20>;
+				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+				clocks = <&coreclk 2>;
+			};
+
+			gic: interrupt-controller@d000 {
+				compatible = "arm,cortex-a9-gic";
+				#interrupt-cells = <3>;
+				#size-cells = <0>;
+				interrupt-controller;
+				reg = <0xd000 0x1000>,
+				      <0xc100 0x100>;
+			};
+
+			spi0: spi@10600 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10600 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <0>;
+				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			spi1: spi@10680 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10680 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <1>;
+				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c0: i2c@11000 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c@11100 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11100 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c@11200 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11200 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c3: i2c@11300 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11300 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart0: serial@12000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart1: serial@12100 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12100 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart2: serial@12200 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12200 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart3: serial@12300 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12300 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			pinctrl@18000 {
+				i2c0_pins: i2c0-pins {
+					marvell,pins = "mpp2", "mpp3";
+					marvell,function = "i2c0";
+				};
+
+				uart0_pins: uart0-pins {
+					marvell,pins = "mpp0", "mpp1";
+					marvell,function = "ua0";
+				};
+
+				uart1_pins: uart1-pins {
+					marvell,pins = "mpp19", "mpp20";
+					marvell,function = "ua1";
+				};
+
+				spi1_pins: spi1-pins {
+					marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
+					marvell,function = "spi1";
+				};
+
+				nand_pins: nand-pins {
+					marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+						       "mpp38", "mpp28", "mpp40", "mpp42",
+						       "mpp35", "mpp36", "mpp25", "mpp30",
+						       "mpp32";
+					marvell,function = "dev";
+				};
+			};
+
+			system-controller@18200 {
+				compatible = "marvell,armada-390-system-controller",
+					     "marvell,armada-370-xp-system-controller";
+				reg = <0x18200 0x100>;
+			};
+
+			gateclk: clock-gating-control@18220 {
+				compatible = "marvell,armada-390-gating-clock";
+				reg = <0x18220 0x4>;
+				clocks = <&coreclk 0>;
+				#clock-cells = <1>;
+			};
+
+			coreclk: mvebu-sar@18600 {
+				compatible = "marvell,armada-390-core-clock";
+				reg = <0x18600 0x04>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller@20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
+			};
+
+			mpic: interrupt-controller@20000 {
+				compatible = "marvell,mpic";
+				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+				#interrupt-cells = <1>;
+				#size-cells = <1>;
+				interrupt-controller;
+				msi-controller;
+				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			timer@20300 {
+				compatible = "marvell,armada-380-timer",
+					     "marvell,armada-xp-timer";
+				reg = <0x20300 0x30>, <0x21040 0x30>;
+				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+						      <&mpic 5>,
+						      <&mpic 6>;
+				clocks = <&coreclk 2>, <&coreclk 5>;
+				clock-names = "nbclk", "fixed";
+			};
+
+			cpurst@20800 {
+				compatible = "marvell,armada-370-cpu-reset";
+				reg = <0x20800 0x10>;
+			};
+
+			pmsu@22000 {
+				compatible = "marvell,armada-390-pmsu",
+					     "marvell,armada-380-pmsu";
+				reg = <0x22000 0x1000>;
+			};
+
+			xor@60800 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60800 0x100
+				       0x60a00 0x100>;
+				clocks = <&gateclk 22>;
+				status = "okay";
+
+				xor00 {
+					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor01 {
+					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			xor@60900 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
+				clocks = <&gateclk 28>;
+				status = "okay";
+
+				xor10 {
+					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor11 {
+					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			flash@d0000 {
+				compatible = "marvell,armada370-nand";
+				reg = <0xd0000 0x54>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&coredivclk 0>;
+				status = "disabled";
+			};
+
+			sdhci@d8000 {
+				compatible = "marvell,armada-380-sdhci";
+				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gateclk 17>;
+				mrvl,clk-delay-cycles = <0x1F>;
+				status = "disabled";
+			};
+
+			coredivclk: clock@e4250 {
+				compatible = "marvell,armada-390-corediv-clock",
+					     "marvell,armada-380-corediv-clock";
+				reg = <0xe4250 0xc>;
+				#clock-cells = <1>;
+				clocks = <&mainpll>;
+				clock-output-names = "nand";
+			};
+		};
+
+		pcie-controller {
+			compatible = "marvell,armada-370-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			msi-parent = <&mpic>;
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
+				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
+				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
+
+			/*
+			 * This port can be either x4 or x1. When
+			 * configured in x4 by the bootloader, then
+			 * pcie@4,0 is not available.
+			 */
+			pcie@1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 8>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie@2,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <1>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 5>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie@3,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+				reg = <0x1800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <2>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 6>;
+				status = "disabled";
+			};
+
+			/*
+			 * x1 port only available when pcie@1,0 is
+			 * configured as a x1 port
+			 */
+			pcie@4,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+				reg = <0x2000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <3>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 7>;
+				status = "disabled";
+			};
+		};
+	};
+
+	clocks {
+		/* 2 GHz fixed main PLL */
+		mainpll: mainpll {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <2000000000>;
+		};
+	};
+};
-- 
2.1.0

[PATCHv2 14/15] ARM: mvebu: add Device Tree files for Armada 39x SoC and board

[Thomas Petazzoni]

This commit adds the Device Tree files for the Armada 39x family of
processors, as well as one Armada 398 Development Board.

Like for other Marvell EBU families, a common armada-39x.dtsi contains
the description of the common features of all Armada 39x SoCs, while
armada-390.dtsi and armada-398.dtsi respectively describe the
specificities of those SoCs.

Finally, an armada-398-db.dts file is added to describe the Armada 398
Development Board itself.

So far, the following features are supported:

 * SMP: dual Cortex-A9
 * Basic ARM IPs: SCU, timer, GIC
 * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus
   controller, MPIC interrupt controller, timer, CPU reset for SMP,
   PMSU.
 * I2C
 * UART
 * PCIe

Additional features will be supported in the future.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 arch/arm/boot/dts/Makefile          |   2 +
 arch/arm/boot/dts/armada-390.dtsi   |  57 +++++
 arch/arm/boot/dts/armada-398-db.dts | 154 +++++++++++
 arch/arm/boot/dts/armada-398.dtsi   |  60 +++++
 arch/arm/boot/dts/armada-39x.dtsi   | 494 ++++++++++++++++++++++++++++++++++++
 5 files changed, 767 insertions(+)
 create mode 100644 arch/arm/boot/dts/armada-390.dtsi
 create mode 100644 arch/arm/boot/dts/armada-398-db.dts
 create mode 100644 arch/arm/boot/dts/armada-398.dtsi
 create mode 100644 arch/arm/boot/dts/armada-39x.dtsi

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 968bc7a..64886fb 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -540,6 +540,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
 	armada-388-db.dtb \
 	armada-388-gp.dtb \
 	armada-388-rd.dtb
+dtb-$(CONFIG_MACH_ARMADA_39X) += \
+	armada-398-db.dtb
 dtb-$(CONFIG_MACH_ARMADA_XP) += \
 	armada-xp-axpwifiap.dtb \
 	armada-xp-db.dtb \
diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi
new file mode 100644
index 0000000..094e39c
--- /dev/null
+++ b/arch/arm/boot/dts/armada-390.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada 390 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-39x.dtsi"
+
+/ {
+	soc {
+		internal-regs {
+			pinctrl at 18000 {
+				compatible = "marvell,mv88f6920-pinctrl";
+				reg = <0x18000 0x20>;
+			};
+		};
+};
diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
new file mode 100644
index 0000000..15dac29
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398-db.dts
@@ -0,0 +1,154 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 Development Board
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-398.dtsi"
+
+/ {
+	model = "Marvell Armada 398 Development Board";
+	compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+		stdout-path = &uart0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x80000000>; /* 2 GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi at 10680 {
+				status = "okay";
+				pinctrl-0 = <&spi1_pins>;
+				pinctrl-names = "default";
+
+				spi-flash at 0 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					compatible = "n25q128a13";
+					reg = <0>;
+					spi-max-frequency = <108000000>;
+
+					partition at 0 {
+						label = "U-Boot";
+						reg = <0 0x400000>;
+					};
+
+					partition at 400000 {
+						label = "Filesystem";
+						reg = <0x400000 0x1000000>;
+					};
+				};
+			};
+
+			i2c at 11000 {
+				pinctrl-0 = <&i2c0_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+				clock-frequency = <100000>;
+			};
+
+			serial at 12000 {
+				pinctrl-0 = <&uart0_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+			};
+
+			serial at 12100 {
+				pinctrl-0 = <&uart1_pins>;
+				pinctrl-names = "default";
+				status = "okay";
+			};
+
+			flash at d0000 {
+				status = "okay";
+				pinctrl-0 = <&nand_pins>;
+				pinctrl-names = "default";
+				num-cs = <1>;
+				marvell,nand-keep-config;
+				marvell,nand-enable-arbiter;
+				nand-on-flash-bbt;
+				nand-ecc-strength = <8>;
+				nand-ecc-step-size = <512>;
+
+				partition at 0 {
+					label = "U-Boot";
+					reg = <0 0x800000>;
+				};
+				partition at 800000 {
+					label = "Linux";
+					reg = <0x800000 0x800000>;
+				};
+				partition at 1000000 {
+					label = "Filesystem";
+					reg = <0x1000000 0x3f000000>;
+				};
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie at 1,0 {
+				status = "okay";
+			};
+
+			pcie at 2,0 {
+				status = "okay";
+			};
+
+			pcie at 3,0 {
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi
new file mode 100644
index 0000000..fdc2591
--- /dev/null
+++ b/arch/arm/boot/dts/armada-398.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Device Tree Include file for Marvell Armada 398 SoC.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-39x.dtsi"
+
+/ {
+	compatible = "marvell,armada398", "marvell,armada390";
+
+	soc {
+		internal-regs {
+			pinctrl at 18000 {
+				compatible = "marvell,mv88f6928-pinctrl";
+				reg = <0x18000 0x20>;
+			};
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
new file mode 100644
index 0000000..fe43cd7
--- /dev/null
+++ b/arch/arm/boot/dts/armada-39x.dtsi
@@ -0,0 +1,494 @@
+/*
+ * Device Tree Include file for Marvell Armada 39x family of SoCs.
+ *
+ * Copyright (C) 2015 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "skeleton.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
+
+/ {
+	model = "Marvell Armada 39x family SoC";
+	compatible = "marvell,armada390";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		enable-method = "marvell,armada-390-smp";
+
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+		cpu at 1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+		};
+	};
+
+	soc {
+		compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
+			     "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <1>;
+		controller = <&mbusc>;
+		interrupt-parent = <&gic>;
+		pcie-mem-aperture = <0xe0000000 0x8000000>;
+		pcie-io-aperture  = <0xe8000000 0x100000>;
+
+		bootrom {
+			compatible = "marvell,bootrom";
+			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
+		};
+
+		internal-regs {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+
+			scu at c000 {
+				compatible = "arm,cortex-a9-scu";
+				reg = <0xc000 0x100>;
+			};
+
+			timer at c600 {
+				compatible = "arm,cortex-a9-twd-timer";
+				reg = <0xc600 0x20>;
+				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
+				clocks = <&coreclk 2>;
+			};
+
+			gic: interrupt-controller at d000 {
+				compatible = "arm,cortex-a9-gic";
+				#interrupt-cells = <3>;
+				#size-cells = <0>;
+				interrupt-controller;
+				reg = <0xd000 0x1000>,
+				      <0xc100 0x100>;
+			};
+
+			spi0: spi at 10600 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10600 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <0>;
+				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			spi1: spi at 10680 {
+				compatible = "marvell,orion-spi";
+				reg = <0x10680 0x50>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cell-index = <1>;
+				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c0: i2c at 11000 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11000 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c1: i2c at 11100 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11100 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c2: i2c at 11200 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11200 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			i2c3: i2c at 11300 {
+				compatible = "marvell,mv64xxx-i2c";
+				reg = <0x11300 0x20>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+				timeout-ms = <1000>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart0: serial at 12000 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12000 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart1: serial at 12100 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12100 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart2: serial at 12200 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12200 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			uart3: serial at 12300 {
+				compatible = "snps,dw-apb-uart";
+				reg = <0x12300 0x100>;
+				reg-shift = <2>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+				reg-io-width = <1>;
+				clocks = <&coreclk 0>;
+				status = "disabled";
+			};
+
+			pinctrl at 18000 {
+				i2c0_pins: i2c0-pins {
+					marvell,pins = "mpp2", "mpp3";
+					marvell,function = "i2c0";
+				};
+
+				uart0_pins: uart0-pins {
+					marvell,pins = "mpp0", "mpp1";
+					marvell,function = "ua0";
+				};
+
+				uart1_pins: uart1-pins {
+					marvell,pins = "mpp19", "mpp20";
+					marvell,function = "ua1";
+				};
+
+				spi1_pins: spi1-pins {
+					marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
+					marvell,function = "spi1";
+				};
+
+				nand_pins: nand-pins {
+					marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
+						       "mpp38", "mpp28", "mpp40", "mpp42",
+						       "mpp35", "mpp36", "mpp25", "mpp30",
+						       "mpp32";
+					marvell,function = "dev";
+				};
+			};
+
+			system-controller at 18200 {
+				compatible = "marvell,armada-390-system-controller",
+					     "marvell,armada-370-xp-system-controller";
+				reg = <0x18200 0x100>;
+			};
+
+			gateclk: clock-gating-control at 18220 {
+				compatible = "marvell,armada-390-gating-clock";
+				reg = <0x18220 0x4>;
+				clocks = <&coreclk 0>;
+				#clock-cells = <1>;
+			};
+
+			coreclk: mvebu-sar at 18600 {
+				compatible = "marvell,armada-390-core-clock";
+				reg = <0x18600 0x04>;
+				#clock-cells = <1>;
+			};
+
+			mbusc: mbus-controller at 20000 {
+				compatible = "marvell,mbus-controller";
+				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
+			};
+
+			mpic: interrupt-controller at 20000 {
+				compatible = "marvell,mpic";
+				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
+				#interrupt-cells = <1>;
+				#size-cells = <1>;
+				interrupt-controller;
+				msi-controller;
+				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			timer at 20300 {
+				compatible = "marvell,armada-380-timer",
+					     "marvell,armada-xp-timer";
+				reg = <0x20300 0x30>, <0x21040 0x30>;
+				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
+						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
+						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+						      <&mpic 5>,
+						      <&mpic 6>;
+				clocks = <&coreclk 2>, <&coreclk 5>;
+				clock-names = "nbclk", "fixed";
+			};
+
+			cpurst at 20800 {
+				compatible = "marvell,armada-370-cpu-reset";
+				reg = <0x20800 0x10>;
+			};
+
+			pmsu at 22000 {
+				compatible = "marvell,armada-390-pmsu",
+					     "marvell,armada-380-pmsu";
+				reg = <0x22000 0x1000>;
+			};
+
+			xor at 60800 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60800 0x100
+				       0x60a00 0x100>;
+				clocks = <&gateclk 22>;
+				status = "okay";
+
+				xor00 {
+					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor01 {
+					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			xor at 60900 {
+				compatible = "marvell,orion-xor";
+				reg = <0x60900 0x100
+				       0x60b00 0x100>;
+				clocks = <&gateclk 28>;
+				status = "okay";
+
+				xor10 {
+					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+				};
+				xor11 {
+					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+					dmacap,memcpy;
+					dmacap,xor;
+					dmacap,memset;
+				};
+			};
+
+			flash at d0000 {
+				compatible = "marvell,armada370-nand";
+				reg = <0xd0000 0x54>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&coredivclk 0>;
+				status = "disabled";
+			};
+
+			sdhci at d8000 {
+				compatible = "marvell,armada-380-sdhci";
+				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&gateclk 17>;
+				mrvl,clk-delay-cycles = <0x1F>;
+				status = "disabled";
+			};
+
+			coredivclk: clock at e4250 {
+				compatible = "marvell,armada-390-corediv-clock",
+					     "marvell,armada-380-corediv-clock";
+				reg = <0xe4250 0xc>;
+				#clock-cells = <1>;
+				clocks = <&mainpll>;
+				clock-output-names = "nand";
+			};
+		};
+
+		pcie-controller {
+			compatible = "marvell,armada-370-pcie";
+			status = "disabled";
+			device_type = "pci";
+
+			#address-cells = <3>;
+			#size-cells = <2>;
+
+			msi-parent = <&mpic>;
+			bus-range = <0x00 0xff>;
+
+			ranges =
+			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
+				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
+				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
+				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
+				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
+				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
+				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
+				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
+				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
+				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
+				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
+
+			/*
+			 * This port can be either x4 or x1. When
+			 * configured in x4 by the bootloader, then
+			 * pcie at 4,0 is not available.
+			 */
+			pcie at 1,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+				reg = <0x0800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <0>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 8>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie at 2,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
+				reg = <0x1000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
+					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <1>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 5>;
+				status = "disabled";
+			};
+
+			/* x1 port */
+			pcie at 3,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
+				reg = <0x1800 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
+					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <2>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 6>;
+				status = "disabled";
+			};
+
+			/*
+			 * x1 port only available when pcie at 1,0 is
+			 * configured as a x1 port
+			 */
+			pcie at 4,0 {
+				device_type = "pci";
+				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
+				reg = <0x2000 0 0 0 0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				#interrupt-cells = <1>;
+				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
+					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
+				interrupt-map-mask = <0 0 0 0>;
+				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+				marvell,pcie-port = <3>;
+				marvell,pcie-lane = <0>;
+				clocks = <&gateclk 7>;
+				status = "disabled";
+			};
+		};
+	};
+
+	clocks {
+		/* 2 GHz fixed main PLL */
+		mainpll: mainpll {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <2000000000>;
+		};
+	};
+};
-- 
2.1.0

[PATCHv2 15/15] Documentation: arm: update supported Marvell EBU processors

[Thomas Petazzoni]

Now that we support Armada 39x, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details
about those processors. Unfortunately, no datasheet is publicly
available at this time.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 Documentation/arm/Marvell/README | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index 1745379..18a775d 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -96,6 +96,11 @@ EBU Armada family
 	88F6820
 	88F6828
 
+  Armada 390/398 Flavors:
+	88F6920
+	88F6928
+    Product infos: http://www.marvell.com/embedded-processors/armada-39x/
+
   Armada XP Flavors:
         MV78230
         MV78260
-- 
2.1.0

[PATCHv2 15/15] Documentation: arm: update supported Marvell EBU processors

[Thomas Petazzoni]

Now that we support Armada 39x, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details
about those processors. Unfortunately, no datasheet is publicly
available at this time.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
 Documentation/arm/Marvell/README | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index 1745379..18a775d 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -96,6 +96,11 @@ EBU Armada family
 	88F6820
 	88F6828
 
+  Armada 390/398 Flavors:
+	88F6920
+	88F6928
+    Product infos: http://www.marvell.com/embedded-processors/armada-39x/
+
   Armada XP Flavors:
         MV78230
         MV78260
-- 
2.1.0

Re: [PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Mike Turquette]

Quoting Thomas Petazzoni (2015-02-20 09:04:29)
> The Armada 39x, contrary to its predecessor, has a configurable
> reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
> previous SoCs, it was fixed to 25 Mhz and described directly as such
> in the Device Tree.
> 
> For Armada 39x, we need to read certain registers to know whether the
> frequency is 25 or 40 Mhz. Therefore, this commit extends the common
> mvebu clock code to allow the SoC-specific code to say it wants to
> register a reference clock, by giving a non-NULL ->get_refclk_freq()
> function pointer in its coreclk_soc_desc structure.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Looks fine to me. I'll apply after -rc1 drops.

Regards,
Mike

> ---
>  drivers/clk/mvebu/common.c | 17 +++++++++++++++++
>  drivers/clk/mvebu/common.h |  1 +
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
> index 0d4d121..15b370f 100644
> --- a/drivers/clk/mvebu/common.c
> +++ b/drivers/clk/mvebu/common.c
> @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>  
>         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
>         clk_data.clk_num = 2 + desc->num_ratios;
> +
> +       /* One more clock for the optional refclk */
> +       if (desc->get_refclk_freq)
> +               clk_data.clk_num += 1;
> +
>         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
>                                 GFP_KERNEL);
>         if (WARN_ON(!clk_data.clks)) {
> @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
>         };
>  
> +       /* Register optional refclk */
> +       if (desc->get_refclk_freq) {
> +               const char *name = "refclk";
> +               of_property_read_string_index(np, "clock-output-names",
> +                                             2 + desc->num_ratios, &name);
> +               rate = desc->get_refclk_freq(base);
> +               clk_data.clks[2 + desc->num_ratios] =
> +                       clk_register_fixed_rate(NULL, name, NULL,
> +                                               CLK_IS_ROOT, rate);
> +               WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
> +       }
> +
>         /* SAR register isn't needed anymore */
>         iounmap(base);
>  
> diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
> index 783b563..f0de6c8 100644
> --- a/drivers/clk/mvebu/common.h
> +++ b/drivers/clk/mvebu/common.h
> @@ -30,6 +30,7 @@ struct coreclk_soc_desc {
>         u32 (*get_tclk_freq)(void __iomem *sar);
>         u32 (*get_cpu_freq)(void __iomem *sar);
>         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
> +       u32 (*get_refclk_freq)(void __iomem *sar);
>         bool (*is_sscg_enabled)(void __iomem *sar);
>         u32 (*fix_sscg_deviation)(u32 system_clk);
>         const struct coreclk_ratio *ratios;
> -- 
> 2.1.0
> 

[PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Mike Turquette]

Quoting Thomas Petazzoni (2015-02-20 09:04:29)
> The Armada 39x, contrary to its predecessor, has a configurable
> reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
> previous SoCs, it was fixed to 25 Mhz and described directly as such
> in the Device Tree.
> 
> For Armada 39x, we need to read certain registers to know whether the
> frequency is 25 or 40 Mhz. Therefore, this commit extends the common
> mvebu clock code to allow the SoC-specific code to say it wants to
> register a reference clock, by giving a non-NULL ->get_refclk_freq()
> function pointer in its coreclk_soc_desc structure.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Looks fine to me. I'll apply after -rc1 drops.

Regards,
Mike

> ---
>  drivers/clk/mvebu/common.c | 17 +++++++++++++++++
>  drivers/clk/mvebu/common.h |  1 +
>  2 files changed, 18 insertions(+)
> 
> diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
> index 0d4d121..15b370f 100644
> --- a/drivers/clk/mvebu/common.c
> +++ b/drivers/clk/mvebu/common.c
> @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>  
>         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
>         clk_data.clk_num = 2 + desc->num_ratios;
> +
> +       /* One more clock for the optional refclk */
> +       if (desc->get_refclk_freq)
> +               clk_data.clk_num += 1;
> +
>         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
>                                 GFP_KERNEL);
>         if (WARN_ON(!clk_data.clks)) {
> @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
>         };
>  
> +       /* Register optional refclk */
> +       if (desc->get_refclk_freq) {
> +               const char *name = "refclk";
> +               of_property_read_string_index(np, "clock-output-names",
> +                                             2 + desc->num_ratios, &name);
> +               rate = desc->get_refclk_freq(base);
> +               clk_data.clks[2 + desc->num_ratios] =
> +                       clk_register_fixed_rate(NULL, name, NULL,
> +                                               CLK_IS_ROOT, rate);
> +               WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
> +       }
> +
>         /* SAR register isn't needed anymore */
>         iounmap(base);
>  
> diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
> index 783b563..f0de6c8 100644
> --- a/drivers/clk/mvebu/common.h
> +++ b/drivers/clk/mvebu/common.h
> @@ -30,6 +30,7 @@ struct coreclk_soc_desc {
>         u32 (*get_tclk_freq)(void __iomem *sar);
>         u32 (*get_cpu_freq)(void __iomem *sar);
>         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
> +       u32 (*get_refclk_freq)(void __iomem *sar);
>         bool (*is_sscg_enabled)(void __iomem *sar);
>         u32 (*fix_sscg_deviation)(u32 system_clk);
>         const struct coreclk_ratio *ratios;
> -- 
> 2.1.0
> 

Re: [PATCHv2 01/15] ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat tables

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> As suggested by Stephen Boyd, this commit adds the __initconst
> specifier to the dt_compat table declarations used by the
> DT_MACHINE_START structures in mach-mvebu land.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/board-v7.c | 6 +++---
>  arch/arm/mach-mvebu/dove.c     | 2 +-
>  arch/arm/mach-mvebu/kirkwood.c | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
> index 89a139e..31b66f2 100644
> --- a/arch/arm/mach-mvebu/board-v7.c
> +++ b/arch/arm/mach-mvebu/board-v7.c
> @@ -184,7 +184,7 @@ static void __init mvebu_dt_init(void)
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
>  
> -static const char * const armada_370_xp_dt_compat[] = {
> +static const char * const armada_370_xp_dt_compat[] __initconst = {
>  	"marvell,armada-370-xp",
>  	NULL,
>  };
> @@ -205,7 +205,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
>  	.dt_compat	= armada_370_xp_dt_compat,
>  MACHINE_END
>  
> -static const char * const armada_375_dt_compat[] = {
> +static const char * const armada_375_dt_compat[] __initconst = {
>  	"marvell,armada375",
>  	NULL,
>  };
> @@ -219,7 +219,7 @@ DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
>  	.dt_compat	= armada_375_dt_compat,
>  MACHINE_END
>  
> -static const char * const armada_38x_dt_compat[] = {
> +static const char * const armada_38x_dt_compat[] __initconst = {
>  	"marvell,armada380",
>  	"marvell,armada385",
>  	NULL,
> diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
> index b50464e..5a17415 100644
> --- a/arch/arm/mach-mvebu/dove.c
> +++ b/arch/arm/mach-mvebu/dove.c
> @@ -27,7 +27,7 @@ static void __init dove_init(void)
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
>  
> -static const char * const dove_dt_compat[] = {
> +static const char * const dove_dt_compat[] __initconst = {
>  	"marvell,dove",
>  	NULL
>  };
> diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
> index 6b53108..925f75f 100644
> --- a/arch/arm/mach-mvebu/kirkwood.c
> +++ b/arch/arm/mach-mvebu/kirkwood.c
> @@ -186,7 +186,7 @@ static void __init kirkwood_dt_init(void)
>  	of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
>  }
>  
> -static const char * const kirkwood_dt_board_compat[] = {
> +static const char * const kirkwood_dt_board_compat[] __initconst = {
>  	"marvell,kirkwood",
>  	NULL
>  };
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 01/15] ARM: mvebu: add __initconst specifiers on DT_MACHINE_START dt_compat tables

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> As suggested by Stephen Boyd, this commit adds the __initconst
> specifier to the dt_compat table declarations used by the
> DT_MACHINE_START structures in mach-mvebu land.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/mach-mvebu/board-v7.c | 6 +++---
>  arch/arm/mach-mvebu/dove.c     | 2 +-
>  arch/arm/mach-mvebu/kirkwood.c | 2 +-
>  3 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
> index 89a139e..31b66f2 100644
> --- a/arch/arm/mach-mvebu/board-v7.c
> +++ b/arch/arm/mach-mvebu/board-v7.c
> @@ -184,7 +184,7 @@ static void __init mvebu_dt_init(void)
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
>  
> -static const char * const armada_370_xp_dt_compat[] = {
> +static const char * const armada_370_xp_dt_compat[] __initconst = {
>  	"marvell,armada-370-xp",
>  	NULL,
>  };
> @@ -205,7 +205,7 @@ DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
>  	.dt_compat	= armada_370_xp_dt_compat,
>  MACHINE_END
>  
> -static const char * const armada_375_dt_compat[] = {
> +static const char * const armada_375_dt_compat[] __initconst = {
>  	"marvell,armada375",
>  	NULL,
>  };
> @@ -219,7 +219,7 @@ DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
>  	.dt_compat	= armada_375_dt_compat,
>  MACHINE_END
>  
> -static const char * const armada_38x_dt_compat[] = {
> +static const char * const armada_38x_dt_compat[] __initconst = {
>  	"marvell,armada380",
>  	"marvell,armada385",
>  	NULL,
> diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
> index b50464e..5a17415 100644
> --- a/arch/arm/mach-mvebu/dove.c
> +++ b/arch/arm/mach-mvebu/dove.c
> @@ -27,7 +27,7 @@ static void __init dove_init(void)
>  	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
>  }
>  
> -static const char * const dove_dt_compat[] = {
> +static const char * const dove_dt_compat[] __initconst = {
>  	"marvell,dove",
>  	NULL
>  };
> diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
> index 6b53108..925f75f 100644
> --- a/arch/arm/mach-mvebu/kirkwood.c
> +++ b/arch/arm/mach-mvebu/kirkwood.c
> @@ -186,7 +186,7 @@ static void __init kirkwood_dt_init(void)
>  	of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
>  }
>  
> -static const char * const kirkwood_dt_board_compat[] = {
> +static const char * const kirkwood_dt_board_compat[] __initconst = {
>  	"marvell,kirkwood",
>  	NULL
>  };
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 02/15] ARM: mvebu: fix usb@ unit address on Armada 38x to match register address

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> On Marvell Armada 38x, the USB2 controller registers are at 0x58000,
> so the corresponding Device Tree node should have a unit address of
> 58000, and not 50000. We were using 50000 due to an incorrect
> copy/pastebin of Armada 370/XP code.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/boot/dts/armada-388-db.dts | 2 +-
>  arch/arm/boot/dts/armada-388-gp.dts | 2 +-
>  arch/arm/boot/dts/armada-38x.dtsi   | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
> index 16512ef..af6c74e 100644
> --- a/arch/arm/boot/dts/armada-388-db.dts
> +++ b/arch/arm/boot/dts/armada-388-db.dts
> @@ -99,7 +99,7 @@
>  				phy-mode = "rgmii-id";
>  			};
>  
> -			usb@50000 {
> +			usb@58000 {
>  				status = "ok";
>  			};
>  
> diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
> index 590b383..3ff0573 100644
> --- a/arch/arm/boot/dts/armada-388-gp.dts
> +++ b/arch/arm/boot/dts/armada-388-gp.dts
> @@ -135,7 +135,7 @@
>  			};
>  
>  			/* CON4 */
> -			usb@50000 {
> +			usb@58000 {
>  				vcc-supply = <&reg_usb2_0_vbus>;
>  				status = "okay";
>  			};
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 54ebce7..96d7cf0 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -435,7 +435,7 @@
>  				status = "disabled";
>  			};
>  
> -			usb@50000 {
> +			usb@58000 {
>  				compatible = "marvell,orion-ehci";
>  				reg = <0x58000 0x500>;
>  				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 02/15] ARM: mvebu: fix usb@ unit address on Armada 38x to match register address

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> On Marvell Armada 38x, the USB2 controller registers are at 0x58000,
> so the corresponding Device Tree node should have a unit address of
> 58000, and not 50000. We were using 50000 due to an incorrect
> copy/pastebin of Armada 370/XP code.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/boot/dts/armada-388-db.dts | 2 +-
>  arch/arm/boot/dts/armada-388-gp.dts | 2 +-
>  arch/arm/boot/dts/armada-38x.dtsi   | 2 +-
>  3 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
> index 16512ef..af6c74e 100644
> --- a/arch/arm/boot/dts/armada-388-db.dts
> +++ b/arch/arm/boot/dts/armada-388-db.dts
> @@ -99,7 +99,7 @@
>  				phy-mode = "rgmii-id";
>  			};
>  
> -			usb at 50000 {
> +			usb at 58000 {
>  				status = "ok";
>  			};
>  
> diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
> index 590b383..3ff0573 100644
> --- a/arch/arm/boot/dts/armada-388-gp.dts
> +++ b/arch/arm/boot/dts/armada-388-gp.dts
> @@ -135,7 +135,7 @@
>  			};
>  
>  			/* CON4 */
> -			usb at 50000 {
> +			usb at 58000 {
>  				vcc-supply = <&reg_usb2_0_vbus>;
>  				status = "okay";
>  			};
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 54ebce7..96d7cf0 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -435,7 +435,7 @@
>  				status = "disabled";
>  			};
>  
> -			usb at 50000 {
> +			usb at 58000 {
>  				compatible = "marvell,orion-ehci";
>  				reg = <0x58000 0x500>;
>  				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 03/15] ARM: mvebu: add missing UART alias on Armada 38x

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> The Armada 38x had an alias for UART0, but not UART1. This commit
> fixes that.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/boot/dts/armada-38x.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 96d7cf0..8c76a8d 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -216,7 +216,7 @@
>  				status = "disabled";
>  			};
>  
> -			serial@12100 {
> +			uart1: serial@12100 {
>  				compatible = "snps,dw-apb-uart";
>  				reg = <0x12100 0x100>;
>  				reg-shift = <2>;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 03/15] ARM: mvebu: add missing UART alias on Armada 38x

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> The Armada 38x had an alias for UART0, but not UART1. This commit
> fixes that.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  arch/arm/boot/dts/armada-38x.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 96d7cf0..8c76a8d 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -216,7 +216,7 @@
>  				status = "disabled";
>  			};
>  
> -			serial at 12100 {
> +			uart1: serial at 12100 {
>  				compatible = "snps,dw-apb-uart";
>  				reg = <0x12100 0x100>;
>  				reg-shift = <2>;
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 04/15] ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> The Armada 38x SDHCI controller definition in the SoC Device Tree file
> is using hardcoded values instead of the nice GIC and IRQ macros
> provided by DT header files. This commit fixes that, which allows the
> SDHCI interrupt definition to be consistent with was is done in the
> rest of the file.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

I already submitted this fix as part of the "fixes and improvements for SDHCI" series.

Thanks,

Gregory

> ---
>  arch/arm/boot/dts/armada-38x.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 8c76a8d..0f0cc41 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -542,7 +542,7 @@
>  			sdhci@d8000 {
>  				compatible = "marvell,armada-380-sdhci";
>  				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
> -				interrupts = <0 25 0x4>;
> +				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&gateclk 17>;
>  				mrvl,clk-delay-cycles = <0x1F>;
>  				status = "disabled";
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 04/15] ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> The Armada 38x SDHCI controller definition in the SoC Device Tree file
> is using hardcoded values instead of the nice GIC and IRQ macros
> provided by DT header files. This commit fixes that, which allows the
> SDHCI interrupt definition to be consistent with was is done in the
> rest of the file.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

I already submitted this fix as part of the "fixes and improvements for SDHCI" series.

Thanks,

Gregory

> ---
>  arch/arm/boot/dts/armada-38x.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
> index 8c76a8d..0f0cc41 100644
> --- a/arch/arm/boot/dts/armada-38x.dtsi
> +++ b/arch/arm/boot/dts/armada-38x.dtsi
> @@ -542,7 +542,7 @@
>  			sdhci at d8000 {
>  				compatible = "marvell,armada-380-sdhci";
>  				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
> -				interrupts = <0 25 0x4>;
> +				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>  				clocks = <&gateclk 17>;
>  				mrvl,clk-delay-cycles = <0x1F>;
>  				status = "disabled";
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> This commit adds the stdout-path property in /chosen for all Armada
> boards that were not yet carrying this property.

I though the main motivation for using the stdout-path property was
for removing the earlyprintk in the command line. Arnd told that there
should be a mean to use stdout-path instead of earlyprintk.

So what about going further and removing "earlyprintk" in the same time?

Thanks,

Gregory

> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-db.dts              | 1 +
>  arch/arm/boot/dts/armada-370-mirabox.dts         | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn102.dts   | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn104.dts   | 1 +
>  arch/arm/boot/dts/armada-370-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-375-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-xp-axpwifiap.dts        | 1 +
>  arch/arm/boot/dts/armada-xp-db.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-gp.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-matrix.dts           | 1 +
>  arch/arm/boot/dts/armada-xp-netgear-rn2120.dts   | 1 +
>  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 1 +
>  14 files changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
> index e993c46..286bedd 100644
> --- a/arch/arm/boot/dts/armada-370-db.dts
> +++ b/arch/arm/boot/dts/armada-370-db.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
> index b10ceb4..ec77b86 100644
> --- a/arch/arm/boot/dts/armada-370-mirabox.dts
> +++ b/arch/arm/boot/dts/armada-370-mirabox.dts
> @@ -52,6 +52,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> index 7c5c4ff..8c786cf 100644
> --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> @@ -54,6 +54,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
> index 1de53b5..1d64532 100644
> --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
> +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
> @@ -54,6 +54,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
> index 6ae36a3..f40d35b 100644
> --- a/arch/arm/boot/dts/armada-370-rd.dts
> +++ b/arch/arm/boot/dts/armada-370-rd.dts
> @@ -65,6 +65,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
> index 0440891..033665c 100644
> --- a/arch/arm/boot/dts/armada-375-db.dts
> +++ b/arch/arm/boot/dts/armada-375-db.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
> index af6c74e..c56ccd74 100644
> --- a/arch/arm/boot/dts/armada-388-db.dts
> +++ b/arch/arm/boot/dts/armada-388-db.dts
> @@ -55,6 +55,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
> index d99baac..e17edbb 100644
> --- a/arch/arm/boot/dts/armada-388-rd.dts
> +++ b/arch/arm/boot/dts/armada-388-rd.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
> index c1fbab2..a7fd474 100644
> --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
> +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
> @@ -60,6 +60,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
> index 48bdafe..a12e159 100644
> --- a/arch/arm/boot/dts/armada-xp-db.dts
> +++ b/arch/arm/boot/dts/armada-xp-db.dts
> @@ -65,6 +65,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
> index 206aebb..8a2e49e 100644
> --- a/arch/arm/boot/dts/armada-xp-gp.dts
> +++ b/arch/arm/boot/dts/armada-xp-gp.dts
> @@ -66,6 +66,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
> index 56f958e..3e81f22 100644
> --- a/arch/arm/boot/dts/armada-xp-matrix.dts
> +++ b/arch/arm/boot/dts/armada-xp-matrix.dts
> @@ -53,6 +53,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
> index a7ceafd..508a395 100644
> --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
> +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
> @@ -54,6 +54,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
> index 0c76d9f..7b2ea2060 100644
> --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
> +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
> @@ -55,6 +55,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> This commit adds the stdout-path property in /chosen for all Armada
> boards that were not yet carrying this property.

I though the main motivation for using the stdout-path property was
for removing the earlyprintk in the command line. Arnd told that there
should be a mean to use stdout-path instead of earlyprintk.

So what about going further and removing "earlyprintk" in the same time?

Thanks,

Gregory

> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-db.dts              | 1 +
>  arch/arm/boot/dts/armada-370-mirabox.dts         | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn102.dts   | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn104.dts   | 1 +
>  arch/arm/boot/dts/armada-370-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-375-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-xp-axpwifiap.dts        | 1 +
>  arch/arm/boot/dts/armada-xp-db.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-gp.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-matrix.dts           | 1 +
>  arch/arm/boot/dts/armada-xp-netgear-rn2120.dts   | 1 +
>  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 1 +
>  14 files changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
> index e993c46..286bedd 100644
> --- a/arch/arm/boot/dts/armada-370-db.dts
> +++ b/arch/arm/boot/dts/armada-370-db.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
> index b10ceb4..ec77b86 100644
> --- a/arch/arm/boot/dts/armada-370-mirabox.dts
> +++ b/arch/arm/boot/dts/armada-370-mirabox.dts
> @@ -52,6 +52,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> index 7c5c4ff..8c786cf 100644
> --- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> +++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
> @@ -54,6 +54,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
> index 1de53b5..1d64532 100644
> --- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
> +++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
> @@ -54,6 +54,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
> index 6ae36a3..f40d35b 100644
> --- a/arch/arm/boot/dts/armada-370-rd.dts
> +++ b/arch/arm/boot/dts/armada-370-rd.dts
> @@ -65,6 +65,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
> index 0440891..033665c 100644
> --- a/arch/arm/boot/dts/armada-375-db.dts
> +++ b/arch/arm/boot/dts/armada-375-db.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
> index af6c74e..c56ccd74 100644
> --- a/arch/arm/boot/dts/armada-388-db.dts
> +++ b/arch/arm/boot/dts/armada-388-db.dts
> @@ -55,6 +55,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
> index d99baac..e17edbb 100644
> --- a/arch/arm/boot/dts/armada-388-rd.dts
> +++ b/arch/arm/boot/dts/armada-388-rd.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
> index c1fbab2..a7fd474 100644
> --- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
> +++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
> @@ -60,6 +60,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
> index 48bdafe..a12e159 100644
> --- a/arch/arm/boot/dts/armada-xp-db.dts
> +++ b/arch/arm/boot/dts/armada-xp-db.dts
> @@ -65,6 +65,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
> index 206aebb..8a2e49e 100644
> --- a/arch/arm/boot/dts/armada-xp-gp.dts
> +++ b/arch/arm/boot/dts/armada-xp-gp.dts
> @@ -66,6 +66,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
> index 56f958e..3e81f22 100644
> --- a/arch/arm/boot/dts/armada-xp-matrix.dts
> +++ b/arch/arm/boot/dts/armada-xp-matrix.dts
> @@ -53,6 +53,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
> index a7ceafd..508a395 100644
> --- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
> +++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
> @@ -54,6 +54,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
> index 0c76d9f..7b2ea2060 100644
> --- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
> +++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
> @@ -55,6 +55,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;
>  	};
>  
>  	memory {
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 06/15] devicetree: bindings: add DT binding for the Marvell Armada 39x SoC family

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the
> Armada 398, with a slightly different number of interfaces. This
> commit introduces the Device Tree binding that documents the top-level
> compatible strings for Armada 39x based platforms.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  Documentation/devicetree/bindings/arm/armada-39x.txt | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/armada-39x.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt b/Documentation/devicetree/bindings/arm/armada-39x.txt
> new file mode 100644
> index 0000000..53d4ff9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/armada-39x.txt
> @@ -0,0 +1,20 @@
> +Marvell Armada 39x Platforms Device Tree Bindings
> +-------------------------------------------------
> +
> +Boards with a SoC of the Marvell Armada 39x family shall have the
> +following property:
> +
> +Required root node property:
> +
> + - compatible: must contain "marvell,armada390"
> +
> +In addition, boards using the Marvell Armada 398 SoC shall have the
> +following property before the previous one:
> +
> +Required root node property:
> +
> +compatible: must contain "marvell,armada398"
> +
> +Example:
> +
> +compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 06/15] devicetree: bindings: add DT binding for the Marvell Armada 39x SoC family

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> The Marvell Armada 39x is a family of two SoCs: the Armada 390 and the
> Armada 398, with a slightly different number of interfaces. This
> commit introduces the Device Tree binding that documents the top-level
> compatible strings for Armada 39x based platforms.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>

Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>


Thanks,

Gregory

> ---
>  Documentation/devicetree/bindings/arm/armada-39x.txt | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/arm/armada-39x.txt
> 
> diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt b/Documentation/devicetree/bindings/arm/armada-39x.txt
> new file mode 100644
> index 0000000..53d4ff9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/armada-39x.txt
> @@ -0,0 +1,20 @@
> +Marvell Armada 39x Platforms Device Tree Bindings
> +-------------------------------------------------
> +
> +Boards with a SoC of the Marvell Armada 39x family shall have the
> +following property:
> +
> +Required root node property:
> +
> + - compatible: must contain "marvell,armada390"
> +
> +In addition, boards using the Marvell Armada 398 SoC shall have the
> +following property before the previous one:
> +
> +Required root node property:
> +
> +compatible: must contain "marvell,armada398"
> +
> +Example:
> +
> +compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Rob Herring]

On Mon, Feb 23, 2015 at 10:00 AM, Gregory CLEMENT
<gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Hi Thomas,
>
> On 20/02/2015 18:04, Thomas Petazzoni wrote:
>> This commit adds the stdout-path property in /chosen for all Armada
>> boards that were not yet carrying this property.
>
> I though the main motivation for using the stdout-path property was
> for removing the earlyprintk in the command line. Arnd told that there
> should be a mean to use stdout-path instead of earlyprintk.
>
> So what about going further and removing "earlyprintk" in the same time?

Not exactly, stdout-path allows for removing "console" from the
command line. earlyprintk is a debug/developer option, so it should
not be in a default command line IMO.

So bootargs should be removed entirely.

Rob
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[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Rob Herring]

On Mon, Feb 23, 2015 at 10:00 AM, Gregory CLEMENT
<gregory.clement@free-electrons.com> wrote:
> Hi Thomas,
>
> On 20/02/2015 18:04, Thomas Petazzoni wrote:
>> This commit adds the stdout-path property in /chosen for all Armada
>> boards that were not yet carrying this property.
>
> I though the main motivation for using the stdout-path property was
> for removing the earlyprintk in the command line. Arnd told that there
> should be a mean to use stdout-path instead of earlyprintk.
>
> So what about going further and removing "earlyprintk" in the same time?

Not exactly, stdout-path allows for removing "console" from the
command line. earlyprintk is a debug/developer option, so it should
not be in a default command line IMO.

So bootargs should be removed entirely.

Rob

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Dear Rob Herring,

On Mon, 23 Feb 2015 10:50:26 -0600, Rob Herring wrote:

> Not exactly, stdout-path allows for removing "console" from the
> command line. earlyprintk is a debug/developer option, so it should
> not be in a default command line IMO.
> 
> So bootargs should be removed entirely.

Ok, will be in v3, rebased on top of 4.0-rc1.

I also noticed another issue in the patch series: missing Armada 375
UART aliases. I'll fix that up as well when sending v3.

Thanks for the feedback!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Dear Rob Herring,

On Mon, 23 Feb 2015 10:50:26 -0600, Rob Herring wrote:

> Not exactly, stdout-path allows for removing "console" from the
> command line. earlyprintk is a debug/developer option, so it should
> not be in a default command line IMO.
> 
> So bootargs should be removed entirely.

Ok, will be in v3, rebased on top of 4.0-rc1.

I also noticed another issue in the patch series: missing Armada 375
UART aliases. I'll fix that up as well when sending v3.

Thanks for the feedback!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Mark Rutland]

On Fri, Feb 20, 2015 at 05:04:24PM +0000, Thomas Petazzoni wrote:
> This commit adds the stdout-path property in /chosen for all Armada
> boards that were not yet carrying this property.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-db.dts              | 1 +
>  arch/arm/boot/dts/armada-370-mirabox.dts         | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn102.dts   | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn104.dts   | 1 +
>  arch/arm/boot/dts/armada-370-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-375-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-xp-axpwifiap.dts        | 1 +
>  arch/arm/boot/dts/armada-xp-db.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-gp.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-matrix.dts           | 1 +
>  arch/arm/boot/dts/armada-xp-netgear-rn2120.dts   | 1 +
>  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 1 +
>  14 files changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
> index e993c46..286bedd 100644
> --- a/arch/arm/boot/dts/armada-370-db.dts
> +++ b/arch/arm/boot/dts/armada-370-db.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;

stdout-path can now take a config too (including the rate), which will
avoid any reliance on the serial core choosing the right rate by
default.

If you have an alias serial0, this could be:

	stdout-path = "serial0:115200n8";

Otherwise you can use the full path instead of serial0.

That's documented in Documentation/devicetree/bindings/chosen.txt

Mark.

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Mark Rutland]

On Fri, Feb 20, 2015 at 05:04:24PM +0000, Thomas Petazzoni wrote:
> This commit adds the stdout-path property in /chosen for all Armada
> boards that were not yet carrying this property.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/armada-370-db.dts              | 1 +
>  arch/arm/boot/dts/armada-370-mirabox.dts         | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn102.dts   | 1 +
>  arch/arm/boot/dts/armada-370-netgear-rn104.dts   | 1 +
>  arch/arm/boot/dts/armada-370-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-375-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-db.dts              | 1 +
>  arch/arm/boot/dts/armada-388-rd.dts              | 1 +
>  arch/arm/boot/dts/armada-xp-axpwifiap.dts        | 1 +
>  arch/arm/boot/dts/armada-xp-db.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-gp.dts               | 1 +
>  arch/arm/boot/dts/armada-xp-matrix.dts           | 1 +
>  arch/arm/boot/dts/armada-xp-netgear-rn2120.dts   | 1 +
>  arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 1 +
>  14 files changed, 14 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
> index e993c46..286bedd 100644
> --- a/arch/arm/boot/dts/armada-370-db.dts
> +++ b/arch/arm/boot/dts/armada-370-db.dts
> @@ -56,6 +56,7 @@
>  
>  	chosen {
>  		bootargs = "console=ttyS0,115200 earlyprintk";
> +		stdout-path = &uart0;

stdout-path can now take a config too (including the rate), which will
avoid any reliance on the serial core choosing the right rate by
default.

If you have an alias serial0, this could be:

	stdout-path = "serial0:115200n8";

Otherwise you can use the full path instead of serial0.

That's documented in Documentation/devicetree/bindings/chosen.txt

Mark.

Re: [PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Gregory CLEMENT]

Hi Mike,

On 20/02/2015 19:21, Mike Turquette wrote:
> Quoting Thomas Petazzoni (2015-02-20 09:04:29)
>> The Armada 39x, contrary to its predecessor, has a configurable
>> reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
>> previous SoCs, it was fixed to 25 Mhz and described directly as such
>> in the Device Tree.
>>
>> For Armada 39x, we need to read certain registers to know whether the
>> frequency is 25 or 40 Mhz. Therefore, this commit extends the common
>> mvebu clock code to allow the SoC-specific code to say it wants to
>> register a reference clock, by giving a non-NULL ->get_refclk_freq()
>> function pointer in its coreclk_soc_desc structure.
>>
>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> 
> Looks fine to me. I'll apply after -rc1 drops.

What about the other clock related patch: "clk: mvebu: add Marvell
Armada 39x driver" ? Will you apply it too, or do you expect a pull request
for the mvebu related clocks ?


Thanks,

Gregory

> 
> Regards,
> Mike
> 
>> ---
>>  drivers/clk/mvebu/common.c | 17 +++++++++++++++++
>>  drivers/clk/mvebu/common.h |  1 +
>>  2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
>> index 0d4d121..15b370f 100644
>> --- a/drivers/clk/mvebu/common.c
>> +++ b/drivers/clk/mvebu/common.c
>> @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>>  
>>         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
>>         clk_data.clk_num = 2 + desc->num_ratios;
>> +
>> +       /* One more clock for the optional refclk */
>> +       if (desc->get_refclk_freq)
>> +               clk_data.clk_num += 1;
>> +
>>         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
>>                                 GFP_KERNEL);
>>         if (WARN_ON(!clk_data.clks)) {
>> @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>>                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
>>         };
>>  
>> +       /* Register optional refclk */
>> +       if (desc->get_refclk_freq) {
>> +               const char *name = "refclk";
>> +               of_property_read_string_index(np, "clock-output-names",
>> +                                             2 + desc->num_ratios, &name);
>> +               rate = desc->get_refclk_freq(base);
>> +               clk_data.clks[2 + desc->num_ratios] =
>> +                       clk_register_fixed_rate(NULL, name, NULL,
>> +                                               CLK_IS_ROOT, rate);
>> +               WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
>> +       }
>> +
>>         /* SAR register isn't needed anymore */
>>         iounmap(base);
>>  
>> diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
>> index 783b563..f0de6c8 100644
>> --- a/drivers/clk/mvebu/common.h
>> +++ b/drivers/clk/mvebu/common.h
>> @@ -30,6 +30,7 @@ struct coreclk_soc_desc {
>>         u32 (*get_tclk_freq)(void __iomem *sar);
>>         u32 (*get_cpu_freq)(void __iomem *sar);
>>         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
>> +       u32 (*get_refclk_freq)(void __iomem *sar);
>>         bool (*is_sscg_enabled)(void __iomem *sar);
>>         u32 (*fix_sscg_deviation)(u32 system_clk);
>>         const struct coreclk_ratio *ratios;
>> -- 
>> 2.1.0
>>


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Gregory CLEMENT]

Hi Mike,

On 20/02/2015 19:21, Mike Turquette wrote:
> Quoting Thomas Petazzoni (2015-02-20 09:04:29)
>> The Armada 39x, contrary to its predecessor, has a configurable
>> reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
>> previous SoCs, it was fixed to 25 Mhz and described directly as such
>> in the Device Tree.
>>
>> For Armada 39x, we need to read certain registers to know whether the
>> frequency is 25 or 40 Mhz. Therefore, this commit extends the common
>> mvebu clock code to allow the SoC-specific code to say it wants to
>> register a reference clock, by giving a non-NULL ->get_refclk_freq()
>> function pointer in its coreclk_soc_desc structure.
>>
>> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> 
> Looks fine to me. I'll apply after -rc1 drops.

What about the other clock related patch: "clk: mvebu: add Marvell
Armada 39x driver" ? Will you apply it too, or do you expect a pull request
for the mvebu related clocks ?


Thanks,

Gregory

> 
> Regards,
> Mike
> 
>> ---
>>  drivers/clk/mvebu/common.c | 17 +++++++++++++++++
>>  drivers/clk/mvebu/common.h |  1 +
>>  2 files changed, 18 insertions(+)
>>
>> diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
>> index 0d4d121..15b370f 100644
>> --- a/drivers/clk/mvebu/common.c
>> +++ b/drivers/clk/mvebu/common.c
>> @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>>  
>>         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
>>         clk_data.clk_num = 2 + desc->num_ratios;
>> +
>> +       /* One more clock for the optional refclk */
>> +       if (desc->get_refclk_freq)
>> +               clk_data.clk_num += 1;
>> +
>>         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
>>                                 GFP_KERNEL);
>>         if (WARN_ON(!clk_data.clks)) {
>> @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
>>                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
>>         };
>>  
>> +       /* Register optional refclk */
>> +       if (desc->get_refclk_freq) {
>> +               const char *name = "refclk";
>> +               of_property_read_string_index(np, "clock-output-names",
>> +                                             2 + desc->num_ratios, &name);
>> +               rate = desc->get_refclk_freq(base);
>> +               clk_data.clks[2 + desc->num_ratios] =
>> +                       clk_register_fixed_rate(NULL, name, NULL,
>> +                                               CLK_IS_ROOT, rate);
>> +               WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
>> +       }
>> +
>>         /* SAR register isn't needed anymore */
>>         iounmap(base);
>>  
>> diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
>> index 783b563..f0de6c8 100644
>> --- a/drivers/clk/mvebu/common.h
>> +++ b/drivers/clk/mvebu/common.h
>> @@ -30,6 +30,7 @@ struct coreclk_soc_desc {
>>         u32 (*get_tclk_freq)(void __iomem *sar);
>>         u32 (*get_cpu_freq)(void __iomem *sar);
>>         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
>> +       u32 (*get_refclk_freq)(void __iomem *sar);
>>         bool (*is_sscg_enabled)(void __iomem *sar);
>>         u32 (*fix_sscg_deviation)(u32 system_clk);
>>         const struct coreclk_ratio *ratios;
>> -- 
>> 2.1.0
>>


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 13/15] ARM: mvebu: add core support for Armada 39x

[Gregory CLEMENT]

Hi Thomas,


On 20/02/2015 18:04, Thomas Petazzoni wrote:
> This commit adds the core support for Armada 39x, which is quite
> simple:
> 
>  - a new Kconfig option which selects the appropriate clock and
>    pinctrl drivers as well as other common features (GIC, L2 cache,
>    SMP, etc.)
> 
>  - a new DT_MACHINE_START which references the top-level compatible
>    strings supported for the Marvell Armada 39x.
> 
>  - a new SMP enable-method. The mechanism to enable CPUs for Armada
>    39x appears to be the same as Armada 38x. However, we do not want
>    to use marvell,armada-380-smp in the Device Tree, in the case of
>    the discovery of a subtle difference in the future, which would
>    require changing the Device Tree. And the enable-method isn't a
>    compatible string: you can't specify several values and expect a
>    fallback on the second string if the first one isn't
>    supported. Therefore, we simply declare the SMP enable method
>    "marvell,armada-390-smp" as doing the same thing as the
>    "marvell,armada-380-smp" one.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/mach-mvebu/Kconfig      | 14 ++++++++++++++
>  arch/arm/mach-mvebu/board-v7.c   | 14 ++++++++++++++
>  arch/arm/mach-mvebu/platsmp-a9.c |  2 ++
>  3 files changed, 30 insertions(+)
> 
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index c1e4567..9747316 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -64,6 +64,20 @@ config MACH_ARMADA_38X
>  	  Say 'Y' here if you want your kernel to support boards based
>  	  on the Marvell Armada 380/385 SoC with device tree.
>  
> +config MACH_ARMADA_39X
> +	bool "Marvell Armada 39x boards" if ARCH_MULTI_V7

As you don't select it by default we should update the mvebu_v7_defconfig
with this symbol.

Thanks,

Gregory

> +	select ARM_GIC
> +	select ARMADA_39X_CLK
> +	select CACHE_L2X0
> +	select HAVE_ARM_SCU
> +	select HAVE_ARM_TWD if SMP
> +	select HAVE_SMP
> +	select MACH_MVEBU_V7
> +	select PINCTRL_ARMADA_39X
> +	help
> +	  Say 'Y' here if you want your kernel to support boards based
> +	  on the Marvell Armada 39x SoC with device tree.
> +
>  config MACH_ARMADA_XP
>  	bool "Marvell Armada XP boards" if ARCH_MULTI_V7
>  	select ARMADA_XP_CLK
> diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
> index 31b66f2..afee908 100644
> --- a/arch/arm/mach-mvebu/board-v7.c
> +++ b/arch/arm/mach-mvebu/board-v7.c
> @@ -232,3 +232,17 @@ DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
>  	.restart	= mvebu_restart,
>  	.dt_compat	= armada_38x_dt_compat,
>  MACHINE_END
> +
> +static const char * const armada_39x_dt_compat[] __initconst = {
> +	"marvell,armada390",
> +	"marvell,armada398",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
> +	.l2c_aux_val	= 0,
> +	.l2c_aux_mask	= ~0,
> +	.init_irq       = mvebu_init_irq,
> +	.restart	= mvebu_restart,
> +	.dt_compat	= armada_39x_dt_compat,
> +MACHINE_END
> diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
> index 2ec1a42..df0a9cc 100644
> --- a/arch/arm/mach-mvebu/platsmp-a9.c
> +++ b/arch/arm/mach-mvebu/platsmp-a9.c
> @@ -110,3 +110,5 @@ CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
>  		      &mvebu_cortex_a9_smp_ops);
>  CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
>  		      &armada_38x_smp_ops);
> +CPU_METHOD_OF_DECLARE(mvebu_armada_390_smp, "marvell,armada-390-smp",
> +		      &armada_38x_smp_ops);
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 13/15] ARM: mvebu: add core support for Armada 39x

[Gregory CLEMENT]

Hi Thomas,


On 20/02/2015 18:04, Thomas Petazzoni wrote:
> This commit adds the core support for Armada 39x, which is quite
> simple:
> 
>  - a new Kconfig option which selects the appropriate clock and
>    pinctrl drivers as well as other common features (GIC, L2 cache,
>    SMP, etc.)
> 
>  - a new DT_MACHINE_START which references the top-level compatible
>    strings supported for the Marvell Armada 39x.
> 
>  - a new SMP enable-method. The mechanism to enable CPUs for Armada
>    39x appears to be the same as Armada 38x. However, we do not want
>    to use marvell,armada-380-smp in the Device Tree, in the case of
>    the discovery of a subtle difference in the future, which would
>    require changing the Device Tree. And the enable-method isn't a
>    compatible string: you can't specify several values and expect a
>    fallback on the second string if the first one isn't
>    supported. Therefore, we simply declare the SMP enable method
>    "marvell,armada-390-smp" as doing the same thing as the
>    "marvell,armada-380-smp" one.
> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/mach-mvebu/Kconfig      | 14 ++++++++++++++
>  arch/arm/mach-mvebu/board-v7.c   | 14 ++++++++++++++
>  arch/arm/mach-mvebu/platsmp-a9.c |  2 ++
>  3 files changed, 30 insertions(+)
> 
> diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
> index c1e4567..9747316 100644
> --- a/arch/arm/mach-mvebu/Kconfig
> +++ b/arch/arm/mach-mvebu/Kconfig
> @@ -64,6 +64,20 @@ config MACH_ARMADA_38X
>  	  Say 'Y' here if you want your kernel to support boards based
>  	  on the Marvell Armada 380/385 SoC with device tree.
>  
> +config MACH_ARMADA_39X
> +	bool "Marvell Armada 39x boards" if ARCH_MULTI_V7

As you don't select it by default we should update the mvebu_v7_defconfig
with this symbol.

Thanks,

Gregory

> +	select ARM_GIC
> +	select ARMADA_39X_CLK
> +	select CACHE_L2X0
> +	select HAVE_ARM_SCU
> +	select HAVE_ARM_TWD if SMP
> +	select HAVE_SMP
> +	select MACH_MVEBU_V7
> +	select PINCTRL_ARMADA_39X
> +	help
> +	  Say 'Y' here if you want your kernel to support boards based
> +	  on the Marvell Armada 39x SoC with device tree.
> +
>  config MACH_ARMADA_XP
>  	bool "Marvell Armada XP boards" if ARCH_MULTI_V7
>  	select ARMADA_XP_CLK
> diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
> index 31b66f2..afee908 100644
> --- a/arch/arm/mach-mvebu/board-v7.c
> +++ b/arch/arm/mach-mvebu/board-v7.c
> @@ -232,3 +232,17 @@ DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
>  	.restart	= mvebu_restart,
>  	.dt_compat	= armada_38x_dt_compat,
>  MACHINE_END
> +
> +static const char * const armada_39x_dt_compat[] __initconst = {
> +	"marvell,armada390",
> +	"marvell,armada398",
> +	NULL,
> +};
> +
> +DT_MACHINE_START(ARMADA_39X_DT, "Marvell Armada 39x (Device Tree)")
> +	.l2c_aux_val	= 0,
> +	.l2c_aux_mask	= ~0,
> +	.init_irq       = mvebu_init_irq,
> +	.restart	= mvebu_restart,
> +	.dt_compat	= armada_39x_dt_compat,
> +MACHINE_END
> diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
> index 2ec1a42..df0a9cc 100644
> --- a/arch/arm/mach-mvebu/platsmp-a9.c
> +++ b/arch/arm/mach-mvebu/platsmp-a9.c
> @@ -110,3 +110,5 @@ CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
>  		      &mvebu_cortex_a9_smp_ops);
>  CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
>  		      &armada_38x_smp_ops);
> +CPU_METHOD_OF_DECLARE(mvebu_armada_390_smp, "marvell,armada-390-smp",
> +		      &armada_38x_smp_ops);
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 14/15] ARM: mvebu: add Device Tree files for Armada 39x SoC and board

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> This commit adds the Device Tree files for the Armada 39x family of
> processors, as well as one Armada 398 Development Board.
> 
> Like for other Marvell EBU families, a common armada-39x.dtsi contains
> the description of the common features of all Armada 39x SoCs, while
> armada-390.dtsi and armada-398.dtsi respectively describe the
> specificities of those SoCs.
> 
> Finally, an armada-398-db.dts file is added to describe the Armada 398
> Development Board itself.
> 
> So far, the following features are supported:
> 
>  * SMP: dual Cortex-A9
>  * Basic ARM IPs: SCU, timer, GIC
>  * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus
>    controller, MPIC interrupt controller, timer, CPU reset for SMP,
>    PMSU.
>  * I2C
>  * UART
>  * PCIe
> 
> Additional features will be supported in the future.

These device trees seem OK, I only found a small typo in the mpic node,
see below.

I also booted the kernel and I got the following error:
L2C: failed to init: -19

Actually it seems that the L2 cache controller node is missing.
Is it intentional?

If for now you don't want to add the support for the L2 cache controller then
you should remove the initialization of the l2c_aux_val and l2c_aux_mask field
in the machine_desc structure.


> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/Makefile          |   2 +
>  arch/arm/boot/dts/armada-390.dtsi   |  57 +++++
>  arch/arm/boot/dts/armada-398-db.dts | 154 +++++++++++
>  arch/arm/boot/dts/armada-398.dtsi   |  60 +++++
>  arch/arm/boot/dts/armada-39x.dtsi   | 494 ++++++++++++++++++++++++++++++++++++
>  5 files changed, 767 insertions(+)
>  create mode 100644 arch/arm/boot/dts/armada-390.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-398-db.dts
>  create mode 100644 arch/arm/boot/dts/armada-398.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-39x.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 968bc7a..64886fb 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -540,6 +540,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
>  	armada-388-db.dtb \
>  	armada-388-gp.dtb \
>  	armada-388-rd.dtb
> +dtb-$(CONFIG_MACH_ARMADA_39X) += \
> +	armada-398-db.dtb
>  dtb-$(CONFIG_MACH_ARMADA_XP) += \
>  	armada-xp-axpwifiap.dtb \
>  	armada-xp-db.dtb \
> diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi
> new file mode 100644
> index 0000000..094e39c
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-390.dtsi
> @@ -0,0 +1,57 @@
> +/*
> + * Device Tree Include file for Marvell Armada 390 SoC.
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "armada-39x.dtsi"
> +
> +/ {
> +	soc {
> +		internal-regs {
> +			pinctrl@18000 {
> +				compatible = "marvell,mv88f6920-pinctrl";
> +				reg = <0x18000 0x20>;
> +			};
> +		};
> +};
> diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
> new file mode 100644
> index 0000000..15dac29
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-398-db.dts
> @@ -0,0 +1,154 @@
> +/*
> + * Device Tree Include file for Marvell Armada 398 Development Board
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "armada-398.dtsi"
> +
> +/ {
> +	model = "Marvell Armada 398 Development Board";
> +	compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200";
> +		stdout-path = &uart0;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x80000000>; /* 2 GB */
> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
> +			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
> +
> +		internal-regs {
> +			spi@10680 {
> +				status = "okay";
> +				pinctrl-0 = <&spi1_pins>;
> +				pinctrl-names = "default";
> +
> +				spi-flash@0 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					compatible = "n25q128a13";
> +					reg = <0>;
> +					spi-max-frequency = <108000000>;
> +
> +					partition@0 {
> +						label = "U-Boot";
> +						reg = <0 0x400000>;
> +					};
> +
> +					partition@400000 {
> +						label = "Filesystem";
> +						reg = <0x400000 0x1000000>;
> +					};
> +				};
> +			};
> +
> +			i2c@11000 {
> +				pinctrl-0 = <&i2c0_pins>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +				clock-frequency = <100000>;
> +			};
> +
> +			serial@12000 {
> +				pinctrl-0 = <&uart0_pins>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +			};
> +
> +			serial@12100 {
> +				pinctrl-0 = <&uart1_pins>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +			};
> +
> +			flash@d0000 {
> +				status = "okay";
> +				pinctrl-0 = <&nand_pins>;
> +				pinctrl-names = "default";
> +				num-cs = <1>;
> +				marvell,nand-keep-config;
> +				marvell,nand-enable-arbiter;
> +				nand-on-flash-bbt;
> +				nand-ecc-strength = <8>;
> +				nand-ecc-step-size = <512>;
> +
> +				partition@0 {
> +					label = "U-Boot";
> +					reg = <0 0x800000>;
> +				};
> +				partition@800000 {
> +					label = "Linux";
> +					reg = <0x800000 0x800000>;
> +				};
> +				partition@1000000 {
> +					label = "Filesystem";
> +					reg = <0x1000000 0x3f000000>;
> +				};
> +			};
> +		};
> +
> +		pcie-controller {
> +			status = "okay";
> +
> +			pcie@1,0 {
> +				status = "okay";
> +			};
> +
> +			pcie@2,0 {
> +				status = "okay";
> +			};
> +
> +			pcie@3,0 {
> +				status = "okay";
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi
> new file mode 100644
> index 0000000..fdc2591
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-398.dtsi
> @@ -0,0 +1,60 @@
> +/*
> + * Device Tree Include file for Marvell Armada 398 SoC.
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "armada-39x.dtsi"
> +
> +/ {
> +	compatible = "marvell,armada398", "marvell,armada390";
> +
> +	soc {
> +		internal-regs {
> +			pinctrl@18000 {
> +				compatible = "marvell,mv88f6928-pinctrl";
> +				reg = <0x18000 0x20>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
> new file mode 100644
> index 0000000..fe43cd7
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-39x.dtsi
> @@ -0,0 +1,494 @@
> +/*
> + * Device Tree Include file for Marvell Armada 39x family of SoCs.
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "skeleton.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
> +
> +/ {
> +	model = "Marvell Armada 39x family SoC";
> +	compatible = "marvell,armada390";
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "marvell,armada-390-smp";
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0>;
> +		};
> +		cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <1>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
> +			     "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		controller = <&mbusc>;
> +		interrupt-parent = <&gic>;
> +		pcie-mem-aperture = <0xe0000000 0x8000000>;
> +		pcie-io-aperture  = <0xe8000000 0x100000>;
> +
> +		bootrom {
> +			compatible = "marvell,bootrom";
> +			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
> +		};
> +
> +		internal-regs {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
> +
> +			scu@c000 {
> +				compatible = "arm,cortex-a9-scu";
> +				reg = <0xc000 0x100>;
> +			};
> +
> +			timer@c600 {
> +				compatible = "arm,cortex-a9-twd-timer";
> +				reg = <0xc600 0x20>;
> +				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
> +				clocks = <&coreclk 2>;
> +			};
> +
> +			gic: interrupt-controller@d000 {
> +				compatible = "arm,cortex-a9-gic";
> +				#interrupt-cells = <3>;
> +				#size-cells = <0>;
> +				interrupt-controller;
> +				reg = <0xd000 0x1000>,
> +				      <0xc100 0x100>;
> +			};
> +
> +			spi0: spi@10600 {
> +				compatible = "marvell,orion-spi";
> +				reg = <0x10600 0x50>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				cell-index = <0>;
> +				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			spi1: spi@10680 {
> +				compatible = "marvell,orion-spi";
> +				reg = <0x10680 0x50>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				cell-index = <1>;
> +				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c0: i2c@11000 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11000 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c@11100 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11100 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c@11200 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11200 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c@11300 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11300 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart0: serial@12000 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12000 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart1: serial@12100 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12100 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart2: serial@12200 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12200 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart3: serial@12300 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12300 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			pinctrl@18000 {
> +				i2c0_pins: i2c0-pins {
> +					marvell,pins = "mpp2", "mpp3";
> +					marvell,function = "i2c0";
> +				};
> +
> +				uart0_pins: uart0-pins {
> +					marvell,pins = "mpp0", "mpp1";
> +					marvell,function = "ua0";
> +				};
> +
> +				uart1_pins: uart1-pins {
> +					marvell,pins = "mpp19", "mpp20";
> +					marvell,function = "ua1";
> +				};
> +
> +				spi1_pins: spi1-pins {
> +					marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
> +					marvell,function = "spi1";
> +				};
> +
> +				nand_pins: nand-pins {
> +					marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
> +						       "mpp38", "mpp28", "mpp40", "mpp42",
> +						       "mpp35", "mpp36", "mpp25", "mpp30",
> +						       "mpp32";
> +					marvell,function = "dev";
> +				};
> +			};
> +
> +			system-controller@18200 {
> +				compatible = "marvell,armada-390-system-controller",
> +					     "marvell,armada-370-xp-system-controller";
> +				reg = <0x18200 0x100>;
> +			};
> +
> +			gateclk: clock-gating-control@18220 {
> +				compatible = "marvell,armada-390-gating-clock";
> +				reg = <0x18220 0x4>;
> +				clocks = <&coreclk 0>;
> +				#clock-cells = <1>;
> +			};
> +
> +			coreclk: mvebu-sar@18600 {
> +				compatible = "marvell,armada-390-core-clock";
> +				reg = <0x18600 0x04>;
> +				#clock-cells = <1>;
> +			};
> +
> +			mbusc: mbus-controller@20000 {
> +				compatible = "marvell,mbus-controller";
> +				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
> +			};
> +
> +			mpic: interrupt-controller@20000 {

it should be
			mpic: interrupt-controller@20a00 {


Thanks,

Gregory


> +				compatible = "marvell,mpic";
> +				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> +				#interrupt-cells = <1>;
> +				#size-cells = <1>;
> +				interrupt-controller;
> +				msi-controller;
> +				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			timer@20300 {
> +				compatible = "marvell,armada-380-timer",
> +					     "marvell,armada-xp-timer";
> +				reg = <0x20300 0x30>, <0x21040 0x30>;
> +				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&mpic 5>,
> +						      <&mpic 6>;
> +				clocks = <&coreclk 2>, <&coreclk 5>;
> +				clock-names = "nbclk", "fixed";
> +			};
> +
> +			cpurst@20800 {
> +				compatible = "marvell,armada-370-cpu-reset";
> +				reg = <0x20800 0x10>;
> +			};
> +
> +			pmsu@22000 {
> +				compatible = "marvell,armada-390-pmsu",
> +					     "marvell,armada-380-pmsu";
> +				reg = <0x22000 0x1000>;
> +			};
> +
> +			xor@60800 {
> +				compatible = "marvell,orion-xor";
> +				reg = <0x60800 0x100
> +				       0x60a00 0x100>;
> +				clocks = <&gateclk 22>;
> +				status = "okay";
> +
> +				xor00 {
> +					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +				};
> +				xor01 {
> +					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +					dmacap,memset;
> +				};
> +			};
> +
> +			xor@60900 {
> +				compatible = "marvell,orion-xor";
> +				reg = <0x60900 0x100
> +				       0x60b00 0x100>;
> +				clocks = <&gateclk 28>;
> +				status = "okay";
> +
> +				xor10 {
> +					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +				};
> +				xor11 {
> +					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +					dmacap,memset;
> +				};
> +			};
> +
> +			flash@d0000 {
> +				compatible = "marvell,armada370-nand";
> +				reg = <0xd0000 0x54>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&coredivclk 0>;
> +				status = "disabled";
> +			};
> +
> +			sdhci@d8000 {
> +				compatible = "marvell,armada-380-sdhci";
> +				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
> +				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&gateclk 17>;
> +				mrvl,clk-delay-cycles = <0x1F>;
> +				status = "disabled";
> +			};
> +
> +			coredivclk: clock@e4250 {
> +				compatible = "marvell,armada-390-corediv-clock",
> +					     "marvell,armada-380-corediv-clock";
> +				reg = <0xe4250 0xc>;
> +				#clock-cells = <1>;
> +				clocks = <&mainpll>;
> +				clock-output-names = "nand";
> +			};
> +		};
> +
> +		pcie-controller {
> +			compatible = "marvell,armada-370-pcie";
> +			status = "disabled";
> +			device_type = "pci";
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +
> +			msi-parent = <&mpic>;
> +			bus-range = <0x00 0xff>;
> +
> +			ranges =
> +			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
> +				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
> +				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
> +				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
> +				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
> +				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
> +				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
> +				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
> +				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
> +				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
> +				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
> +				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
> +
> +			/*
> +			 * This port can be either x4 or x1. When
> +			 * configured in x4 by the bootloader, then
> +			 * pcie@4,0 is not available.
> +			 */
> +			pcie@1,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
> +				reg = <0x0800 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> +					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <0>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 8>;
> +				status = "disabled";
> +			};
> +
> +			/* x1 port */
> +			pcie@2,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> +				reg = <0x1000 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
> +					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <1>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 5>;
> +				status = "disabled";
> +			};
> +
> +			/* x1 port */
> +			pcie@3,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
> +				reg = <0x1800 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
> +					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <2>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 6>;
> +				status = "disabled";
> +			};
> +
> +			/*
> +			 * x1 port only available when pcie@1,0 is
> +			 * configured as a x1 port
> +			 */
> +			pcie@4,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
> +				reg = <0x2000 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
> +					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <3>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 7>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	clocks {
> +		/* 2 GHz fixed main PLL */
> +		mainpll: mainpll {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <2000000000>;
> +		};
> +	};
> +};
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCHv2 14/15] ARM: mvebu: add Device Tree files for Armada 39x SoC and board

[Gregory CLEMENT]

Hi Thomas,

On 20/02/2015 18:04, Thomas Petazzoni wrote:
> This commit adds the Device Tree files for the Armada 39x family of
> processors, as well as one Armada 398 Development Board.
> 
> Like for other Marvell EBU families, a common armada-39x.dtsi contains
> the description of the common features of all Armada 39x SoCs, while
> armada-390.dtsi and armada-398.dtsi respectively describe the
> specificities of those SoCs.
> 
> Finally, an armada-398-db.dts file is added to describe the Armada 398
> Development Board itself.
> 
> So far, the following features are supported:
> 
>  * SMP: dual Cortex-A9
>  * Basic ARM IPs: SCU, timer, GIC
>  * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus
>    controller, MPIC interrupt controller, timer, CPU reset for SMP,
>    PMSU.
>  * I2C
>  * UART
>  * PCIe
> 
> Additional features will be supported in the future.

These device trees seem OK, I only found a small typo in the mpic node,
see below.

I also booted the kernel and I got the following error:
L2C: failed to init: -19

Actually it seems that the L2 cache controller node is missing.
Is it intentional?

If for now you don't want to add the support for the L2 cache controller then
you should remove the initialization of the l2c_aux_val and l2c_aux_mask field
in the machine_desc structure.


> 
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> ---
>  arch/arm/boot/dts/Makefile          |   2 +
>  arch/arm/boot/dts/armada-390.dtsi   |  57 +++++
>  arch/arm/boot/dts/armada-398-db.dts | 154 +++++++++++
>  arch/arm/boot/dts/armada-398.dtsi   |  60 +++++
>  arch/arm/boot/dts/armada-39x.dtsi   | 494 ++++++++++++++++++++++++++++++++++++
>  5 files changed, 767 insertions(+)
>  create mode 100644 arch/arm/boot/dts/armada-390.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-398-db.dts
>  create mode 100644 arch/arm/boot/dts/armada-398.dtsi
>  create mode 100644 arch/arm/boot/dts/armada-39x.dtsi
> 
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 968bc7a..64886fb 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -540,6 +540,8 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
>  	armada-388-db.dtb \
>  	armada-388-gp.dtb \
>  	armada-388-rd.dtb
> +dtb-$(CONFIG_MACH_ARMADA_39X) += \
> +	armada-398-db.dtb
>  dtb-$(CONFIG_MACH_ARMADA_XP) += \
>  	armada-xp-axpwifiap.dtb \
>  	armada-xp-db.dtb \
> diff --git a/arch/arm/boot/dts/armada-390.dtsi b/arch/arm/boot/dts/armada-390.dtsi
> new file mode 100644
> index 0000000..094e39c
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-390.dtsi
> @@ -0,0 +1,57 @@
> +/*
> + * Device Tree Include file for Marvell Armada 390 SoC.
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "armada-39x.dtsi"
> +
> +/ {
> +	soc {
> +		internal-regs {
> +			pinctrl at 18000 {
> +				compatible = "marvell,mv88f6920-pinctrl";
> +				reg = <0x18000 0x20>;
> +			};
> +		};
> +};
> diff --git a/arch/arm/boot/dts/armada-398-db.dts b/arch/arm/boot/dts/armada-398-db.dts
> new file mode 100644
> index 0000000..15dac29
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-398-db.dts
> @@ -0,0 +1,154 @@
> +/*
> + * Device Tree Include file for Marvell Armada 398 Development Board
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "armada-398.dtsi"
> +
> +/ {
> +	model = "Marvell Armada 398 Development Board";
> +	compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390";
> +
> +	chosen {
> +		bootargs = "console=ttyS0,115200";
> +		stdout-path = &uart0;
> +	};
> +
> +	memory {
> +		device_type = "memory";
> +		reg = <0x00000000 0x80000000>; /* 2 GB */
> +	};
> +
> +	soc {
> +		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
> +			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
> +
> +		internal-regs {
> +			spi at 10680 {
> +				status = "okay";
> +				pinctrl-0 = <&spi1_pins>;
> +				pinctrl-names = "default";
> +
> +				spi-flash at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					compatible = "n25q128a13";
> +					reg = <0>;
> +					spi-max-frequency = <108000000>;
> +
> +					partition at 0 {
> +						label = "U-Boot";
> +						reg = <0 0x400000>;
> +					};
> +
> +					partition at 400000 {
> +						label = "Filesystem";
> +						reg = <0x400000 0x1000000>;
> +					};
> +				};
> +			};
> +
> +			i2c at 11000 {
> +				pinctrl-0 = <&i2c0_pins>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +				clock-frequency = <100000>;
> +			};
> +
> +			serial at 12000 {
> +				pinctrl-0 = <&uart0_pins>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +			};
> +
> +			serial at 12100 {
> +				pinctrl-0 = <&uart1_pins>;
> +				pinctrl-names = "default";
> +				status = "okay";
> +			};
> +
> +			flash at d0000 {
> +				status = "okay";
> +				pinctrl-0 = <&nand_pins>;
> +				pinctrl-names = "default";
> +				num-cs = <1>;
> +				marvell,nand-keep-config;
> +				marvell,nand-enable-arbiter;
> +				nand-on-flash-bbt;
> +				nand-ecc-strength = <8>;
> +				nand-ecc-step-size = <512>;
> +
> +				partition at 0 {
> +					label = "U-Boot";
> +					reg = <0 0x800000>;
> +				};
> +				partition at 800000 {
> +					label = "Linux";
> +					reg = <0x800000 0x800000>;
> +				};
> +				partition at 1000000 {
> +					label = "Filesystem";
> +					reg = <0x1000000 0x3f000000>;
> +				};
> +			};
> +		};
> +
> +		pcie-controller {
> +			status = "okay";
> +
> +			pcie at 1,0 {
> +				status = "okay";
> +			};
> +
> +			pcie at 2,0 {
> +				status = "okay";
> +			};
> +
> +			pcie at 3,0 {
> +				status = "okay";
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-398.dtsi b/arch/arm/boot/dts/armada-398.dtsi
> new file mode 100644
> index 0000000..fdc2591
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-398.dtsi
> @@ -0,0 +1,60 @@
> +/*
> + * Device Tree Include file for Marvell Armada 398 SoC.
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "armada-39x.dtsi"
> +
> +/ {
> +	compatible = "marvell,armada398", "marvell,armada390";
> +
> +	soc {
> +		internal-regs {
> +			pinctrl at 18000 {
> +				compatible = "marvell,mv88f6928-pinctrl";
> +				reg = <0x18000 0x20>;
> +			};
> +		};
> +	};
> +};
> diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi
> new file mode 100644
> index 0000000..fe43cd7
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-39x.dtsi
> @@ -0,0 +1,494 @@
> +/*
> + * Device Tree Include file for Marvell Armada 39x family of SoCs.
> + *
> + * Copyright (C) 2015 Marvell
> + *
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + *  a) This file is free software; you can redistribute it and/or
> + *     modify it under the terms of the GNU General Public License as
> + *     published by the Free Software Foundation; either version 2 of the
> + *     License, or (at your option) any later version.
> + *
> + *     This file is distributed in the hope that it will be useful
> + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
> + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + *     GNU General Public License for more details.
> + *
> + * Or, alternatively
> + *
> + *  b) Permission is hereby granted, free of charge, to any person
> + *     obtaining a copy of this software and associated documentation
> + *     files (the "Software"), to deal in the Software without
> + *     restriction, including without limitation the rights to use
> + *     copy, modify, merge, publish, distribute, sublicense, and/or
> + *     sell copies of the Software, and to permit persons to whom the
> + *     Software is furnished to do so, subject to the following
> + *     conditions:
> + *
> + *     The above copyright notice and this permission notice shall be
> + *     included in all copies or substantial portions of the Software.
> + *
> + *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
> + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
> + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + *     OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include "skeleton.dtsi"
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
> +
> +/ {
> +	model = "Marvell Armada 39x family SoC";
> +	compatible = "marvell,armada390";
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		enable-method = "marvell,armada-390-smp";
> +
> +		cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <0>;
> +		};
> +		cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a9";
> +			reg = <1>;
> +		};
> +	};
> +
> +	soc {
> +		compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
> +			     "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <1>;
> +		controller = <&mbusc>;
> +		interrupt-parent = <&gic>;
> +		pcie-mem-aperture = <0xe0000000 0x8000000>;
> +		pcie-io-aperture  = <0xe8000000 0x100000>;
> +
> +		bootrom {
> +			compatible = "marvell,bootrom";
> +			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
> +		};
> +
> +		internal-regs {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
> +
> +			scu at c000 {
> +				compatible = "arm,cortex-a9-scu";
> +				reg = <0xc000 0x100>;
> +			};
> +
> +			timer at c600 {
> +				compatible = "arm,cortex-a9-twd-timer";
> +				reg = <0xc600 0x20>;
> +				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
> +				clocks = <&coreclk 2>;
> +			};
> +
> +			gic: interrupt-controller at d000 {
> +				compatible = "arm,cortex-a9-gic";
> +				#interrupt-cells = <3>;
> +				#size-cells = <0>;
> +				interrupt-controller;
> +				reg = <0xd000 0x1000>,
> +				      <0xc100 0x100>;
> +			};
> +
> +			spi0: spi at 10600 {
> +				compatible = "marvell,orion-spi";
> +				reg = <0x10600 0x50>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				cell-index = <0>;
> +				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			spi1: spi at 10680 {
> +				compatible = "marvell,orion-spi";
> +				reg = <0x10680 0x50>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				cell-index = <1>;
> +				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c0: i2c at 11000 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11000 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c at 11100 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11100 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c at 11200 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11200 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c at 11300 {
> +				compatible = "marvell,mv64xxx-i2c";
> +				reg = <0x11300 0x20>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> +				timeout-ms = <1000>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart0: serial at 12000 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12000 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart1: serial at 12100 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12100 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart2: serial at 12200 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12200 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			uart3: serial at 12300 {
> +				compatible = "snps,dw-apb-uart";
> +				reg = <0x12300 0x100>;
> +				reg-shift = <2>;
> +				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +				reg-io-width = <1>;
> +				clocks = <&coreclk 0>;
> +				status = "disabled";
> +			};
> +
> +			pinctrl at 18000 {
> +				i2c0_pins: i2c0-pins {
> +					marvell,pins = "mpp2", "mpp3";
> +					marvell,function = "i2c0";
> +				};
> +
> +				uart0_pins: uart0-pins {
> +					marvell,pins = "mpp0", "mpp1";
> +					marvell,function = "ua0";
> +				};
> +
> +				uart1_pins: uart1-pins {
> +					marvell,pins = "mpp19", "mpp20";
> +					marvell,function = "ua1";
> +				};
> +
> +				spi1_pins: spi1-pins {
> +					marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
> +					marvell,function = "spi1";
> +				};
> +
> +				nand_pins: nand-pins {
> +					marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
> +						       "mpp38", "mpp28", "mpp40", "mpp42",
> +						       "mpp35", "mpp36", "mpp25", "mpp30",
> +						       "mpp32";
> +					marvell,function = "dev";
> +				};
> +			};
> +
> +			system-controller at 18200 {
> +				compatible = "marvell,armada-390-system-controller",
> +					     "marvell,armada-370-xp-system-controller";
> +				reg = <0x18200 0x100>;
> +			};
> +
> +			gateclk: clock-gating-control at 18220 {
> +				compatible = "marvell,armada-390-gating-clock";
> +				reg = <0x18220 0x4>;
> +				clocks = <&coreclk 0>;
> +				#clock-cells = <1>;
> +			};
> +
> +			coreclk: mvebu-sar at 18600 {
> +				compatible = "marvell,armada-390-core-clock";
> +				reg = <0x18600 0x04>;
> +				#clock-cells = <1>;
> +			};
> +
> +			mbusc: mbus-controller at 20000 {
> +				compatible = "marvell,mbus-controller";
> +				reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
> +			};
> +
> +			mpic: interrupt-controller at 20000 {

it should be
			mpic: interrupt-controller at 20a00 {


Thanks,

Gregory


> +				compatible = "marvell,mpic";
> +				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
> +				#interrupt-cells = <1>;
> +				#size-cells = <1>;
> +				interrupt-controller;
> +				msi-controller;
> +				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			timer at 20300 {
> +				compatible = "marvell,armada-380-timer",
> +					     "marvell,armada-xp-timer";
> +				reg = <0x20300 0x30>, <0x21040 0x30>;
> +				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
> +						      <&mpic 5>,
> +						      <&mpic 6>;
> +				clocks = <&coreclk 2>, <&coreclk 5>;
> +				clock-names = "nbclk", "fixed";
> +			};
> +
> +			cpurst at 20800 {
> +				compatible = "marvell,armada-370-cpu-reset";
> +				reg = <0x20800 0x10>;
> +			};
> +
> +			pmsu at 22000 {
> +				compatible = "marvell,armada-390-pmsu",
> +					     "marvell,armada-380-pmsu";
> +				reg = <0x22000 0x1000>;
> +			};
> +
> +			xor at 60800 {
> +				compatible = "marvell,orion-xor";
> +				reg = <0x60800 0x100
> +				       0x60a00 0x100>;
> +				clocks = <&gateclk 22>;
> +				status = "okay";
> +
> +				xor00 {
> +					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +				};
> +				xor01 {
> +					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +					dmacap,memset;
> +				};
> +			};
> +
> +			xor at 60900 {
> +				compatible = "marvell,orion-xor";
> +				reg = <0x60900 0x100
> +				       0x60b00 0x100>;
> +				clocks = <&gateclk 28>;
> +				status = "okay";
> +
> +				xor10 {
> +					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +				};
> +				xor11 {
> +					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
> +					dmacap,memcpy;
> +					dmacap,xor;
> +					dmacap,memset;
> +				};
> +			};
> +
> +			flash at d0000 {
> +				compatible = "marvell,armada370-nand";
> +				reg = <0xd0000 0x54>;
> +				#address-cells = <1>;
> +				#size-cells = <1>;
> +				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&coredivclk 0>;
> +				status = "disabled";
> +			};
> +
> +			sdhci at d8000 {
> +				compatible = "marvell,armada-380-sdhci";
> +				reg = <0xd8000 0x1000>, <0xdc000 0x100>;
> +				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&gateclk 17>;
> +				mrvl,clk-delay-cycles = <0x1F>;
> +				status = "disabled";
> +			};
> +
> +			coredivclk: clock at e4250 {
> +				compatible = "marvell,armada-390-corediv-clock",
> +					     "marvell,armada-380-corediv-clock";
> +				reg = <0xe4250 0xc>;
> +				#clock-cells = <1>;
> +				clocks = <&mainpll>;
> +				clock-output-names = "nand";
> +			};
> +		};
> +
> +		pcie-controller {
> +			compatible = "marvell,armada-370-pcie";
> +			status = "disabled";
> +			device_type = "pci";
> +
> +			#address-cells = <3>;
> +			#size-cells = <2>;
> +
> +			msi-parent = <&mpic>;
> +			bus-range = <0x00 0xff>;
> +
> +			ranges =
> +			       <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
> +				0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
> +				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
> +				0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
> +				0x82000000 0x1 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
> +				0x81000000 0x1 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO  */
> +				0x82000000 0x2 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
> +				0x81000000 0x2 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO  */
> +				0x82000000 0x3 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
> +				0x81000000 0x3 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO  */
> +				0x82000000 0x4 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
> +				0x81000000 0x4 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO  */>;
> +
> +			/*
> +			 * This port can be either x4 or x1. When
> +			 * configured in x4 by the bootloader, then
> +			 * pcie at 4,0 is not available.
> +			 */
> +			pcie at 1,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
> +				reg = <0x0800 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
> +					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <0>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 8>;
> +				status = "disabled";
> +			};
> +
> +			/* x1 port */
> +			pcie at 2,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
> +				reg = <0x1000 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
> +					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <1>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 5>;
> +				status = "disabled";
> +			};
> +
> +			/* x1 port */
> +			pcie at 3,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
> +				reg = <0x1800 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
> +					  0x81000000 0 0 0x81000000 0x3 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <2>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 6>;
> +				status = "disabled";
> +			};
> +
> +			/*
> +			 * x1 port only available when pcie at 1,0 is
> +			 * configured as a x1 port
> +			 */
> +			pcie at 4,0 {
> +				device_type = "pci";
> +				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
> +				reg = <0x2000 0 0 0 0>;
> +				#address-cells = <3>;
> +				#size-cells = <2>;
> +				#interrupt-cells = <1>;
> +				ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
> +					  0x81000000 0 0 0x81000000 0x4 0 1 0>;
> +				interrupt-map-mask = <0 0 0 0>;
> +				interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +				marvell,pcie-port = <3>;
> +				marvell,pcie-lane = <0>;
> +				clocks = <&gateclk 7>;
> +				status = "disabled";
> +			};
> +		};
> +	};
> +
> +	clocks {
> +		/* 2 GHz fixed main PLL */
> +		mainpll: mainpll {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +			clock-frequency = <2000000000>;
> +		};
> +	};
> +};
> 


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Mike Turquette]

Quoting Gregory CLEMENT (2015-02-23 10:06:24)
> Hi Mike,
> 
> On 20/02/2015 19:21, Mike Turquette wrote:
> > Quoting Thomas Petazzoni (2015-02-20 09:04:29)
> >> The Armada 39x, contrary to its predecessor, has a configurable
> >> reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
> >> previous SoCs, it was fixed to 25 Mhz and described directly as such
> >> in the Device Tree.
> >>
> >> For Armada 39x, we need to read certain registers to know whether the
> >> frequency is 25 or 40 Mhz. Therefore, this commit extends the common
> >> mvebu clock code to allow the SoC-specific code to say it wants to
> >> register a reference clock, by giving a non-NULL ->get_refclk_freq()
> >> function pointer in its coreclk_soc_desc structure.
> >>
> >> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > 
> > Looks fine to me. I'll apply after -rc1 drops.
> 
> What about the other clock related patch: "clk: mvebu: add Marvell
> Armada 39x driver" ? Will you apply it too, or do you expect a pull request
> for the mvebu related clocks ?

Both look fine to me, but a PR would be nice in case you have any other
mvebu clk stuff besides these two patches.

Regards,
Mike

> 
> 
> Thanks,
> 
> Gregory
> 
> > 
> > Regards,
> > Mike
> > 
> >> ---
> >>  drivers/clk/mvebu/common.c | 17 +++++++++++++++++
> >>  drivers/clk/mvebu/common.h |  1 +
> >>  2 files changed, 18 insertions(+)
> >>
> >> diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
> >> index 0d4d121..15b370f 100644
> >> --- a/drivers/clk/mvebu/common.c
> >> +++ b/drivers/clk/mvebu/common.c
> >> @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
> >>  
> >>         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
> >>         clk_data.clk_num = 2 + desc->num_ratios;
> >> +
> >> +       /* One more clock for the optional refclk */
> >> +       if (desc->get_refclk_freq)
> >> +               clk_data.clk_num += 1;
> >> +
> >>         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
> >>                                 GFP_KERNEL);
> >>         if (WARN_ON(!clk_data.clks)) {
> >> @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
> >>                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
> >>         };
> >>  
> >> +       /* Register optional refclk */
> >> +       if (desc->get_refclk_freq) {
> >> +               const char *name = "refclk";
> >> +               of_property_read_string_index(np, "clock-output-names",
> >> +                                             2 + desc->num_ratios, &name);
> >> +               rate = desc->get_refclk_freq(base);
> >> +               clk_data.clks[2 + desc->num_ratios] =
> >> +                       clk_register_fixed_rate(NULL, name, NULL,
> >> +                                               CLK_IS_ROOT, rate);
> >> +               WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
> >> +       }
> >> +
> >>         /* SAR register isn't needed anymore */
> >>         iounmap(base);
> >>  
> >> diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
> >> index 783b563..f0de6c8 100644
> >> --- a/drivers/clk/mvebu/common.h
> >> +++ b/drivers/clk/mvebu/common.h
> >> @@ -30,6 +30,7 @@ struct coreclk_soc_desc {
> >>         u32 (*get_tclk_freq)(void __iomem *sar);
> >>         u32 (*get_cpu_freq)(void __iomem *sar);
> >>         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
> >> +       u32 (*get_refclk_freq)(void __iomem *sar);
> >>         bool (*is_sscg_enabled)(void __iomem *sar);
> >>         u32 (*fix_sscg_deviation)(u32 system_clk);
> >>         const struct coreclk_ratio *ratios;
> >> -- 
> >> 2.1.0
> >>
> 
> 
> -- 
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com

[PATCHv2 10/15] clk: mvebu: extend common code to allow an optional refclk

[Mike Turquette]

Quoting Gregory CLEMENT (2015-02-23 10:06:24)
> Hi Mike,
> 
> On 20/02/2015 19:21, Mike Turquette wrote:
> > Quoting Thomas Petazzoni (2015-02-20 09:04:29)
> >> The Armada 39x, contrary to its predecessor, has a configurable
> >> reference clock frequency, of either 25 Mhz, or 40 Mhz. For the
> >> previous SoCs, it was fixed to 25 Mhz and described directly as such
> >> in the Device Tree.
> >>
> >> For Armada 39x, we need to read certain registers to know whether the
> >> frequency is 25 or 40 Mhz. Therefore, this commit extends the common
> >> mvebu clock code to allow the SoC-specific code to say it wants to
> >> register a reference clock, by giving a non-NULL ->get_refclk_freq()
> >> function pointer in its coreclk_soc_desc structure.
> >>
> >> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> > 
> > Looks fine to me. I'll apply after -rc1 drops.
> 
> What about the other clock related patch: "clk: mvebu: add Marvell
> Armada 39x driver" ? Will you apply it too, or do you expect a pull request
> for the mvebu related clocks ?

Both look fine to me, but a PR would be nice in case you have any other
mvebu clk stuff besides these two patches.

Regards,
Mike

> 
> 
> Thanks,
> 
> Gregory
> 
> > 
> > Regards,
> > Mike
> > 
> >> ---
> >>  drivers/clk/mvebu/common.c | 17 +++++++++++++++++
> >>  drivers/clk/mvebu/common.h |  1 +
> >>  2 files changed, 18 insertions(+)
> >>
> >> diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
> >> index 0d4d121..15b370f 100644
> >> --- a/drivers/clk/mvebu/common.c
> >> +++ b/drivers/clk/mvebu/common.c
> >> @@ -121,6 +121,11 @@ void __init mvebu_coreclk_setup(struct device_node *np,
> >>  
> >>         /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
> >>         clk_data.clk_num = 2 + desc->num_ratios;
> >> +
> >> +       /* One more clock for the optional refclk */
> >> +       if (desc->get_refclk_freq)
> >> +               clk_data.clk_num += 1;
> >> +
> >>         clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
> >>                                 GFP_KERNEL);
> >>         if (WARN_ON(!clk_data.clks)) {
> >> @@ -162,6 +167,18 @@ void __init mvebu_coreclk_setup(struct device_node *np,
> >>                 WARN_ON(IS_ERR(clk_data.clks[2+n]));
> >>         };
> >>  
> >> +       /* Register optional refclk */
> >> +       if (desc->get_refclk_freq) {
> >> +               const char *name = "refclk";
> >> +               of_property_read_string_index(np, "clock-output-names",
> >> +                                             2 + desc->num_ratios, &name);
> >> +               rate = desc->get_refclk_freq(base);
> >> +               clk_data.clks[2 + desc->num_ratios] =
> >> +                       clk_register_fixed_rate(NULL, name, NULL,
> >> +                                               CLK_IS_ROOT, rate);
> >> +               WARN_ON(IS_ERR(clk_data.clks[2 + desc->num_ratios]));
> >> +       }
> >> +
> >>         /* SAR register isn't needed anymore */
> >>         iounmap(base);
> >>  
> >> diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
> >> index 783b563..f0de6c8 100644
> >> --- a/drivers/clk/mvebu/common.h
> >> +++ b/drivers/clk/mvebu/common.h
> >> @@ -30,6 +30,7 @@ struct coreclk_soc_desc {
> >>         u32 (*get_tclk_freq)(void __iomem *sar);
> >>         u32 (*get_cpu_freq)(void __iomem *sar);
> >>         void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
> >> +       u32 (*get_refclk_freq)(void __iomem *sar);
> >>         bool (*is_sscg_enabled)(void __iomem *sar);
> >>         u32 (*fix_sscg_deviation)(u32 system_clk);
> >>         const struct coreclk_ratio *ratios;
> >> -- 
> >> 2.1.0
> >>
> 
> 
> -- 
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com

Re: [PATCHv2 04/15] ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x

[Thomas Petazzoni]

Gregory,

On Mon, 23 Feb 2015 16:27:02 +0100, Gregory CLEMENT wrote:

> I already submitted this fix as part of the "fixes and improvements for SDHCI" series.

Ok, I will drop this patch from my series. Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCHv2 04/15] ARM: mvebu: use IRQ macros to define the SDHCI interrupt on Armada 38x

[Thomas Petazzoni]

Gregory,

On Mon, 23 Feb 2015 16:27:02 +0100, Gregory CLEMENT wrote:

> I already submitted this fix as part of the "fixes and improvements for SDHCI" series.

Ok, I will drop this patch from my series. Thanks!

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Rob, Mark,

On Mon, 23 Feb 2015 10:50:26 -0600, Rob Herring wrote:
> On Mon, Feb 23, 2015 at 10:00 AM, Gregory CLEMENT

> Not exactly, stdout-path allows for removing "console" from the
> command line. earlyprintk is a debug/developer option, so it should
> not be in a default command line IMO.
> 
> So bootargs should be removed entirely.

Unfortunately, this doesn't seem to work at all:

 - Setting /chosen/stdout-path = &uart0; and still console=ttyS0,115200
   in /chosen/bootargs works fine. I see a call to
   add_preferred_console fairly early in the boot:

[    0.000000] Kernel command line: loglevel=8 ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs console=ttyS0,115200 earlyprintk
[    0.000000] ------> name=ttyS, idx=0, options=115200, brl_options=(null)
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)

   But of course, this is not the case we're interested in. Note that
   the line "------>" is printed in __add_preferred_console().

 - Setting just /chosen/stdout-path = &uart0; and removing
   completely /chosen/bootargs, there are no kernel messages displayed
   at all. Fortunately, my userspace hooks up on ttyS0, so I can run
   "dmesg" and see when add_preferred_console gets called, and with
   what arguments. It gets called much, much later, i.e only when the
   serial port itself is initialized:

[    0.484951] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.486822] ------> name=ttyS, idx=0, options=(null), brl_options=(null)
[    0.506838] f1012000.serial: ttyS0 at MMIO 0xf1012000 (irq = 21, base_baud = 12500000) is a 16550A
[    9.106098] console [ttyS0] enabled

   So it gets the right port name, the right idx, just the options are
   null. It shouldn't be an issue since the serial port is already
   initialized by the bootloader.

 - So I tried something like stdout-path = "serial0@12000:115200n8";
   and here the result is even more interesting: it simply crashes the
   kernel! So some random data in DT makes the stuff crash.

[    0.000000]  ==> of_alias_scan: serial0@12000:115200n8
[    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000c
[    0.000000] pgd = c0004000
[    0.000000] [0000000c] *pgd=00000000
[    0.000000] Internal error: Oops: 5 [#1] SMP ARM
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.0.0-rc1-00016-g0d60469-dirty #466
[    0.000000] Hardware name: Marvell Armada 39x (Device Tree)
[    0.000000] task: c088b468 ti: c0886000 task.ti: c0886000
[    0.000000] PC is at of_alias_scan+0xa4/0x2bc
[    0.000000] LR is at of_find_node_opts_by_path+0xac/0x230
[    0.000000] pc : [<c03b62b4>]    lr : [<c03b4b68>]    psr: 600001d3
[    0.000000] sp : c0887f38  ip : 00000000  fp : c08e05a4
[    0.000000] r10: 80000200  r9 : c05df908  r8 : c06aec30
[    0.000000] r7 : c088c3a4  r6 : c0890728  r5 : c253dba0  r4 : c08eb334
[    0.000000] r3 : 00000000  r2 : c253dbae  r1 : 00000000  r0 : c0630594
[    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
[    0.000000] Control: 10c5387d  Table: 0000404a  DAC: 00000015
[    0.000000] Process swapper (pid: 0, stack limit = 0xc0886220)
[    0.000000] Stack: (0xc0887f38 to 0xc0888000)
[    0.000000] 7f20:                                                       00000000 0002f7ff
[    0.000000] 7f40: 00001000 00002370 00000001 c0888408 c06b8a2c c0890728 c088c3a4 ef7fce40
[    0.000000] 7f60: c05df908 80000200 c08e05a4 c06942bc ffffffff 10c5387d c08c2e00 c0887fd4
[    0.000000] 7f80: 00000000 00000000 00000000 c0053f98 c05de48c c0887fb4 00000000 00000000
[    0.000000] 7fa0: c08c2cc0 c0888400 ffffffff c08c2cc0 00000000 00000000 00000000 c0691960
[    0.000000] 7fc0: 00000000 00000000 00000000 00000000 00000000 c06c3a78 c08c2f54 c0888480
[    0.000000] 7fe0: c06c3a74 c088c4b4 0000406a 414fc091 00000000 00008074 00000000 00000000
[    0.000000] [<c03b62b4>] (of_alias_scan) from [<c06942bc>] (setup_arch+0x6bc/0x8b8)
[    0.000000] [<c06942bc>] (setup_arch) from [<c0691960>] (start_kernel+0xa0/0x3a0)
[    0.000000] [<c0691960>] (start_kernel) from [<00008074>] (0x8074)
[    0.000000] Code: e594300c e3000594 e5942010 e34c0063 (e593100c) 
[    0.000000] ---[ end trace cb88537fdc8fa200 ]---
[    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[    0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task!

It is worth mentioning that this also happens with

     stdout-path = "uart0:115200n8";

which was explicitly suggested by Mark in his e-mail. uart0 is an alias
to the proper DT node, since stdout-path = &uart0; works almost fine.

This is all on v4.0-rc1. Seems like this stdout-path feature is not
quite working in all situations yet.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Rob, Mark,

On Mon, 23 Feb 2015 10:50:26 -0600, Rob Herring wrote:
> On Mon, Feb 23, 2015 at 10:00 AM, Gregory CLEMENT

> Not exactly, stdout-path allows for removing "console" from the
> command line. earlyprintk is a debug/developer option, so it should
> not be in a default command line IMO.
> 
> So bootargs should be removed entirely.

Unfortunately, this doesn't seem to work at all:

 - Setting /chosen/stdout-path = &uart0; and still console=ttyS0,115200
   in /chosen/bootargs works fine. I see a call to
   add_preferred_console fairly early in the boot:

[    0.000000] Kernel command line: loglevel=8 ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs console=ttyS0,115200 earlyprintk
[    0.000000] ------> name=ttyS, idx=0, options=115200, brl_options=(null)
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)

   But of course, this is not the case we're interested in. Note that
   the line "------>" is printed in __add_preferred_console().

 - Setting just /chosen/stdout-path = &uart0; and removing
   completely /chosen/bootargs, there are no kernel messages displayed
   at all. Fortunately, my userspace hooks up on ttyS0, so I can run
   "dmesg" and see when add_preferred_console gets called, and with
   what arguments. It gets called much, much later, i.e only when the
   serial port itself is initialized:

[    0.484951] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[    0.486822] ------> name=ttyS, idx=0, options=(null), brl_options=(null)
[    0.506838] f1012000.serial: ttyS0 at MMIO 0xf1012000 (irq = 21, base_baud = 12500000) is a 16550A
[    9.106098] console [ttyS0] enabled

   So it gets the right port name, the right idx, just the options are
   null. It shouldn't be an issue since the serial port is already
   initialized by the bootloader.

 - So I tried something like stdout-path = "serial0 at 12000:115200n8";
   and here the result is even more interesting: it simply crashes the
   kernel! So some random data in DT makes the stuff crash.

[    0.000000]  ==> of_alias_scan: serial0 at 12000:115200n8
[    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000c
[    0.000000] pgd = c0004000
[    0.000000] [0000000c] *pgd=00000000
[    0.000000] Internal error: Oops: 5 [#1] SMP ARM
[    0.000000] Modules linked in:
[    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.0.0-rc1-00016-g0d60469-dirty #466
[    0.000000] Hardware name: Marvell Armada 39x (Device Tree)
[    0.000000] task: c088b468 ti: c0886000 task.ti: c0886000
[    0.000000] PC is at of_alias_scan+0xa4/0x2bc
[    0.000000] LR is at of_find_node_opts_by_path+0xac/0x230
[    0.000000] pc : [<c03b62b4>]    lr : [<c03b4b68>]    psr: 600001d3
[    0.000000] sp : c0887f38  ip : 00000000  fp : c08e05a4
[    0.000000] r10: 80000200  r9 : c05df908  r8 : c06aec30
[    0.000000] r7 : c088c3a4  r6 : c0890728  r5 : c253dba0  r4 : c08eb334
[    0.000000] r3 : 00000000  r2 : c253dbae  r1 : 00000000  r0 : c0630594
[    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
[    0.000000] Control: 10c5387d  Table: 0000404a  DAC: 00000015
[    0.000000] Process swapper (pid: 0, stack limit = 0xc0886220)
[    0.000000] Stack: (0xc0887f38 to 0xc0888000)
[    0.000000] 7f20:                                                       00000000 0002f7ff
[    0.000000] 7f40: 00001000 00002370 00000001 c0888408 c06b8a2c c0890728 c088c3a4 ef7fce40
[    0.000000] 7f60: c05df908 80000200 c08e05a4 c06942bc ffffffff 10c5387d c08c2e00 c0887fd4
[    0.000000] 7f80: 00000000 00000000 00000000 c0053f98 c05de48c c0887fb4 00000000 00000000
[    0.000000] 7fa0: c08c2cc0 c0888400 ffffffff c08c2cc0 00000000 00000000 00000000 c0691960
[    0.000000] 7fc0: 00000000 00000000 00000000 00000000 00000000 c06c3a78 c08c2f54 c0888480
[    0.000000] 7fe0: c06c3a74 c088c4b4 0000406a 414fc091 00000000 00008074 00000000 00000000
[    0.000000] [<c03b62b4>] (of_alias_scan) from [<c06942bc>] (setup_arch+0x6bc/0x8b8)
[    0.000000] [<c06942bc>] (setup_arch) from [<c0691960>] (start_kernel+0xa0/0x3a0)
[    0.000000] [<c0691960>] (start_kernel) from [<00008074>] (0x8074)
[    0.000000] Code: e594300c e3000594 e5942010 e34c0063 (e593100c) 
[    0.000000] ---[ end trace cb88537fdc8fa200 ]---
[    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
[    0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task!

It is worth mentioning that this also happens with

     stdout-path = "uart0:115200n8";

which was explicitly suggested by Mark in his e-mail. uart0 is an alias
to the proper DT node, since stdout-path = &uart0; works almost fine.

This is all on v4.0-rc1. Seems like this stdout-path feature is not
quite working in all situations yet.

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Rob Herring]

On Fri, Feb 27, 2015 at 10:48 AM, Thomas Petazzoni
<thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> Rob, Mark,
>
> On Mon, 23 Feb 2015 10:50:26 -0600, Rob Herring wrote:
>> On Mon, Feb 23, 2015 at 10:00 AM, Gregory CLEMENT
>
>> Not exactly, stdout-path allows for removing "console" from the
>> command line. earlyprintk is a debug/developer option, so it should
>> not be in a default command line IMO.
>>
>> So bootargs should be removed entirely.
>
> Unfortunately, this doesn't seem to work at all:

This must have all been tested on QEMU (or Fast Models?) which ignores
baud rate.

>  - Setting /chosen/stdout-path = &uart0; and still console=ttyS0,115200
>    in /chosen/bootargs works fine. I see a call to
>    add_preferred_console fairly early in the boot:
>
> [    0.000000] Kernel command line: loglevel=8 ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs console=ttyS0,115200 earlyprintk
> [    0.000000] ------> name=ttyS, idx=0, options=115200, brl_options=(null)
> [    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
>
>    But of course, this is not the case we're interested in. Note that
>    the line "------>" is printed in __add_preferred_console().
>
>  - Setting just /chosen/stdout-path = &uart0; and removing
>    completely /chosen/bootargs, there are no kernel messages displayed
>    at all. Fortunately, my userspace hooks up on ttyS0, so I can run
>    "dmesg" and see when add_preferred_console gets called, and with
>    what arguments. It gets called much, much later, i.e only when the
>    serial port itself is initialized:
>
> [    0.484951] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
> [    0.486822] ------> name=ttyS, idx=0, options=(null), brl_options=(null)
> [    0.506838] f1012000.serial: ttyS0 at MMIO 0xf1012000 (irq = 21, base_baud = 12500000) is a 16550A
> [    9.106098] console [ttyS0] enabled
>
>    So it gets the right port name, the right idx, just the options are
>    null. It shouldn't be an issue since the serial port is already
>    initialized by the bootloader.

I think the default baudrate is 9600, not what the bootloader set.

>  - So I tried something like stdout-path = "serial0@12000:115200n8";
>    and here the result is even more interesting: it simply crashes the
>    kernel! So some random data in DT makes the stuff crash.

You need the full path here though. But garbage should not crash things.

Peter Hurley found just yesterday that the path parsing doesn't work
right with options. Only alias parsing works.

> [    0.000000]  ==> of_alias_scan: serial0@12000:115200n8
> [    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000c
> [    0.000000] pgd = c0004000
> [    0.000000] [0000000c] *pgd=00000000
> [    0.000000] Internal error: Oops: 5 [#1] SMP ARM
> [    0.000000] Modules linked in:
> [    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.0.0-rc1-00016-g0d60469-dirty #466
> [    0.000000] Hardware name: Marvell Armada 39x (Device Tree)
> [    0.000000] task: c088b468 ti: c0886000 task.ti: c0886000
> [    0.000000] PC is at of_alias_scan+0xa4/0x2bc
> [    0.000000] LR is at of_find_node_opts_by_path+0xac/0x230
> [    0.000000] pc : [<c03b62b4>]    lr : [<c03b4b68>]    psr: 600001d3
> [    0.000000] sp : c0887f38  ip : 00000000  fp : c08e05a4
> [    0.000000] r10: 80000200  r9 : c05df908  r8 : c06aec30
> [    0.000000] r7 : c088c3a4  r6 : c0890728  r5 : c253dba0  r4 : c08eb334
> [    0.000000] r3 : 00000000  r2 : c253dbae  r1 : 00000000  r0 : c0630594
> [    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
> [    0.000000] Control: 10c5387d  Table: 0000404a  DAC: 00000015
> [    0.000000] Process swapper (pid: 0, stack limit = 0xc0886220)
> [    0.000000] Stack: (0xc0887f38 to 0xc0888000)
> [    0.000000] 7f20:                                                       00000000 0002f7ff
> [    0.000000] 7f40: 00001000 00002370 00000001 c0888408 c06b8a2c c0890728 c088c3a4 ef7fce40
> [    0.000000] 7f60: c05df908 80000200 c08e05a4 c06942bc ffffffff 10c5387d c08c2e00 c0887fd4
> [    0.000000] 7f80: 00000000 00000000 00000000 c0053f98 c05de48c c0887fb4 00000000 00000000
> [    0.000000] 7fa0: c08c2cc0 c0888400 ffffffff c08c2cc0 00000000 00000000 00000000 c0691960
> [    0.000000] 7fc0: 00000000 00000000 00000000 00000000 00000000 c06c3a78 c08c2f54 c0888480
> [    0.000000] 7fe0: c06c3a74 c088c4b4 0000406a 414fc091 00000000 00008074 00000000 00000000
> [    0.000000] [<c03b62b4>] (of_alias_scan) from [<c06942bc>] (setup_arch+0x6bc/0x8b8)
> [    0.000000] [<c06942bc>] (setup_arch) from [<c0691960>] (start_kernel+0xa0/0x3a0)
> [    0.000000] [<c0691960>] (start_kernel) from [<00008074>] (0x8074)
> [    0.000000] Code: e594300c e3000594 e5942010 e34c0063 (e593100c)
> [    0.000000] ---[ end trace cb88537fdc8fa200 ]---
> [    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
> [    0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task!
>
> It is worth mentioning that this also happens with
>
>      stdout-path = "uart0:115200n8";
>
> which was explicitly suggested by Mark in his e-mail. uart0 is an alias
> to the proper DT node, since stdout-path = &uart0; works almost fine.

Mark forgot the '&'. So does 'stdout-path = "&uart0:115200n8";' work?

Rob
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[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Rob Herring]

On Fri, Feb 27, 2015 at 10:48 AM, Thomas Petazzoni
<thomas.petazzoni@free-electrons.com> wrote:
> Rob, Mark,
>
> On Mon, 23 Feb 2015 10:50:26 -0600, Rob Herring wrote:
>> On Mon, Feb 23, 2015 at 10:00 AM, Gregory CLEMENT
>
>> Not exactly, stdout-path allows for removing "console" from the
>> command line. earlyprintk is a debug/developer option, so it should
>> not be in a default command line IMO.
>>
>> So bootargs should be removed entirely.
>
> Unfortunately, this doesn't seem to work at all:

This must have all been tested on QEMU (or Fast Models?) which ignores
baud rate.

>  - Setting /chosen/stdout-path = &uart0; and still console=ttyS0,115200
>    in /chosen/bootargs works fine. I see a call to
>    add_preferred_console fairly early in the boot:
>
> [    0.000000] Kernel command line: loglevel=8 ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs console=ttyS0,115200 earlyprintk
> [    0.000000] ------> name=ttyS, idx=0, options=115200, brl_options=(null)
> [    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
>
>    But of course, this is not the case we're interested in. Note that
>    the line "------>" is printed in __add_preferred_console().
>
>  - Setting just /chosen/stdout-path = &uart0; and removing
>    completely /chosen/bootargs, there are no kernel messages displayed
>    at all. Fortunately, my userspace hooks up on ttyS0, so I can run
>    "dmesg" and see when add_preferred_console gets called, and with
>    what arguments. It gets called much, much later, i.e only when the
>    serial port itself is initialized:
>
> [    0.484951] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
> [    0.486822] ------> name=ttyS, idx=0, options=(null), brl_options=(null)
> [    0.506838] f1012000.serial: ttyS0 at MMIO 0xf1012000 (irq = 21, base_baud = 12500000) is a 16550A
> [    9.106098] console [ttyS0] enabled
>
>    So it gets the right port name, the right idx, just the options are
>    null. It shouldn't be an issue since the serial port is already
>    initialized by the bootloader.

I think the default baudrate is 9600, not what the bootloader set.

>  - So I tried something like stdout-path = "serial0 at 12000:115200n8";
>    and here the result is even more interesting: it simply crashes the
>    kernel! So some random data in DT makes the stuff crash.

You need the full path here though. But garbage should not crash things.

Peter Hurley found just yesterday that the path parsing doesn't work
right with options. Only alias parsing works.

> [    0.000000]  ==> of_alias_scan: serial0 at 12000:115200n8
> [    0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000c
> [    0.000000] pgd = c0004000
> [    0.000000] [0000000c] *pgd=00000000
> [    0.000000] Internal error: Oops: 5 [#1] SMP ARM
> [    0.000000] Modules linked in:
> [    0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.0.0-rc1-00016-g0d60469-dirty #466
> [    0.000000] Hardware name: Marvell Armada 39x (Device Tree)
> [    0.000000] task: c088b468 ti: c0886000 task.ti: c0886000
> [    0.000000] PC is at of_alias_scan+0xa4/0x2bc
> [    0.000000] LR is at of_find_node_opts_by_path+0xac/0x230
> [    0.000000] pc : [<c03b62b4>]    lr : [<c03b4b68>]    psr: 600001d3
> [    0.000000] sp : c0887f38  ip : 00000000  fp : c08e05a4
> [    0.000000] r10: 80000200  r9 : c05df908  r8 : c06aec30
> [    0.000000] r7 : c088c3a4  r6 : c0890728  r5 : c253dba0  r4 : c08eb334
> [    0.000000] r3 : 00000000  r2 : c253dbae  r1 : 00000000  r0 : c0630594
> [    0.000000] Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
> [    0.000000] Control: 10c5387d  Table: 0000404a  DAC: 00000015
> [    0.000000] Process swapper (pid: 0, stack limit = 0xc0886220)
> [    0.000000] Stack: (0xc0887f38 to 0xc0888000)
> [    0.000000] 7f20:                                                       00000000 0002f7ff
> [    0.000000] 7f40: 00001000 00002370 00000001 c0888408 c06b8a2c c0890728 c088c3a4 ef7fce40
> [    0.000000] 7f60: c05df908 80000200 c08e05a4 c06942bc ffffffff 10c5387d c08c2e00 c0887fd4
> [    0.000000] 7f80: 00000000 00000000 00000000 c0053f98 c05de48c c0887fb4 00000000 00000000
> [    0.000000] 7fa0: c08c2cc0 c0888400 ffffffff c08c2cc0 00000000 00000000 00000000 c0691960
> [    0.000000] 7fc0: 00000000 00000000 00000000 00000000 00000000 c06c3a78 c08c2f54 c0888480
> [    0.000000] 7fe0: c06c3a74 c088c4b4 0000406a 414fc091 00000000 00008074 00000000 00000000
> [    0.000000] [<c03b62b4>] (of_alias_scan) from [<c06942bc>] (setup_arch+0x6bc/0x8b8)
> [    0.000000] [<c06942bc>] (setup_arch) from [<c0691960>] (start_kernel+0xa0/0x3a0)
> [    0.000000] [<c0691960>] (start_kernel) from [<00008074>] (0x8074)
> [    0.000000] Code: e594300c e3000594 e5942010 e34c0063 (e593100c)
> [    0.000000] ---[ end trace cb88537fdc8fa200 ]---
> [    0.000000] Kernel panic - not syncing: Attempted to kill the idle task!
> [    0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task!
>
> It is worth mentioning that this also happens with
>
>      stdout-path = "uart0:115200n8";
>
> which was explicitly suggested by Mark in his e-mail. uart0 is an alias
> to the proper DT node, since stdout-path = &uart0; works almost fine.

Mark forgot the '&'. So does 'stdout-path = "&uart0:115200n8";' work?

Rob

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Dear Rob Herring,

On Fri, 27 Feb 2015 11:42:43 -0600, Rob Herring wrote:

> > Unfortunately, this doesn't seem to work at all:
> 
> This must have all been tested on QEMU (or Fast Models?) which ignores
> baud rate.


Ok.

> >    So it gets the right port name, the right idx, just the options are
> >    null. It shouldn't be an issue since the serial port is already
> >    initialized by the bootloader.
> 
> I think the default baudrate is 9600, not what the bootloader set.

That might explain the issue then.

> You need the full path here though. But garbage should not crash things.

Indeed, I was surprised that a different DT string was crashing the
kernel.


> > It is worth mentioning that this also happens with
> >
> >      stdout-path = "uart0:115200n8";
> >
> > which was explicitly suggested by Mark in his e-mail. uart0 is an alias
> > to the proper DT node, since stdout-path = &uart0; works almost fine.
> 
> Mark forgot the '&'. So does 'stdout-path = "&uart0:115200n8";' work?

I don't have the board at hand right now, will try this on Tuesday when
coming back to the office. Thanks for the suggestion!

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Dear Rob Herring,

On Fri, 27 Feb 2015 11:42:43 -0600, Rob Herring wrote:

> > Unfortunately, this doesn't seem to work at all:
> 
> This must have all been tested on QEMU (or Fast Models?) which ignores
> baud rate.


Ok.

> >    So it gets the right port name, the right idx, just the options are
> >    null. It shouldn't be an issue since the serial port is already
> >    initialized by the bootloader.
> 
> I think the default baudrate is 9600, not what the bootloader set.

That might explain the issue then.

> You need the full path here though. But garbage should not crash things.

Indeed, I was surprised that a different DT string was crashing the
kernel.


> > It is worth mentioning that this also happens with
> >
> >      stdout-path = "uart0:115200n8";
> >
> > which was explicitly suggested by Mark in his e-mail. uart0 is an alias
> > to the proper DT node, since stdout-path = &uart0; works almost fine.
> 
> Mark forgot the '&'. So does 'stdout-path = "&uart0:115200n8";' work?

I don't have the board at hand right now, will try this on Tuesday when
coming back to the office. Thanks for the suggestion!

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

Re: [PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Dear Rob Herring,

On Fri, 27 Feb 2015 11:42:43 -0600, Rob Herring wrote:

> > It is worth mentioning that this also happens with
> >
> >      stdout-path = "uart0:115200n8";
> >
> > which was explicitly suggested by Mark in his e-mail. uart0 is an alias
> > to the proper DT node, since stdout-path = &uart0; works almost fine.
> 
> Mark forgot the '&'. So does 'stdout-path = "&uart0:115200n8";' work?

Nah, there is really no '&' needed, Mark was right. What was wrong in
my setup was that uart0 was a *label* for the serial port DT node, and
not an alias. Once I created an alias 'serial0' for '&uart0', things
started working all right.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

[PATCHv2 05/15] ARM: mvebu: add stdout-path to all armada-*.dts

[Thomas Petazzoni]

Dear Rob Herring,

On Fri, 27 Feb 2015 11:42:43 -0600, Rob Herring wrote:

> > It is worth mentioning that this also happens with
> >
> >      stdout-path = "uart0:115200n8";
> >
> > which was explicitly suggested by Mark in his e-mail. uart0 is an alias
> > to the proper DT node, since stdout-path = &uart0; works almost fine.
> 
> Mark forgot the '&'. So does 'stdout-path = "&uart0:115200n8";' work?

Nah, there is really no '&' needed, Mark was right. What was wrong in
my setup was that uart0 was a *label* for the serial port DT node, and
not an alias. Once I created an alias 'serial0' for '&uart0', things
started working all right.

Thanks,

Thomas
-- 
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com