* [PATCH v7 1/7] ARM: Add platform support for Fujitsu MB86S7X SoCs
2015-03-04 10:52 ` Vincent Yang
@ 2015-03-04 10:58 ` Vincent Yang
-1 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 10:58 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
Tetsuya Nuriya
From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
The MB86S7X is a bigLITTLE configuration of 2xCA7 & 2xCA15 under Linux.
And the remote master firmware (called SCB) running on CM3. Linux asks
for things to be done over Mailbox API, to SCB which controls most of
the important things. variations S70 & S73 are supported.
Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
---
Documentation/devicetree/bindings/arm/mb86s7x.txt | 8 +
.../devicetree/bindings/soc/mb86s7x/scb_mhu.txt | 35 ++
MAINTAINERS | 7 +
arch/arm/Kconfig | 2 +
arch/arm/Makefile | 1 +
arch/arm/mach-mb86s7x/Kconfig | 19 +
arch/arm/mach-mb86s7x/Makefile | 1 +
arch/arm/mach-mb86s7x/board.c | 23 +
drivers/soc/Makefile | 1 +
drivers/soc/mb86s7x/Makefile | 4 +
drivers/soc/mb86s7x/scb_mhu.c | 517 +++++++++++++++++++++
include/soc/mb86s7x/scb_mhu.h | 97 ++++
12 files changed, 715 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mb86s7x.txt
create mode 100644 Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt
create mode 100644 arch/arm/mach-mb86s7x/Kconfig
create mode 100644 arch/arm/mach-mb86s7x/Makefile
create mode 100644 arch/arm/mach-mb86s7x/board.c
create mode 100644 drivers/soc/mb86s7x/Makefile
create mode 100644 drivers/soc/mb86s7x/scb_mhu.c
create mode 100644 include/soc/mb86s7x/scb_mhu.h
diff --git a/Documentation/devicetree/bindings/arm/mb86s7x.txt b/Documentation/devicetree/bindings/arm/mb86s7x.txt
new file mode 100644
index 0000000..fbaad20
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mb86s7x.txt
@@ -0,0 +1,8 @@
+Fujitsu MB86S7X Device Tree Bindings
+
+Fujitsu has a few closely related platforms that are basically different
+configurations of each others. Like MB86S7{0,1,2,3}.
+
+The EVB boards with S70/S73 have the following property:
+Required root node property:
+ compatible: must contain "fujitsu,mb86s70-evb" or "fujitsu,mb86s73-evb"
diff --git a/Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt b/Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt
new file mode 100644
index 0000000..f466a05
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt
@@ -0,0 +1,35 @@
+Fujitsu SCB (Mailbox's Remote Firmware) bindings
+------------------------------------------------
+
+The firmware (running of a remote Cortex-M3 master) on Fujitsu's MB86S7X
+platforms is named SCB. The SCB owns most of core h/w IPs like Clock,
+CPUFreq/DVFS, CPUIdle/SMP, Thermal, a recovery block device and even an
+I2C controller. Linux has to map all of these functionalities on to
+the Mailbox API and get things done by the remote master.
+ Let the current state of SCB firmware be versioned 1.0.
+
+Required properties :
+- compatible : Shall contain "fujitsu,mb86s70-scb-1.0"
+- reg : Point to SharedMemory used for Mailbox protocol.
+- mboxes : phandle to the mailbox controller:channel node.
+
+The consumer specifies the desired clock pointing to its phandle.
+
+Example:
+
+ mhu: mhu0@2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu";
+ reg = <0 0x2b1f0000 0x1000>;
+ interrupts = <0 36 4>, /* LP Non-Sec */
+ <0 35 4>, /* HP Non-Sec */
+ <0 37 4>; /* Secure */
+ clocks = <&clk 0 2 1>;
+ clock-names = "apb_pclk";
+ };
+
+ mhu_client: scb@2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0x4000>; /* SHM for IPC */
+ mboxes = <&mhu 1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index eaf9996..e8faa31 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1127,6 +1127,13 @@ M: Lennert Buytenhek <kernel-OLH4Qvv75CYX/NnBR394Jw@public.gmane.org>
L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)
S: Maintained
+ARM/MB86S7X SOC SUPPORT
+M: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
+M: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
+L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)
+S: Supported
+F: arch/arm/mach-mb86s7x/
+
ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE
M: Santosh Shilimkar <ssantosh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f1f09a..c2da7b1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -888,6 +888,8 @@ source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
+source "arch/arm/mach-mb86s7x/Kconfig"
+
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-msm/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7f99cd6..159f678 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -167,6 +167,7 @@ machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_KS8695) += ks8695
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
+machine-$(CONFIG_ARCH_MB86S7X) += mb86s7x
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MOXART) += moxart
diff --git a/arch/arm/mach-mb86s7x/Kconfig b/arch/arm/mach-mb86s7x/Kconfig
new file mode 100644
index 0000000..f58b104
--- /dev/null
+++ b/arch/arm/mach-mb86s7x/Kconfig
@@ -0,0 +1,19 @@
+config ARCH_MB86S7X
+ bool "Fujitsu MB86S7x platforms" if ARCH_MULTI_V7
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+ select ARCH_HAS_CPUFREQ
+ select ARCH_HAS_OPP
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_AMBA
+ select ARM_CCI
+ select ARM_GIC
+ select ARM_TIMER_SP804
+ select BIG_LITTLE
+ select HAVE_ARM_ARCH_TIMER
+ select MAILBOX
+ select PINCTRL
+ select PINCTRL_MB86S7X
+ select PM_OPP
+ select ZONE_DMA if ARM_LPAE
+ help
+ Support for Fujitsu MB86S7x based platforms
diff --git a/arch/arm/mach-mb86s7x/Makefile b/arch/arm/mach-mb86s7x/Makefile
new file mode 100644
index 0000000..97640b6
--- /dev/null
+++ b/arch/arm/mach-mb86s7x/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_MB86S7X) += board.o
diff --git a/arch/arm/mach-mb86s7x/board.c b/arch/arm/mach-mb86s7x/board.c
new file mode 100644
index 0000000..222b63f
--- /dev/null
+++ b/arch/arm/mach-mb86s7x/board.c
@@ -0,0 +1,23 @@
+/*
+ * Support for the Fujitsu's MB86S7x based devices.
+ *
+ * Copyright (C) 2015 Linaro, LTD
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ */
+
+#include <linux/of.h>
+#include <asm/mach/arch.h>
+
+static const char *mb86s7x_dt_match[] __initconst = {
+ "fujitsu,mb86s70-evb",
+ "fujitsu,mb86s73-evb",
+ NULL,
+};
+
+DT_MACHINE_START(MB86S7X_DT, "Fujitsu MB86S7X-based board")
+ .dt_compat = mb86s7x_dt_match,
+MACHINE_END
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..fb64bf2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
+obj-$(CONFIG_ARCH_MB86S7X) += mb86s7x/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/mb86s7x/Makefile b/drivers/soc/mb86s7x/Makefile
new file mode 100644
index 0000000..f6b96cf
--- /dev/null
+++ b/drivers/soc/mb86s7x/Makefile
@@ -0,0 +1,4 @@
+#
+# Fujitsu's MB86S7X drivers
+#
+obj-$(CONFIG_ARCH_MB86S7X) += scb_mhu.o
diff --git a/drivers/soc/mb86s7x/scb_mhu.c b/drivers/soc/mb86s7x/scb_mhu.c
new file mode 100644
index 0000000..c1d66f4
--- /dev/null
+++ b/drivers/soc/mb86s7x/scb_mhu.c
@@ -0,0 +1,517 @@
+/*
+ * arch/arm/mach-mb86s7x/scb_mhu.c Shim 'server' for Mailbox clients
+ *
+ * Created by: Jassi Brar <jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ * Copyright: (C) 2013-2015 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/mailbox_client.h>
+#include <linux/platform_device.h>
+
+#include <soc/mb86s7x/scb_mhu.h>
+
+#include <asm/system_misc.h>
+
+#define INTR_STAT_OFS 0x0
+#define INTR_SET_OFS 0x8
+#define INTR_CLR_OFS 0x10
+
+static LIST_HEAD(free_xfers);
+static LIST_HEAD(pending_xfers);
+static DEFINE_SPINLOCK(fsm_lock);
+static struct completion fsm_rsp;
+static struct mbox_client mhu_cl;
+static struct mbox_chan *mhu_chan;
+static mb86s7x_mhu_handler_t handler[MHU_NUM_CMDS];
+
+static void __iomem *mhu_base, *mb86s7x_shm_base;
+static void __iomem *cmd_to_scb, *rsp_to_scb;
+static void __iomem *cmd_from_scb, *rsp_from_scb;
+
+static enum {
+ MHU_PARK = 0,
+ MHU_WRR, /* Waiting to get Remote's Reply */
+ MHU_WRL, /* Waiting to send Reply */
+ MHU_WRRL, /* WAIT_Ra && WAIT_Rb */
+ MHU_INVLD,
+} fsm_state;
+
+enum fsm_event {
+ EV_LC = 0, /* Local sent a command */
+ EV_RC, /* Remote sent a command */
+ EV_RR, /* Remote sent a reply */
+ EV_LR, /* Local sent a reply */
+};
+
+static int mhu_fsm[4][4] = {
+ [MHU_PARK] = {
+ [EV_LC] = MHU_WRR,
+ [EV_RC] = MHU_WRL,
+ [EV_RR] = MHU_INVLD,
+ [EV_LR] = MHU_INVLD,
+ },
+ [MHU_WRR] = {
+ [EV_LC] = MHU_INVLD,
+ [EV_RC] = MHU_WRRL,
+ [EV_RR] = MHU_PARK,
+ [EV_LR] = MHU_INVLD,
+ },
+ [MHU_WRL] = {
+ [EV_LC] = MHU_WRRL,
+ [EV_RC] = MHU_INVLD,
+ [EV_RR] = MHU_INVLD,
+ [EV_LR] = MHU_PARK,
+ },
+ [MHU_WRRL] = {
+ [EV_LC] = MHU_INVLD,
+ [EV_RC] = MHU_INVLD,
+ [EV_RR] = MHU_WRL,
+ [EV_LR] = MHU_WRR,
+ },
+};
+
+static struct mhu_xfer {
+ int len;
+ u32 code;
+ void *buf;
+ struct completion *c;
+ struct list_head node;
+} *ax; /* stages of xfer */
+
+static int mhu_alloc_xfers(int n, struct list_head *list)
+{
+ struct mhu_xfer *x = kcalloc(n, sizeof(struct mhu_xfer), GFP_ATOMIC);
+ int i;
+
+ if (!x)
+ return -ENOMEM;
+
+ for (i = 0; i < n; i++)
+ list_add(&x[i].node, &free_xfers);
+
+ return 0;
+}
+
+static void got_data(u32 code)
+{
+ mb86s7x_mhu_handler_t hndlr = NULL;
+ unsigned long flags;
+ int ev;
+
+ if (code & RESP_BIT)
+ ev = EV_RR;
+ else
+ ev = EV_RC;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (mhu_fsm[fsm_state][ev] == MHU_INVLD) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ pr_err("State-%d EV-%d FSM Broken!\n", fsm_state, ev);
+ return;
+ }
+ fsm_state = mhu_fsm[fsm_state][ev];
+
+ if (code & RESP_BIT) {
+ memcpy_fromio(ax->buf, rsp_from_scb, ax->len);
+ if (ax->c)
+ complete(ax->c);
+ list_move(&ax->node, &free_xfers);
+ ax = NULL;
+ } else {
+ /* Find and dispatch relevant registered handler */
+ if (code < MHU_NUM_CMDS)
+ hndlr = handler[code];
+ if (hndlr)
+ hndlr(code, cmd_from_scb);
+ else
+ pr_err("No handler for CMD_%u\n", code);
+ }
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+}
+
+static int do_xfer(void)
+{
+ unsigned long flags;
+ struct mhu_xfer *x;
+ u32 code;
+ int ev;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (list_empty(&pending_xfers)) {
+ struct mbox_chan *_ch = NULL;
+ int cmd;
+
+ for (cmd = 0; cmd < MHU_NUM_CMDS && !handler[cmd]; cmd++)
+ ;
+ /* Don't free channel if any user is listening */
+ if (cmd != MHU_NUM_CMDS) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ return 0;
+ }
+
+ if (fsm_state == MHU_PARK) {
+ _ch = mhu_chan;
+ mhu_chan = NULL;
+ }
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ if (_ch)
+ mbox_free_channel(_ch);
+
+ return 0;
+ }
+
+ x = list_first_entry(&pending_xfers, struct mhu_xfer, node);
+ code = x->code;
+
+ ev = code & RESP_BIT ? EV_LR : EV_LC;
+ if (mhu_fsm[fsm_state][ev] == MHU_INVLD) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ return 1;
+ }
+ list_del_init(&x->node);
+
+ /* Layout the SHM */
+ if (code & RESP_BIT)
+ memcpy_toio(rsp_to_scb, x->buf, x->len);
+ else
+ memcpy_toio(cmd_to_scb, x->buf, x->len);
+
+ if (ev == EV_LC)
+ ax = x;
+ else
+ list_move(&x->node, &free_xfers);
+ fsm_state = mhu_fsm[fsm_state][ev];
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ /* Prefer mailbox API */
+ if (!mhu_chan) {
+ struct mbox_chan *_ch;
+
+ _ch = mbox_request_channel(&mhu_cl, 0);
+ if (!IS_ERR(_ch))
+ mhu_chan = _ch;
+ }
+
+ if (mhu_chan) {
+ int ret;
+
+ init_completion(&fsm_rsp);
+
+ /* Send via generic api */
+ ret = mbox_send_message(mhu_chan, (void *)&code);
+ if (ret < 0) {
+ pr_err("%s:%d CMD_%d Send Failed\n",
+ __func__, __LINE__, code);
+ BUG();
+ }
+ if (!(code & RESP_BIT)) {
+ ret = wait_for_completion_timeout(&fsm_rsp,
+ msecs_to_jiffies(1000));
+ if (!ret) {
+ pr_err("%s:%d CMD_%d Got No Reply\n",
+ __func__, __LINE__, code);
+ BUG();
+ }
+ got_data(ax->code);
+ }
+ } else {
+ void __iomem *tx_reg = mhu_base + 0x120; /* HP-NonSec */
+ void __iomem *rx_reg = mhu_base + 0x20; /* HP-NonSec */
+ u32 val, count;
+
+ /* Send via early-boot api */
+ val = readl_relaxed(tx_reg + INTR_STAT_OFS);
+ if (val) {
+ pr_err("Last CMD not yet read by SCB\n");
+ writel_relaxed(val, tx_reg + INTR_CLR_OFS);
+ }
+
+ writel_relaxed(x->code, tx_reg + INTR_SET_OFS);
+
+ /* Wait until this message is read */
+ count = 0x1000000;
+ do {
+ cpu_relax();
+ val = readl_relaxed(tx_reg + INTR_STAT_OFS);
+ } while (--count && val);
+ if (val)
+ pr_err("%s:%d SCB not listening!\n",
+ __func__, __LINE__);
+
+ if (!ax) {
+ /* A quick poll for pending remote cmd */
+ val = readl_relaxed(rx_reg + INTR_STAT_OFS);
+ if (val) {
+ got_data(val);
+ writel_relaxed(val, rx_reg + INTR_CLR_OFS);
+ }
+ } else {
+ do {
+ /* Wait until we get reply */
+ count = 0x1000000;
+ do {
+ cpu_relax();
+ val = readl_relaxed(
+ rx_reg + INTR_STAT_OFS);
+ } while (--count && !val);
+
+ if (val) {
+ got_data(val);
+ writel_relaxed(val,
+ rx_reg + INTR_CLR_OFS);
+ } else {
+ pr_err("%s:%d SCB didn't reply\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ } while (!(val & RESP_BIT));
+ }
+ if (list_empty(&pending_xfers))
+ return 0;
+ }
+
+ return do_xfer();
+}
+
+static void mhu_recv(struct mbox_client *cl, void *data)
+{
+ u32 *arg = data;
+
+ if (*arg & RESP_BIT) {
+ /* Now that we got a reply to last TX, that
+ * must mean the last TX was successful */
+ mbox_client_txdone(mhu_chan, 0);
+
+ ax->code = *arg; /* Save response */
+ complete(&fsm_rsp);
+ return;
+ }
+
+ got_data(*arg);
+}
+
+int mb86s7x_hndlr_set(u32 cmd, mb86s7x_mhu_handler_t hndlr)
+{
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+ if (cmd < MHU_NUM_CMDS && !handler[cmd]) {
+ ret = 0;
+ handler[cmd] = hndlr;
+ }
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ if (!mhu_chan) {
+ struct mbox_chan *_ch;
+
+ _ch = mbox_request_channel(&mhu_cl, 0);
+ if (!IS_ERR(_ch))
+ mhu_chan = _ch;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mb86s7x_hndlr_set);
+
+void mb86s7x_hndlr_clr(u32 cmd, mb86s7x_mhu_handler_t hndlr)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (cmd < MHU_NUM_CMDS && handler[cmd] == hndlr)
+ handler[cmd] = NULL;
+
+ if (list_empty(&pending_xfers)) {
+ struct mbox_chan *_ch = NULL;
+
+ for (cmd = 0; cmd < MHU_NUM_CMDS && !handler[cmd]; cmd++)
+ ;
+ /* Don't free channel if any user is listening */
+ if (cmd != MHU_NUM_CMDS) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ return;
+ }
+
+ if (fsm_state == MHU_PARK) {
+ _ch = mhu_chan;
+ mhu_chan = NULL;
+ }
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ if (_ch)
+ mbox_free_channel(_ch);
+
+ return;
+ }
+ spin_unlock_irqrestore(&fsm_lock, flags);
+}
+EXPORT_SYMBOL_GPL(mb86s7x_hndlr_clr);
+
+static int setup_mhu(void)
+{
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,mhu");
+ mhu_base = of_iomap(node, 0);
+ if (mhu_base == NULL) {
+ pr_err("Can't work without MHU\n");
+ return -ENODEV;
+ }
+
+ node = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
+ mb86s7x_shm_base = of_iomap(node, 0);
+ if (mb86s7x_shm_base == NULL) {
+ pr_err("Can't work without SHM SRAM\n");
+ return -ENODEV;
+ }
+
+ cmd_from_scb = mb86s7x_shm_base + 0x3800;
+ rsp_from_scb = mb86s7x_shm_base + 0x3900;
+ cmd_to_scb = mb86s7x_shm_base + 0x3a00;
+ rsp_to_scb = mb86s7x_shm_base + 0x3b00;
+
+ return 0;
+}
+
+int mb86s7x_send_packet(u32 code, void *buf, int len)
+{
+ struct completion got_rsp;
+ unsigned long flags;
+ struct mhu_xfer *x;
+ int ret;
+
+ /*
+ * The first caller could be as early as system clocksource,
+ * when the platform devices are not populated yet.
+ */
+ if (unlikely(!mb86s7x_shm_base) && setup_mhu())
+ return -ENODEV;
+
+ if ((code & ~0xff) || ((code & RESP_BIT)
+ && fsm_state != MHU_WRRL
+ && fsm_state != MHU_WRL)) {
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ init_completion(&got_rsp);
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (list_empty(&free_xfers) && mhu_alloc_xfers(5, &free_xfers)) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ pr_err("%s:%d OOM\n", __func__, __LINE__);
+ return -EAGAIN;
+ }
+
+ x = list_first_entry(&free_xfers, struct mhu_xfer, node);
+ x->code = code;
+ x->buf = buf;
+ x->len = len;
+ x->c = &got_rsp;
+
+ if (code & RESP_BIT)
+ list_move(&x->node, &pending_xfers);
+ else
+ list_move_tail(&x->node, &pending_xfers);
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ ret = do_xfer();
+ if (ret > 0) {
+ ret = wait_for_completion_timeout(&got_rsp,
+ msecs_to_jiffies(1000));
+ return ret ? 0 : -EIO;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mb86s7x_send_packet);
+
+struct mb86s7x_hard_reset {
+ u32 payload_size;
+ u32 delay;
+};
+
+static void mb86s7x_reboot(u32 delay)
+{
+ void __iomem *tx_reg = mhu_base + 0x120; /* HP-NonSec */
+ struct mb86s7x_hard_reset cmd;
+ u32 val;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.delay = delay;
+
+ val = readl_relaxed(tx_reg + INTR_STAT_OFS);
+ if (val) /* Flush anything pending */
+ writel_relaxed(val, tx_reg + INTR_CLR_OFS);
+
+ memcpy_toio(cmd_to_scb, &cmd, sizeof(cmd));
+ writel_relaxed(CMD_HARD_RESET_REQ, tx_reg + INTR_SET_OFS);
+}
+
+static void
+mb86s7x_restart(enum reboot_mode reboot_mode, const char *unused)
+{
+ /* Reboot immediately (after 50ms) */
+ mb86s7x_reboot(50);
+}
+
+static void mb86s7x_poweroff(void)
+{
+ /* Reboot never, remain dead */
+ mb86s7x_reboot(~0);
+}
+
+static int f_scb_probe(struct platform_device *pdev)
+{
+ mhu_cl.tx_block = true;
+ mhu_cl.knows_txdone = true;
+ mhu_cl.rx_callback = mhu_recv;
+ mhu_cl.dev = &pdev->dev;
+
+ arm_pm_restart = mb86s7x_restart;
+ pm_power_off = mb86s7x_poweroff;
+
+ return 0;
+}
+
+static const struct of_device_id scb_dt_ids[] = {
+ { .compatible = "fujitsu,mb86s70-scb-1.0" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, scb_dt_ids);
+
+static struct platform_driver f_scb_driver = {
+ .driver = {
+ .name = "f_scb",
+ .of_match_table = scb_dt_ids,
+ },
+ .probe = f_scb_probe,
+};
+
+static int __init f_scb_init(void)
+{
+ return platform_driver_register(&f_scb_driver);
+}
+module_init(f_scb_init);
diff --git a/include/soc/mb86s7x/scb_mhu.h b/include/soc/mb86s7x/scb_mhu.h
new file mode 100644
index 0000000..42a1baa
--- /dev/null
+++ b/include/soc/mb86s7x/scb_mhu.h
@@ -0,0 +1,97 @@
+/*
+ * include/soc/mb86s7x/scb_mhu.h
+ *
+ * Created by: Jassi Brar <jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
+ * Copyright: (C) 2013-2015 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MB86S7X_SCB_MHU_H
+#define __MB86S7X_SCB_MHU_H
+
+#define CMD_MASK 0x7f /* 128 possible commands */
+#define RESP_BIT (1 << 7) /* If it's a response */
+
+#define ENC_CMD(c) ((c) & CMD_MASK)
+#define DEC_CMD(v) (((v) & ~CMD_MASK) ? CMD_INVALID : ((v) & CMD_MASK))
+
+#define ENC_REP(r) (((r) & CMD_MASK) | RESP_BIT)
+
+/* If v is the reply to command c */
+#define IS_A_REP(v, c) (((v) & RESP_BIT) && (((v) & CMD_MASK) == (c)))
+
+enum {
+ CMD_INVALID = 0,
+ CMD_I2C_XFER_REQ = 1,
+ CMD_PERI_POWER_SET_REQ = 2,
+ CMD_PERI_CLOCK_GATE_SET_REQ = 3,
+ CMD_PERI_CLOCK_GATE_GET_REQ = 4,
+ CMD_PERI_CLOCK_RATE_SET_REQ = 5,
+ CMD_PERI_CLOCK_RATE_GET_REQ = 6,
+ CMD_CPU_CLOCK_GATE_SET_REQ = 7,
+ CMD_CPU_CLOCK_GATE_GET_REQ = 8,
+ CMD_CPU_CLOCK_RATE_SET_REQ = 9,
+ CMD_CPU_CLOCK_RATE_GET_REQ = 0xa,
+ CMD_CLUSTER_OPP_GET_REQ = 0xb,
+ CMD_CLOCK_DSI_PIXEL_REQ = 0xc,
+ CMD_SCB_CAPABILITY_GET_REQ = 0xd,
+ CMD_SYS_RESET_CAUSE_GET_REQ = 0xe,
+ CMD_SYS_SPECIFIC_INFO_GET_REQ = 0xf,
+ CMD_REBOOT_AP_AFTER_REQ = 0x10,
+ CMD_TAIKI_REQ = 0x11,
+ CMD_TAIKI_ASYNC_MSG_REQ = 0x12,
+ CMD_GET_WORD_REQ = 0x13,
+ CMD_HARD_RESET_REQ = 0x14,
+ CMD_MAINTENANCE_MODE_REQ = 0x15,
+ CMD_STG_GET_SIZE_REQ = 0x16,
+ CMD_STG_BLOCK_READ_REQ = 0x17,
+ CMD_STG_BLOCK_WRITE_REQ = 0x18,
+ CMD_MEMORY_LAYOUT_GET_REQ = 0x19,
+ CMD_POWERDOMAIN_GET_REQ = 0x1a,
+ CMD_POWERDOMAIN_SET_REQ = 0x1b,
+ CMD_STG_BLOCK_ERASE_REQ = 0x1c,
+
+ /* Do NOT add new commands below this line */
+ MHU_NUM_CMDS,
+};
+
+#define CMD_I2C_XFER_REP ENC_REP(CMD_I2C_XFER_REQ)
+#define CMD_PERI_POWER_SET_REP ENC_REP(CMD_PERI_POWER_SET_REQ)
+#define CMD_PERI_CLOCK_GATE_SET_REP ENC_REP(CMD_PERI_CLOCK_GATE_SET_REQ)
+#define CMD_PERI_CLOCK_GATE_GET_REP ENC_REP(CMD_PERI_CLOCK_GATE_GET_REQ)
+#define CMD_PERI_CLOCK_RATE_SET_REP ENC_REP(CMD_PERI_CLOCK_RATE_SET_REQ)
+#define CMD_PERI_CLOCK_RATE_GET_REP ENC_REP(CMD_PERI_CLOCK_RATE_GET_REQ)
+#define CMD_CPU_CLOCK_GATE_SET_REP ENC_REP(CMD_CPU_CLOCK_GATE_SET_REQ)
+#define CMD_CPU_CLOCK_GATE_GET_REP ENC_REP(CMD_CPU_CLOCK_GATE_GET_REQ)
+#define CMD_CPU_CLOCK_RATE_SET_REP ENC_REP(CMD_CPU_CLOCK_RATE_SET_REQ)
+#define CMD_CPU_CLOCK_RATE_GET_REP ENC_REP(CMD_CPU_CLOCK_RATE_GET_REQ)
+#define CMD_CLUSTER_OPP_GET_REP ENC_REP(CMD_CLUSTER_OPP_GET_REQ)
+#define CMD_CLOCK_DSI_PIXEL_REP ENC_REP(CMD_CLOCK_DSI_PIXEL_REQ)
+#define CMD_SCB_CAPABILITY_GET_REP ENC_REP(CMD_SCB_CAPABILITY_GET_REQ)
+#define CMD_SYS_RESET_CAUSE_GET_REP ENC_REP(CMD_SYS_RESET_CAUSE_GET_REQ)
+#define CMD_SYS_SPECIFIC_INFO_GET_REP ENC_REP(CMD_SYS_SPECIFIC_INFO_GET_REQ)
+#define CMD_GET_WORD_REP ENC_REP(CMD_GET_WORD_REQ)
+#define CMD_REBOOT_AP_AFTER_REP ENC_REP(CMD_REBOOT_AP_AFTER_REQ)
+#define CMD_TAIKI_REP ENC_REP(CMD_TAIKI_REQ)
+#define CMD_TAIKI_ASYNC_MSG_REP ENC_REP(CMD_TAIKI_ASYNC_MSG_REQ)
+#define CMD_HARD_RESET_REP ENC_REP(CMD_HARD_RESET_REQ)
+#define CMD_MAINTENANCE_MODE_REP ENC_RSP(CMD_MAINTENANCE_MODE_REQ)
+#define CMD_STG_GET_SIZE_REP ENC_REP(CMD_STG_GET_SIZE_REQ)
+#define CMD_STG_BLOCK_READ_REP ENC_REP(CMD_STG_BLOCK_READ_REQ)
+#define CMD_STG_BLOCK_WRITE_REP ENC_REP(CMD_STG_BLOCK_WRITE_REQ)
+#define CMD_MEMORY_LAYOUT_GET_REP ENC_REP(CMD_MEMORY_LAYOUT_GET_REQ)
+#define CMD_POWERDOMAIN_GET_REP ENC_REP(CMD_POWERDOMAIN_GET_REQ)
+#define CMD_POWERDOMAIN_SET_REP ENC_REP(CMD_POWERDOMAIN_SET_REQ)
+#define CMD_STG_BLOCK_ERASE_REP ENC_REP(CMD_STG_BLOCK_ERASE_REQ)
+
+/* Helper functions to talk to remote */
+int mb86s7x_send_packet(u32 code, void *buf, int len);
+
+typedef void (*mb86s7x_mhu_handler_t)(u32 cmd, u8 rcbuf[]);
+int mb86s7x_hndlr_set(u32 cmd, mb86s7x_mhu_handler_t);
+void mb86s7x_hndlr_clr(u32 cmd, mb86s7x_mhu_handler_t);
+
+#endif /* __MB86S7X_SCB_MHU_H */
--
1.9.0
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v7 1/7] ARM: Add platform support for Fujitsu MB86S7X SoCs
@ 2015-03-04 10:58 ` Vincent Yang
0 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 10:58 UTC (permalink / raw)
To: linux-arm-kernel
From: Jassi Brar <jaswinder.singh@linaro.org>
The MB86S7X is a bigLITTLE configuration of 2xCA7 & 2xCA15 under Linux.
And the remote master firmware (called SCB) running on CM3. Linux asks
for things to be done over Mailbox API, to SCB which controls most of
the important things. variations S70 & S73 are supported.
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
---
Documentation/devicetree/bindings/arm/mb86s7x.txt | 8 +
.../devicetree/bindings/soc/mb86s7x/scb_mhu.txt | 35 ++
MAINTAINERS | 7 +
arch/arm/Kconfig | 2 +
arch/arm/Makefile | 1 +
arch/arm/mach-mb86s7x/Kconfig | 19 +
arch/arm/mach-mb86s7x/Makefile | 1 +
arch/arm/mach-mb86s7x/board.c | 23 +
drivers/soc/Makefile | 1 +
drivers/soc/mb86s7x/Makefile | 4 +
drivers/soc/mb86s7x/scb_mhu.c | 517 +++++++++++++++++++++
include/soc/mb86s7x/scb_mhu.h | 97 ++++
12 files changed, 715 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/mb86s7x.txt
create mode 100644 Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt
create mode 100644 arch/arm/mach-mb86s7x/Kconfig
create mode 100644 arch/arm/mach-mb86s7x/Makefile
create mode 100644 arch/arm/mach-mb86s7x/board.c
create mode 100644 drivers/soc/mb86s7x/Makefile
create mode 100644 drivers/soc/mb86s7x/scb_mhu.c
create mode 100644 include/soc/mb86s7x/scb_mhu.h
diff --git a/Documentation/devicetree/bindings/arm/mb86s7x.txt b/Documentation/devicetree/bindings/arm/mb86s7x.txt
new file mode 100644
index 0000000..fbaad20
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mb86s7x.txt
@@ -0,0 +1,8 @@
+Fujitsu MB86S7X Device Tree Bindings
+
+Fujitsu has a few closely related platforms that are basically different
+configurations of each others. Like MB86S7{0,1,2,3}.
+
+The EVB boards with S70/S73 have the following property:
+Required root node property:
+ compatible: must contain "fujitsu,mb86s70-evb" or "fujitsu,mb86s73-evb"
diff --git a/Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt b/Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt
new file mode 100644
index 0000000..f466a05
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mb86s7x/scb_mhu.txt
@@ -0,0 +1,35 @@
+Fujitsu SCB (Mailbox's Remote Firmware) bindings
+------------------------------------------------
+
+The firmware (running of a remote Cortex-M3 master) on Fujitsu's MB86S7X
+platforms is named SCB. The SCB owns most of core h/w IPs like Clock,
+CPUFreq/DVFS, CPUIdle/SMP, Thermal, a recovery block device and even an
+I2C controller. Linux has to map all of these functionalities on to
+the Mailbox API and get things done by the remote master.
+ Let the current state of SCB firmware be versioned 1.0.
+
+Required properties :
+- compatible : Shall contain "fujitsu,mb86s70-scb-1.0"
+- reg : Point to SharedMemory used for Mailbox protocol.
+- mboxes : phandle to the mailbox controller:channel node.
+
+The consumer specifies the desired clock pointing to its phandle.
+
+Example:
+
+ mhu: mhu0 at 2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu";
+ reg = <0 0x2b1f0000 0x1000>;
+ interrupts = <0 36 4>, /* LP Non-Sec */
+ <0 35 4>, /* HP Non-Sec */
+ <0 37 4>; /* Secure */
+ clocks = <&clk 0 2 1>;
+ clock-names = "apb_pclk";
+ };
+
+ mhu_client: scb at 2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0x4000>; /* SHM for IPC */
+ mboxes = <&mhu 1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index eaf9996..e8faa31 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1127,6 +1127,13 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
+ARM/MB86S7X SOC SUPPORT
+M: Vincent Yang <vincent.yang@socionext.com>
+M: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
+L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S: Supported
+F: arch/arm/mach-mb86s7x/
+
ARM/TEXAS INSTRUMENT KEYSTONE ARCHITECTURE
M: Santosh Shilimkar <ssantosh@kernel.org>
L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f1f09a..c2da7b1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -888,6 +888,8 @@ source "arch/arm/mach-keystone/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
+source "arch/arm/mach-mb86s7x/Kconfig"
+
source "arch/arm/mach-meson/Kconfig"
source "arch/arm/mach-msm/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 7f99cd6..159f678 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -167,6 +167,7 @@ machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
machine-$(CONFIG_ARCH_KS8695) += ks8695
machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
+machine-$(CONFIG_ARCH_MB86S7X) += mb86s7x
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MOXART) += moxart
diff --git a/arch/arm/mach-mb86s7x/Kconfig b/arch/arm/mach-mb86s7x/Kconfig
new file mode 100644
index 0000000..f58b104
--- /dev/null
+++ b/arch/arm/mach-mb86s7x/Kconfig
@@ -0,0 +1,19 @@
+config ARCH_MB86S7X
+ bool "Fujitsu MB86S7x platforms" if ARCH_MULTI_V7
+ select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+ select ARCH_HAS_CPUFREQ
+ select ARCH_HAS_OPP
+ select ARCH_REQUIRE_GPIOLIB
+ select ARM_AMBA
+ select ARM_CCI
+ select ARM_GIC
+ select ARM_TIMER_SP804
+ select BIG_LITTLE
+ select HAVE_ARM_ARCH_TIMER
+ select MAILBOX
+ select PINCTRL
+ select PINCTRL_MB86S7X
+ select PM_OPP
+ select ZONE_DMA if ARM_LPAE
+ help
+ Support for Fujitsu MB86S7x based platforms
diff --git a/arch/arm/mach-mb86s7x/Makefile b/arch/arm/mach-mb86s7x/Makefile
new file mode 100644
index 0000000..97640b6
--- /dev/null
+++ b/arch/arm/mach-mb86s7x/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_ARCH_MB86S7X) += board.o
diff --git a/arch/arm/mach-mb86s7x/board.c b/arch/arm/mach-mb86s7x/board.c
new file mode 100644
index 0000000..222b63f
--- /dev/null
+++ b/arch/arm/mach-mb86s7x/board.c
@@ -0,0 +1,23 @@
+/*
+ * Support for the Fujitsu's MB86S7x based devices.
+ *
+ * Copyright (C) 2015 Linaro, LTD
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ */
+
+#include <linux/of.h>
+#include <asm/mach/arch.h>
+
+static const char *mb86s7x_dt_match[] __initconst = {
+ "fujitsu,mb86s70-evb",
+ "fujitsu,mb86s73-evb",
+ NULL,
+};
+
+DT_MACHINE_START(MB86S7X_DT, "Fujitsu MB86S7X-based board")
+ .dt_compat = mb86s7x_dt_match,
+MACHINE_END
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 063113d..fb64bf2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
# Makefile for the Linux Kernel SOC specific device drivers.
#
+obj-$(CONFIG_ARCH_MB86S7X) += mb86s7x/
obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_SOC_TI) += ti/
diff --git a/drivers/soc/mb86s7x/Makefile b/drivers/soc/mb86s7x/Makefile
new file mode 100644
index 0000000..f6b96cf
--- /dev/null
+++ b/drivers/soc/mb86s7x/Makefile
@@ -0,0 +1,4 @@
+#
+# Fujitsu's MB86S7X drivers
+#
+obj-$(CONFIG_ARCH_MB86S7X) += scb_mhu.o
diff --git a/drivers/soc/mb86s7x/scb_mhu.c b/drivers/soc/mb86s7x/scb_mhu.c
new file mode 100644
index 0000000..c1d66f4
--- /dev/null
+++ b/drivers/soc/mb86s7x/scb_mhu.c
@@ -0,0 +1,517 @@
+/*
+ * arch/arm/mach-mb86s7x/scb_mhu.c Shim 'server' for Mailbox clients
+ *
+ * Created by: Jassi Brar <jassisinghbrar@gmail.com>
+ * Copyright: (C) 2013-2015 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/reboot.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/mailbox_client.h>
+#include <linux/platform_device.h>
+
+#include <soc/mb86s7x/scb_mhu.h>
+
+#include <asm/system_misc.h>
+
+#define INTR_STAT_OFS 0x0
+#define INTR_SET_OFS 0x8
+#define INTR_CLR_OFS 0x10
+
+static LIST_HEAD(free_xfers);
+static LIST_HEAD(pending_xfers);
+static DEFINE_SPINLOCK(fsm_lock);
+static struct completion fsm_rsp;
+static struct mbox_client mhu_cl;
+static struct mbox_chan *mhu_chan;
+static mb86s7x_mhu_handler_t handler[MHU_NUM_CMDS];
+
+static void __iomem *mhu_base, *mb86s7x_shm_base;
+static void __iomem *cmd_to_scb, *rsp_to_scb;
+static void __iomem *cmd_from_scb, *rsp_from_scb;
+
+static enum {
+ MHU_PARK = 0,
+ MHU_WRR, /* Waiting to get Remote's Reply */
+ MHU_WRL, /* Waiting to send Reply */
+ MHU_WRRL, /* WAIT_Ra && WAIT_Rb */
+ MHU_INVLD,
+} fsm_state;
+
+enum fsm_event {
+ EV_LC = 0, /* Local sent a command */
+ EV_RC, /* Remote sent a command */
+ EV_RR, /* Remote sent a reply */
+ EV_LR, /* Local sent a reply */
+};
+
+static int mhu_fsm[4][4] = {
+ [MHU_PARK] = {
+ [EV_LC] = MHU_WRR,
+ [EV_RC] = MHU_WRL,
+ [EV_RR] = MHU_INVLD,
+ [EV_LR] = MHU_INVLD,
+ },
+ [MHU_WRR] = {
+ [EV_LC] = MHU_INVLD,
+ [EV_RC] = MHU_WRRL,
+ [EV_RR] = MHU_PARK,
+ [EV_LR] = MHU_INVLD,
+ },
+ [MHU_WRL] = {
+ [EV_LC] = MHU_WRRL,
+ [EV_RC] = MHU_INVLD,
+ [EV_RR] = MHU_INVLD,
+ [EV_LR] = MHU_PARK,
+ },
+ [MHU_WRRL] = {
+ [EV_LC] = MHU_INVLD,
+ [EV_RC] = MHU_INVLD,
+ [EV_RR] = MHU_WRL,
+ [EV_LR] = MHU_WRR,
+ },
+};
+
+static struct mhu_xfer {
+ int len;
+ u32 code;
+ void *buf;
+ struct completion *c;
+ struct list_head node;
+} *ax; /* stages of xfer */
+
+static int mhu_alloc_xfers(int n, struct list_head *list)
+{
+ struct mhu_xfer *x = kcalloc(n, sizeof(struct mhu_xfer), GFP_ATOMIC);
+ int i;
+
+ if (!x)
+ return -ENOMEM;
+
+ for (i = 0; i < n; i++)
+ list_add(&x[i].node, &free_xfers);
+
+ return 0;
+}
+
+static void got_data(u32 code)
+{
+ mb86s7x_mhu_handler_t hndlr = NULL;
+ unsigned long flags;
+ int ev;
+
+ if (code & RESP_BIT)
+ ev = EV_RR;
+ else
+ ev = EV_RC;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (mhu_fsm[fsm_state][ev] == MHU_INVLD) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ pr_err("State-%d EV-%d FSM Broken!\n", fsm_state, ev);
+ return;
+ }
+ fsm_state = mhu_fsm[fsm_state][ev];
+
+ if (code & RESP_BIT) {
+ memcpy_fromio(ax->buf, rsp_from_scb, ax->len);
+ if (ax->c)
+ complete(ax->c);
+ list_move(&ax->node, &free_xfers);
+ ax = NULL;
+ } else {
+ /* Find and dispatch relevant registered handler */
+ if (code < MHU_NUM_CMDS)
+ hndlr = handler[code];
+ if (hndlr)
+ hndlr(code, cmd_from_scb);
+ else
+ pr_err("No handler for CMD_%u\n", code);
+ }
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+}
+
+static int do_xfer(void)
+{
+ unsigned long flags;
+ struct mhu_xfer *x;
+ u32 code;
+ int ev;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (list_empty(&pending_xfers)) {
+ struct mbox_chan *_ch = NULL;
+ int cmd;
+
+ for (cmd = 0; cmd < MHU_NUM_CMDS && !handler[cmd]; cmd++)
+ ;
+ /* Don't free channel if any user is listening */
+ if (cmd != MHU_NUM_CMDS) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ return 0;
+ }
+
+ if (fsm_state == MHU_PARK) {
+ _ch = mhu_chan;
+ mhu_chan = NULL;
+ }
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ if (_ch)
+ mbox_free_channel(_ch);
+
+ return 0;
+ }
+
+ x = list_first_entry(&pending_xfers, struct mhu_xfer, node);
+ code = x->code;
+
+ ev = code & RESP_BIT ? EV_LR : EV_LC;
+ if (mhu_fsm[fsm_state][ev] == MHU_INVLD) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ return 1;
+ }
+ list_del_init(&x->node);
+
+ /* Layout the SHM */
+ if (code & RESP_BIT)
+ memcpy_toio(rsp_to_scb, x->buf, x->len);
+ else
+ memcpy_toio(cmd_to_scb, x->buf, x->len);
+
+ if (ev == EV_LC)
+ ax = x;
+ else
+ list_move(&x->node, &free_xfers);
+ fsm_state = mhu_fsm[fsm_state][ev];
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ /* Prefer mailbox API */
+ if (!mhu_chan) {
+ struct mbox_chan *_ch;
+
+ _ch = mbox_request_channel(&mhu_cl, 0);
+ if (!IS_ERR(_ch))
+ mhu_chan = _ch;
+ }
+
+ if (mhu_chan) {
+ int ret;
+
+ init_completion(&fsm_rsp);
+
+ /* Send via generic api */
+ ret = mbox_send_message(mhu_chan, (void *)&code);
+ if (ret < 0) {
+ pr_err("%s:%d CMD_%d Send Failed\n",
+ __func__, __LINE__, code);
+ BUG();
+ }
+ if (!(code & RESP_BIT)) {
+ ret = wait_for_completion_timeout(&fsm_rsp,
+ msecs_to_jiffies(1000));
+ if (!ret) {
+ pr_err("%s:%d CMD_%d Got No Reply\n",
+ __func__, __LINE__, code);
+ BUG();
+ }
+ got_data(ax->code);
+ }
+ } else {
+ void __iomem *tx_reg = mhu_base + 0x120; /* HP-NonSec */
+ void __iomem *rx_reg = mhu_base + 0x20; /* HP-NonSec */
+ u32 val, count;
+
+ /* Send via early-boot api */
+ val = readl_relaxed(tx_reg + INTR_STAT_OFS);
+ if (val) {
+ pr_err("Last CMD not yet read by SCB\n");
+ writel_relaxed(val, tx_reg + INTR_CLR_OFS);
+ }
+
+ writel_relaxed(x->code, tx_reg + INTR_SET_OFS);
+
+ /* Wait until this message is read */
+ count = 0x1000000;
+ do {
+ cpu_relax();
+ val = readl_relaxed(tx_reg + INTR_STAT_OFS);
+ } while (--count && val);
+ if (val)
+ pr_err("%s:%d SCB not listening!\n",
+ __func__, __LINE__);
+
+ if (!ax) {
+ /* A quick poll for pending remote cmd */
+ val = readl_relaxed(rx_reg + INTR_STAT_OFS);
+ if (val) {
+ got_data(val);
+ writel_relaxed(val, rx_reg + INTR_CLR_OFS);
+ }
+ } else {
+ do {
+ /* Wait until we get reply */
+ count = 0x1000000;
+ do {
+ cpu_relax();
+ val = readl_relaxed(
+ rx_reg + INTR_STAT_OFS);
+ } while (--count && !val);
+
+ if (val) {
+ got_data(val);
+ writel_relaxed(val,
+ rx_reg + INTR_CLR_OFS);
+ } else {
+ pr_err("%s:%d SCB didn't reply\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ } while (!(val & RESP_BIT));
+ }
+ if (list_empty(&pending_xfers))
+ return 0;
+ }
+
+ return do_xfer();
+}
+
+static void mhu_recv(struct mbox_client *cl, void *data)
+{
+ u32 *arg = data;
+
+ if (*arg & RESP_BIT) {
+ /* Now that we got a reply to last TX, that
+ * must mean the last TX was successful */
+ mbox_client_txdone(mhu_chan, 0);
+
+ ax->code = *arg; /* Save response */
+ complete(&fsm_rsp);
+ return;
+ }
+
+ got_data(*arg);
+}
+
+int mb86s7x_hndlr_set(u32 cmd, mb86s7x_mhu_handler_t hndlr)
+{
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+ if (cmd < MHU_NUM_CMDS && !handler[cmd]) {
+ ret = 0;
+ handler[cmd] = hndlr;
+ }
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ if (!mhu_chan) {
+ struct mbox_chan *_ch;
+
+ _ch = mbox_request_channel(&mhu_cl, 0);
+ if (!IS_ERR(_ch))
+ mhu_chan = _ch;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mb86s7x_hndlr_set);
+
+void mb86s7x_hndlr_clr(u32 cmd, mb86s7x_mhu_handler_t hndlr)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (cmd < MHU_NUM_CMDS && handler[cmd] == hndlr)
+ handler[cmd] = NULL;
+
+ if (list_empty(&pending_xfers)) {
+ struct mbox_chan *_ch = NULL;
+
+ for (cmd = 0; cmd < MHU_NUM_CMDS && !handler[cmd]; cmd++)
+ ;
+ /* Don't free channel if any user is listening */
+ if (cmd != MHU_NUM_CMDS) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ return;
+ }
+
+ if (fsm_state == MHU_PARK) {
+ _ch = mhu_chan;
+ mhu_chan = NULL;
+ }
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ if (_ch)
+ mbox_free_channel(_ch);
+
+ return;
+ }
+ spin_unlock_irqrestore(&fsm_lock, flags);
+}
+EXPORT_SYMBOL_GPL(mb86s7x_hndlr_clr);
+
+static int setup_mhu(void)
+{
+ struct device_node *node;
+
+ node = of_find_compatible_node(NULL, NULL, "arm,mhu");
+ mhu_base = of_iomap(node, 0);
+ if (mhu_base == NULL) {
+ pr_err("Can't work without MHU\n");
+ return -ENODEV;
+ }
+
+ node = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
+ mb86s7x_shm_base = of_iomap(node, 0);
+ if (mb86s7x_shm_base == NULL) {
+ pr_err("Can't work without SHM SRAM\n");
+ return -ENODEV;
+ }
+
+ cmd_from_scb = mb86s7x_shm_base + 0x3800;
+ rsp_from_scb = mb86s7x_shm_base + 0x3900;
+ cmd_to_scb = mb86s7x_shm_base + 0x3a00;
+ rsp_to_scb = mb86s7x_shm_base + 0x3b00;
+
+ return 0;
+}
+
+int mb86s7x_send_packet(u32 code, void *buf, int len)
+{
+ struct completion got_rsp;
+ unsigned long flags;
+ struct mhu_xfer *x;
+ int ret;
+
+ /*
+ * The first caller could be as early as system clocksource,
+ * when the platform devices are not populated yet.
+ */
+ if (unlikely(!mb86s7x_shm_base) && setup_mhu())
+ return -ENODEV;
+
+ if ((code & ~0xff) || ((code & RESP_BIT)
+ && fsm_state != MHU_WRRL
+ && fsm_state != MHU_WRL)) {
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ init_completion(&got_rsp);
+
+ spin_lock_irqsave(&fsm_lock, flags);
+
+ if (list_empty(&free_xfers) && mhu_alloc_xfers(5, &free_xfers)) {
+ spin_unlock_irqrestore(&fsm_lock, flags);
+ pr_err("%s:%d OOM\n", __func__, __LINE__);
+ return -EAGAIN;
+ }
+
+ x = list_first_entry(&free_xfers, struct mhu_xfer, node);
+ x->code = code;
+ x->buf = buf;
+ x->len = len;
+ x->c = &got_rsp;
+
+ if (code & RESP_BIT)
+ list_move(&x->node, &pending_xfers);
+ else
+ list_move_tail(&x->node, &pending_xfers);
+
+ spin_unlock_irqrestore(&fsm_lock, flags);
+
+ ret = do_xfer();
+ if (ret > 0) {
+ ret = wait_for_completion_timeout(&got_rsp,
+ msecs_to_jiffies(1000));
+ return ret ? 0 : -EIO;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mb86s7x_send_packet);
+
+struct mb86s7x_hard_reset {
+ u32 payload_size;
+ u32 delay;
+};
+
+static void mb86s7x_reboot(u32 delay)
+{
+ void __iomem *tx_reg = mhu_base + 0x120; /* HP-NonSec */
+ struct mb86s7x_hard_reset cmd;
+ u32 val;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.delay = delay;
+
+ val = readl_relaxed(tx_reg + INTR_STAT_OFS);
+ if (val) /* Flush anything pending */
+ writel_relaxed(val, tx_reg + INTR_CLR_OFS);
+
+ memcpy_toio(cmd_to_scb, &cmd, sizeof(cmd));
+ writel_relaxed(CMD_HARD_RESET_REQ, tx_reg + INTR_SET_OFS);
+}
+
+static void
+mb86s7x_restart(enum reboot_mode reboot_mode, const char *unused)
+{
+ /* Reboot immediately (after 50ms) */
+ mb86s7x_reboot(50);
+}
+
+static void mb86s7x_poweroff(void)
+{
+ /* Reboot never, remain dead */
+ mb86s7x_reboot(~0);
+}
+
+static int f_scb_probe(struct platform_device *pdev)
+{
+ mhu_cl.tx_block = true;
+ mhu_cl.knows_txdone = true;
+ mhu_cl.rx_callback = mhu_recv;
+ mhu_cl.dev = &pdev->dev;
+
+ arm_pm_restart = mb86s7x_restart;
+ pm_power_off = mb86s7x_poweroff;
+
+ return 0;
+}
+
+static const struct of_device_id scb_dt_ids[] = {
+ { .compatible = "fujitsu,mb86s70-scb-1.0" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, scb_dt_ids);
+
+static struct platform_driver f_scb_driver = {
+ .driver = {
+ .name = "f_scb",
+ .of_match_table = scb_dt_ids,
+ },
+ .probe = f_scb_probe,
+};
+
+static int __init f_scb_init(void)
+{
+ return platform_driver_register(&f_scb_driver);
+}
+module_init(f_scb_init);
diff --git a/include/soc/mb86s7x/scb_mhu.h b/include/soc/mb86s7x/scb_mhu.h
new file mode 100644
index 0000000..42a1baa
--- /dev/null
+++ b/include/soc/mb86s7x/scb_mhu.h
@@ -0,0 +1,97 @@
+/*
+ * include/soc/mb86s7x/scb_mhu.h
+ *
+ * Created by: Jassi Brar <jassisinghbrar@gmail.com>
+ * Copyright: (C) 2013-2015 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MB86S7X_SCB_MHU_H
+#define __MB86S7X_SCB_MHU_H
+
+#define CMD_MASK 0x7f /* 128 possible commands */
+#define RESP_BIT (1 << 7) /* If it's a response */
+
+#define ENC_CMD(c) ((c) & CMD_MASK)
+#define DEC_CMD(v) (((v) & ~CMD_MASK) ? CMD_INVALID : ((v) & CMD_MASK))
+
+#define ENC_REP(r) (((r) & CMD_MASK) | RESP_BIT)
+
+/* If v is the reply to command c */
+#define IS_A_REP(v, c) (((v) & RESP_BIT) && (((v) & CMD_MASK) == (c)))
+
+enum {
+ CMD_INVALID = 0,
+ CMD_I2C_XFER_REQ = 1,
+ CMD_PERI_POWER_SET_REQ = 2,
+ CMD_PERI_CLOCK_GATE_SET_REQ = 3,
+ CMD_PERI_CLOCK_GATE_GET_REQ = 4,
+ CMD_PERI_CLOCK_RATE_SET_REQ = 5,
+ CMD_PERI_CLOCK_RATE_GET_REQ = 6,
+ CMD_CPU_CLOCK_GATE_SET_REQ = 7,
+ CMD_CPU_CLOCK_GATE_GET_REQ = 8,
+ CMD_CPU_CLOCK_RATE_SET_REQ = 9,
+ CMD_CPU_CLOCK_RATE_GET_REQ = 0xa,
+ CMD_CLUSTER_OPP_GET_REQ = 0xb,
+ CMD_CLOCK_DSI_PIXEL_REQ = 0xc,
+ CMD_SCB_CAPABILITY_GET_REQ = 0xd,
+ CMD_SYS_RESET_CAUSE_GET_REQ = 0xe,
+ CMD_SYS_SPECIFIC_INFO_GET_REQ = 0xf,
+ CMD_REBOOT_AP_AFTER_REQ = 0x10,
+ CMD_TAIKI_REQ = 0x11,
+ CMD_TAIKI_ASYNC_MSG_REQ = 0x12,
+ CMD_GET_WORD_REQ = 0x13,
+ CMD_HARD_RESET_REQ = 0x14,
+ CMD_MAINTENANCE_MODE_REQ = 0x15,
+ CMD_STG_GET_SIZE_REQ = 0x16,
+ CMD_STG_BLOCK_READ_REQ = 0x17,
+ CMD_STG_BLOCK_WRITE_REQ = 0x18,
+ CMD_MEMORY_LAYOUT_GET_REQ = 0x19,
+ CMD_POWERDOMAIN_GET_REQ = 0x1a,
+ CMD_POWERDOMAIN_SET_REQ = 0x1b,
+ CMD_STG_BLOCK_ERASE_REQ = 0x1c,
+
+ /* Do NOT add new commands below this line */
+ MHU_NUM_CMDS,
+};
+
+#define CMD_I2C_XFER_REP ENC_REP(CMD_I2C_XFER_REQ)
+#define CMD_PERI_POWER_SET_REP ENC_REP(CMD_PERI_POWER_SET_REQ)
+#define CMD_PERI_CLOCK_GATE_SET_REP ENC_REP(CMD_PERI_CLOCK_GATE_SET_REQ)
+#define CMD_PERI_CLOCK_GATE_GET_REP ENC_REP(CMD_PERI_CLOCK_GATE_GET_REQ)
+#define CMD_PERI_CLOCK_RATE_SET_REP ENC_REP(CMD_PERI_CLOCK_RATE_SET_REQ)
+#define CMD_PERI_CLOCK_RATE_GET_REP ENC_REP(CMD_PERI_CLOCK_RATE_GET_REQ)
+#define CMD_CPU_CLOCK_GATE_SET_REP ENC_REP(CMD_CPU_CLOCK_GATE_SET_REQ)
+#define CMD_CPU_CLOCK_GATE_GET_REP ENC_REP(CMD_CPU_CLOCK_GATE_GET_REQ)
+#define CMD_CPU_CLOCK_RATE_SET_REP ENC_REP(CMD_CPU_CLOCK_RATE_SET_REQ)
+#define CMD_CPU_CLOCK_RATE_GET_REP ENC_REP(CMD_CPU_CLOCK_RATE_GET_REQ)
+#define CMD_CLUSTER_OPP_GET_REP ENC_REP(CMD_CLUSTER_OPP_GET_REQ)
+#define CMD_CLOCK_DSI_PIXEL_REP ENC_REP(CMD_CLOCK_DSI_PIXEL_REQ)
+#define CMD_SCB_CAPABILITY_GET_REP ENC_REP(CMD_SCB_CAPABILITY_GET_REQ)
+#define CMD_SYS_RESET_CAUSE_GET_REP ENC_REP(CMD_SYS_RESET_CAUSE_GET_REQ)
+#define CMD_SYS_SPECIFIC_INFO_GET_REP ENC_REP(CMD_SYS_SPECIFIC_INFO_GET_REQ)
+#define CMD_GET_WORD_REP ENC_REP(CMD_GET_WORD_REQ)
+#define CMD_REBOOT_AP_AFTER_REP ENC_REP(CMD_REBOOT_AP_AFTER_REQ)
+#define CMD_TAIKI_REP ENC_REP(CMD_TAIKI_REQ)
+#define CMD_TAIKI_ASYNC_MSG_REP ENC_REP(CMD_TAIKI_ASYNC_MSG_REQ)
+#define CMD_HARD_RESET_REP ENC_REP(CMD_HARD_RESET_REQ)
+#define CMD_MAINTENANCE_MODE_REP ENC_RSP(CMD_MAINTENANCE_MODE_REQ)
+#define CMD_STG_GET_SIZE_REP ENC_REP(CMD_STG_GET_SIZE_REQ)
+#define CMD_STG_BLOCK_READ_REP ENC_REP(CMD_STG_BLOCK_READ_REQ)
+#define CMD_STG_BLOCK_WRITE_REP ENC_REP(CMD_STG_BLOCK_WRITE_REQ)
+#define CMD_MEMORY_LAYOUT_GET_REP ENC_REP(CMD_MEMORY_LAYOUT_GET_REQ)
+#define CMD_POWERDOMAIN_GET_REP ENC_REP(CMD_POWERDOMAIN_GET_REQ)
+#define CMD_POWERDOMAIN_SET_REP ENC_REP(CMD_POWERDOMAIN_SET_REQ)
+#define CMD_STG_BLOCK_ERASE_REP ENC_REP(CMD_STG_BLOCK_ERASE_REQ)
+
+/* Helper functions to talk to remote */
+int mb86s7x_send_packet(u32 code, void *buf, int len);
+
+typedef void (*mb86s7x_mhu_handler_t)(u32 cmd, u8 rcbuf[]);
+int mb86s7x_hndlr_set(u32 cmd, mb86s7x_mhu_handler_t);
+void mb86s7x_hndlr_clr(u32 cmd, mb86s7x_mhu_handler_t);
+
+#endif /* __MB86S7X_SCB_MHU_H */
--
1.9.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-04 10:52 ` Vincent Yang
@ 2015-03-04 11:01 ` Vincent Yang
-1 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:01 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, sudeep.holla-5wv7dgnIgG8,
andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
Tetsuya Nuriya
From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
---
.../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
drivers/mailbox/Kconfig | 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
4 files changed, 249 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
create mode 100644 drivers/mailbox/arm_mhu.c
diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
new file mode 100644
index 0000000..4971f03
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
@@ -0,0 +1,43 @@
+ARM MHU Mailbox Driver
+======================
+
+The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
+3 independent channels/links to communicate with remote processor(s).
+ MHU links are hardwired on a platform. A link raises interrupt for any
+received data. However, there is no specified way of knowing if the sent
+data has been read by the remote. This driver assumes the sender polls
+STAT register and the remote clears it after having read the data.
+The last channel is specified to be a 'Secure' resource, hence can't be
+used by Linux running NS.
+
+Mailbox Device Node:
+====================
+
+Required properties:
+--------------------
+- compatible: Shall be "arm,mhu" & "arm,primecell"
+- reg: Contains the mailbox register address range (base
+ address and length)
+- #mbox-cells Shall be 1 - the index of the channel needed.
+- interrupts: Contains the interrupt information corresponding to
+ each of the 3 links of MHU.
+
+Example:
+--------
+
+ mhu: mailbox@2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu", "arm,primecell";
+ reg = <0 0x2b1f0000 0x1000>;
+ interrupts = <0 36 4>, /* LP-NonSecure */
+ <0 35 4>, /* HP-NonSecure */
+ <0 37 4>; /* Secure */
+ clocks = <&clock 0 2 1>;
+ clock-names = "apb_pclk";
+ };
+
+ mhu_client: scb@2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0x4000>;
+ mboxes = <&mhu 1>; /* HP-NonSecure */
+ };
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 84325f2..84b0a2d 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -6,6 +6,15 @@ menuconfig MAILBOX
signals. Say Y if your platform supports hardware mailboxes.
if MAILBOX
+
+config ARM_MHU
+ tristate "ARM MHU Mailbox"
+ depends on ARM_AMBA
+ help
+ Say Y here if you want to build the ARM MHU controller driver.
+ The controller has 3 mailbox channels, the last of which can be
+ used in Secure mode only.
+
config PL320_MBOX
bool "ARM PL320 Mailbox"
depends on ARM_AMBA
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 2e79231..b18201e 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -2,6 +2,8 @@
obj-$(CONFIG_MAILBOX) += mailbox.o
+obj-$(CONFIG_ARM_MHU) += arm_mhu.o
+
obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mailbox.o
diff --git a/drivers/mailbox/arm_mhu.c b/drivers/mailbox/arm_mhu.c
new file mode 100644
index 0000000..ac693c6
--- /dev/null
+++ b/drivers/mailbox/arm_mhu.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/amba/bus.h>
+#include <linux/mailbox_controller.h>
+
+#define INTR_STAT_OFS 0x0
+#define INTR_SET_OFS 0x8
+#define INTR_CLR_OFS 0x10
+
+#define MHU_LP_OFFSET 0x0
+#define MHU_HP_OFFSET 0x20
+#define MHU_SEC_OFFSET 0x200
+#define TX_REG_OFFSET 0x100
+
+#define MHU_CHANS 3
+
+struct mhu_link {
+ unsigned irq;
+ void __iomem *tx_reg;
+ void __iomem *rx_reg;
+};
+
+struct arm_mhu {
+ void __iomem *base;
+ struct mhu_link mlink[MHU_CHANS];
+ struct mbox_chan chan[MHU_CHANS];
+ struct mbox_controller mbox;
+};
+
+static irqreturn_t mhu_rx_interrupt(int irq, void *p)
+{
+ struct mbox_chan *chan = p;
+ struct mhu_link *mlink = chan->con_priv;
+ u32 val;
+
+ val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
+ if (!val)
+ return IRQ_NONE;
+
+ mbox_chan_received_data(chan, (void *)&val);
+
+ writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
+
+ return IRQ_HANDLED;
+}
+
+static bool mhu_last_tx_done(struct mbox_chan *chan)
+{
+ struct mhu_link *mlink = chan->con_priv;
+ u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
+
+ return (val == 0);
+}
+
+static int mhu_send_data(struct mbox_chan *chan, void *data)
+{
+ struct mhu_link *mlink = chan->con_priv;
+ u32 *arg = data;
+
+ writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
+
+ return 0;
+}
+
+static int mhu_startup(struct mbox_chan *chan)
+{
+ struct mhu_link *mlink = chan->con_priv;
+ u32 val;
+ int ret;
+
+ val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
+ writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
+
+ ret = request_irq(mlink->irq, mhu_rx_interrupt,
+ IRQF_SHARED, "mhu_link", chan);
+ if (ret) {
+ dev_err(chan->mbox->dev,
+ "Unable to aquire IRQ %d\n", mlink->irq);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void mhu_shutdown(struct mbox_chan *chan)
+{
+ struct mhu_link *mlink = chan->con_priv;
+
+ free_irq(mlink->irq, chan);
+}
+
+static struct mbox_chan_ops mhu_ops = {
+ .send_data = mhu_send_data,
+ .startup = mhu_startup,
+ .shutdown = mhu_shutdown,
+ .last_tx_done = mhu_last_tx_done,
+};
+
+static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ int i, err;
+ struct arm_mhu *mhu;
+ struct device *dev = &adev->dev;
+ int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
+
+ /* Allocate memory for device */
+ mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
+ if (!mhu)
+ return -ENOMEM;
+
+ mhu->base = devm_ioremap_resource(dev, &adev->res);
+ if (IS_ERR(mhu->base)) {
+ dev_err(dev, "ioremap failed\n");
+ return PTR_ERR(mhu->base);
+ }
+
+ for (i = 0; i < MHU_CHANS; i++) {
+ mhu->chan[i].con_priv = &mhu->mlink[i];
+ mhu->mlink[i].irq = adev->irq[i];
+ mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
+ mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
+ }
+
+ mhu->mbox.dev = dev;
+ mhu->mbox.chans = &mhu->chan[0];
+ mhu->mbox.num_chans = MHU_CHANS;
+ mhu->mbox.ops = &mhu_ops;
+ mhu->mbox.txdone_irq = false;
+ mhu->mbox.txdone_poll = true;
+ mhu->mbox.txpoll_period = 10;
+
+ amba_set_drvdata(adev, mhu);
+
+ err = mbox_controller_register(&mhu->mbox);
+ if (err) {
+ dev_err(dev, "Failed to register mailboxes %d\n", err);
+ return err;
+ }
+
+ dev_info(dev, "ARM MHU Mailbox registered\n");
+ return 0;
+}
+
+static int mhu_remove(struct amba_device *adev)
+{
+ struct arm_mhu *mhu = amba_get_drvdata(adev);
+
+ mbox_controller_unregister(&mhu->mbox);
+
+ return 0;
+}
+
+static struct amba_id mhu_ids[] = {
+ {
+ .id = 0x1bb098,
+ .mask = 0xffffff,
+ },
+ { 0, 0 },
+};
+MODULE_DEVICE_TABLE(amba, mhu_ids);
+
+static struct amba_driver arm_mhu_driver = {
+ .drv = {
+ .name = "mhu",
+ },
+ .id_table = mhu_ids,
+ .probe = mhu_probe,
+ .remove = mhu_remove,
+};
+module_amba_driver(arm_mhu_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ARM MHU Driver");
+MODULE_AUTHOR("Jassi Brar <jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>");
--
1.9.0
--
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-04 11:01 ` Vincent Yang
0 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Jassi Brar <jaswinder.singh@linaro.org>
Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
---
.../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
drivers/mailbox/Kconfig | 9 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
4 files changed, 249 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
create mode 100644 drivers/mailbox/arm_mhu.c
diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
new file mode 100644
index 0000000..4971f03
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
@@ -0,0 +1,43 @@
+ARM MHU Mailbox Driver
+======================
+
+The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
+3 independent channels/links to communicate with remote processor(s).
+ MHU links are hardwired on a platform. A link raises interrupt for any
+received data. However, there is no specified way of knowing if the sent
+data has been read by the remote. This driver assumes the sender polls
+STAT register and the remote clears it after having read the data.
+The last channel is specified to be a 'Secure' resource, hence can't be
+used by Linux running NS.
+
+Mailbox Device Node:
+====================
+
+Required properties:
+--------------------
+- compatible: Shall be "arm,mhu" & "arm,primecell"
+- reg: Contains the mailbox register address range (base
+ address and length)
+- #mbox-cells Shall be 1 - the index of the channel needed.
+- interrupts: Contains the interrupt information corresponding to
+ each of the 3 links of MHU.
+
+Example:
+--------
+
+ mhu: mailbox at 2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu", "arm,primecell";
+ reg = <0 0x2b1f0000 0x1000>;
+ interrupts = <0 36 4>, /* LP-NonSecure */
+ <0 35 4>, /* HP-NonSecure */
+ <0 37 4>; /* Secure */
+ clocks = <&clock 0 2 1>;
+ clock-names = "apb_pclk";
+ };
+
+ mhu_client: scb at 2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0x4000>;
+ mboxes = <&mhu 1>; /* HP-NonSecure */
+ };
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 84325f2..84b0a2d 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -6,6 +6,15 @@ menuconfig MAILBOX
signals. Say Y if your platform supports hardware mailboxes.
if MAILBOX
+
+config ARM_MHU
+ tristate "ARM MHU Mailbox"
+ depends on ARM_AMBA
+ help
+ Say Y here if you want to build the ARM MHU controller driver.
+ The controller has 3 mailbox channels, the last of which can be
+ used in Secure mode only.
+
config PL320_MBOX
bool "ARM PL320 Mailbox"
depends on ARM_AMBA
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 2e79231..b18201e 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -2,6 +2,8 @@
obj-$(CONFIG_MAILBOX) += mailbox.o
+obj-$(CONFIG_ARM_MHU) += arm_mhu.o
+
obj-$(CONFIG_PL320_MBOX) += pl320-ipc.o
obj-$(CONFIG_OMAP2PLUS_MBOX) += omap-mailbox.o
diff --git a/drivers/mailbox/arm_mhu.c b/drivers/mailbox/arm_mhu.c
new file mode 100644
index 0000000..ac693c6
--- /dev/null
+++ b/drivers/mailbox/arm_mhu.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Jassi Brar <jaswinder.singh@linaro.org>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/amba/bus.h>
+#include <linux/mailbox_controller.h>
+
+#define INTR_STAT_OFS 0x0
+#define INTR_SET_OFS 0x8
+#define INTR_CLR_OFS 0x10
+
+#define MHU_LP_OFFSET 0x0
+#define MHU_HP_OFFSET 0x20
+#define MHU_SEC_OFFSET 0x200
+#define TX_REG_OFFSET 0x100
+
+#define MHU_CHANS 3
+
+struct mhu_link {
+ unsigned irq;
+ void __iomem *tx_reg;
+ void __iomem *rx_reg;
+};
+
+struct arm_mhu {
+ void __iomem *base;
+ struct mhu_link mlink[MHU_CHANS];
+ struct mbox_chan chan[MHU_CHANS];
+ struct mbox_controller mbox;
+};
+
+static irqreturn_t mhu_rx_interrupt(int irq, void *p)
+{
+ struct mbox_chan *chan = p;
+ struct mhu_link *mlink = chan->con_priv;
+ u32 val;
+
+ val = readl_relaxed(mlink->rx_reg + INTR_STAT_OFS);
+ if (!val)
+ return IRQ_NONE;
+
+ mbox_chan_received_data(chan, (void *)&val);
+
+ writel_relaxed(val, mlink->rx_reg + INTR_CLR_OFS);
+
+ return IRQ_HANDLED;
+}
+
+static bool mhu_last_tx_done(struct mbox_chan *chan)
+{
+ struct mhu_link *mlink = chan->con_priv;
+ u32 val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
+
+ return (val == 0);
+}
+
+static int mhu_send_data(struct mbox_chan *chan, void *data)
+{
+ struct mhu_link *mlink = chan->con_priv;
+ u32 *arg = data;
+
+ writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
+
+ return 0;
+}
+
+static int mhu_startup(struct mbox_chan *chan)
+{
+ struct mhu_link *mlink = chan->con_priv;
+ u32 val;
+ int ret;
+
+ val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
+ writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
+
+ ret = request_irq(mlink->irq, mhu_rx_interrupt,
+ IRQF_SHARED, "mhu_link", chan);
+ if (ret) {
+ dev_err(chan->mbox->dev,
+ "Unable to aquire IRQ %d\n", mlink->irq);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void mhu_shutdown(struct mbox_chan *chan)
+{
+ struct mhu_link *mlink = chan->con_priv;
+
+ free_irq(mlink->irq, chan);
+}
+
+static struct mbox_chan_ops mhu_ops = {
+ .send_data = mhu_send_data,
+ .startup = mhu_startup,
+ .shutdown = mhu_shutdown,
+ .last_tx_done = mhu_last_tx_done,
+};
+
+static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ int i, err;
+ struct arm_mhu *mhu;
+ struct device *dev = &adev->dev;
+ int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
+
+ /* Allocate memory for device */
+ mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
+ if (!mhu)
+ return -ENOMEM;
+
+ mhu->base = devm_ioremap_resource(dev, &adev->res);
+ if (IS_ERR(mhu->base)) {
+ dev_err(dev, "ioremap failed\n");
+ return PTR_ERR(mhu->base);
+ }
+
+ for (i = 0; i < MHU_CHANS; i++) {
+ mhu->chan[i].con_priv = &mhu->mlink[i];
+ mhu->mlink[i].irq = adev->irq[i];
+ mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
+ mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
+ }
+
+ mhu->mbox.dev = dev;
+ mhu->mbox.chans = &mhu->chan[0];
+ mhu->mbox.num_chans = MHU_CHANS;
+ mhu->mbox.ops = &mhu_ops;
+ mhu->mbox.txdone_irq = false;
+ mhu->mbox.txdone_poll = true;
+ mhu->mbox.txpoll_period = 10;
+
+ amba_set_drvdata(adev, mhu);
+
+ err = mbox_controller_register(&mhu->mbox);
+ if (err) {
+ dev_err(dev, "Failed to register mailboxes %d\n", err);
+ return err;
+ }
+
+ dev_info(dev, "ARM MHU Mailbox registered\n");
+ return 0;
+}
+
+static int mhu_remove(struct amba_device *adev)
+{
+ struct arm_mhu *mhu = amba_get_drvdata(adev);
+
+ mbox_controller_unregister(&mhu->mbox);
+
+ return 0;
+}
+
+static struct amba_id mhu_ids[] = {
+ {
+ .id = 0x1bb098,
+ .mask = 0xffffff,
+ },
+ { 0, 0 },
+};
+MODULE_DEVICE_TABLE(amba, mhu_ids);
+
+static struct amba_driver arm_mhu_driver = {
+ .drv = {
+ .name = "mhu",
+ },
+ .id_table = mhu_ids,
+ .probe = mhu_probe,
+ .remove = mhu_remove,
+};
+module_amba_driver(arm_mhu_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("ARM MHU Driver");
+MODULE_AUTHOR("Jassi Brar <jassisinghbrar@gmail.com>");
--
1.9.0
^ permalink raw reply related [flat|nested] 34+ messages in thread[parent not found: <1425466884-30648-1-git-send-email-vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>]
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-04 11:01 ` Vincent Yang
@ 2015-03-18 9:57 ` Sudeep Holla
-1 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 9:57 UTC (permalink / raw)
To: Vincent Yang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Sudeep Holla, arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Pawel Moll, Mark Rutland,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
Tetsuya Nuriya
Hi Vincent,
I see that this driver is queued but most of my earlier comments were
not addressed. *No ACK from DT binding maintainers too*.
On 04/03/15 11:01, Vincent Yang wrote:
> From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
>
> Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> ---
> .../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
> drivers/mailbox/Kconfig | 9 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> create mode 100644 drivers/mailbox/arm_mhu.c
>
> diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> new file mode 100644
> index 0000000..4971f03
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> @@ -0,0 +1,43 @@
> +ARM MHU Mailbox Driver
> +======================
> +
> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
> +3 independent channels/links to communicate with remote processor(s).
> + MHU links are hardwired on a platform. A link raises interrupt for any
As I had mentioned before it's just one implementation, the IP had
provision bi-directional interrupts and the binding *has to consider*
that instead of having to workaround that later.
> +received data. However, there is no specified way of knowing if the sent
You can drop the above line or specify as you can still poll.
> +data has been read by the remote. This driver assumes the sender polls
Bindings not supposed have any details on how driver handle it. You can
just mention that in absence of interrupt, we can know the status of
transmission by polling STAT register.
> +STAT register and the remote clears it after having read the data.
> +The last channel is specified to be a 'Secure' resource, hence can't be
> +used by Linux running NS.
> +
Correct so drop the support for secure channel until the first user
comes up. I am worried it might generate abort if someone tries to
access it in ARM64 which always runs in non-secure.
> +Mailbox Device Node:
> +====================
> +
> +Required properties:
> +--------------------
> +- compatible: Shall be "arm,mhu" & "arm,primecell"
> +- reg: Contains the mailbox register address range (base
> + address and length)
> +- #mbox-cells Shall be 1 - the index of the channel needed.
> +- interrupts: Contains the interrupt information corresponding to
> + each of the 3 links of MHU.
> +
As mentioned multiple times before, please add interrupt-names to make
sure we can handle bi-directional interrupt.
> +Example:
> +--------
> +
> + mhu: mailbox@2b1f0000 {
> + #mbox-cells = <1>;
> + compatible = "arm,mhu", "arm,primecell";
> + reg = <0 0x2b1f0000 0x1000>;
> + interrupts = <0 36 4>, /* LP-NonSecure */
> + <0 35 4>, /* HP-NonSecure */
> + <0 37 4>; /* Secure */
> + clocks = <&clock 0 2 1>;
> + clock-names = "apb_pclk";
> + };
> +
> + mhu_client: scb@2e000000 {
> + compatible = "fujitsu,mb86s70-scb-1.0";
> + reg = <0 0x2e000000 0x4000>;
> + mboxes = <&mhu 1>; /* HP-NonSecure */
> + };
[...]
> diff --git a/drivers/mailbox/arm_mhu.c b/drivers/mailbox/arm_mhu.c
> new file mode 100644
> index 0000000..ac693c6
> --- /dev/null
> +++ b/drivers/mailbox/arm_mhu.c
> @@ -0,0 +1,195 @@
> +/*
> + * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/spinlock.h>
> +#include <linux/mutex.h>
> +#include <linux/delay.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/amba/bus.h>
> +#include <linux/mailbox_controller.h>
> +
> +#define INTR_STAT_OFS 0x0
> +#define INTR_SET_OFS 0x8
> +#define INTR_CLR_OFS 0x10
> +
> +#define MHU_LP_OFFSET 0x0
> +#define MHU_HP_OFFSET 0x20
> +#define MHU_SEC_OFFSET 0x200
> +#define TX_REG_OFFSET 0x100
> +
> +#define MHU_CHANS 3
> +
For now I prefer 2.
[...]
> +static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + int i, err;
> + struct arm_mhu *mhu;
> + struct device *dev = &adev->dev;
> + int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
> +
> + /* Allocate memory for device */
> + mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
> + if (!mhu)
> + return -ENOMEM;
> +
> + mhu->base = devm_ioremap_resource(dev, &adev->res);
> + if (IS_ERR(mhu->base)) {
> + dev_err(dev, "ioremap failed\n");
> + return PTR_ERR(mhu->base);
> + }
> +
> + for (i = 0; i < MHU_CHANS; i++) {
> + mhu->chan[i].con_priv = &mhu->mlink[i];
> + mhu->mlink[i].irq = adev->irq[i];
> + mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
> + mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
> + }
> +
> + mhu->mbox.dev = dev;
> + mhu->mbox.chans = &mhu->chan[0];
> + mhu->mbox.num_chans = MHU_CHANS;
> + mhu->mbox.ops = &mhu_ops;
> + mhu->mbox.txdone_irq = false;
> + mhu->mbox.txdone_poll = true;
> + mhu->mbox.txpoll_period = 10;
IMO too high value, as I mentioned you assume jiffy value. The kernel
will take care of conversion.
[...]
> +
> +static struct amba_id mhu_ids[] = {
> + {
> + .id = 0x1bb098,
As I mentioned couple of times this is broken. Please refer my earlier
mail for details. You are skipping a field to compare which incorrect.
You are just trying to get it working with existing AMBA driver without
any changes matching the IDs partially.
Regards,
Sudeep
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-18 9:57 ` Sudeep Holla
0 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 9:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Vincent,
I see that this driver is queued but most of my earlier comments were
not addressed. *No ACK from DT binding maintainers too*.
On 04/03/15 11:01, Vincent Yang wrote:
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> Signed-off-by: Andy Green <andy.green@linaro.org>
> Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
> ---
> .../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
> drivers/mailbox/Kconfig | 9 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> create mode 100644 drivers/mailbox/arm_mhu.c
>
> diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> new file mode 100644
> index 0000000..4971f03
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> @@ -0,0 +1,43 @@
> +ARM MHU Mailbox Driver
> +======================
> +
> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
> +3 independent channels/links to communicate with remote processor(s).
> + MHU links are hardwired on a platform. A link raises interrupt for any
As I had mentioned before it's just one implementation, the IP had
provision bi-directional interrupts and the binding *has to consider*
that instead of having to workaround that later.
> +received data. However, there is no specified way of knowing if the sent
You can drop the above line or specify as you can still poll.
> +data has been read by the remote. This driver assumes the sender polls
Bindings not supposed have any details on how driver handle it. You can
just mention that in absence of interrupt, we can know the status of
transmission by polling STAT register.
> +STAT register and the remote clears it after having read the data.
> +The last channel is specified to be a 'Secure' resource, hence can't be
> +used by Linux running NS.
> +
Correct so drop the support for secure channel until the first user
comes up. I am worried it might generate abort if someone tries to
access it in ARM64 which always runs in non-secure.
> +Mailbox Device Node:
> +====================
> +
> +Required properties:
> +--------------------
> +- compatible: Shall be "arm,mhu" & "arm,primecell"
> +- reg: Contains the mailbox register address range (base
> + address and length)
> +- #mbox-cells Shall be 1 - the index of the channel needed.
> +- interrupts: Contains the interrupt information corresponding to
> + each of the 3 links of MHU.
> +
As mentioned multiple times before, please add interrupt-names to make
sure we can handle bi-directional interrupt.
> +Example:
> +--------
> +
> + mhu: mailbox at 2b1f0000 {
> + #mbox-cells = <1>;
> + compatible = "arm,mhu", "arm,primecell";
> + reg = <0 0x2b1f0000 0x1000>;
> + interrupts = <0 36 4>, /* LP-NonSecure */
> + <0 35 4>, /* HP-NonSecure */
> + <0 37 4>; /* Secure */
> + clocks = <&clock 0 2 1>;
> + clock-names = "apb_pclk";
> + };
> +
> + mhu_client: scb at 2e000000 {
> + compatible = "fujitsu,mb86s70-scb-1.0";
> + reg = <0 0x2e000000 0x4000>;
> + mboxes = <&mhu 1>; /* HP-NonSecure */
> + };
[...]
> diff --git a/drivers/mailbox/arm_mhu.c b/drivers/mailbox/arm_mhu.c
> new file mode 100644
> index 0000000..ac693c6
> --- /dev/null
> +++ b/drivers/mailbox/arm_mhu.c
> @@ -0,0 +1,195 @@
> +/*
> + * Copyright (C) 2013-2015 Fujitsu Semiconductor Ltd.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Jassi Brar <jaswinder.singh@linaro.org>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/spinlock.h>
> +#include <linux/mutex.h>
> +#include <linux/delay.h>
> +#include <linux/slab.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/amba/bus.h>
> +#include <linux/mailbox_controller.h>
> +
> +#define INTR_STAT_OFS 0x0
> +#define INTR_SET_OFS 0x8
> +#define INTR_CLR_OFS 0x10
> +
> +#define MHU_LP_OFFSET 0x0
> +#define MHU_HP_OFFSET 0x20
> +#define MHU_SEC_OFFSET 0x200
> +#define TX_REG_OFFSET 0x100
> +
> +#define MHU_CHANS 3
> +
For now I prefer 2.
[...]
> +static int mhu_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + int i, err;
> + struct arm_mhu *mhu;
> + struct device *dev = &adev->dev;
> + int mhu_reg[MHU_CHANS] = {MHU_LP_OFFSET, MHU_HP_OFFSET, MHU_SEC_OFFSET};
> +
> + /* Allocate memory for device */
> + mhu = devm_kzalloc(dev, sizeof(*mhu), GFP_KERNEL);
> + if (!mhu)
> + return -ENOMEM;
> +
> + mhu->base = devm_ioremap_resource(dev, &adev->res);
> + if (IS_ERR(mhu->base)) {
> + dev_err(dev, "ioremap failed\n");
> + return PTR_ERR(mhu->base);
> + }
> +
> + for (i = 0; i < MHU_CHANS; i++) {
> + mhu->chan[i].con_priv = &mhu->mlink[i];
> + mhu->mlink[i].irq = adev->irq[i];
> + mhu->mlink[i].rx_reg = mhu->base + mhu_reg[i];
> + mhu->mlink[i].tx_reg = mhu->mlink[i].rx_reg + TX_REG_OFFSET;
> + }
> +
> + mhu->mbox.dev = dev;
> + mhu->mbox.chans = &mhu->chan[0];
> + mhu->mbox.num_chans = MHU_CHANS;
> + mhu->mbox.ops = &mhu_ops;
> + mhu->mbox.txdone_irq = false;
> + mhu->mbox.txdone_poll = true;
> + mhu->mbox.txpoll_period = 10;
IMO too high value, as I mentioned you assume jiffy value. The kernel
will take care of conversion.
[...]
> +
> +static struct amba_id mhu_ids[] = {
> + {
> + .id = 0x1bb098,
As I mentioned couple of times this is broken. Please refer my earlier
mail for details. You are skipping a field to compare which incorrect.
You are just trying to get it working with existing AMBA driver without
any changes matching the IDs partially.
Regards,
Sudeep
^ permalink raw reply [flat|nested] 34+ messages in thread[parent not found: <55094BEF.9060006-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-18 9:57 ` Sudeep Holla
@ 2015-03-18 12:56 ` Jassi Brar
-1 siblings, 0 replies; 34+ messages in thread
From: Jassi Brar @ 2015-03-18 12:56 UTC (permalink / raw)
To: Sudeep Holla
Cc: Vincent Yang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
andy.green-QSEj5FYQhm4dnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
arm-DgEjT+Ai2ygdnm+yROfE0A, arnd-r2nGTMty4D4,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Tetsuya Nuriya,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Pawel Moll,
patches-QSEj5FYQhm4dnm+yROfE0A, olof-nZhT3qVonbNeoWH0uzbU5w,
Vincent Yang
On Wed, Mar 18, 2015 at 3:27 PM, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
> Hi Vincent,
>
> I see that this driver is queued but most of my earlier comments were
> not addressed.
>
Some of your comments have been addressed as changes and some as replies.
> *No ACK from DT binding maintainers too*.
>
Yeah it would have been great to have some ack. It has been many
months now, but I see its not uncommon for bindings go in via
maintainers. I assume folks find it just normal.
>> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
>> @@ -0,0 +1,43 @@
>> +ARM MHU Mailbox Driver
>> +======================
>> +
>> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
>> +3 independent channels/links to communicate with remote processor(s).
>> + MHU links are hardwired on a platform. A link raises interrupt for any
>
>
> As I had mentioned before it's just one implementation, the IP had
> provision bi-directional interrupts and the binding *has to consider*
> that instead of having to workaround that later.
>
I will reply in yet another way.... the spec I have don't mention that
(and it makes sense) and your platform doesn't do that either. I would
have had to do something about it, had there been such a weird setup,
but there's none known.
So let us please avoid getting into bikeshedding discussion yet
again. Otherwise almost every binding is broken because there could
always be some platform that does weird things with irqs.
>> +The last channel is specified to be a 'Secure' resource, hence can't be
>> +used by Linux running NS.
>
> Correct so drop the support for secure channel until the first user
> comes up.
>
In your last post you said:
"Sorry my statement was not clear, I wanted to ask you to add that info
to the binding."
Not that it makes sense to say the obvious, I added it just to
address your comment.
> I am worried it might generate abort if someone tries to
> access it in ARM64 which always runs in non-secure.
>
Abort should have happened years ago if someone _tries_ to access a
secure resource from non-secure mode ;)
How do you protect such people from "trying to" dereference NULL
pointers? (you made me repeat Nth time).
>> +
>> +static struct amba_id mhu_ids[] = {
>> + {
>> + .id = 0x1bb098,
>
>
> As I mentioned couple of times this is broken. Please refer my earlier mail
> for details. You are skipping a field to compare which incorrect.
> You are just trying to get it working with existing AMBA driver without any
> changes matching the IDs partially.
>
I did not miss your last mail. Let me try to reply in even simpler
terms... PID[0,3] identification is fine grained enough. If/when we
have some platform with non-ARM MHU, we could catch that in this
driver. Most likely even then the reg-map won't change drastically, if
at all. So we could ignore the PID4, otherwise we check PID4 in this
driver and adapt the behavior.
-Jassi
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To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-18 12:56 ` Jassi Brar
0 siblings, 0 replies; 34+ messages in thread
From: Jassi Brar @ 2015-03-18 12:56 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Mar 18, 2015 at 3:27 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
> Hi Vincent,
>
> I see that this driver is queued but most of my earlier comments were
> not addressed.
>
Some of your comments have been addressed as changes and some as replies.
> *No ACK from DT binding maintainers too*.
>
Yeah it would have been great to have some ack. It has been many
months now, but I see its not uncommon for bindings go in via
maintainers. I assume folks find it just normal.
>> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
>> @@ -0,0 +1,43 @@
>> +ARM MHU Mailbox Driver
>> +======================
>> +
>> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
>> +3 independent channels/links to communicate with remote processor(s).
>> + MHU links are hardwired on a platform. A link raises interrupt for any
>
>
> As I had mentioned before it's just one implementation, the IP had
> provision bi-directional interrupts and the binding *has to consider*
> that instead of having to workaround that later.
>
I will reply in yet another way.... the spec I have don't mention that
(and it makes sense) and your platform doesn't do that either. I would
have had to do something about it, had there been such a weird setup,
but there's none known.
So let us please avoid getting into bikeshedding discussion yet
again. Otherwise almost every binding is broken because there could
always be some platform that does weird things with irqs.
>> +The last channel is specified to be a 'Secure' resource, hence can't be
>> +used by Linux running NS.
>
> Correct so drop the support for secure channel until the first user
> comes up.
>
In your last post you said:
"Sorry my statement was not clear, I wanted to ask you to add that info
to the binding."
Not that it makes sense to say the obvious, I added it just to
address your comment.
> I am worried it might generate abort if someone tries to
> access it in ARM64 which always runs in non-secure.
>
Abort should have happened years ago if someone _tries_ to access a
secure resource from non-secure mode ;)
How do you protect such people from "trying to" dereference NULL
pointers? (you made me repeat Nth time).
>> +
>> +static struct amba_id mhu_ids[] = {
>> + {
>> + .id = 0x1bb098,
>
>
> As I mentioned couple of times this is broken. Please refer my earlier mail
> for details. You are skipping a field to compare which incorrect.
> You are just trying to get it working with existing AMBA driver without any
> changes matching the IDs partially.
>
I did not miss your last mail. Let me try to reply in even simpler
terms... PID[0,3] identification is fine grained enough. If/when we
have some platform with non-ARM MHU, we could catch that in this
driver. Most likely even then the reg-map won't change drastically, if
at all. So we could ignore the PID4, otherwise we check PID4 in this
driver and adapt the behavior.
-Jassi
^ permalink raw reply [flat|nested] 34+ messages in thread[parent not found: <CABb+yY2woK6qWbrgPGRBRXJqJdf=1HxE_-Am-SY1_Uf_dNgTew-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-18 12:56 ` Jassi Brar
@ 2015-03-18 14:08 ` Sudeep Holla
-1 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 14:08 UTC (permalink / raw)
To: Jassi Brar
Cc: Sudeep Holla, Vincent Yang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
andy.green-QSEj5FYQhm4dnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
arm-DgEjT+Ai2ygdnm+yROfE0A, arnd-r2nGTMty4D4,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Tetsuya Nuriya,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Pawel Moll,
patches-QSEj5FYQhm4dnm+yROfE0A, olof-nZhT3qVonbNeoWH0uzbU5w,
Vincent Yang
On 18/03/15 12:56, Jassi Brar wrote:
> On Wed, Mar 18, 2015 at 3:27 PM, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>> Hi Vincent,
>>
>> I see that this driver is queued but most of my earlier comments were
>> not addressed.
>>
> Some of your comments have been addressed as changes and some as replies.
>
>> *No ACK from DT binding maintainers too*.
>>
> Yeah it would have been great to have some ack. It has been many
> months now, but I see its not uncommon for bindings go in via
> maintainers. I assume folks find it just normal.
>
OK, but I have one concern in the binding as mentioned previous and
again as below.
>>> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
>>> @@ -0,0 +1,43 @@
>>> +ARM MHU Mailbox Driver
>>> +======================
>>> +
>>> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
>>> +3 independent channels/links to communicate with remote processor(s).
>>> + MHU links are hardwired on a platform. A link raises interrupt for any
>>
>>
>> As I had mentioned before it's just one implementation, the IP had
>> provision bi-directional interrupts and the binding *has to consider*
>> that instead of having to workaround that later.
>>
> I will reply in yet another way.... the spec I have don't mention that
> (and it makes sense) and your platform doesn't do that either. I would
> have had to do something about it, had there been such a weird setup,
> but there's none known.
>
Not just weird setup, even extending Tx support with this binding is not
straight forward.
Simple example:
Today you have:
interrupts = <0 36 4>, /* LP-NonSecure */
<0 35 4>, /* HP-NonSecure */
<0 37 4>; /* Secure */
I don't want to specify Secure IRQ on my platform, which should be fine.
In future a variant of that platform gets Tx interrupts, then I will add
something like below:
interrupts = <0 36 4>, /* LP-NonSecure Rx */
<0 35 4>, /* HP-NonSecure Rx */
<0 39 4>, /* LP-NonSecure Tx */
<0 38 4>, /* HP-NonSecure Tx */
Now how will we handle this ?
I am just suggesting to use interrupt-names so that we don't depend on
ordering in DT implicitly from first by fixing the binding.
> So let us please avoid getting into bikeshedding discussion yet
> again. Otherwise almost every binding is broken because there could
> always be some platform that does weird things with irqs.
>
Sorry I don't buy that given that using interrupt-names simplifies
things and also helps to hand any such cases.
>>> +The last channel is specified to be a 'Secure' resource, hence can't be
>>> +used by Linux running NS.
>>
>> Correct so drop the support for secure channel until the first user
>> comes up.
>>
> In your last post you said:
> "Sorry my statement was not clear, I wanted to ask you to add that info
> to the binding."
> Not that it makes sense to say the obvious, I added it just to
> address your comment.
>
>> I am worried it might generate abort if someone tries to
>> access it in ARM64 which always runs in non-secure.
>>
> Abort should have happened years ago if someone _tries_ to access a
> secure resource from non-secure mode ;)
> How do you protect such people from "trying to" dereference NULL
> pointers? (you made me repeat Nth time).
>
When the general practice everywhere in the kernel is to avoid secure
accesses *unless and until absolutely necessary*, I don't understand
*why exactly we need the exception here* ? I am OK if you add that
justification with the first user of that channel. We have seen several
cases/issues around that and I am just looking for a strong reason to
add secure channel support here.
>>> +
>>> +static struct amba_id mhu_ids[] = {
>>> + {
>>> + .id = 0x1bb098,
>>
>>
>> As I mentioned couple of times this is broken. Please refer my earlier mail
>> for details. You are skipping a field to compare which incorrect.
>> You are just trying to get it working with existing AMBA driver without any
>> changes matching the IDs partially.
>>
> I did not miss your last mail. Let me try to reply in even simpler
> terms... PID[0,3] identification is fine grained enough. If/when we
> have some platform with non-ARM MHU, we could catch that in this
> driver. Most likely even then the reg-map won't change drastically, if
> at all. So we could ignore the PID4, otherwise we check PID4 in this
> driver and adapt the behavior.
I am just looking for ARM MHU implementation, not any non-ARM MHU.
If look at the MHU spec[1], excerpts below:
PID_4 Register
[31:8] - Reserved. Read as zero.
[7:4] SIZE Indicates the log2 of the number of 4KB blocks that the
interface occupies. Set to 0x0.
[3:0] DES_2 JEP106 continuation code that identifies the designer. Set
to 0x4 for ARM.
PID_1 Register
[31:8] - Reserved. Read as zero.
[7:4] DES_0 Bits [3:0] of the JEP Identity. Set to 0xB for ARM.
[3:0] PART_1 Bits [11:8] of the part number. Set to 0x0.
Now by skipping PID4 DES_2 part, you are not comparing the designer
correctly. It may be OK to fix in the driver as you mentioned.
Not sure if it's better to fix AMBA, or just don't use AMBA for
IP with JEP106 code. I don't have any strong opinion there.
Regards,
Sudeep
[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0515b/CHDBFACE.html#id5278622
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-18 14:08 ` Sudeep Holla
0 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 14:08 UTC (permalink / raw)
To: linux-arm-kernel
On 18/03/15 12:56, Jassi Brar wrote:
> On Wed, Mar 18, 2015 at 3:27 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
>> Hi Vincent,
>>
>> I see that this driver is queued but most of my earlier comments were
>> not addressed.
>>
> Some of your comments have been addressed as changes and some as replies.
>
>> *No ACK from DT binding maintainers too*.
>>
> Yeah it would have been great to have some ack. It has been many
> months now, but I see its not uncommon for bindings go in via
> maintainers. I assume folks find it just normal.
>
OK, but I have one concern in the binding as mentioned previous and
again as below.
>>> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
>>> @@ -0,0 +1,43 @@
>>> +ARM MHU Mailbox Driver
>>> +======================
>>> +
>>> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
>>> +3 independent channels/links to communicate with remote processor(s).
>>> + MHU links are hardwired on a platform. A link raises interrupt for any
>>
>>
>> As I had mentioned before it's just one implementation, the IP had
>> provision bi-directional interrupts and the binding *has to consider*
>> that instead of having to workaround that later.
>>
> I will reply in yet another way.... the spec I have don't mention that
> (and it makes sense) and your platform doesn't do that either. I would
> have had to do something about it, had there been such a weird setup,
> but there's none known.
>
Not just weird setup, even extending Tx support with this binding is not
straight forward.
Simple example:
Today you have:
interrupts = <0 36 4>, /* LP-NonSecure */
<0 35 4>, /* HP-NonSecure */
<0 37 4>; /* Secure */
I don't want to specify Secure IRQ on my platform, which should be fine.
In future a variant of that platform gets Tx interrupts, then I will add
something like below:
interrupts = <0 36 4>, /* LP-NonSecure Rx */
<0 35 4>, /* HP-NonSecure Rx */
<0 39 4>, /* LP-NonSecure Tx */
<0 38 4>, /* HP-NonSecure Tx */
Now how will we handle this ?
I am just suggesting to use interrupt-names so that we don't depend on
ordering in DT implicitly from first by fixing the binding.
> So let us please avoid getting into bikeshedding discussion yet
> again. Otherwise almost every binding is broken because there could
> always be some platform that does weird things with irqs.
>
Sorry I don't buy that given that using interrupt-names simplifies
things and also helps to hand any such cases.
>>> +The last channel is specified to be a 'Secure' resource, hence can't be
>>> +used by Linux running NS.
>>
>> Correct so drop the support for secure channel until the first user
>> comes up.
>>
> In your last post you said:
> "Sorry my statement was not clear, I wanted to ask you to add that info
> to the binding."
> Not that it makes sense to say the obvious, I added it just to
> address your comment.
>
>> I am worried it might generate abort if someone tries to
>> access it in ARM64 which always runs in non-secure.
>>
> Abort should have happened years ago if someone _tries_ to access a
> secure resource from non-secure mode ;)
> How do you protect such people from "trying to" dereference NULL
> pointers? (you made me repeat Nth time).
>
When the general practice everywhere in the kernel is to avoid secure
accesses *unless and until absolutely necessary*, I don't understand
*why exactly we need the exception here* ? I am OK if you add that
justification with the first user of that channel. We have seen several
cases/issues around that and I am just looking for a strong reason to
add secure channel support here.
>>> +
>>> +static struct amba_id mhu_ids[] = {
>>> + {
>>> + .id = 0x1bb098,
>>
>>
>> As I mentioned couple of times this is broken. Please refer my earlier mail
>> for details. You are skipping a field to compare which incorrect.
>> You are just trying to get it working with existing AMBA driver without any
>> changes matching the IDs partially.
>>
> I did not miss your last mail. Let me try to reply in even simpler
> terms... PID[0,3] identification is fine grained enough. If/when we
> have some platform with non-ARM MHU, we could catch that in this
> driver. Most likely even then the reg-map won't change drastically, if
> at all. So we could ignore the PID4, otherwise we check PID4 in this
> driver and adapt the behavior.
I am just looking for ARM MHU implementation, not any non-ARM MHU.
If look at the MHU spec[1], excerpts below:
PID_4 Register
[31:8] - Reserved. Read as zero.
[7:4] SIZE Indicates the log2 of the number of 4KB blocks that the
interface occupies. Set to 0x0.
[3:0] DES_2 JEP106 continuation code that identifies the designer. Set
to 0x4 for ARM.
PID_1 Register
[31:8] - Reserved. Read as zero.
[7:4] DES_0 Bits [3:0] of the JEP Identity. Set to 0xB for ARM.
[3:0] PART_1 Bits [11:8] of the part number. Set to 0x0.
Now by skipping PID4 DES_2 part, you are not comparing the designer
correctly. It may be OK to fix in the driver as you mentioned.
Not sure if it's better to fix AMBA, or just don't use AMBA for
IP with JEP106 code. I don't have any strong opinion there.
Regards,
Sudeep
[1]
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0515b/CHDBFACE.html#id5278622
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-04 11:01 ` Vincent Yang
@ 2015-03-18 10:25 ` Sudeep Holla
-1 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 10:25 UTC (permalink / raw)
To: Vincent Yang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Sudeep Holla, arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Pawel Moll, Mark Rutland,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
Tetsuya Nuriya
Hi Vincent,
Forgot couple of things earlier:
On 04/03/15 11:01, Vincent Yang wrote:
> From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
>
> Signed-off-by: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> ---
> .../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
> drivers/mailbox/Kconfig | 9 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> create mode 100644 drivers/mailbox/arm_mhu.c
>
[...]
> +static int mhu_send_data(struct mbox_chan *chan, void *data)
> +{
> + struct mhu_link *mlink = chan->con_priv;
> + u32 *arg = data;
> +
Arnd doesn't like this and had suggestions in some other thread.
> + writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
> +
> + return 0;
> +}
> +
> +static int mhu_startup(struct mbox_chan *chan)
> +{
> + struct mhu_link *mlink = chan->con_priv;
> + u32 val;
> + int ret;
> +
> + val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
> + writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
> +
> + ret = request_irq(mlink->irq, mhu_rx_interrupt,
> + IRQF_SHARED, "mhu_link", chan);
Any reason we can't move this to probe and have {en,dis}able_irq here if
needed. I has seen it was too heavy to have these especially when
sending small packets.
Regards,
Sudeep
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-18 10:25 ` Sudeep Holla
0 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 10:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi Vincent,
Forgot couple of things earlier:
On 04/03/15 11:01, Vincent Yang wrote:
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> Signed-off-by: Andy Green <andy.green@linaro.org>
> Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
> ---
> .../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
> drivers/mailbox/Kconfig | 9 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> create mode 100644 drivers/mailbox/arm_mhu.c
>
[...]
> +static int mhu_send_data(struct mbox_chan *chan, void *data)
> +{
> + struct mhu_link *mlink = chan->con_priv;
> + u32 *arg = data;
> +
Arnd doesn't like this and had suggestions in some other thread.
> + writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
> +
> + return 0;
> +}
> +
> +static int mhu_startup(struct mbox_chan *chan)
> +{
> + struct mhu_link *mlink = chan->con_priv;
> + u32 val;
> + int ret;
> +
> + val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
> + writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
> +
> + ret = request_irq(mlink->irq, mhu_rx_interrupt,
> + IRQF_SHARED, "mhu_link", chan);
Any reason we can't move this to probe and have {en,dis}able_irq here if
needed. I has seen it was too heavy to have these especially when
sending small packets.
Regards,
Sudeep
^ permalink raw reply [flat|nested] 34+ messages in thread[parent not found: <55095297.5060605-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-18 10:25 ` Sudeep Holla
@ 2015-03-18 13:19 ` Jassi Brar
-1 siblings, 0 replies; 34+ messages in thread
From: Jassi Brar @ 2015-03-18 13:19 UTC (permalink / raw)
To: Sudeep Holla
Cc: Vincent Yang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
andy.green-QSEj5FYQhm4dnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
arm-DgEjT+Ai2ygdnm+yROfE0A, arnd-r2nGTMty4D4,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Tetsuya Nuriya,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Pawel Moll,
patches-QSEj5FYQhm4dnm+yROfE0A, olof-nZhT3qVonbNeoWH0uzbU5w,
Vincent Yang
On Wed, Mar 18, 2015 at 3:55 PM, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>
>> +static int mhu_send_data(struct mbox_chan *chan, void *data)
>> +{
>> + struct mhu_link *mlink = chan->con_priv;
>> + u32 *arg = data;
>
> Arnd doesn't like this and had suggestions in some other thread.
>
No, Arnd suggested doing it this way. And another platform's driver
was made to do this way.
>> + writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
>> +
>> + return 0;
>> +}
>> +
>> +static int mhu_startup(struct mbox_chan *chan)
>> +{
>> + struct mhu_link *mlink = chan->con_priv;
>> + u32 val;
>> + int ret;
>> +
>> + val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
>> + writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
>> +
>> + ret = request_irq(mlink->irq, mhu_rx_interrupt,
>> + IRQF_SHARED, "mhu_link", chan);
>
>
> Any reason we can't move this to probe and have {en,dis}able_irq here if
> needed. I has seen it was too heavy to have these especially when
> sending small packets.
>
I see you used to do memcpy in irq-handler
https://git.linaro.org/landing-teams/working/arm/kernel.git/blob/HEAD:/drivers/mailbox/arm_mhu.c
perhaps you were using your old driver?
If you use this new driver, and send packets so often that
request-release irq has effect, maybe should hold the mailbox
reference for lifetime. I remember suggesting you that already and I
remember you said that's how it was.
-Jassi
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-18 13:19 ` Jassi Brar
0 siblings, 0 replies; 34+ messages in thread
From: Jassi Brar @ 2015-03-18 13:19 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Mar 18, 2015 at 3:55 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
>
>> +static int mhu_send_data(struct mbox_chan *chan, void *data)
>> +{
>> + struct mhu_link *mlink = chan->con_priv;
>> + u32 *arg = data;
>
> Arnd doesn't like this and had suggestions in some other thread.
>
No, Arnd suggested doing it this way. And another platform's driver
was made to do this way.
>> + writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
>> +
>> + return 0;
>> +}
>> +
>> +static int mhu_startup(struct mbox_chan *chan)
>> +{
>> + struct mhu_link *mlink = chan->con_priv;
>> + u32 val;
>> + int ret;
>> +
>> + val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
>> + writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
>> +
>> + ret = request_irq(mlink->irq, mhu_rx_interrupt,
>> + IRQF_SHARED, "mhu_link", chan);
>
>
> Any reason we can't move this to probe and have {en,dis}able_irq here if
> needed. I has seen it was too heavy to have these especially when
> sending small packets.
>
I see you used to do memcpy in irq-handler
https://git.linaro.org/landing-teams/working/arm/kernel.git/blob/HEAD:/drivers/mailbox/arm_mhu.c
perhaps you were using your old driver?
If you use this new driver, and send packets so often that
request-release irq has effect, maybe should hold the mailbox
reference for lifetime. I remember suggesting you that already and I
remember you said that's how it was.
-Jassi
^ permalink raw reply [flat|nested] 34+ messages in thread[parent not found: <CABb+yY0qRSocL-ePosUzszAh4X6161ve8_qUq4VizbLWMAmMCQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-18 13:19 ` Jassi Brar
@ 2015-03-18 14:23 ` Sudeep Holla
-1 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 14:23 UTC (permalink / raw)
To: Jassi Brar, arnd-r2nGTMty4D4
Cc: Sudeep Holla, Vincent Yang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
andy.green-QSEj5FYQhm4dnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
arm-DgEjT+Ai2ygdnm+yROfE0A,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Tetsuya Nuriya,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Pawel Moll,
patches-QSEj5FYQhm4dnm+yROfE0A, olof-nZhT3qVonbNeoWH0uzbU5w,
Vincent Yang
On 18/03/15 13:19, Jassi Brar wrote:
> On Wed, Mar 18, 2015 at 3:55 PM, Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org> wrote:
>>
>>> +static int mhu_send_data(struct mbox_chan *chan, void *data)
>>> +{
>>> + struct mhu_link *mlink = chan->con_priv;
>>> + u32 *arg = data;
>>
>> Arnd doesn't like this and had suggestions in some other thread.
>>
> No, Arnd suggested doing it this way. And another platform's driver
> was made to do this way.
>
IIUC he suggested that it's better to add another interface/API
to pass fixed-length something like
inline int mbox_send_message_u32(struct mbox_chan *chan, u32 msg)
{
mbox_send_message(chan, &msg, sizeof(msg));
}
and add a length argument to the existing mbox_send_message like:
int mbox_send_message(struct mbox_chan *chan, void *mssg, int length)
Am I missing something here ?
>>> + writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int mhu_startup(struct mbox_chan *chan)
>>> +{
>>> + struct mhu_link *mlink = chan->con_priv;
>>> + u32 val;
>>> + int ret;
>>> +
>>> + val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
>>> + writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
>>> +
>>> + ret = request_irq(mlink->irq, mhu_rx_interrupt,
>>> + IRQF_SHARED, "mhu_link", chan);
>>
>>
>> Any reason we can't move this to probe and have {en,dis}able_irq here if
>> needed. I has seen it was too heavy to have these especially when
>> sending small packets.
>>
> I see you used to do memcpy in irq-handler
> https://git.linaro.org/landing-teams/working/arm/kernel.git/blob/HEAD:/drivers/mailbox/arm_mhu.c
> perhaps you were using your old driver?
>
That driver is too old and long abandoned. It mixes up the protocol
details and was written when mailbox f/w was still under discussion.
So you can forget that, it's out of scope of this discussion.
> If you use this new driver, and send packets so often that
> request-release irq has effect, maybe should hold the mailbox
> reference for lifetime. I remember suggesting you that already and I
> remember you said that's how it was.
>
Ah right, I keep getting confused that ops->startup is called from
mbox_send_message for no reason, sorry for the noise. However,
I found threaded_irq is much better for large packets.
Regards,
Sudeep
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-18 14:23 ` Sudeep Holla
0 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-18 14:23 UTC (permalink / raw)
To: linux-arm-kernel
On 18/03/15 13:19, Jassi Brar wrote:
> On Wed, Mar 18, 2015 at 3:55 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
>>
>>> +static int mhu_send_data(struct mbox_chan *chan, void *data)
>>> +{
>>> + struct mhu_link *mlink = chan->con_priv;
>>> + u32 *arg = data;
>>
>> Arnd doesn't like this and had suggestions in some other thread.
>>
> No, Arnd suggested doing it this way. And another platform's driver
> was made to do this way.
>
IIUC he suggested that it's better to add another interface/API
to pass fixed-length something like
inline int mbox_send_message_u32(struct mbox_chan *chan, u32 msg)
{
mbox_send_message(chan, &msg, sizeof(msg));
}
and add a length argument to the existing mbox_send_message like:
int mbox_send_message(struct mbox_chan *chan, void *mssg, int length)
Am I missing something here ?
>>> + writel_relaxed(*arg, mlink->tx_reg + INTR_SET_OFS);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int mhu_startup(struct mbox_chan *chan)
>>> +{
>>> + struct mhu_link *mlink = chan->con_priv;
>>> + u32 val;
>>> + int ret;
>>> +
>>> + val = readl_relaxed(mlink->tx_reg + INTR_STAT_OFS);
>>> + writel_relaxed(val, mlink->tx_reg + INTR_CLR_OFS);
>>> +
>>> + ret = request_irq(mlink->irq, mhu_rx_interrupt,
>>> + IRQF_SHARED, "mhu_link", chan);
>>
>>
>> Any reason we can't move this to probe and have {en,dis}able_irq here if
>> needed. I has seen it was too heavy to have these especially when
>> sending small packets.
>>
> I see you used to do memcpy in irq-handler
> https://git.linaro.org/landing-teams/working/arm/kernel.git/blob/HEAD:/drivers/mailbox/arm_mhu.c
> perhaps you were using your old driver?
>
That driver is too old and long abandoned. It mixes up the protocol
details and was written when mailbox f/w was still under discussion.
So you can forget that, it's out of scope of this discussion.
> If you use this new driver, and send packets so often that
> request-release irq has effect, maybe should hold the mailbox
> reference for lifetime. I remember suggesting you that already and I
> remember you said that's how it was.
>
Ah right, I keep getting confused that ops->startup is called from
mbox_send_message for no reason, sorry for the noise. However,
I found threaded_irq is much better for large packets.
Regards,
Sudeep
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-04 11:01 ` Vincent Yang
@ 2015-03-26 11:43 ` Sudeep Holla
-1 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-26 11:43 UTC (permalink / raw)
To: devicetree, linux-arm-kernel, jaswinder.singh
Cc: Mark Rutland, andy.green, linux, Pawel Moll, arnd,
ijc+devicetree, galak, robh+dt, Tetsuya Nuriya, arm, patches,
Vincent Yang, Sudeep Holla, olof, Vincent Yang
On 04/03/15 11:01, Vincent Yang wrote:
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> Signed-off-by: Andy Green <andy.green@linaro.org>
> Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
> ---
> .../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
> drivers/mailbox/Kconfig | 9 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> create mode 100644 drivers/mailbox/arm_mhu.c
>
> diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> new file mode 100644
> index 0000000..4971f03
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> @@ -0,0 +1,43 @@
> +ARM MHU Mailbox Driver
> +======================
> +
> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
> +3 independent channels/links to communicate with remote processor(s).
> + MHU links are hardwired on a platform. A link raises interrupt for any
> +received data. However, there is no specified way of knowing if the sent
> +data has been read by the remote. This driver assumes the sender polls
> +STAT register and the remote clears it after having read the data.
> +The last channel is specified to be a 'Secure' resource, hence can't be
> +used by Linux running NS.
> +
> +Mailbox Device Node:
> +====================
> +
> +Required properties:
> +--------------------
> +- compatible: Shall be "arm,mhu" & "arm,primecell"
> +- reg: Contains the mailbox register address range (base
> + address and length)
> +- #mbox-cells Shall be 1 - the index of the channel needed.
> +- interrupts: Contains the interrupt information corresponding to
> + each of the 3 links of MHU.
> +
I tried using this driver and found that AMBA driver expects apb_clk
without which probe fails. Though your example have it, it's not
explicit from the binding. Also AMBA binding expects the primecell id in
the binding.
Regards,
Sudeep
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-26 11:43 ` Sudeep Holla
0 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-26 11:43 UTC (permalink / raw)
To: linux-arm-kernel
On 04/03/15 11:01, Vincent Yang wrote:
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> Add driver for the ARM Primecell Message-Handling-Unit(MHU) controller.
>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> Signed-off-by: Andy Green <andy.green@linaro.org>
> Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
> ---
> .../devicetree/bindings/mailbox/arm-mhu.txt | 43 +++++
> drivers/mailbox/Kconfig | 9 +
> drivers/mailbox/Makefile | 2 +
> drivers/mailbox/arm_mhu.c | 195 +++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> create mode 100644 drivers/mailbox/arm_mhu.c
>
> diff --git a/Documentation/devicetree/bindings/mailbox/arm-mhu.txt b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> new file mode 100644
> index 0000000..4971f03
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/arm-mhu.txt
> @@ -0,0 +1,43 @@
> +ARM MHU Mailbox Driver
> +======================
> +
> +The ARM's Message-Handling-Unit (MHU) is a mailbox controller that has
> +3 independent channels/links to communicate with remote processor(s).
> + MHU links are hardwired on a platform. A link raises interrupt for any
> +received data. However, there is no specified way of knowing if the sent
> +data has been read by the remote. This driver assumes the sender polls
> +STAT register and the remote clears it after having read the data.
> +The last channel is specified to be a 'Secure' resource, hence can't be
> +used by Linux running NS.
> +
> +Mailbox Device Node:
> +====================
> +
> +Required properties:
> +--------------------
> +- compatible: Shall be "arm,mhu" & "arm,primecell"
> +- reg: Contains the mailbox register address range (base
> + address and length)
> +- #mbox-cells Shall be 1 - the index of the channel needed.
> +- interrupts: Contains the interrupt information corresponding to
> + each of the 3 links of MHU.
> +
I tried using this driver and found that AMBA driver expects apb_clk
without which probe fails. Though your example have it, it's not
explicit from the binding. Also AMBA binding expects the primecell id in
the binding.
Regards,
Sudeep
^ permalink raw reply [flat|nested] 34+ messages in thread
[parent not found: <5513F0D9.5080807-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-26 11:43 ` Sudeep Holla
@ 2015-03-26 11:49 ` Russell King - ARM Linux
-1 siblings, 0 replies; 34+ messages in thread
From: Russell King - ARM Linux @ 2015-03-26 11:49 UTC (permalink / raw)
To: Sudeep Holla
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Pawel Moll, Mark Rutland, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang, Tetsuya Nuriya
On Thu, Mar 26, 2015 at 11:43:21AM +0000, Sudeep Holla wrote:
> I tried using this driver and found that AMBA driver expects apb_clk
> without which probe fails. Though your example have it, it's not
> explicit from the binding. Also AMBA binding expects the primecell id in
> the binding.
That's optional:
Optional properties:
- arm,primecell-periphid : Value to override the h/w value with
It's only required when the hardware doesn't provide the correct value.
--
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-26 11:49 ` Russell King - ARM Linux
0 siblings, 0 replies; 34+ messages in thread
From: Russell King - ARM Linux @ 2015-03-26 11:49 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Mar 26, 2015 at 11:43:21AM +0000, Sudeep Holla wrote:
> I tried using this driver and found that AMBA driver expects apb_clk
> without which probe fails. Though your example have it, it's not
> explicit from the binding. Also AMBA binding expects the primecell id in
> the binding.
That's optional:
Optional properties:
- arm,primecell-periphid : Value to override the h/w value with
It's only required when the hardware doesn't provide the correct value.
--
FTTC broadband for 0.8mile line: currently at 10.5Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply [flat|nested] 34+ messages in thread
[parent not found: <20150326114955.GE8656-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>]
* Re: [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
2015-03-26 11:49 ` Russell King - ARM Linux
@ 2015-03-26 11:58 ` Sudeep Holla
-1 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-26 11:58 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Sudeep Holla, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Pawel Moll, Mark Rutland, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang, Tetsuya Nuriya
On 26/03/15 11:49, Russell King - ARM Linux wrote:
> On Thu, Mar 26, 2015 at 11:43:21AM +0000, Sudeep Holla wrote:
>> I tried using this driver and found that AMBA driver expects apb_clk
>> without which probe fails. Though your example have it, it's not
>> explicit from the binding. Also AMBA binding expects the primecell id in
>> the binding.
>
> That's optional:
>
> Optional properties:
>
> - arm,primecell-periphid : Value to override the h/w value with
>
> It's only required when the hardware doesn't provide the correct value.
>
Ah sorry my bad, I meant the compatible(somehow left this word at the
end of earlier email - it should have been" .. AMBA binding expects the
primecell id in the binding compatible")
- compatible : should be a specific name for the peripheral and
"arm,primecell". The specific name will match the ARM
engineering name for the logic block in the form: "arm,pl???"
So I wanted to make sure either we follow that here(unlikely as ARM is
not publishing this as standard primecell yet) or specify that it's
exception here.
Regards,
Sudeep
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v7 2/7] mailbox: arm_mhu: add driver for ARM MHU controller
@ 2015-03-26 11:58 ` Sudeep Holla
0 siblings, 0 replies; 34+ messages in thread
From: Sudeep Holla @ 2015-03-26 11:58 UTC (permalink / raw)
To: linux-arm-kernel
On 26/03/15 11:49, Russell King - ARM Linux wrote:
> On Thu, Mar 26, 2015 at 11:43:21AM +0000, Sudeep Holla wrote:
>> I tried using this driver and found that AMBA driver expects apb_clk
>> without which probe fails. Though your example have it, it's not
>> explicit from the binding. Also AMBA binding expects the primecell id in
>> the binding.
>
> That's optional:
>
> Optional properties:
>
> - arm,primecell-periphid : Value to override the h/w value with
>
> It's only required when the hardware doesn't provide the correct value.
>
Ah sorry my bad, I meant the compatible(somehow left this word at the
end of earlier email - it should have been" .. AMBA binding expects the
primecell id in the binding compatible")
- compatible : should be a specific name for the peripheral and
"arm,primecell". The specific name will match the ARM
engineering name for the logic block in the form: "arm,pl???"
So I wanted to make sure either we follow that here(unlikely as ARM is
not publishing this as standard primecell yet) or specify that it's
exception here.
Regards,
Sudeep
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v7 4/7] clk: Add clock driver for mb86s7x
2015-03-04 10:52 ` Vincent Yang
@ 2015-03-04 11:04 ` Vincent Yang
-1 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:04 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-QSEj5FYQhm4dnm+yROfE0A,
andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
Tetsuya Nuriya
From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
---
.../bindings/clock/fujitsu,mb86s70-crg11.txt | 26 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-mb86s7x.c | 386 +++++++++++++++++++++
3 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
create mode 100644 drivers/clk/clk-mb86s7x.c
diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
new file mode 100644
index 0000000..3323962
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
@@ -0,0 +1,26 @@
+Fujitsu CRG11 clock driver bindings
+-----------------------------------
+
+Required properties :
+- compatible : Shall contain "fujitsu,mb86s70-crg11"
+- #clock-cells : Shall be 3 {cntrlr domain port}
+
+The consumer specifies the desired clock pointing to its phandle.
+
+Example:
+
+ clock: crg11 {
+ compatible = "fujitsu,mb86s70-crg11";
+ #clock-cells = <3>;
+ };
+
+ mhu: mhu0@2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu";
+ reg = <0 0x2B1F0000 0x1000>;
+ interrupts = <0 36 4>, /* LP Non-Sec */
+ <0 35 4>, /* HP Non-Sec */
+ <0 37 4>; /* Secure */
+ clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
+ clock-names = "clk";
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d478ceb..1d35f3b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX77802) += clk-max77802.o
+obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
diff --git a/drivers/clk/clk-mb86s7x.c b/drivers/clk/clk-mb86s7x.c
new file mode 100644
index 0000000..f39c25a
--- /dev/null
+++ b/drivers/clk/clk-mb86s7x.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/cpu.h>
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/topology.h>
+#include <linux/mailbox_client.h>
+#include <linux/platform_device.h>
+
+#include <soc/mb86s7x/scb_mhu.h>
+
+#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
+#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
+
+struct mb86s7x_peri_clk {
+ u32 payload_size;
+ u32 cntrlr;
+ u32 domain;
+ u32 port;
+ u32 en;
+ u64 frequency;
+} __packed __aligned(4);
+
+struct hack_rate {
+ unsigned clk_id;
+ unsigned long rate;
+ int gated;
+};
+
+struct crg_clk {
+ struct clk_hw hw;
+ u8 cntrlr, domain, port;
+};
+
+static int crg_gate_control(struct clk_hw *hw, int en)
+{
+ struct crg_clk *crgclk = to_crg_clk(hw);
+ struct mb86s7x_peri_clk cmd;
+ int ret;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.cntrlr = crgclk->cntrlr;
+ cmd.domain = crgclk->domain;
+ cmd.port = crgclk->port;
+ cmd.en = en;
+
+ /* Port is UngatedCLK */
+ if (cmd.port == 8)
+ return en ? 0 : -EINVAL;
+
+ pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.en);
+
+ ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
+ &cmd, sizeof(cmd));
+ if (ret < 0) {
+ pr_err("%s:%d failed!\n", __func__, __LINE__);
+ return ret;
+ }
+
+ pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.en);
+
+ /* If the request was rejected */
+ if (cmd.en != en)
+ ret = -EINVAL;
+ else
+ ret = 0;
+
+ return ret;
+}
+
+static int crg_port_prepare(struct clk_hw *hw)
+{
+ return crg_gate_control(hw, 1);
+}
+
+static void crg_port_unprepare(struct clk_hw *hw)
+{
+ crg_gate_control(hw, 0);
+}
+
+static int
+crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
+{
+ struct crg_clk *crgclk = to_crg_clk(hw);
+ struct mb86s7x_peri_clk cmd;
+ int code, ret;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.cntrlr = crgclk->cntrlr;
+ cmd.domain = crgclk->domain;
+ cmd.port = crgclk->port;
+ cmd.frequency = *rate;
+
+ if (set) {
+ code = CMD_PERI_CLOCK_RATE_SET_REQ;
+ pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.frequency);
+ } else {
+ code = CMD_PERI_CLOCK_RATE_GET_REQ;
+ pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port);
+ }
+
+ ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
+ if (ret < 0) {
+ pr_err("%s:%d failed!\n", __func__, __LINE__);
+ return ret;
+ }
+
+ if (set)
+ pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.frequency);
+ else
+ pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.frequency);
+
+ *rate = cmd.frequency;
+ return 0;
+}
+
+static unsigned long
+crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ unsigned long rate;
+
+ crg_rate_control(hw, 0, &rate);
+
+ return rate;
+}
+
+static long
+crg_port_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *pr)
+{
+ return rate;
+}
+
+static int
+crg_port_set_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long parent_rate)
+{
+ return crg_rate_control(hw, 1, &rate);
+}
+
+const struct clk_ops crg_port_ops = {
+ .prepare = crg_port_prepare,
+ .unprepare = crg_port_unprepare,
+ .recalc_rate = crg_port_recalc_rate,
+ .round_rate = crg_port_round_rate,
+ .set_rate = crg_port_set_rate,
+};
+
+struct mb86s70_crg11 {
+ struct mutex lock; /* protects CLK populating and searching */
+};
+
+static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct mb86s70_crg11 *crg11 = data;
+ struct clk_init_data init;
+ u32 cntrlr, domain, port;
+ struct crg_clk *crgclk;
+ struct clk *clk;
+ char clkp[20];
+
+ if (clkspec->args_count != 3)
+ return ERR_PTR(-EINVAL);
+
+ cntrlr = clkspec->args[0];
+ domain = clkspec->args[1];
+ port = clkspec->args[2];
+
+ if (port > 7)
+ snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
+ else
+ snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
+
+ mutex_lock(&crg11->lock);
+
+ clk = __clk_lookup(clkp);
+ if (clk) {
+ mutex_unlock(&crg11->lock);
+ return clk;
+ }
+
+ crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
+ if (!crgclk) {
+ mutex_unlock(&crg11->lock);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = clkp;
+ init.num_parents = 0;
+ init.ops = &crg_port_ops;
+ init.flags = CLK_IS_ROOT;
+ crgclk->hw.init = &init;
+ crgclk->cntrlr = cntrlr;
+ crgclk->domain = domain;
+ crgclk->port = port;
+ clk = clk_register(NULL, &crgclk->hw);
+ if (IS_ERR(clk))
+ pr_err("%s:%d Error!\n", __func__, __LINE__);
+ else
+ pr_debug("Registered %s\n", clkp);
+
+ clk_register_clkdev(clk, clkp, NULL);
+ mutex_unlock(&crg11->lock);
+ return clk;
+}
+
+static void __init crg_port_init(struct device_node *node)
+{
+ struct mb86s70_crg11 *crg11;
+
+ crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
+ if (!crg11)
+ return;
+
+ mutex_init(&crg11->lock);
+
+ of_clk_add_provider(node, crg11_get, crg11);
+}
+CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
+
+struct cl_clk {
+ struct clk_hw hw;
+ int cluster;
+};
+
+struct mb86s7x_cpu_freq {
+ u32 payload_size;
+ u32 cluster_class;
+ u32 cluster_id;
+ u32 cpu_id;
+ u64 frequency;
+};
+
+static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
+{
+ struct cl_clk *clc = to_clc_clk(hw);
+ struct mb86s7x_cpu_freq cmd;
+ int code, ret;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.cluster_class = 0;
+ cmd.cluster_id = clc->cluster;
+ cmd.cpu_id = 0;
+ cmd.frequency = *rate;
+
+ if (get)
+ code = CMD_CPU_CLOCK_RATE_GET_REQ;
+ else
+ code = CMD_CPU_CLOCK_RATE_SET_REQ;
+
+ pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
+ __func__, __LINE__, cmd.cluster_class,
+ cmd.cluster_id, cmd.cpu_id, cmd.frequency);
+
+ ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
+ if (ret < 0) {
+ pr_err("%s:%d failed!\n", __func__, __LINE__);
+ return;
+ }
+
+ pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
+ __func__, __LINE__, cmd.cluster_class,
+ cmd.cluster_id, cmd.cpu_id, cmd.frequency);
+
+ *rate = cmd.frequency;
+}
+
+static unsigned long
+clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
+{
+ unsigned long rate;
+
+ mhu_cluster_rate(hw, &rate, 1);
+ return rate;
+}
+
+static long
+clc_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *unused)
+{
+ return rate;
+}
+
+static int
+clc_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long unused)
+{
+ unsigned long res = rate;
+
+ mhu_cluster_rate(hw, &res, 0);
+
+ return (res == rate) ? 0 : -EINVAL;
+}
+
+static struct clk_ops clk_clc_ops = {
+ .recalc_rate = clc_recalc_rate,
+ .round_rate = clc_round_rate,
+ .set_rate = clc_set_rate,
+};
+
+struct clk *mb86s7x_clclk_register(struct device *cpu_dev)
+{
+ struct clk_init_data init;
+ struct cl_clk *clc;
+
+ clc = kzalloc(sizeof(*clc), GFP_KERNEL);
+ if (!clc)
+ return ERR_PTR(-ENOMEM);
+
+ clc->hw.init = &init;
+ clc->cluster = topology_physical_package_id(cpu_dev->id);
+
+ init.name = dev_name(cpu_dev);
+ init.ops = &clk_clc_ops;
+ init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
+ init.num_parents = 0;
+
+ return devm_clk_register(cpu_dev, &clc->hw);
+}
+
+static int mb86s7x_clclk_of_init(void)
+{
+ int cpu, ret = -ENODEV;
+ struct device_node *np;
+ struct clk *clk;
+
+ np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
+ if (!np || !of_device_is_available(np))
+ goto exit;
+
+ for_each_possible_cpu(cpu) {
+ struct device *cpu_dev = get_cpu_device(cpu);
+
+ if (!cpu_dev) {
+ pr_err("failed to get cpu%d device\n", cpu);
+ continue;
+ }
+
+ clk = mb86s7x_clclk_register(cpu_dev);
+ if (IS_ERR(clk)) {
+ pr_err("failed to register cpu%d clock\n", cpu);
+ continue;
+ }
+ if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
+ pr_err("failed to register cpu%d clock lookup\n", cpu);
+ continue;
+ }
+ pr_debug("registered clk for %s\n", dev_name(cpu_dev));
+ }
+ ret = 0;
+
+ platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
+exit:
+ of_node_put(np);
+ return ret;
+}
+module_init(mb86s7x_clclk_of_init);
--
1.9.0
--
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v7 4/7] clk: Add clock driver for mb86s7x
@ 2015-03-04 11:04 ` Vincent Yang
0 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Jassi Brar <jaswinder.singh@linaro.org>
The CRG11 clock controller is managed by remote f/w.
This driver simply maps Linux CLK ops onto mailbox api.
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
---
.../bindings/clock/fujitsu,mb86s70-crg11.txt | 26 ++
drivers/clk/Makefile | 1 +
drivers/clk/clk-mb86s7x.c | 386 +++++++++++++++++++++
3 files changed, 413 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
create mode 100644 drivers/clk/clk-mb86s7x.c
diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
new file mode 100644
index 0000000..3323962
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
@@ -0,0 +1,26 @@
+Fujitsu CRG11 clock driver bindings
+-----------------------------------
+
+Required properties :
+- compatible : Shall contain "fujitsu,mb86s70-crg11"
+- #clock-cells : Shall be 3 {cntrlr domain port}
+
+The consumer specifies the desired clock pointing to its phandle.
+
+Example:
+
+ clock: crg11 {
+ compatible = "fujitsu,mb86s70-crg11";
+ #clock-cells = <3>;
+ };
+
+ mhu: mhu0 at 2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu";
+ reg = <0 0x2B1F0000 0x1000>;
+ interrupts = <0 36 4>, /* LP Non-Sec */
+ <0 35 4>, /* HP Non-Sec */
+ <0 37 4>; /* Secure */
+ clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
+ clock-names = "clk";
+ };
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index d478ceb..1d35f3b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_MAX77802) += clk-max77802.o
+obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
diff --git a/drivers/clk/clk-mb86s7x.c b/drivers/clk/clk-mb86s7x.c
new file mode 100644
index 0000000..f39c25a
--- /dev/null
+++ b/drivers/clk/clk-mb86s7x.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/cpu.h>
+#include <linux/clk-provider.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/topology.h>
+#include <linux/mailbox_client.h>
+#include <linux/platform_device.h>
+
+#include <soc/mb86s7x/scb_mhu.h>
+
+#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
+#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
+
+struct mb86s7x_peri_clk {
+ u32 payload_size;
+ u32 cntrlr;
+ u32 domain;
+ u32 port;
+ u32 en;
+ u64 frequency;
+} __packed __aligned(4);
+
+struct hack_rate {
+ unsigned clk_id;
+ unsigned long rate;
+ int gated;
+};
+
+struct crg_clk {
+ struct clk_hw hw;
+ u8 cntrlr, domain, port;
+};
+
+static int crg_gate_control(struct clk_hw *hw, int en)
+{
+ struct crg_clk *crgclk = to_crg_clk(hw);
+ struct mb86s7x_peri_clk cmd;
+ int ret;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.cntrlr = crgclk->cntrlr;
+ cmd.domain = crgclk->domain;
+ cmd.port = crgclk->port;
+ cmd.en = en;
+
+ /* Port is UngatedCLK */
+ if (cmd.port == 8)
+ return en ? 0 : -EINVAL;
+
+ pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.en);
+
+ ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
+ &cmd, sizeof(cmd));
+ if (ret < 0) {
+ pr_err("%s:%d failed!\n", __func__, __LINE__);
+ return ret;
+ }
+
+ pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.en);
+
+ /* If the request was rejected */
+ if (cmd.en != en)
+ ret = -EINVAL;
+ else
+ ret = 0;
+
+ return ret;
+}
+
+static int crg_port_prepare(struct clk_hw *hw)
+{
+ return crg_gate_control(hw, 1);
+}
+
+static void crg_port_unprepare(struct clk_hw *hw)
+{
+ crg_gate_control(hw, 0);
+}
+
+static int
+crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
+{
+ struct crg_clk *crgclk = to_crg_clk(hw);
+ struct mb86s7x_peri_clk cmd;
+ int code, ret;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.cntrlr = crgclk->cntrlr;
+ cmd.domain = crgclk->domain;
+ cmd.port = crgclk->port;
+ cmd.frequency = *rate;
+
+ if (set) {
+ code = CMD_PERI_CLOCK_RATE_SET_REQ;
+ pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.frequency);
+ } else {
+ code = CMD_PERI_CLOCK_RATE_GET_REQ;
+ pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port);
+ }
+
+ ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
+ if (ret < 0) {
+ pr_err("%s:%d failed!\n", __func__, __LINE__);
+ return ret;
+ }
+
+ if (set)
+ pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.frequency);
+ else
+ pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
+ __func__, __LINE__, cmd.cntrlr,
+ cmd.domain, cmd.port, cmd.frequency);
+
+ *rate = cmd.frequency;
+ return 0;
+}
+
+static unsigned long
+crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ unsigned long rate;
+
+ crg_rate_control(hw, 0, &rate);
+
+ return rate;
+}
+
+static long
+crg_port_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *pr)
+{
+ return rate;
+}
+
+static int
+crg_port_set_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long parent_rate)
+{
+ return crg_rate_control(hw, 1, &rate);
+}
+
+const struct clk_ops crg_port_ops = {
+ .prepare = crg_port_prepare,
+ .unprepare = crg_port_unprepare,
+ .recalc_rate = crg_port_recalc_rate,
+ .round_rate = crg_port_round_rate,
+ .set_rate = crg_port_set_rate,
+};
+
+struct mb86s70_crg11 {
+ struct mutex lock; /* protects CLK populating and searching */
+};
+
+static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
+{
+ struct mb86s70_crg11 *crg11 = data;
+ struct clk_init_data init;
+ u32 cntrlr, domain, port;
+ struct crg_clk *crgclk;
+ struct clk *clk;
+ char clkp[20];
+
+ if (clkspec->args_count != 3)
+ return ERR_PTR(-EINVAL);
+
+ cntrlr = clkspec->args[0];
+ domain = clkspec->args[1];
+ port = clkspec->args[2];
+
+ if (port > 7)
+ snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
+ else
+ snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
+
+ mutex_lock(&crg11->lock);
+
+ clk = __clk_lookup(clkp);
+ if (clk) {
+ mutex_unlock(&crg11->lock);
+ return clk;
+ }
+
+ crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
+ if (!crgclk) {
+ mutex_unlock(&crg11->lock);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ init.name = clkp;
+ init.num_parents = 0;
+ init.ops = &crg_port_ops;
+ init.flags = CLK_IS_ROOT;
+ crgclk->hw.init = &init;
+ crgclk->cntrlr = cntrlr;
+ crgclk->domain = domain;
+ crgclk->port = port;
+ clk = clk_register(NULL, &crgclk->hw);
+ if (IS_ERR(clk))
+ pr_err("%s:%d Error!\n", __func__, __LINE__);
+ else
+ pr_debug("Registered %s\n", clkp);
+
+ clk_register_clkdev(clk, clkp, NULL);
+ mutex_unlock(&crg11->lock);
+ return clk;
+}
+
+static void __init crg_port_init(struct device_node *node)
+{
+ struct mb86s70_crg11 *crg11;
+
+ crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
+ if (!crg11)
+ return;
+
+ mutex_init(&crg11->lock);
+
+ of_clk_add_provider(node, crg11_get, crg11);
+}
+CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
+
+struct cl_clk {
+ struct clk_hw hw;
+ int cluster;
+};
+
+struct mb86s7x_cpu_freq {
+ u32 payload_size;
+ u32 cluster_class;
+ u32 cluster_id;
+ u32 cpu_id;
+ u64 frequency;
+};
+
+static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
+{
+ struct cl_clk *clc = to_clc_clk(hw);
+ struct mb86s7x_cpu_freq cmd;
+ int code, ret;
+
+ cmd.payload_size = sizeof(cmd);
+ cmd.cluster_class = 0;
+ cmd.cluster_id = clc->cluster;
+ cmd.cpu_id = 0;
+ cmd.frequency = *rate;
+
+ if (get)
+ code = CMD_CPU_CLOCK_RATE_GET_REQ;
+ else
+ code = CMD_CPU_CLOCK_RATE_SET_REQ;
+
+ pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
+ __func__, __LINE__, cmd.cluster_class,
+ cmd.cluster_id, cmd.cpu_id, cmd.frequency);
+
+ ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
+ if (ret < 0) {
+ pr_err("%s:%d failed!\n", __func__, __LINE__);
+ return;
+ }
+
+ pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
+ __func__, __LINE__, cmd.cluster_class,
+ cmd.cluster_id, cmd.cpu_id, cmd.frequency);
+
+ *rate = cmd.frequency;
+}
+
+static unsigned long
+clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
+{
+ unsigned long rate;
+
+ mhu_cluster_rate(hw, &rate, 1);
+ return rate;
+}
+
+static long
+clc_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *unused)
+{
+ return rate;
+}
+
+static int
+clc_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long unused)
+{
+ unsigned long res = rate;
+
+ mhu_cluster_rate(hw, &res, 0);
+
+ return (res == rate) ? 0 : -EINVAL;
+}
+
+static struct clk_ops clk_clc_ops = {
+ .recalc_rate = clc_recalc_rate,
+ .round_rate = clc_round_rate,
+ .set_rate = clc_set_rate,
+};
+
+struct clk *mb86s7x_clclk_register(struct device *cpu_dev)
+{
+ struct clk_init_data init;
+ struct cl_clk *clc;
+
+ clc = kzalloc(sizeof(*clc), GFP_KERNEL);
+ if (!clc)
+ return ERR_PTR(-ENOMEM);
+
+ clc->hw.init = &init;
+ clc->cluster = topology_physical_package_id(cpu_dev->id);
+
+ init.name = dev_name(cpu_dev);
+ init.ops = &clk_clc_ops;
+ init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
+ init.num_parents = 0;
+
+ return devm_clk_register(cpu_dev, &clc->hw);
+}
+
+static int mb86s7x_clclk_of_init(void)
+{
+ int cpu, ret = -ENODEV;
+ struct device_node *np;
+ struct clk *clk;
+
+ np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
+ if (!np || !of_device_is_available(np))
+ goto exit;
+
+ for_each_possible_cpu(cpu) {
+ struct device *cpu_dev = get_cpu_device(cpu);
+
+ if (!cpu_dev) {
+ pr_err("failed to get cpu%d device\n", cpu);
+ continue;
+ }
+
+ clk = mb86s7x_clclk_register(cpu_dev);
+ if (IS_ERR(clk)) {
+ pr_err("failed to register cpu%d clock\n", cpu);
+ continue;
+ }
+ if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
+ pr_err("failed to register cpu%d clock lookup\n", cpu);
+ continue;
+ }
+ pr_debug("registered clk for %s\n", dev_name(cpu_dev));
+ }
+ ret = 0;
+
+ platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
+exit:
+ of_node_put(np);
+ return ret;
+}
+module_init(mb86s7x_clclk_of_init);
--
1.9.0
^ permalink raw reply related [flat|nested] 34+ messages in thread[parent not found: <1425467043-30733-1-git-send-email-vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>]
* Re: [PATCH v7 4/7] clk: Add clock driver for mb86s7x
2015-03-04 11:04 ` Vincent Yang
@ 2015-04-10 20:52 ` Michael Turquette
-1 siblings, 0 replies; 34+ messages in thread
From: Michael Turquette @ 2015-04-10 20:52 UTC (permalink / raw)
To: Vincent Yang, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, linux-lFZ/pmaqli7XmaaqVzeoHQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
Tetsuya Nuriya
Quoting Vincent Yang (2015-03-04 03:04:03)
> From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> The CRG11 clock controller is managed by remote f/w.
> This driver simply maps Linux CLK ops onto mailbox api.
>
> Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Patch looks OK to me. We might to replace that __clk_lookup in crg11_get
with clk_get or something else like it someday if I ever get around to
removing __clk_lookup.
Applied.
Regards,
Mike
> ---
> .../bindings/clock/fujitsu,mb86s70-crg11.txt | 26 ++
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-mb86s7x.c | 386 +++++++++++++++++++++
> 3 files changed, 413 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
> create mode 100644 drivers/clk/clk-mb86s7x.c
>
> diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
> new file mode 100644
> index 0000000..3323962
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
> @@ -0,0 +1,26 @@
> +Fujitsu CRG11 clock driver bindings
> +-----------------------------------
> +
> +Required properties :
> +- compatible : Shall contain "fujitsu,mb86s70-crg11"
> +- #clock-cells : Shall be 3 {cntrlr domain port}
> +
> +The consumer specifies the desired clock pointing to its phandle.
> +
> +Example:
> +
> + clock: crg11 {
> + compatible = "fujitsu,mb86s70-crg11";
> + #clock-cells = <3>;
> + };
> +
> + mhu: mhu0@2b1f0000 {
> + #mbox-cells = <1>;
> + compatible = "arm,mhu";
> + reg = <0 0x2B1F0000 0x1000>;
> + interrupts = <0 36 4>, /* LP Non-Sec */
> + <0 35 4>, /* HP Non-Sec */
> + <0 37 4>; /* Secure */
> + clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
> + clock-names = "clk";
> + };
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index d478ceb..1d35f3b 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
> obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o
> obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
> obj-$(CONFIG_COMMON_CLK_MAX77802) += clk-max77802.o
> +obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
> obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
> obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
> obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
> diff --git a/drivers/clk/clk-mb86s7x.c b/drivers/clk/clk-mb86s7x.c
> new file mode 100644
> index 0000000..f39c25a
> --- /dev/null
> +++ b/drivers/clk/clk-mb86s7x.c
> @@ -0,0 +1,386 @@
> +/*
> + * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
> + * Copyright (C) 2015 Linaro Ltd.
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/cpu.h>
> +#include <linux/clk-provider.h>
> +#include <linux/spinlock.h>
> +#include <linux/module.h>
> +#include <linux/topology.h>
> +#include <linux/mailbox_client.h>
> +#include <linux/platform_device.h>
> +
> +#include <soc/mb86s7x/scb_mhu.h>
> +
> +#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
> +#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
> +
> +struct mb86s7x_peri_clk {
> + u32 payload_size;
> + u32 cntrlr;
> + u32 domain;
> + u32 port;
> + u32 en;
> + u64 frequency;
> +} __packed __aligned(4);
> +
> +struct hack_rate {
> + unsigned clk_id;
> + unsigned long rate;
> + int gated;
> +};
> +
> +struct crg_clk {
> + struct clk_hw hw;
> + u8 cntrlr, domain, port;
> +};
> +
> +static int crg_gate_control(struct clk_hw *hw, int en)
> +{
> + struct crg_clk *crgclk = to_crg_clk(hw);
> + struct mb86s7x_peri_clk cmd;
> + int ret;
> +
> + cmd.payload_size = sizeof(cmd);
> + cmd.cntrlr = crgclk->cntrlr;
> + cmd.domain = crgclk->domain;
> + cmd.port = crgclk->port;
> + cmd.en = en;
> +
> + /* Port is UngatedCLK */
> + if (cmd.port == 8)
> + return en ? 0 : -EINVAL;
> +
> + pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.en);
> +
> + ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
> + &cmd, sizeof(cmd));
> + if (ret < 0) {
> + pr_err("%s:%d failed!\n", __func__, __LINE__);
> + return ret;
> + }
> +
> + pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.en);
> +
> + /* If the request was rejected */
> + if (cmd.en != en)
> + ret = -EINVAL;
> + else
> + ret = 0;
> +
> + return ret;
> +}
> +
> +static int crg_port_prepare(struct clk_hw *hw)
> +{
> + return crg_gate_control(hw, 1);
> +}
> +
> +static void crg_port_unprepare(struct clk_hw *hw)
> +{
> + crg_gate_control(hw, 0);
> +}
> +
> +static int
> +crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
> +{
> + struct crg_clk *crgclk = to_crg_clk(hw);
> + struct mb86s7x_peri_clk cmd;
> + int code, ret;
> +
> + cmd.payload_size = sizeof(cmd);
> + cmd.cntrlr = crgclk->cntrlr;
> + cmd.domain = crgclk->domain;
> + cmd.port = crgclk->port;
> + cmd.frequency = *rate;
> +
> + if (set) {
> + code = CMD_PERI_CLOCK_RATE_SET_REQ;
> + pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.frequency);
> + } else {
> + code = CMD_PERI_CLOCK_RATE_GET_REQ;
> + pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port);
> + }
> +
> + ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
> + if (ret < 0) {
> + pr_err("%s:%d failed!\n", __func__, __LINE__);
> + return ret;
> + }
> +
> + if (set)
> + pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.frequency);
> + else
> + pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.frequency);
> +
> + *rate = cmd.frequency;
> + return 0;
> +}
> +
> +static unsigned long
> +crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + unsigned long rate;
> +
> + crg_rate_control(hw, 0, &rate);
> +
> + return rate;
> +}
> +
> +static long
> +crg_port_round_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long *pr)
> +{
> + return rate;
> +}
> +
> +static int
> +crg_port_set_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long parent_rate)
> +{
> + return crg_rate_control(hw, 1, &rate);
> +}
> +
> +const struct clk_ops crg_port_ops = {
> + .prepare = crg_port_prepare,
> + .unprepare = crg_port_unprepare,
> + .recalc_rate = crg_port_recalc_rate,
> + .round_rate = crg_port_round_rate,
> + .set_rate = crg_port_set_rate,
> +};
> +
> +struct mb86s70_crg11 {
> + struct mutex lock; /* protects CLK populating and searching */
> +};
> +
> +static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct mb86s70_crg11 *crg11 = data;
> + struct clk_init_data init;
> + u32 cntrlr, domain, port;
> + struct crg_clk *crgclk;
> + struct clk *clk;
> + char clkp[20];
> +
> + if (clkspec->args_count != 3)
> + return ERR_PTR(-EINVAL);
> +
> + cntrlr = clkspec->args[0];
> + domain = clkspec->args[1];
> + port = clkspec->args[2];
> +
> + if (port > 7)
> + snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
> + else
> + snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
> +
> + mutex_lock(&crg11->lock);
> +
> + clk = __clk_lookup(clkp);
> + if (clk) {
> + mutex_unlock(&crg11->lock);
> + return clk;
> + }
> +
> + crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
> + if (!crgclk) {
> + mutex_unlock(&crg11->lock);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + init.name = clkp;
> + init.num_parents = 0;
> + init.ops = &crg_port_ops;
> + init.flags = CLK_IS_ROOT;
> + crgclk->hw.init = &init;
> + crgclk->cntrlr = cntrlr;
> + crgclk->domain = domain;
> + crgclk->port = port;
> + clk = clk_register(NULL, &crgclk->hw);
> + if (IS_ERR(clk))
> + pr_err("%s:%d Error!\n", __func__, __LINE__);
> + else
> + pr_debug("Registered %s\n", clkp);
> +
> + clk_register_clkdev(clk, clkp, NULL);
> + mutex_unlock(&crg11->lock);
> + return clk;
> +}
> +
> +static void __init crg_port_init(struct device_node *node)
> +{
> + struct mb86s70_crg11 *crg11;
> +
> + crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
> + if (!crg11)
> + return;
> +
> + mutex_init(&crg11->lock);
> +
> + of_clk_add_provider(node, crg11_get, crg11);
> +}
> +CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
> +
> +struct cl_clk {
> + struct clk_hw hw;
> + int cluster;
> +};
> +
> +struct mb86s7x_cpu_freq {
> + u32 payload_size;
> + u32 cluster_class;
> + u32 cluster_id;
> + u32 cpu_id;
> + u64 frequency;
> +};
> +
> +static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
> +{
> + struct cl_clk *clc = to_clc_clk(hw);
> + struct mb86s7x_cpu_freq cmd;
> + int code, ret;
> +
> + cmd.payload_size = sizeof(cmd);
> + cmd.cluster_class = 0;
> + cmd.cluster_id = clc->cluster;
> + cmd.cpu_id = 0;
> + cmd.frequency = *rate;
> +
> + if (get)
> + code = CMD_CPU_CLOCK_RATE_GET_REQ;
> + else
> + code = CMD_CPU_CLOCK_RATE_SET_REQ;
> +
> + pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
> + __func__, __LINE__, cmd.cluster_class,
> + cmd.cluster_id, cmd.cpu_id, cmd.frequency);
> +
> + ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
> + if (ret < 0) {
> + pr_err("%s:%d failed!\n", __func__, __LINE__);
> + return;
> + }
> +
> + pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
> + __func__, __LINE__, cmd.cluster_class,
> + cmd.cluster_id, cmd.cpu_id, cmd.frequency);
> +
> + *rate = cmd.frequency;
> +}
> +
> +static unsigned long
> +clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
> +{
> + unsigned long rate;
> +
> + mhu_cluster_rate(hw, &rate, 1);
> + return rate;
> +}
> +
> +static long
> +clc_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *unused)
> +{
> + return rate;
> +}
> +
> +static int
> +clc_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long unused)
> +{
> + unsigned long res = rate;
> +
> + mhu_cluster_rate(hw, &res, 0);
> +
> + return (res == rate) ? 0 : -EINVAL;
> +}
> +
> +static struct clk_ops clk_clc_ops = {
> + .recalc_rate = clc_recalc_rate,
> + .round_rate = clc_round_rate,
> + .set_rate = clc_set_rate,
> +};
> +
> +struct clk *mb86s7x_clclk_register(struct device *cpu_dev)
> +{
> + struct clk_init_data init;
> + struct cl_clk *clc;
> +
> + clc = kzalloc(sizeof(*clc), GFP_KERNEL);
> + if (!clc)
> + return ERR_PTR(-ENOMEM);
> +
> + clc->hw.init = &init;
> + clc->cluster = topology_physical_package_id(cpu_dev->id);
> +
> + init.name = dev_name(cpu_dev);
> + init.ops = &clk_clc_ops;
> + init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
> + init.num_parents = 0;
> +
> + return devm_clk_register(cpu_dev, &clc->hw);
> +}
> +
> +static int mb86s7x_clclk_of_init(void)
> +{
> + int cpu, ret = -ENODEV;
> + struct device_node *np;
> + struct clk *clk;
> +
> + np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
> + if (!np || !of_device_is_available(np))
> + goto exit;
> +
> + for_each_possible_cpu(cpu) {
> + struct device *cpu_dev = get_cpu_device(cpu);
> +
> + if (!cpu_dev) {
> + pr_err("failed to get cpu%d device\n", cpu);
> + continue;
> + }
> +
> + clk = mb86s7x_clclk_register(cpu_dev);
> + if (IS_ERR(clk)) {
> + pr_err("failed to register cpu%d clock\n", cpu);
> + continue;
> + }
> + if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
> + pr_err("failed to register cpu%d clock lookup\n", cpu);
> + continue;
> + }
> + pr_debug("registered clk for %s\n", dev_name(cpu_dev));
> + }
> + ret = 0;
> +
> + platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
> +exit:
> + of_node_put(np);
> + return ret;
> +}
> +module_init(mb86s7x_clclk_of_init);
> --
> 1.9.0
>
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^ permalink raw reply [flat|nested] 34+ messages in thread* [PATCH v7 4/7] clk: Add clock driver for mb86s7x
@ 2015-04-10 20:52 ` Michael Turquette
0 siblings, 0 replies; 34+ messages in thread
From: Michael Turquette @ 2015-04-10 20:52 UTC (permalink / raw)
To: linux-arm-kernel
Quoting Vincent Yang (2015-03-04 03:04:03)
> From: Jassi Brar <jaswinder.singh@linaro.org>
>
> The CRG11 clock controller is managed by remote f/w.
> This driver simply maps Linux CLK ops onto mailbox api.
>
> Signed-off-by: Andy Green <andy.green@linaro.org>
> Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
> Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
Patch looks OK to me. We might to replace that __clk_lookup in crg11_get
with clk_get or something else like it someday if I ever get around to
removing __clk_lookup.
Applied.
Regards,
Mike
> ---
> .../bindings/clock/fujitsu,mb86s70-crg11.txt | 26 ++
> drivers/clk/Makefile | 1 +
> drivers/clk/clk-mb86s7x.c | 386 +++++++++++++++++++++
> 3 files changed, 413 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
> create mode 100644 drivers/clk/clk-mb86s7x.c
>
> diff --git a/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
> new file mode 100644
> index 0000000..3323962
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/fujitsu,mb86s70-crg11.txt
> @@ -0,0 +1,26 @@
> +Fujitsu CRG11 clock driver bindings
> +-----------------------------------
> +
> +Required properties :
> +- compatible : Shall contain "fujitsu,mb86s70-crg11"
> +- #clock-cells : Shall be 3 {cntrlr domain port}
> +
> +The consumer specifies the desired clock pointing to its phandle.
> +
> +Example:
> +
> + clock: crg11 {
> + compatible = "fujitsu,mb86s70-crg11";
> + #clock-cells = <3>;
> + };
> +
> + mhu: mhu0 at 2b1f0000 {
> + #mbox-cells = <1>;
> + compatible = "arm,mhu";
> + reg = <0 0x2B1F0000 0x1000>;
> + interrupts = <0 36 4>, /* LP Non-Sec */
> + <0 35 4>, /* HP Non-Sec */
> + <0 37 4>; /* Secure */
> + clocks = <&clock 0 2 1>; /* Cntrlr:0 Domain:2 Port:1 */
> + clock-names = "clk";
> + };
> diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
> index d478ceb..1d35f3b 100644
> --- a/drivers/clk/Makefile
> +++ b/drivers/clk/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
> obj-$(CONFIG_COMMON_CLK_MAX_GEN) += clk-max-gen.o
> obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
> obj-$(CONFIG_COMMON_CLK_MAX77802) += clk-max77802.o
> +obj-$(CONFIG_ARCH_MB86S7X) += clk-mb86s7x.o
> obj-$(CONFIG_ARCH_MOXART) += clk-moxart.o
> obj-$(CONFIG_ARCH_NOMADIK) += clk-nomadik.o
> obj-$(CONFIG_ARCH_NSPIRE) += clk-nspire.o
> diff --git a/drivers/clk/clk-mb86s7x.c b/drivers/clk/clk-mb86s7x.c
> new file mode 100644
> index 0000000..f39c25a
> --- /dev/null
> +++ b/drivers/clk/clk-mb86s7x.c
> @@ -0,0 +1,386 @@
> +/*
> + * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
> + * Copyright (C) 2015 Linaro Ltd.
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, version 2 of the License.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clkdev.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/cpu.h>
> +#include <linux/clk-provider.h>
> +#include <linux/spinlock.h>
> +#include <linux/module.h>
> +#include <linux/topology.h>
> +#include <linux/mailbox_client.h>
> +#include <linux/platform_device.h>
> +
> +#include <soc/mb86s7x/scb_mhu.h>
> +
> +#define to_crg_clk(p) container_of(p, struct crg_clk, hw)
> +#define to_clc_clk(p) container_of(p, struct cl_clk, hw)
> +
> +struct mb86s7x_peri_clk {
> + u32 payload_size;
> + u32 cntrlr;
> + u32 domain;
> + u32 port;
> + u32 en;
> + u64 frequency;
> +} __packed __aligned(4);
> +
> +struct hack_rate {
> + unsigned clk_id;
> + unsigned long rate;
> + int gated;
> +};
> +
> +struct crg_clk {
> + struct clk_hw hw;
> + u8 cntrlr, domain, port;
> +};
> +
> +static int crg_gate_control(struct clk_hw *hw, int en)
> +{
> + struct crg_clk *crgclk = to_crg_clk(hw);
> + struct mb86s7x_peri_clk cmd;
> + int ret;
> +
> + cmd.payload_size = sizeof(cmd);
> + cmd.cntrlr = crgclk->cntrlr;
> + cmd.domain = crgclk->domain;
> + cmd.port = crgclk->port;
> + cmd.en = en;
> +
> + /* Port is UngatedCLK */
> + if (cmd.port == 8)
> + return en ? 0 : -EINVAL;
> +
> + pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u En-%u}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.en);
> +
> + ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
> + &cmd, sizeof(cmd));
> + if (ret < 0) {
> + pr_err("%s:%d failed!\n", __func__, __LINE__);
> + return ret;
> + }
> +
> + pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u En-%u}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.en);
> +
> + /* If the request was rejected */
> + if (cmd.en != en)
> + ret = -EINVAL;
> + else
> + ret = 0;
> +
> + return ret;
> +}
> +
> +static int crg_port_prepare(struct clk_hw *hw)
> +{
> + return crg_gate_control(hw, 1);
> +}
> +
> +static void crg_port_unprepare(struct clk_hw *hw)
> +{
> + crg_gate_control(hw, 0);
> +}
> +
> +static int
> +crg_rate_control(struct clk_hw *hw, int set, unsigned long *rate)
> +{
> + struct crg_clk *crgclk = to_crg_clk(hw);
> + struct mb86s7x_peri_clk cmd;
> + int code, ret;
> +
> + cmd.payload_size = sizeof(cmd);
> + cmd.cntrlr = crgclk->cntrlr;
> + cmd.domain = crgclk->domain;
> + cmd.port = crgclk->port;
> + cmd.frequency = *rate;
> +
> + if (set) {
> + code = CMD_PERI_CLOCK_RATE_SET_REQ;
> + pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.frequency);
> + } else {
> + code = CMD_PERI_CLOCK_RATE_GET_REQ;
> + pr_debug("%s:%d CMD Cntrlr-%u Dom-%u Port-%u Rate-GET}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port);
> + }
> +
> + ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
> + if (ret < 0) {
> + pr_err("%s:%d failed!\n", __func__, __LINE__);
> + return ret;
> + }
> +
> + if (set)
> + pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-SET %lluHz}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.frequency);
> + else
> + pr_debug("%s:%d REP Cntrlr-%u Dom-%u Port-%u Rate-GOT %lluHz}\n",
> + __func__, __LINE__, cmd.cntrlr,
> + cmd.domain, cmd.port, cmd.frequency);
> +
> + *rate = cmd.frequency;
> + return 0;
> +}
> +
> +static unsigned long
> +crg_port_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
> +{
> + unsigned long rate;
> +
> + crg_rate_control(hw, 0, &rate);
> +
> + return rate;
> +}
> +
> +static long
> +crg_port_round_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long *pr)
> +{
> + return rate;
> +}
> +
> +static int
> +crg_port_set_rate(struct clk_hw *hw,
> + unsigned long rate, unsigned long parent_rate)
> +{
> + return crg_rate_control(hw, 1, &rate);
> +}
> +
> +const struct clk_ops crg_port_ops = {
> + .prepare = crg_port_prepare,
> + .unprepare = crg_port_unprepare,
> + .recalc_rate = crg_port_recalc_rate,
> + .round_rate = crg_port_round_rate,
> + .set_rate = crg_port_set_rate,
> +};
> +
> +struct mb86s70_crg11 {
> + struct mutex lock; /* protects CLK populating and searching */
> +};
> +
> +static struct clk *crg11_get(struct of_phandle_args *clkspec, void *data)
> +{
> + struct mb86s70_crg11 *crg11 = data;
> + struct clk_init_data init;
> + u32 cntrlr, domain, port;
> + struct crg_clk *crgclk;
> + struct clk *clk;
> + char clkp[20];
> +
> + if (clkspec->args_count != 3)
> + return ERR_PTR(-EINVAL);
> +
> + cntrlr = clkspec->args[0];
> + domain = clkspec->args[1];
> + port = clkspec->args[2];
> +
> + if (port > 7)
> + snprintf(clkp, 20, "UngatedCLK%d_%X", cntrlr, domain);
> + else
> + snprintf(clkp, 20, "CLK%d_%X_%d", cntrlr, domain, port);
> +
> + mutex_lock(&crg11->lock);
> +
> + clk = __clk_lookup(clkp);
> + if (clk) {
> + mutex_unlock(&crg11->lock);
> + return clk;
> + }
> +
> + crgclk = kzalloc(sizeof(*crgclk), GFP_KERNEL);
> + if (!crgclk) {
> + mutex_unlock(&crg11->lock);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + init.name = clkp;
> + init.num_parents = 0;
> + init.ops = &crg_port_ops;
> + init.flags = CLK_IS_ROOT;
> + crgclk->hw.init = &init;
> + crgclk->cntrlr = cntrlr;
> + crgclk->domain = domain;
> + crgclk->port = port;
> + clk = clk_register(NULL, &crgclk->hw);
> + if (IS_ERR(clk))
> + pr_err("%s:%d Error!\n", __func__, __LINE__);
> + else
> + pr_debug("Registered %s\n", clkp);
> +
> + clk_register_clkdev(clk, clkp, NULL);
> + mutex_unlock(&crg11->lock);
> + return clk;
> +}
> +
> +static void __init crg_port_init(struct device_node *node)
> +{
> + struct mb86s70_crg11 *crg11;
> +
> + crg11 = kzalloc(sizeof(*crg11), GFP_KERNEL);
> + if (!crg11)
> + return;
> +
> + mutex_init(&crg11->lock);
> +
> + of_clk_add_provider(node, crg11_get, crg11);
> +}
> +CLK_OF_DECLARE(crg11_gate, "fujitsu,mb86s70-crg11", crg_port_init);
> +
> +struct cl_clk {
> + struct clk_hw hw;
> + int cluster;
> +};
> +
> +struct mb86s7x_cpu_freq {
> + u32 payload_size;
> + u32 cluster_class;
> + u32 cluster_id;
> + u32 cpu_id;
> + u64 frequency;
> +};
> +
> +static void mhu_cluster_rate(struct clk_hw *hw, unsigned long *rate, int get)
> +{
> + struct cl_clk *clc = to_clc_clk(hw);
> + struct mb86s7x_cpu_freq cmd;
> + int code, ret;
> +
> + cmd.payload_size = sizeof(cmd);
> + cmd.cluster_class = 0;
> + cmd.cluster_id = clc->cluster;
> + cmd.cpu_id = 0;
> + cmd.frequency = *rate;
> +
> + if (get)
> + code = CMD_CPU_CLOCK_RATE_GET_REQ;
> + else
> + code = CMD_CPU_CLOCK_RATE_SET_REQ;
> +
> + pr_debug("%s:%d CMD Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
> + __func__, __LINE__, cmd.cluster_class,
> + cmd.cluster_id, cmd.cpu_id, cmd.frequency);
> +
> + ret = mb86s7x_send_packet(code, &cmd, sizeof(cmd));
> + if (ret < 0) {
> + pr_err("%s:%d failed!\n", __func__, __LINE__);
> + return;
> + }
> +
> + pr_debug("%s:%d REP Cl_Class-%u CL_ID-%u CPU_ID-%u Freq-%llu}\n",
> + __func__, __LINE__, cmd.cluster_class,
> + cmd.cluster_id, cmd.cpu_id, cmd.frequency);
> +
> + *rate = cmd.frequency;
> +}
> +
> +static unsigned long
> +clc_recalc_rate(struct clk_hw *hw, unsigned long unused)
> +{
> + unsigned long rate;
> +
> + mhu_cluster_rate(hw, &rate, 1);
> + return rate;
> +}
> +
> +static long
> +clc_round_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long *unused)
> +{
> + return rate;
> +}
> +
> +static int
> +clc_set_rate(struct clk_hw *hw, unsigned long rate,
> + unsigned long unused)
> +{
> + unsigned long res = rate;
> +
> + mhu_cluster_rate(hw, &res, 0);
> +
> + return (res == rate) ? 0 : -EINVAL;
> +}
> +
> +static struct clk_ops clk_clc_ops = {
> + .recalc_rate = clc_recalc_rate,
> + .round_rate = clc_round_rate,
> + .set_rate = clc_set_rate,
> +};
> +
> +struct clk *mb86s7x_clclk_register(struct device *cpu_dev)
> +{
> + struct clk_init_data init;
> + struct cl_clk *clc;
> +
> + clc = kzalloc(sizeof(*clc), GFP_KERNEL);
> + if (!clc)
> + return ERR_PTR(-ENOMEM);
> +
> + clc->hw.init = &init;
> + clc->cluster = topology_physical_package_id(cpu_dev->id);
> +
> + init.name = dev_name(cpu_dev);
> + init.ops = &clk_clc_ops;
> + init.flags = CLK_IS_ROOT | CLK_GET_RATE_NOCACHE;
> + init.num_parents = 0;
> +
> + return devm_clk_register(cpu_dev, &clc->hw);
> +}
> +
> +static int mb86s7x_clclk_of_init(void)
> +{
> + int cpu, ret = -ENODEV;
> + struct device_node *np;
> + struct clk *clk;
> +
> + np = of_find_compatible_node(NULL, NULL, "fujitsu,mb86s70-scb-1.0");
> + if (!np || !of_device_is_available(np))
> + goto exit;
> +
> + for_each_possible_cpu(cpu) {
> + struct device *cpu_dev = get_cpu_device(cpu);
> +
> + if (!cpu_dev) {
> + pr_err("failed to get cpu%d device\n", cpu);
> + continue;
> + }
> +
> + clk = mb86s7x_clclk_register(cpu_dev);
> + if (IS_ERR(clk)) {
> + pr_err("failed to register cpu%d clock\n", cpu);
> + continue;
> + }
> + if (clk_register_clkdev(clk, NULL, dev_name(cpu_dev))) {
> + pr_err("failed to register cpu%d clock lookup\n", cpu);
> + continue;
> + }
> + pr_debug("registered clk for %s\n", dev_name(cpu_dev));
> + }
> + ret = 0;
> +
> + platform_device_register_simple("arm-bL-cpufreq-dt", -1, NULL, 0);
> +exit:
> + of_node_put(np);
> + return ret;
> +}
> +module_init(mb86s7x_clclk_of_init);
> --
> 1.9.0
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* [PATCH v7 5/7] dt: mb86s7x: add dt files for MB86S7x evbs
2015-03-04 10:52 ` Vincent Yang
@ 2015-03-04 11:05 ` Vincent Yang
-1 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:05 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A,
Sneeker.Yeh-l16TxrwUIHTQFUHtdCDX3A, Vincent Yang, Tetsuya Nuriya
From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Add dt files for MB86S7x evb.
Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/mb86s70.dtsi | 91 +++++++++++++++++++++++++
arch/arm/boot/dts/mb86s70eb.dts | 57 ++++++++++++++++
arch/arm/boot/dts/mb86s73.dtsi | 63 ++++++++++++++++++
arch/arm/boot/dts/mb86s73eb.dts | 44 +++++++++++++
arch/arm/boot/dts/mb86s7x.dtsi | 142 ++++++++++++++++++++++++++++++++++++++++
6 files changed, 400 insertions(+)
create mode 100644 arch/arm/boot/dts/mb86s70.dtsi
create mode 100644 arch/arm/boot/dts/mb86s70eb.dts
create mode 100644 arch/arm/boot/dts/mb86s73.dtsi
create mode 100644 arch/arm/boot/dts/mb86s73eb.dts
create mode 100644 arch/arm/boot/dts/mb86s7x.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b..aa0e6d4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -197,6 +197,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += \
ea3250.dtb phy3250.dtb
+dtb-$(CONFIG_ARCH_MB86S7X) += \
+ mb86s70eb.dtb \
+ mb86s73eb.dtb
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_ARCH_MMP) += \
diff --git a/arch/arm/boot/dts/mb86s70.dtsi b/arch/arm/boot/dts/mb86s70.dtsi
new file mode 100644
index 0000000..057e135
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s70.dtsi
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+#include "mb86s7x.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ cci-control-port = <&cci_control4>;
+ clock-frequency = <1200000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ cci-control-port = <&cci_control4>;
+ clock-frequency = <1200000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+ };
+
+ cci@2c090000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x2c090000 0x1000>;
+ ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+ cci_control3: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control4: slave-if@5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu@9000 {
+ compatible = "arm,cci-400-pmu";
+ reg = <0x9000 0x5000>;
+ interrupts = <0 77 4>,
+ <0 77 4>,
+ <0 77 4>,
+ <0 77 4>,
+ <0 77 4>;
+ };
+ };
+};
+
+&archtimer {
+ status = "disabled";
+};
+
+&pmua7 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/mb86s70eb.dts b/arch/arm/boot/dts/mb86s70eb.dts
new file mode 100644
index 0000000..1e51ce0
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s70eb.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+/dts-v1/;
+
+#include "mb86s70.dtsi"
+
+/ {
+ model = "Fujitsu MB86S70 EVB";
+ compatible = "fujitsu,mb86s70-evb";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0x80000000>, <0x08 0x80000000 0x80000000>;
+
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw";
+ linux,initrd-start = <0xc0000000>;
+ linux,initrd-end = <0xc0800000>;
+ };
+
+ vccq_sdhci1: regulator@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHCI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 7 0>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+};
+
+&sdhci0 {
+ status = "ok";
+ bus-width = <8>;
+};
+
+&sdhci1 {
+ status = "ok";
+ bus-width = <4>;
+ vqmmc-supply = <&vccq_sdhci1>;
+};
diff --git a/arch/arm/boot/dts/mb86s73.dtsi b/arch/arm/boot/dts/mb86s73.dtsi
new file mode 100644
index 0000000..3c9d8d0
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s73.dtsi
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+#include "mb86s7x.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu1: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+ };
+
+ cci@2c090000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x2c090000 0x1000>;
+ ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+ cci_control3: slave-if@4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+ };
+
+ hcd21_ehci: f_usb20ho_echi@34240000 {
+ compatible = "fujitsu,f_usb20ho", "generic-ehci";
+ reg = <0 0x34240000 0x1000>;
+ interrupts = <0 419 0x4>;
+ clocks = <&clock 2 2 4>, <&clock 2 4 5>, <&clock 4 0 0>;
+ };
+
+ hcd21_ohci: f_usb20ho_ochi@34240000 {
+ compatible = "fujitsu,f_usb20ho", "generic-ohci";
+ reg = <0 0x34241000 0x1000>;
+ interrupts = <0 419 0x4>;
+ clocks = <&clock 2 2 4>, <&clock 2 4 5>, <&clock 4 0 0>;
+ };
+};
diff --git a/arch/arm/boot/dts/mb86s73eb.dts b/arch/arm/boot/dts/mb86s73eb.dts
new file mode 100644
index 0000000..43f2fc6
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s73eb.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+/dts-v1/;
+
+#include "mb86s73.dtsi"
+
+/ {
+ model = "Fujitsu MB86S73 EVB";
+ compatible = "fujitsu,mb86s73-evb";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw";
+ linux,initrd-start = <0xc0000000>;
+ linux,initrd-end = <0xc0800000>;
+ };
+};
+
+&sdhci0 {
+ status = "ok";
+ bus-width = <8>;
+};
+
+&sdhci1 {
+ status = "ok";
+ bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/mb86s7x.dtsi b/arch/arm/boot/dts/mb86s7x.dtsi
new file mode 100644
index 0000000..4731af1
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s7x.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ pmua7: pmu_a7 {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <0 18 4>,
+ <0 22 4>;
+ };
+
+ clock: crg11 {
+ compatible = "fujitsu,mb86s70-crg11";
+ #clock-cells = <3>;
+ };
+
+ timer0: timer@31080000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0 0x31080000 0x1000>;
+ interrupts = <0 324 4>,
+ <0 325 4>;
+ clocks = <&clock 0 6 8>;
+ clock-names = "apb_pclk";
+ };
+
+ archtimer: archtimer {
+ compatible = "arm,armv7-timer";
+ clock-frequency = <125000000>;
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0x2c001000 0x1000>,
+ <0 0x2c002000 0x1000>,
+ <0 0x2c004000 0x2000>,
+ <0 0x2c006000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ mhu: mailbox@2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu", "arm,primecell";
+ reg = <0 0x2b1f0000 0x1000>;
+ interrupts = <0 36 4>, /* LP Non-Sec */
+ <0 35 4>, /* HP Non-Sec */
+ <0 37 4>; /* Secure */
+ clocks = <&clock 0 6 8>;
+ clock-names = "apb_pclk";
+ };
+
+ mhu_client: scb@2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0x4000>; /* SHM for IPC */
+ mboxes = <&mhu 1>;
+ };
+
+ uart0: serial@31040000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0 0x31040000 0x100>;
+ interrupts = <0 320 0x4>;
+ clock-frequency = <62500000>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&clock 0 2 1>;
+ clock-names = "sclk";
+ };
+
+ uart1: serial@31050000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0 0x31050000 0x100>;
+ interrupts = <0 321 0x4>;
+ clock-frequency = <62500000>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&clock 0 2 1>;
+ clock-names = "sclk";
+ };
+
+ uart2: serial@31060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0 0x31060000 0x100>;
+ interrupts = <0 322 0x4>;
+ clock-frequency = <62500000>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&clock 0 2 1>;
+ clock-names = "sclk";
+ };
+
+ gpio0: gpio@31000000 {
+ compatible = "fujitsu,mb86s70-gpio";
+ reg = <0 0x31000000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clock 0 2 1>;
+ };
+
+ gpio1: gpio@31010000 {
+ compatible = "fujitsu,mb86s70-gpio";
+ reg = <0 0x31010000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clock 0 2 1>;
+ };
+
+ sdhci0: mmc@300c0000 {
+ status = "disabled";
+ compatible = "fujitsu,mb86s70-sdhci-3.0";
+ reg = <0 0x300c0000 0x1000>;
+ interrupts = <0 164 0x4>,
+ <0 165 0x4>;
+ clocks = <&clock 0 0xc 0>, <&clock 0 0xb 0>;
+ clock-names = "iface", "core";
+ };
+
+ sdhci1: mmc@36600000 {
+ status = "disabled";
+ compatible = "fujitsu,mb86s70-sdhci-3.0";
+ reg = <0 0x36600000 0x1000>;
+ interrupts = <0 172 0x4>,
+ <0 173 0x4>;
+ clocks = <&clock 2 0xc 0>, <&clock 2 0xd 0>;
+ clock-names = "iface", "core";
+ };
+};
--
1.9.0
--
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^ permalink raw reply related [flat|nested] 34+ messages in thread* [PATCH v7 5/7] dt: mb86s7x: add dt files for MB86S7x evbs
@ 2015-03-04 11:05 ` Vincent Yang
0 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:05 UTC (permalink / raw)
To: linux-arm-kernel
From: Jassi Brar <jaswinder.singh@linaro.org>
Add dt files for MB86S7x evb.
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
---
arch/arm/boot/dts/Makefile | 3 +
arch/arm/boot/dts/mb86s70.dtsi | 91 +++++++++++++++++++++++++
arch/arm/boot/dts/mb86s70eb.dts | 57 ++++++++++++++++
arch/arm/boot/dts/mb86s73.dtsi | 63 ++++++++++++++++++
arch/arm/boot/dts/mb86s73eb.dts | 44 +++++++++++++
arch/arm/boot/dts/mb86s7x.dtsi | 142 ++++++++++++++++++++++++++++++++++++++++
6 files changed, 400 insertions(+)
create mode 100644 arch/arm/boot/dts/mb86s70.dtsi
create mode 100644 arch/arm/boot/dts/mb86s70eb.dts
create mode 100644 arch/arm/boot/dts/mb86s73.dtsi
create mode 100644 arch/arm/boot/dts/mb86s73eb.dts
create mode 100644 arch/arm/boot/dts/mb86s7x.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a1c776b..aa0e6d4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -197,6 +197,9 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += \
kirkwood-ts419-6282.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += \
ea3250.dtb phy3250.dtb
+dtb-$(CONFIG_ARCH_MB86S7X) += \
+ mb86s70eb.dtb \
+ mb86s73eb.dtb
dtb-$(CONFIG_MACH_MESON6) += \
meson6-atv1200.dtb
dtb-$(CONFIG_ARCH_MMP) += \
diff --git a/arch/arm/boot/dts/mb86s70.dtsi b/arch/arm/boot/dts/mb86s70.dtsi
new file mode 100644
index 0000000..057e135
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s70.dtsi
@@ -0,0 +1,91 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+#include "mb86s7x.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ cci-control-port = <&cci_control4>;
+ clock-frequency = <1200000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ cci-control-port = <&cci_control4>;
+ clock-frequency = <1200000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu2: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu3: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+ };
+
+ cci at 2c090000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x2c090000 0x1000>;
+ ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+ cci_control3: slave-if at 4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+
+ cci_control4: slave-if at 5000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+
+ pmu at 9000 {
+ compatible = "arm,cci-400-pmu";
+ reg = <0x9000 0x5000>;
+ interrupts = <0 77 4>,
+ <0 77 4>,
+ <0 77 4>,
+ <0 77 4>,
+ <0 77 4>;
+ };
+ };
+};
+
+&archtimer {
+ status = "disabled";
+};
+
+&pmua7 {
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/mb86s70eb.dts b/arch/arm/boot/dts/mb86s70eb.dts
new file mode 100644
index 0000000..1e51ce0
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s70eb.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+/dts-v1/;
+
+#include "mb86s70.dtsi"
+
+/ {
+ model = "Fujitsu MB86S70 EVB";
+ compatible = "fujitsu,mb86s70-evb";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0x80000000>, <0x08 0x80000000 0x80000000>;
+
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw";
+ linux,initrd-start = <0xc0000000>;
+ linux,initrd-end = <0xc0800000>;
+ };
+
+ vccq_sdhci1: regulator at 0 {
+ compatible = "regulator-gpio";
+ regulator-name = "SDHCI1 VccQ";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&gpio0 7 0>;
+ gpios-states = <1>;
+ states = <3300000 1
+ 1800000 0>;
+ };
+};
+
+&sdhci0 {
+ status = "ok";
+ bus-width = <8>;
+};
+
+&sdhci1 {
+ status = "ok";
+ bus-width = <4>;
+ vqmmc-supply = <&vccq_sdhci1>;
+};
diff --git a/arch/arm/boot/dts/mb86s73.dtsi b/arch/arm/boot/dts/mb86s73.dtsi
new file mode 100644
index 0000000..3c9d8d0
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s73.dtsi
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+#include "mb86s7x.dtsi"
+
+/ {
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+
+ cpu1: cpu at 101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ cci-control-port = <&cci_control3>;
+ clock-frequency = <800000000>;
+ clock-latency = <100000>;
+ };
+ };
+
+ cci at 2c090000 {
+ compatible = "arm,cci-400";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0x2c090000 0x1000>;
+ ranges = <0x0 0x0 0x2c090000 0x10000>;
+
+ cci_control3: slave-if at 4000 {
+ compatible = "arm,cci-400-ctrl-if";
+ interface-type = "ace";
+ reg = <0x4000 0x1000>;
+ };
+ };
+
+ hcd21_ehci: f_usb20ho_echi at 34240000 {
+ compatible = "fujitsu,f_usb20ho", "generic-ehci";
+ reg = <0 0x34240000 0x1000>;
+ interrupts = <0 419 0x4>;
+ clocks = <&clock 2 2 4>, <&clock 2 4 5>, <&clock 4 0 0>;
+ };
+
+ hcd21_ohci: f_usb20ho_ochi at 34240000 {
+ compatible = "fujitsu,f_usb20ho", "generic-ohci";
+ reg = <0 0x34241000 0x1000>;
+ interrupts = <0 419 0x4>;
+ clocks = <&clock 2 2 4>, <&clock 2 4 5>, <&clock 4 0 0>;
+ };
+};
diff --git a/arch/arm/boot/dts/mb86s73eb.dts b/arch/arm/boot/dts/mb86s73eb.dts
new file mode 100644
index 0000000..43f2fc6
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s73eb.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+/dts-v1/;
+
+#include "mb86s73.dtsi"
+
+/ {
+ model = "Fujitsu MB86S73 EVB";
+ compatible = "fujitsu,mb86s73-evb";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0 0x80000000 0x80000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyS0,115200 root=/dev/mmcblk1p1 rootfstype=ext4 rootwait rw";
+ linux,initrd-start = <0xc0000000>;
+ linux,initrd-end = <0xc0800000>;
+ };
+};
+
+&sdhci0 {
+ status = "ok";
+ bus-width = <8>;
+};
+
+&sdhci1 {
+ status = "ok";
+ bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/mb86s7x.dtsi b/arch/arm/boot/dts/mb86s7x.dtsi
new file mode 100644
index 0000000..4731af1
--- /dev/null
+++ b/arch/arm/boot/dts/mb86s7x.dtsi
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2013-2015 FUJITSU SEMICONDUCTOR LIMITED
+ * Copyright (C) 2015 Linaro Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 2 of the License.
+ */
+
+#include "skeleton.dtsi"
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ pmua7: pmu_a7 {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <0 18 4>,
+ <0 22 4>;
+ };
+
+ clock: crg11 {
+ compatible = "fujitsu,mb86s70-crg11";
+ #clock-cells = <3>;
+ };
+
+ timer0: timer at 31080000 {
+ compatible = "arm,sp804", "arm,primecell";
+ reg = <0 0x31080000 0x1000>;
+ interrupts = <0 324 4>,
+ <0 325 4>;
+ clocks = <&clock 0 6 8>;
+ clock-names = "apb_pclk";
+ };
+
+ archtimer: archtimer {
+ compatible = "arm,armv7-timer";
+ clock-frequency = <125000000>;
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ gic: interrupt-controller at 2c001000 {
+ compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0 0x2c001000 0x1000>,
+ <0 0x2c002000 0x1000>,
+ <0 0x2c004000 0x2000>,
+ <0 0x2c006000 0x2000>;
+ interrupts = <1 9 0xf04>;
+ };
+
+ mhu: mailbox at 2b1f0000 {
+ #mbox-cells = <1>;
+ compatible = "arm,mhu", "arm,primecell";
+ reg = <0 0x2b1f0000 0x1000>;
+ interrupts = <0 36 4>, /* LP Non-Sec */
+ <0 35 4>, /* HP Non-Sec */
+ <0 37 4>; /* Secure */
+ clocks = <&clock 0 6 8>;
+ clock-names = "apb_pclk";
+ };
+
+ mhu_client: scb at 2e000000 {
+ compatible = "fujitsu,mb86s70-scb-1.0";
+ reg = <0 0x2e000000 0x4000>; /* SHM for IPC */
+ mboxes = <&mhu 1>;
+ };
+
+ uart0: serial at 31040000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0 0x31040000 0x100>;
+ interrupts = <0 320 0x4>;
+ clock-frequency = <62500000>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&clock 0 2 1>;
+ clock-names = "sclk";
+ };
+
+ uart1: serial at 31050000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0 0x31050000 0x100>;
+ interrupts = <0 321 0x4>;
+ clock-frequency = <62500000>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&clock 0 2 1>;
+ clock-names = "sclk";
+ };
+
+ uart2: serial at 31060000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0 0x31060000 0x100>;
+ interrupts = <0 322 0x4>;
+ clock-frequency = <62500000>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ clocks = <&clock 0 2 1>;
+ clock-names = "sclk";
+ };
+
+ gpio0: gpio at 31000000 {
+ compatible = "fujitsu,mb86s70-gpio";
+ reg = <0 0x31000000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clock 0 2 1>;
+ };
+
+ gpio1: gpio at 31010000 {
+ compatible = "fujitsu,mb86s70-gpio";
+ reg = <0 0x31010000 0x10000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ clocks = <&clock 0 2 1>;
+ };
+
+ sdhci0: mmc at 300c0000 {
+ status = "disabled";
+ compatible = "fujitsu,mb86s70-sdhci-3.0";
+ reg = <0 0x300c0000 0x1000>;
+ interrupts = <0 164 0x4>,
+ <0 165 0x4>;
+ clocks = <&clock 0 0xc 0>, <&clock 0 0xb 0>;
+ clock-names = "iface", "core";
+ };
+
+ sdhci1: mmc at 36600000 {
+ status = "disabled";
+ compatible = "fujitsu,mb86s70-sdhci-3.0";
+ reg = <0 0x36600000 0x1000>;
+ interrupts = <0 172 0x4>,
+ <0 173 0x4>;
+ clocks = <&clock 2 0xc 0>, <&clock 2 0xd 0>;
+ clock-names = "iface", "core";
+ };
+};
--
1.9.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v7 6/7] of: add Fujitsu vendor prefix
2015-03-04 10:52 ` Vincent Yang
@ 2015-03-04 11:07 ` Vincent Yang
-1 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:07 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: arnd-r2nGTMty4D4, olof-nZhT3qVonbNeoWH0uzbU5w,
arm-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, andy.green-QSEj5FYQhm4dnm+yROfE0A,
patches-QSEj5FYQhm4dnm+yROfE0A,
jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A, Vincent Yang,
Tetsuya Nuriya
From: Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Add 'fujitsu' as the vendor prefix for Fujitsu Semiconductor Ltd.
Signed-off-by: Andy Green <andy.green-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Vincent Yang <vincent.yang-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 389ca13..00d6e71 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -70,6 +70,7 @@ excito Excito
fcs Fairchild Semiconductor
firefly Firefly
fsl Freescale Semiconductor
+fujitsu Fujitsu Semiconductor Ltd.
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
--
1.9.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [PATCH v7 6/7] of: add Fujitsu vendor prefix
@ 2015-03-04 11:07 ` Vincent Yang
0 siblings, 0 replies; 34+ messages in thread
From: Vincent Yang @ 2015-03-04 11:07 UTC (permalink / raw)
To: linux-arm-kernel
From: Jassi Brar <jaswinder.singh@linaro.org>
Add 'fujitsu' as the vendor prefix for Fujitsu Semiconductor Ltd.
Signed-off-by: Andy Green <andy.green@linaro.org>
Signed-off-by: Vincent Yang <vincent.yang@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Tetsuya Nuriya <nuriya.tetsuya@socionext.com>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 389ca13..00d6e71 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -70,6 +70,7 @@ excito Excito
fcs Fairchild Semiconductor
firefly Firefly
fsl Freescale Semiconductor
+fujitsu Fujitsu Semiconductor Ltd.
GEFanuc GE Fanuc Intelligent Platforms Embedded Systems, Inc.
gef GE Fanuc Intelligent Platforms Embedded Systems, Inc.
geniatech Geniatech, Inc.
--
1.9.0
^ permalink raw reply related [flat|nested] 34+ messages in thread