* [PATCH u-boot-marvell 1/1] clk: armada-37xx-periph: fix DDR PHY clock divider values
@ 2020-04-14 22:59 Marek Behún
2020-04-15 6:37 ` Stefan Roese
0 siblings, 1 reply; 2+ messages in thread
From: Marek Behún @ 2020-04-14 22:59 UTC (permalink / raw)
To: u-boot
Register value table for DDR PHY clock divider are wrong. They should be
0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current
values do not make sense, since 2 cannot be achieved, because the
register is only 1 bit long (mask is set to 1).
This fixes clk dump reporting DDR PHY clock rate differently from Linux.
Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
---
drivers/clk/mvebu/armada-37xx-periph.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
index 068e48ea04..855f979b4f 100644
--- a/drivers/clk/mvebu/armada-37xx-periph.c
+++ b/drivers/clk/mvebu/armada-37xx-periph.c
@@ -89,8 +89,8 @@ static const struct clk_div_table div_table1[] = {
};
static const struct clk_div_table div_table2[] = {
- { 2, 1 },
- { 4, 2 },
+ { 2, 0 },
+ { 4, 1 },
{ 0, 0 },
};
--
2.24.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH u-boot-marvell 1/1] clk: armada-37xx-periph: fix DDR PHY clock divider values
2020-04-14 22:59 [PATCH u-boot-marvell 1/1] clk: armada-37xx-periph: fix DDR PHY clock divider values Marek Behún
@ 2020-04-15 6:37 ` Stefan Roese
0 siblings, 0 replies; 2+ messages in thread
From: Stefan Roese @ 2020-04-15 6:37 UTC (permalink / raw)
To: u-boot
On 15.04.20 00:59, Marek Beh?n wrote:
> Register value table for DDR PHY clock divider are wrong. They should be
> 0 or 1 for divide-by-2 or divide-by-4, respectively. Not 1 or 2. Current
> values do not make sense, since 2 cannot be achieved, because the
> register is only 1 bit long (mask is set to 1).
>
> This fixes clk dump reporting DDR PHY clock rate differently from Linux.
>
> Signed-off-by: Marek Beh?n <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Thanks,
Stefan
> ---
> drivers/clk/mvebu/armada-37xx-periph.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/mvebu/armada-37xx-periph.c b/drivers/clk/mvebu/armada-37xx-periph.c
> index 068e48ea04..855f979b4f 100644
> --- a/drivers/clk/mvebu/armada-37xx-periph.c
> +++ b/drivers/clk/mvebu/armada-37xx-periph.c
> @@ -89,8 +89,8 @@ static const struct clk_div_table div_table1[] = {
> };
>
> static const struct clk_div_table div_table2[] = {
> - { 2, 1 },
> - { 4, 2 },
> + { 2, 0 },
> + { 4, 1 },
> { 0, 0 },
> };
>
>
Viele Gr??e,
Stefan
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr at denx.de
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2020-04-14 22:59 [PATCH u-boot-marvell 1/1] clk: armada-37xx-periph: fix DDR PHY clock divider values Marek Behún
2020-04-15 6:37 ` Stefan Roese
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