[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Keerthy]

This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
crystal is not enabled at power up. Instead the CPU falls back to using
an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
20MHz on boards so far (which gives an emulated frequency of 32.786KHz)

Modelling the same in device tree.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
Errata Document: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf
Errata number: i856

Tested the debugfs clock tree nodes on DRA7-EVM.

Changes in v2:

Added missing Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

 arch/arm/boot/dts/dra7xx-clocks.dtsi | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bede..7f1f892 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -98,12 +98,20 @@
 		clock-frequency = <32768>;
 	};
 
-	sys_32k_ck: sys_32k_ck {
+	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
 
+	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin1>;
+		clock-mult = <1>;
+		clock-div = <610>;
+	};
+
 	virt_12000000_ck: virt_12000000_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -2146,4 +2154,12 @@
 		ti,bit-shift = <0>;
 		reg = <0x558>;
 	};
+
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x6c4>;
+	};
 };
-- 
1.9.1

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Keerthy]

This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
crystal is not enabled at power up. Instead the CPU falls back to using
an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
20MHz on boards so far (which gives an emulated frequency of 32.786KHz)

Modelling the same in device tree.

Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
---
Errata Document: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf
Errata number: i856

Tested the debugfs clock tree nodes on DRA7-EVM.

Changes in v2:

Added missing Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

 arch/arm/boot/dts/dra7xx-clocks.dtsi | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bede..7f1f892 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -98,12 +98,20 @@
 		clock-frequency = <32768>;
 	};
 
-	sys_32k_ck: sys_32k_ck {
+	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
 
+	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin1>;
+		clock-mult = <1>;
+		clock-div = <610>;
+	};
+
 	virt_12000000_ck: virt_12000000_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -2146,4 +2154,12 @@
 		ti,bit-shift = <0>;
 		reg = <0x558>;
 	};
+
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x6c4>;
+	};
 };
-- 
1.9.1

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Keerthy]

This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
crystal is not enabled at power up. Instead the CPU falls back to using
an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
20MHz on boards so far (which gives an emulated frequency of 32.786KHz)

Modelling the same in device tree.

Signed-off-by: Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org>
Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>
---
Errata Document: http://www.ti.com/lit/er/sprz429h/sprz429h.pdf
Errata number: i856

Tested the debugfs clock tree nodes on DRA7-EVM.

Changes in v2:

Added missing Signed-off-by: Lokesh Vutla <lokeshvutla-l0cyMroinI0@public.gmane.org>

 arch/arm/boot/dts/dra7xx-clocks.dtsi | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 357bede..7f1f892 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -98,12 +98,20 @@
 		clock-frequency = <32768>;
 	};
 
-	sys_32k_ck: sys_32k_ck {
+	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
 		clock-frequency = <32768>;
 	};
 
+	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
+		#clock-cells = <0>;
+		compatible = "fixed-factor-clock";
+		clocks = <&sys_clkin1>;
+		clock-mult = <1>;
+		clock-div = <610>;
+	};
+
 	virt_12000000_ck: virt_12000000_ck {
 		#clock-cells = <0>;
 		compatible = "fixed-clock";
@@ -2146,4 +2154,12 @@
 		ti,bit-shift = <0>;
 		reg = <0x558>;
 	};
+
+	sys_32k_ck: sys_32k_ck {
+		#clock-cells = <0>;
+		compatible = "ti,mux-clock";
+		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
+		ti,bit-shift = <8>;
+		reg = <0x6c4>;
+	};
 };
-- 
1.9.1

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Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> crystal is not enabled at power up. Instead the CPU falls back to using
> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)

Thanks applying into omap-for-v4.6/fixes.

Tony

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> crystal is not enabled at power up. Instead the CPU falls back to using
> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)

Thanks applying into omap-for-v4.6/fixes.

Tony

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org> [160314 05:04]:
> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> crystal is not enabled at power up. Instead the CPU falls back to using
> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)

Thanks applying into omap-for-v4.6/fixes.

Tony
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Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
> > This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> > crystal is not enabled at power up. Instead the CPU falls back to using
> > an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> > 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> 
> Thanks applying into omap-for-v4.6/fixes.

Actually let's wait a review from Tero on this one, not sure
about the pseudo clock naming here. So dropping for now.

Regards,

Tony

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
> > This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> > crystal is not enabled at power up. Instead the CPU falls back to using
> > an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> > 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> 
> Thanks applying into omap-for-v4.6/fixes.

Actually let's wait a review from Tero on this one, not sure
about the pseudo clock naming here. So dropping for now.

Regards,

Tony

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [160330 14:19]:
> * Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org> [160314 05:04]:
> > This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
> > crystal is not enabled at power up. Instead the CPU falls back to using
> > an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
> > 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> 
> Thanks applying into omap-for-v4.6/fixes.

Actually let's wait a review from Tero on this one, not sure
about the pseudo clock naming here. So dropping for now.

Regards,

Tony
--
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Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tero Kristo]

On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>
>> Thanks applying into omap-for-v4.6/fixes.
>
> Actually let's wait a review from Tero on this one, not sure
> about the pseudo clock naming here. So dropping for now.

The patch is fine for me, I didn't comment anything before as I thought 
you already applied it.

Acked-by: Tero Kristo <t-kristo@ti.com>

>
> Regards,
>
> Tony
>

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tero Kristo]

On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>
>> Thanks applying into omap-for-v4.6/fixes.
>
> Actually let's wait a review from Tero on this one, not sure
> about the pseudo clock naming here. So dropping for now.

The patch is fine for me, I didn't comment anything before as I thought 
you already applied it.

Acked-by: Tero Kristo <t-kristo@ti.com>

>
> Regards,
>
> Tony
>

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tero Kristo]

On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is usually
>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>
>> Thanks applying into omap-for-v4.6/fixes.
>
> Actually let's wait a review from Tero on this one, not sure
> about the pseudo clock naming here. So dropping for now.

The patch is fine for me, I didn't comment anything before as I thought 
you already applied it.

Acked-by: Tero Kristo <t-kristo@ti.com>

>
> Regards,
>
> Tony
>

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Keerthy]

On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>> external
>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>> usually
>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>
>>> Thanks applying into omap-for-v4.6/fixes.
>>
>> Actually let's wait a review from Tero on this one, not sure
>> about the pseudo clock naming here. So dropping for now.
>
> The patch is fine for me, I didn't comment anything before as I thought
> you already applied it.
>
> Acked-by: Tero Kristo <t-kristo@ti.com>

Thanks Tero.

>
>>
>> Regards,
>>
>> Tony
>>
>

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Keerthy]

On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>> external
>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>> usually
>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>
>>> Thanks applying into omap-for-v4.6/fixes.
>>
>> Actually let's wait a review from Tero on this one, not sure
>> about the pseudo clock naming here. So dropping for now.
>
> The patch is fine for me, I didn't comment anything before as I thought
> you already applied it.
>
> Acked-by: Tero Kristo <t-kristo@ti.com>

Thanks Tero.

>
>>
>> Regards,
>>
>> Tony
>>
>

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Keerthy]

On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>> external
>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>> usually
>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>
>>> Thanks applying into omap-for-v4.6/fixes.
>>
>> Actually let's wait a review from Tero on this one, not sure
>> about the pseudo clock naming here. So dropping for now.
>
> The patch is fine for me, I didn't comment anything before as I thought
> you already applied it.
>
> Acked-by: Tero Kristo <t-kristo@ti.com>

Thanks Tero.

>
>>
>> Regards,
>>
>> Tony
>>
>

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Keerthy <a0393675@ti.com> [160331 02:26]:
> 
> 
> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> >>* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> >>>* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> >>>>external
> >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> >>>>usually
> >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> >>>
> >>>Thanks applying into omap-for-v4.6/fixes.
> >>
> >>Actually let's wait a review from Tero on this one, not sure
> >>about the pseudo clock naming here. So dropping for now.
> >
> >The patch is fine for me, I didn't comment anything before as I thought
> >you already applied it.
> >
> >Acked-by: Tero Kristo <t-kristo@ti.com>
> 
> Thanks Tero.

OK applying with Tero's ack.

Tony

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Keerthy <a0393675@ti.com> [160331 02:26]:
> 
> 
> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> >>* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> >>>* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> >>>>external
> >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> >>>>usually
> >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> >>>
> >>>Thanks applying into omap-for-v4.6/fixes.
> >>
> >>Actually let's wait a review from Tero on this one, not sure
> >>about the pseudo clock naming here. So dropping for now.
> >
> >The patch is fine for me, I didn't comment anything before as I thought
> >you already applied it.
> >
> >Acked-by: Tero Kristo <t-kristo@ti.com>
> 
> Thanks Tero.

OK applying with Tero's ack.

Tony

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Keerthy <a0393675-l0cyMroinI0@public.gmane.org> [160331 02:26]:
> 
> 
> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> >>* Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [160330 14:19]:
> >>>* Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org> [160314 05:04]:
> >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> >>>>external
> >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> >>>>usually
> >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> >>>
> >>>Thanks applying into omap-for-v4.6/fixes.
> >>
> >>Actually let's wait a review from Tero on this one, not sure
> >>about the pseudo clock naming here. So dropping for now.
> >
> >The patch is fine for me, I didn't comment anything before as I thought
> >you already applied it.
> >
> >Acked-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
> 
> Thanks Tero.

OK applying with Tero's ack.

Tony
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Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

Hi,

* Tony Lindgren <tony@atomide.com> [160331 10:04]:
> * Keerthy <a0393675@ti.com> [160331 02:26]:
> > 
> > 
> > On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> > >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> > >>* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> > >>>* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> > >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> > >>>>external
> > >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> > >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> > >>>>usually
> > >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> > >>>
> > >>>Thanks applying into omap-for-v4.6/fixes.
> > >>
> > >>Actually let's wait a review from Tero on this one, not sure
> > >>about the pseudo clock naming here. So dropping for now.
> > >
> > >The patch is fine for me, I didn't comment anything before as I thought
> > >you already applied it.
> > >
> > >Acked-by: Tero Kristo <t-kristo@ti.com>
> > 
> > Thanks Tero.
> 
> OK applying with Tero's ack.

I'm dropping this again as it introduces new warnings with make dtbs:

Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra7-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra72-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck

Regards,

Tony

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

Hi,

* Tony Lindgren <tony@atomide.com> [160331 10:04]:
> * Keerthy <a0393675@ti.com> [160331 02:26]:
> > 
> > 
> > On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> > >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> > >>* Tony Lindgren <tony@atomide.com> [160330 14:19]:
> > >>>* Keerthy <j-keerthy@ti.com> [160314 05:04]:
> > >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> > >>>>external
> > >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> > >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> > >>>>usually
> > >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> > >>>
> > >>>Thanks applying into omap-for-v4.6/fixes.
> > >>
> > >>Actually let's wait a review from Tero on this one, not sure
> > >>about the pseudo clock naming here. So dropping for now.
> > >
> > >The patch is fine for me, I didn't comment anything before as I thought
> > >you already applied it.
> > >
> > >Acked-by: Tero Kristo <t-kristo@ti.com>
> > 
> > Thanks Tero.
> 
> OK applying with Tero's ack.

I'm dropping this again as it introduces new warnings with make dtbs:

Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra7-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra72-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck

Regards,

Tony

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

Hi,

* Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [160331 10:04]:
> * Keerthy <a0393675-l0cyMroinI0@public.gmane.org> [160331 02:26]:
> > 
> > 
> > On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
> > >On 03/31/2016 12:32 AM, Tony Lindgren wrote:
> > >>* Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [160330 14:19]:
> > >>>* Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org> [160314 05:04]:
> > >>>>This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
> > >>>>Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
> > >>>>external
> > >>>>crystal is not enabled at power up. Instead the CPU falls back to using
> > >>>>an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
> > >>>>usually
> > >>>>20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
> > >>>
> > >>>Thanks applying into omap-for-v4.6/fixes.
> > >>
> > >>Actually let's wait a review from Tero on this one, not sure
> > >>about the pseudo clock naming here. So dropping for now.
> > >
> > >The patch is fine for me, I didn't comment anything before as I thought
> > >you already applied it.
> > >
> > >Acked-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
> > 
> > Thanks Tero.
> 
> OK applying with Tero's ack.

I'm dropping this again as it introduces new warnings with make dtbs:

Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra7-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
  DTC     arch/arm/boot/dts/dra72-evm.dtb
Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck

Regards,

Tony
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Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tero Kristo]

On 04/01/2016 06:36 PM, Tony Lindgren wrote:
> Hi,
>
> * Tony Lindgren <tony@atomide.com> [160331 10:04]:
>> * Keerthy <a0393675@ti.com> [160331 02:26]:
>>>
>>>
>>> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
>>>> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>>>>>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>>>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>>>>> external
>>>>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>>>>> usually
>>>>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>>>>
>>>>>> Thanks applying into omap-for-v4.6/fixes.
>>>>>
>>>>> Actually let's wait a review from Tero on this one, not sure
>>>>> about the pseudo clock naming here. So dropping for now.
>>>>
>>>> The patch is fine for me, I didn't comment anything before as I thought
>>>> you already applied it.
>>>>
>>>> Acked-by: Tero Kristo <t-kristo@ti.com>
>>>
>>> Thanks Tero.
>>
>> OK applying with Tero's ack.
>
> I'm dropping this again as it introduces new warnings with make dtbs:
>
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra7-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra72-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>
> Regards,
>
> Tony
>

Looks like a merge conflict to me, sys_32k_ck has gone under 
clockdomains for some reason. It should be under clocks.

-Tero

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tero Kristo]

On 04/01/2016 06:36 PM, Tony Lindgren wrote:
> Hi,
>
> * Tony Lindgren <tony@atomide.com> [160331 10:04]:
>> * Keerthy <a0393675@ti.com> [160331 02:26]:
>>>
>>>
>>> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
>>>> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony@atomide.com> [160330 14:19]:
>>>>>> * Keerthy <j-keerthy@ti.com> [160314 05:04]:
>>>>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>>>>> external
>>>>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>>>>> usually
>>>>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>>>>
>>>>>> Thanks applying into omap-for-v4.6/fixes.
>>>>>
>>>>> Actually let's wait a review from Tero on this one, not sure
>>>>> about the pseudo clock naming here. So dropping for now.
>>>>
>>>> The patch is fine for me, I didn't comment anything before as I thought
>>>> you already applied it.
>>>>
>>>> Acked-by: Tero Kristo <t-kristo@ti.com>
>>>
>>> Thanks Tero.
>>
>> OK applying with Tero's ack.
>
> I'm dropping this again as it introduces new warnings with make dtbs:
>
> Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra7-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra72-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4 at 4a000000/cm_core at 8000/clockdomains/sys_32k_ck
>
> Regards,
>
> Tony
>

Looks like a merge conflict to me, sys_32k_ck has gone under 
clockdomains for some reason. It should be under clocks.

-Tero

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tero Kristo]

On 04/01/2016 06:36 PM, Tony Lindgren wrote:
> Hi,
>
> * Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [160331 10:04]:
>> * Keerthy <a0393675-l0cyMroinI0@public.gmane.org> [160331 02:26]:
>>>
>>>
>>> On Thursday 31 March 2016 12:00 PM, Tero Kristo wrote:
>>>> On 03/31/2016 12:32 AM, Tony Lindgren wrote:
>>>>> * Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> [160330 14:19]:
>>>>>> * Keerthy <j-keerthy-l0cyMroinI0@public.gmane.org> [160314 05:04]:
>>>>>>> This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
>>>>>>> Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz
>>>>>>> external
>>>>>>> crystal is not enabled at power up. Instead the CPU falls back to using
>>>>>>> an emulation for the 32KHz clock which is SYSCLK1/610.  SYSCLK1 is
>>>>>>> usually
>>>>>>> 20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
>>>>>>
>>>>>> Thanks applying into omap-for-v4.6/fixes.
>>>>>
>>>>> Actually let's wait a review from Tero on this one, not sure
>>>>> about the pseudo clock naming here. So dropping for now.
>>>>
>>>> The patch is fine for me, I didn't comment anything before as I thought
>>>> you already applied it.
>>>>
>>>> Acked-by: Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org>
>>>
>>> Thanks Tero.
>>
>> OK applying with Tero's ack.
>
> I'm dropping this again as it introduces new warnings with make dtbs:
>
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-cl-som-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/am57xx-sbc-am57x.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra7-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>    DTC     arch/arm/boot/dts/dra72-evm.dtb
> Warning (reg_format): "reg" property in /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck has invalid length (4 bytes) (#address-cells == 2, #size-cells == 1)
> Warning (avoid_default_addr_size): Relying on default #address-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
> Warning (avoid_default_addr_size): Relying on default #size-cells value for /ocp/l4@4a000000/cm_core@8000/clockdomains/sys_32k_ck
>
> Regards,
>
> Tony
>

Looks like a merge conflict to me, sys_32k_ck has gone under 
clockdomains for some reason. It should be under clocks.

-Tero

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Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [160401 11:50]:
> 
> Looks like a merge conflict to me, sys_32k_ck has gone under clockdomains
> for some reason. It should be under clocks.

Oh OK, I'll wait for an updated patch against v4.6-rc1 then.
Might be worth checking it applies cleanly against
omap-for-v4.6/fixes-rc1 too.

Regards,

Tony

[PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Tero Kristo <t-kristo@ti.com> [160401 11:50]:
> 
> Looks like a merge conflict to me, sys_32k_ck has gone under clockdomains
> for some reason. It should be under clocks.

Oh OK, I'll wait for an updated patch against v4.6-rc1 then.
Might be worth checking it applies cleanly against
omap-for-v4.6/fixes-rc1 too.

Regards,

Tony

Re: [PATCH v2] ARM: dts: dra7: Correct clock tree for sys_32k_ck

[Tony Lindgren]

* Tero Kristo <t-kristo-l0cyMroinI0@public.gmane.org> [160401 11:50]:
> 
> Looks like a merge conflict to me, sys_32k_ck has gone under clockdomains
> for some reason. It should be under clocks.

Oh OK, I'll wait for an updated patch against v4.6-rc1 then.
Might be worth checking it applies cleanly against
omap-for-v4.6/fixes-rc1 too.

Regards,

Tony
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