[PATCH 0/5] rk3399 support ddr frequency scaling

[PATCH 0/5] rk3399 support ddr frequency scaling

[Lin Huang]

rk3399 platform have dfi controller can monitor ddr load,
and dcf controller to handle ddr register so we can get the
right ddr frequency and make ddr controller happy work(which
will implement in bl31). So we do ddr frequency scaling with
following flow:

             kernel                                bl31

        monitor ddr load
                |
                |
        get_target_rate
                |
                |           pass rate to bl31
        clk_set_rate(ddr) --------------------->run dcf flow
                |                                   |
                |                                   |
        wait dcf interrupt<-------------------trigger dcf interrupt
                |
                |
              return


Lin Huang (5):
  Documentation: bindings: add dt documentation for dfi controller
  PM / devfreq: event: support rockchip dfi controller
  Documentation: bindings: add dt documentation for rk3399 dmc
  PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
  drm/rockchip: Add dmc notifier in vop driver

Following patch:
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: rockchip: rk3399: add ddrc clock support
have applied to:
http://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/v4.9-clk/next


 .../bindings/devfreq/event/rockchip-dfi.txt        |  19 +
 .../devicetree/bindings/devfreq/rk3399_dmc.txt     | 173 ++++++++
 drivers/devfreq/Kconfig                            |  11 +
 drivers/devfreq/Makefile                           |   1 +
 drivers/devfreq/event/Kconfig                      |   7 +
 drivers/devfreq/event/Makefile                     |   1 +
 drivers/devfreq/event/rockchip-dfi.c               | 256 +++++++++++
 drivers/devfreq/rk3399_dmc.c                       | 480 +++++++++++++++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        | 116 +++++
 9 files changed, 1064 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
 create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
 create mode 100644 drivers/devfreq/event/rockchip-dfi.c
 create mode 100644 drivers/devfreq/rk3399_dmc.c

-- 
2.6.6

[PATCH 0/5] rk3399 support ddr frequency scaling

[Lin Huang]

rk3399 platform have dfi controller can monitor ddr load,
and dcf controller to handle ddr register so we can get the
right ddr frequency and make ddr controller happy work(which
will implement in bl31). So we do ddr frequency scaling with
following flow:

             kernel                                bl31

        monitor ddr load
                |
                |
        get_target_rate
                |
                |           pass rate to bl31
        clk_set_rate(ddr) --------------------->run dcf flow
                |                                   |
                |                                   |
        wait dcf interrupt<-------------------trigger dcf interrupt
                |
                |
              return


Lin Huang (5):
  Documentation: bindings: add dt documentation for dfi controller
  PM / devfreq: event: support rockchip dfi controller
  Documentation: bindings: add dt documentation for rk3399 dmc
  PM / devfreq: rockchip: add devfreq driver for rk3399 dmc
  drm/rockchip: Add dmc notifier in vop driver

Following patch:
clk: rockchip: add new clock-type for the ddrclk
clk: rockchip: rk3399: add SCLK_DDRCLK ID for ddrc
clk: rockchip: rk3399: add ddrc clock support
have applied to:
http://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/v4.9-clk/next


 .../bindings/devfreq/event/rockchip-dfi.txt        |  19 +
 .../devicetree/bindings/devfreq/rk3399_dmc.txt     | 173 ++++++++
 drivers/devfreq/Kconfig                            |  11 +
 drivers/devfreq/Makefile                           |   1 +
 drivers/devfreq/event/Kconfig                      |   7 +
 drivers/devfreq/event/Makefile                     |   1 +
 drivers/devfreq/event/rockchip-dfi.c               | 256 +++++++++++
 drivers/devfreq/rk3399_dmc.c                       | 480 +++++++++++++++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c        | 116 +++++
 9 files changed, 1064 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
 create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
 create mode 100644 drivers/devfreq/event/rockchip-dfi.c
 create mode 100644 drivers/devfreq/rk3399_dmc.c

-- 
2.6.6

[PATCH 1/5] Documentation: bindings: add dt documentation for dfi controller

[Lin Huang]

This patch adds the documentation for rockchip dfi devfreq-event driver.

Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v8:
- delete a unuse blank line

Changes in v7:
- None

Changes in v6:
- None

Changes in v5:
- None

Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- None 

Changes in v1:
- None

 .../bindings/devfreq/event/rockchip-dfi.txt           | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt

diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
new file mode 100644
index 0000000..d66aca6
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
@@ -0,0 +1,19 @@
+
+* Rockchip rk3399 DFI device
+
+Required properties:
+- compatible: Must be "rockchip,rk3399-dfi".
+- reg: physical base address of each DFI and length of memory mapped region
+- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
+- clocks: phandles for clock specified in "clock-names" property
+- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
+
+Example:
+	dfi: dfi@0xff630000 {
+		reg = <0x00 0xff630000 0x00 0x4000>;
+		compatible = "rockchip,rk3399-dfi";
+		rockchip,pmu = <&pmugrf>;
+		clocks = <&cru PCLK_DDR_MON>;
+		clock-names = "pclk_ddr_mon";
+		status = "disabled";
+	};
-- 
2.6.6

[PATCH 1/5] Documentation: bindings: add dt documentation for dfi controller

[Lin Huang]

This patch adds the documentation for rockchip dfi devfreq-event driver.

Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v8:
- delete a unuse blank line

Changes in v7:
- None

Changes in v6:
- None

Changes in v5:
- None

Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- None 

Changes in v1:
- None

 .../bindings/devfreq/event/rockchip-dfi.txt           | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt

diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
new file mode 100644
index 0000000..d66aca6
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
@@ -0,0 +1,19 @@
+
+* Rockchip rk3399 DFI device
+
+Required properties:
+- compatible: Must be "rockchip,rk3399-dfi".
+- reg: physical base address of each DFI and length of memory mapped region
+- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
+- clocks: phandles for clock specified in "clock-names" property
+- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
+
+Example:
+	dfi: dfi at 0xff630000 {
+		reg = <0x00 0xff630000 0x00 0x4000>;
+		compatible = "rockchip,rk3399-dfi";
+		rockchip,pmu = <&pmugrf>;
+		clocks = <&cru PCLK_DDR_MON>;
+		clock-names = "pclk_ddr_mon";
+		status = "disabled";
+	};
-- 
2.6.6

Re: [PATCH 1/5] Documentation: bindings: add dt documentation for dfi controller

[Chanwoo Choi]

On 2016년 09월 02일 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip dfi devfreq-event driver.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> ---
> Changes in v8:
> - delete a unuse blank line
> 
> Changes in v7:
> - None
> 
> Changes in v6:
> - None
> 
> Changes in v5:
> - None
> 
> Changes in v4:
> - None
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None 
> 
> Changes in v1:
> - None
> 
>  .../bindings/devfreq/event/rockchip-dfi.txt           | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> new file mode 100644
> index 0000000..d66aca6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> @@ -0,0 +1,19 @@
> +
> +* Rockchip rk3399 DFI device
> +
> +Required properties:
> +- compatible: Must be "rockchip,rk3399-dfi".
> +- reg: physical base address of each DFI and length of memory mapped region
> +- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
> +- clocks: phandles for clock specified in "clock-names" property
> +- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
> +
> +Example:
> +	dfi: dfi@0xff630000 {
> +		reg = <0x00 0xff630000 0x00 0x4000>;
> +		compatible = "rockchip,rk3399-dfi";

As I already commented, you need to reorder between compatible and reg property.

> +		rockchip,pmu = <&pmugrf>;
> +		clocks = <&cru PCLK_DDR_MON>;
> +		clock-names = "pclk_ddr_mon";
> +		status = "disabled";
> +	};
> 


-- 
Best Regards,
Chanwoo Choi

[PATCH 1/5] Documentation: bindings: add dt documentation for dfi controller

[Chanwoo Choi]

On 2016? 09? 02? 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip dfi devfreq-event driver.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> ---
> Changes in v8:
> - delete a unuse blank line
> 
> Changes in v7:
> - None
> 
> Changes in v6:
> - None
> 
> Changes in v5:
> - None
> 
> Changes in v4:
> - None
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None 
> 
> Changes in v1:
> - None
> 
>  .../bindings/devfreq/event/rockchip-dfi.txt           | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> new file mode 100644
> index 0000000..d66aca6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> @@ -0,0 +1,19 @@
> +
> +* Rockchip rk3399 DFI device
> +
> +Required properties:
> +- compatible: Must be "rockchip,rk3399-dfi".
> +- reg: physical base address of each DFI and length of memory mapped region
> +- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
> +- clocks: phandles for clock specified in "clock-names" property
> +- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
> +
> +Example:
> +	dfi: dfi at 0xff630000 {
> +		reg = <0x00 0xff630000 0x00 0x4000>;
> +		compatible = "rockchip,rk3399-dfi";

As I already commented, you need to reorder between compatible and reg property.

> +		rockchip,pmu = <&pmugrf>;
> +		clocks = <&cru PCLK_DDR_MON>;
> +		clock-names = "pclk_ddr_mon";
> +		status = "disabled";
> +	};
> 


-- 
Best Regards,
Chanwoo Choi

Re: [PATCH 1/5] Documentation: bindings: add dt documentation for dfi controller

[Chanwoo Choi]

On 2016년 09월 02일 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip dfi devfreq-event driver.
> 
> Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v8:
> - delete a unuse blank line
> 
> Changes in v7:
> - None
> 
> Changes in v6:
> - None
> 
> Changes in v5:
> - None
> 
> Changes in v4:
> - None
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None 
> 
> Changes in v1:
> - None
> 
>  .../bindings/devfreq/event/rockchip-dfi.txt           | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> new file mode 100644
> index 0000000..d66aca6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
> @@ -0,0 +1,19 @@
> +
> +* Rockchip rk3399 DFI device
> +
> +Required properties:
> +- compatible: Must be "rockchip,rk3399-dfi".
> +- reg: physical base address of each DFI and length of memory mapped region
> +- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
> +- clocks: phandles for clock specified in "clock-names" property
> +- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
> +
> +Example:
> +	dfi: dfi@0xff630000 {
> +		reg = <0x00 0xff630000 0x00 0x4000>;
> +		compatible = "rockchip,rk3399-dfi";

As I already commented, you need to reorder between compatible and reg property.

> +		rockchip,pmu = <&pmugrf>;
> +		clocks = <&cru PCLK_DDR_MON>;
> +		clock-names = "pclk_ddr_mon";
> +		status = "disabled";
> +	};
> 


-- 
Best Regards,
Chanwoo Choi
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[PATCH 2/5] PM / devfreq: event: support rockchip dfi controller

[Lin Huang]

on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Changes in v8:
-None

Changes in v7:
-access need to *4 to get right DDR loading

Changes in v6:
-None

Changes in v5:
-None

Changes in v4:
-None

Changes in v3:
-None

Changes in v2:
-None 

Changes in v1:
-None

 drivers/devfreq/event/Kconfig        |   7 +
 drivers/devfreq/event/Makefile       |   1 +
 drivers/devfreq/event/rockchip-dfi.c | 256 +++++++++++++++++++++++++++++++++++
 3 files changed, 264 insertions(+)
 create mode 100644 drivers/devfreq/event/rockchip-dfi.c

diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
index eb6f74a..20d82c2 100644
--- a/drivers/devfreq/event/Kconfig
+++ b/drivers/devfreq/event/Kconfig
@@ -30,4 +30,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU
 	  (Platform Performance Monitoring Unit) counters to estimate the
 	  utilization of each module.
 
+config DEVFREQ_EVENT_ROCKCHIP_DFI
+	tristate "ROCKCHIP DFI DEVFREQ event Driver"
+	depends on ARCH_ROCKCHIP
+	help
+	  This add the devfreq-event driver for Rockchip SoC. It provides DFI
+	  (DDR Monitor Module) driver to count ddr load.
+
 endif # PM_DEVFREQ_EVENT
diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
index 3d6afd3..dda7090 100644
--- a/drivers/devfreq/event/Makefile
+++ b/drivers/devfreq/event/Makefile
@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP) += exynos-nocp.o
 obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
+obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
new file mode 100644
index 0000000..43fcc5a
--- /dev/null
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Lin Huang <hl@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq-event.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/of.h>
+
+#define RK3399_DMC_NUM_CH	2
+
+/* DDRMON_CTRL */
+#define DDRMON_CTRL	0x04
+#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
+#define LPDDR4_EN	(0x10001 << 4)
+#define HARDWARE_EN	(0x10001 << 3)
+#define LPDDR3_EN	(0x10001 << 2)
+#define SOFTWARE_EN	(0x10001 << 1)
+#define SOFTWARE_DIS	(0x10000 << 1)
+#define TIME_CNT_EN	(0x10001 << 0)
+
+#define DDRMON_CH0_COUNT_NUM		0x28
+#define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
+#define DDRMON_CH1_COUNT_NUM		0x3c
+#define DDRMON_CH1_DFI_ACCESS_NUM	0x40
+
+/* pmu grf */
+#define PMUGRF_OS_REG2	0x308
+#define DDRTYPE_SHIFT	13
+#define DDRTYPE_MASK	7
+
+enum {
+	DDR3 = 3,
+	LPDDR3 = 6,
+	LPDDR4 = 7,
+	UNUSED = 0xFF
+};
+
+struct dmc_usage {
+	u32 access;
+	u32 total;
+};
+
+/*
+ * The dfi controller can monitor DDR load. It has an upper and lower threshold
+ * for the operating points. Whenever the usage leaves these bounds an event is
+ * generated to indicate the DDR frequency should be changed.
+ */
+struct rockchip_dfi {
+	struct devfreq_event_dev *edev;
+	struct devfreq_event_desc *desc;
+	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
+	struct device *dev;
+	void __iomem *regs;
+	struct regmap *regmap_pmu;
+	struct clk *clk;
+};
+
+static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	void __iomem *dfi_regs = info->regs;
+	u32 val;
+	u32 ddr_type;
+
+	/* get ddr type */
+	regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
+	ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
+
+	/* clear DDRMON_CTRL setting */
+	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+
+	/* set ddr type to dfi */
+	if (ddr_type == LPDDR3)
+		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+	else if (ddr_type == LPDDR4)
+		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+
+	/* enable count, use software mode */
+	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
+}
+
+static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	void __iomem *dfi_regs = info->regs;
+
+	writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
+}
+
+static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	u32 tmp, max = 0;
+	u32 i, busier_ch = 0;
+	void __iomem *dfi_regs = info->regs;
+
+	rockchip_dfi_stop_hardware_counter(edev);
+
+	/* Find out which channel is busier */
+	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+		info->ch_usage[i].access = readl_relaxed(dfi_regs +
+				DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
+		info->ch_usage[i].total = readl_relaxed(dfi_regs +
+				DDRMON_CH0_COUNT_NUM + i * 20);
+		tmp = info->ch_usage[i].access;
+		if (tmp > max) {
+			busier_ch = i;
+			max = tmp;
+		}
+	}
+	rockchip_dfi_start_hardware_counter(edev);
+
+	return busier_ch;
+}
+
+static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+	rockchip_dfi_stop_hardware_counter(edev);
+	clk_disable_unprepare(info->clk);
+
+	return 0;
+}
+
+static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	int ret;
+
+	ret = clk_prepare_enable(info->clk);
+	if (ret) {
+		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
+		return ret;
+	}
+
+	rockchip_dfi_start_hardware_counter(edev);
+	return 0;
+}
+
+static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
+{
+	return 0;
+}
+
+static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
+				  struct devfreq_event_data *edata)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	int busier_ch;
+
+	busier_ch = rockchip_dfi_get_busier_ch(edev);
+
+	edata->load_count = info->ch_usage[busier_ch].access;
+	edata->total_count = info->ch_usage[busier_ch].total;
+
+	return 0;
+}
+
+static const struct devfreq_event_ops rockchip_dfi_ops = {
+	.disable = rockchip_dfi_disable,
+	.enable = rockchip_dfi_enable,
+	.get_event = rockchip_dfi_get_event,
+	.set_event = rockchip_dfi_set_event,
+};
+
+static const struct of_device_id rockchip_dfi_id_match[] = {
+	{ .compatible = "rockchip,rk3399-dfi" },
+	{ },
+};
+
+static int rockchip_dfi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rockchip_dfi *data;
+	struct resource *res;
+	struct devfreq_event_desc *desc;
+	struct device_node *np = pdev->dev.of_node, *node;
+
+	data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	data->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(data->regs))
+		return PTR_ERR(data->regs);
+
+	data->clk = devm_clk_get(dev, "pclk_ddr_mon");
+	if (IS_ERR(data->clk)) {
+		dev_err(dev, "Cannot get the clk dmc_clk\n");
+		return PTR_ERR(data->clk);
+	};
+
+	/* try to find the optional reference to the pmu syscon */
+	node = of_parse_phandle(np, "rockchip,pmu", 0);
+	if (node) {
+		data->regmap_pmu = syscon_node_to_regmap(node);
+		if (IS_ERR(data->regmap_pmu))
+			return PTR_ERR(data->regmap_pmu);
+	}
+	data->dev = dev;
+
+	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
+	if (!desc)
+		return -ENOMEM;
+
+	desc->ops = &rockchip_dfi_ops;
+	desc->driver_data = data;
+	desc->name = np->name;
+	data->desc = desc;
+
+	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+	if (IS_ERR(data->edev)) {
+		dev_err(&pdev->dev,
+			"failed to add devfreq-event device\n");
+		return PTR_ERR(data->edev);
+	}
+
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+}
+
+static struct platform_driver rockchip_dfi_driver = {
+	.probe	= rockchip_dfi_probe,
+	.driver = {
+		.name	= "rockchip-dfi",
+		.of_match_table = rockchip_dfi_id_match,
+	},
+};
+module_platform_driver(rockchip_dfi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DFI driver");
-- 
2.6.6

[PATCH 2/5] PM / devfreq: event: support rockchip dfi controller

[Lin Huang]

on rk3399 platform, there is dfi conroller can monitor
ddr load, base on this result, we can do ddr freqency
scaling.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Changes in v8:
-None

Changes in v7:
-access need to *4 to get right DDR loading

Changes in v6:
-None

Changes in v5:
-None

Changes in v4:
-None

Changes in v3:
-None

Changes in v2:
-None 

Changes in v1:
-None

 drivers/devfreq/event/Kconfig        |   7 +
 drivers/devfreq/event/Makefile       |   1 +
 drivers/devfreq/event/rockchip-dfi.c | 256 +++++++++++++++++++++++++++++++++++
 3 files changed, 264 insertions(+)
 create mode 100644 drivers/devfreq/event/rockchip-dfi.c

diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig
index eb6f74a..20d82c2 100644
--- a/drivers/devfreq/event/Kconfig
+++ b/drivers/devfreq/event/Kconfig
@@ -30,4 +30,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU
 	  (Platform Performance Monitoring Unit) counters to estimate the
 	  utilization of each module.
 
+config DEVFREQ_EVENT_ROCKCHIP_DFI
+	tristate "ROCKCHIP DFI DEVFREQ event Driver"
+	depends on ARCH_ROCKCHIP
+	help
+	  This add the devfreq-event driver for Rockchip SoC. It provides DFI
+	  (DDR Monitor Module) driver to count ddr load.
+
 endif # PM_DEVFREQ_EVENT
diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile
index 3d6afd3..dda7090 100644
--- a/drivers/devfreq/event/Makefile
+++ b/drivers/devfreq/event/Makefile
@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP) += exynos-nocp.o
 obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o
+obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
new file mode 100644
index 0000000..43fcc5a
--- /dev/null
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Lin Huang <hl@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq-event.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/list.h>
+#include <linux/of.h>
+
+#define RK3399_DMC_NUM_CH	2
+
+/* DDRMON_CTRL */
+#define DDRMON_CTRL	0x04
+#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
+#define LPDDR4_EN	(0x10001 << 4)
+#define HARDWARE_EN	(0x10001 << 3)
+#define LPDDR3_EN	(0x10001 << 2)
+#define SOFTWARE_EN	(0x10001 << 1)
+#define SOFTWARE_DIS	(0x10000 << 1)
+#define TIME_CNT_EN	(0x10001 << 0)
+
+#define DDRMON_CH0_COUNT_NUM		0x28
+#define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
+#define DDRMON_CH1_COUNT_NUM		0x3c
+#define DDRMON_CH1_DFI_ACCESS_NUM	0x40
+
+/* pmu grf */
+#define PMUGRF_OS_REG2	0x308
+#define DDRTYPE_SHIFT	13
+#define DDRTYPE_MASK	7
+
+enum {
+	DDR3 = 3,
+	LPDDR3 = 6,
+	LPDDR4 = 7,
+	UNUSED = 0xFF
+};
+
+struct dmc_usage {
+	u32 access;
+	u32 total;
+};
+
+/*
+ * The dfi controller can monitor DDR load. It has an upper and lower threshold
+ * for the operating points. Whenever the usage leaves these bounds an event is
+ * generated to indicate the DDR frequency should be changed.
+ */
+struct rockchip_dfi {
+	struct devfreq_event_dev *edev;
+	struct devfreq_event_desc *desc;
+	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
+	struct device *dev;
+	void __iomem *regs;
+	struct regmap *regmap_pmu;
+	struct clk *clk;
+};
+
+static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	void __iomem *dfi_regs = info->regs;
+	u32 val;
+	u32 ddr_type;
+
+	/* get ddr type */
+	regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val);
+	ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK;
+
+	/* clear DDRMON_CTRL setting */
+	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+
+	/* set ddr type to dfi */
+	if (ddr_type == LPDDR3)
+		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+	else if (ddr_type == LPDDR4)
+		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+
+	/* enable count, use software mode */
+	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
+}
+
+static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	void __iomem *dfi_regs = info->regs;
+
+	writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
+}
+
+static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	u32 tmp, max = 0;
+	u32 i, busier_ch = 0;
+	void __iomem *dfi_regs = info->regs;
+
+	rockchip_dfi_stop_hardware_counter(edev);
+
+	/* Find out which channel is busier */
+	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+		info->ch_usage[i].access = readl_relaxed(dfi_regs +
+				DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
+		info->ch_usage[i].total = readl_relaxed(dfi_regs +
+				DDRMON_CH0_COUNT_NUM + i * 20);
+		tmp = info->ch_usage[i].access;
+		if (tmp > max) {
+			busier_ch = i;
+			max = tmp;
+		}
+	}
+	rockchip_dfi_start_hardware_counter(edev);
+
+	return busier_ch;
+}
+
+static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+
+	rockchip_dfi_stop_hardware_counter(edev);
+	clk_disable_unprepare(info->clk);
+
+	return 0;
+}
+
+static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	int ret;
+
+	ret = clk_prepare_enable(info->clk);
+	if (ret) {
+		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
+		return ret;
+	}
+
+	rockchip_dfi_start_hardware_counter(edev);
+	return 0;
+}
+
+static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
+{
+	return 0;
+}
+
+static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
+				  struct devfreq_event_data *edata)
+{
+	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+	int busier_ch;
+
+	busier_ch = rockchip_dfi_get_busier_ch(edev);
+
+	edata->load_count = info->ch_usage[busier_ch].access;
+	edata->total_count = info->ch_usage[busier_ch].total;
+
+	return 0;
+}
+
+static const struct devfreq_event_ops rockchip_dfi_ops = {
+	.disable = rockchip_dfi_disable,
+	.enable = rockchip_dfi_enable,
+	.get_event = rockchip_dfi_get_event,
+	.set_event = rockchip_dfi_set_event,
+};
+
+static const struct of_device_id rockchip_dfi_id_match[] = {
+	{ .compatible = "rockchip,rk3399-dfi" },
+	{ },
+};
+
+static int rockchip_dfi_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct rockchip_dfi *data;
+	struct resource *res;
+	struct devfreq_event_desc *desc;
+	struct device_node *np = pdev->dev.of_node, *node;
+
+	data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	data->regs = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(data->regs))
+		return PTR_ERR(data->regs);
+
+	data->clk = devm_clk_get(dev, "pclk_ddr_mon");
+	if (IS_ERR(data->clk)) {
+		dev_err(dev, "Cannot get the clk dmc_clk\n");
+		return PTR_ERR(data->clk);
+	};
+
+	/* try to find the optional reference to the pmu syscon */
+	node = of_parse_phandle(np, "rockchip,pmu", 0);
+	if (node) {
+		data->regmap_pmu = syscon_node_to_regmap(node);
+		if (IS_ERR(data->regmap_pmu))
+			return PTR_ERR(data->regmap_pmu);
+	}
+	data->dev = dev;
+
+	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
+	if (!desc)
+		return -ENOMEM;
+
+	desc->ops = &rockchip_dfi_ops;
+	desc->driver_data = data;
+	desc->name = np->name;
+	data->desc = desc;
+
+	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+	if (IS_ERR(data->edev)) {
+		dev_err(&pdev->dev,
+			"failed to add devfreq-event device\n");
+		return PTR_ERR(data->edev);
+	}
+
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+}
+
+static struct platform_driver rockchip_dfi_driver = {
+	.probe	= rockchip_dfi_probe,
+	.driver = {
+		.name	= "rockchip-dfi",
+		.of_match_table = rockchip_dfi_id_match,
+	},
+};
+module_platform_driver(rockchip_dfi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DFI driver");
-- 
2.6.6

[PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Lin Huang]

This patch adds the documentation for rockchip rk3399 dmc driver.

Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v8:
- add ddr timing properties

Changes in v7:
-None

Changes in v6:
-Add more detail in Documentation

Changes in v5:
-None

Changes in v4:
-None

Changes in v3:
-None

Changes in v2:
-None 

Changes in v1:
-None

 .../devicetree/bindings/devfreq/rk3399_dmc.txt     | 173 +++++++++++++++++++++
 1 file changed, 173 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
new file mode 100644
index 0000000..1f39b5cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -0,0 +1,173 @@
+* Rockchip rk3399 DMC(Dynamic Memory Controller) device
+
+Required properties:
+- compatible:		 Must be "rockchip,rk3399-dmc".
+- devfreq-events:	 Node to get DDR loading, Refer to
+			 Documentation/devicetree/bindings/devfreq/
+			 rockchip-dfi.txt
+- interrupts:		 The interrupt number to the CPU. The interrupt
+			 specifier format depends on the interrupt controller.
+			 It should be DCF interrupts, when DDR dvfs finish,
+			 it will happen.
+- clocks:		 Phandles for clock specified in "clock-names" property
+- clock-names :		 The name of clock used by the DFI, must be
+			 "pclk_ddr_mon";
+- operating-points-v2:	 Refer to Documentation/devicetree/bindings/power/opp.txt
+			 for details.
+- center-supply:	 DMC supply node.
+- status:		 Marks the node enabled/disabled.
+
+Following properties are ddr timing:
+
+- dram_speed_bin :	 Value is defined at include/dt-bindings/clock/ddr.h,
+			 it select ddr3 cl-trp-trcd type, default value
+			 "DDR3_DEFAULT".it must selected according to
+			 "Speed Bin" in ddr3 datasheet, DO NOT use smaller
+			 "Speed Bin" than ddr3 exactly is.
+
+- pd_idle :		 Config the PD_IDLE value, defined the power-down idle
+			 period, memories are places into power-down mode if
+			 bus is idle for PD_IDLE DFI clocks.
+
+- sr_idle :		 Configure the SR_IDLE value, defined the selfrefresh
+			 idle period, memories are places into self-refresh
+			 mode if bus is idle for SR_IDLE*1024 DFI clocks
+			 (DFI clocks freq is half of dram's clocks), defaule
+			 value is "0".
+
+- sr_mc_gate_idle :	 Defined the self-refresh with memory and controller
+			 clock gating idle period, memories are places into
+			 self-refresh mode and memory controller clock arg
+			 gating if bus is idle for sr_mc_gate_idle*1024 DFI
+			 clocks.
+
+- srpd_lite_idle :	 Defined the self-refresh power down idle period,
+			 memories are places into self-refresh power down
+			 mode if bus is idle for srpd_lite_idle*1024 DFI
+			 clocks. This parameter is for LPDDR4 only.
+
+- standby_idle :	 Defined the standby idle period, memories are places
+			 into self-refresh than controller, pi, phy and dram
+			 clock will gating if bus is idle for
+			 standby_idle * DFI clocks.
+
+- dram_dll_disb_freq :	 It's defined the DDR3 dll bypass frequency in MHz
+			 when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
+			 dll will bypssed note: if dll was bypassed, the
+			 odt also stop working.
+
+- phy_dll_disb_freq :	 Defined the PHY dll bypass frequency in MHz (Mega Hz),
+			 when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
+			 will bypssed. note: phy dll and phy odt are
+			 independent
+
+- ddr3_odt_disb_freq :	 When dram type is DDR3, this parameter defined the
+			 odt disable frequency in MHz (Mega Hz), when ddr
+			 frequency less then ddr3_odt_disb_freq, the odt
+			 on dram side and controller side are both disabled.
+
+- ddr3_drv :		 When dram type is DDR3, this parameter define the
+			 dram side driver stength in ohm, default value is
+			 DDR3_DS_40ohm.
+
+- ddr3_odt :		 When dram type is DDR3, this parameter define the
+			 dram side ODT stength in ohm, default value is
+			 DDR3_ODT_120ohm.
+
+- phy_ddr3_ca_drv :	 When dram type is DDR3, this parameter define the phy
+			 side CA line(incluing command line, address line and
+			 clock line) driver strength. default value is
+			 PHY_DRV_ODT_40.
+
+- phy_ddr3_dq_drv :	 When dram type is DDR3, this parameter define the phy
+			 side DQ line(incluing DQS/DQ/DM line) driver strength.
+			 default value is PHY_DRV_ODT_40.
+
+- phy_ddr3_odt : 	 When dram type is DDR3, this parameter define the
+			 phy side odt strength, default value is
+			 PHY_DRV_ODT_240.
+
+- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then
+			 odt disable frequency in MHz (Mega Hz), when ddr
+			 frequency less then ddr3_odt_disb_freq, the odt on
+			 dram side and controller side are both disabled.
+
+- lpddr3_drv :		 When dram type is LPDDR3, this parameter define the
+			 dram side driver stength in ohm, default value is
+			 LP3_DS_34ohm.
+
+- lpddr3_odt :		 When dram type is LPDDR3, this parameter define the
+			 dram side ODT stength in ohm, default value is
+			 LP3_ODT_240ohm.
+
+- phy_lpddr3_ca_drv :	 When dram type is LPDDR3, this parameter define the
+			 phy side CA line(incluing command line, address line
+			 and clock line) driver strength. default value is
+			 PHY_DRV_ODT_40.
+
+- phy_lpddr3_dq_drv :	 When dram type is LPDDR3, this parameter define the
+			 phy side DQ line(incluing DQS/DQ/DM line) driver
+			 strength. default value is PHY_DRV_ODT_40.
+
+- phy_lpddr3_odt : 	 When dram type is LPDDR3, this parameter define the phy
+			 side odt strength, default value is PHY_DRV_ODT_240.
+
+- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the
+			 odt disable frequency in MHz (Mega Hz), when ddr
+			 frequency less then ddr3_odt_disb_freq, the odt on
+			 dram side and controller side are both disabled.
+
+- lpddr4_drv :		 When dram type is LPDDR4, this parameter define the
+			 dram side driver stength in ohm, default value is
+			 LP4_PDDS_60ohm.
+
+- lpddr4_dq_odt : 	 When dram type is LPDDR4, this parameter define the
+			 dram side ODT on dqs/dq line stength in ohm, default
+			 value is LP4_DQ_ODT_40ohm.
+
+- lpddr4_ca_odt :	 When dram type is LPDDR4, this parameter define the
+			 dram side ODT on ca line stength in ohm, default value
+			 is LP4_CA_ODT_40ohm.
+
+- phy_lpddr4_ca_drv :	 When dram type is LPDDR4, this parameter define the
+			 phy side  CA line(incluing command address line)
+			 driver strength. default value is PHY_DRV_ODT_40.
+
+- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the
+			 phy side clock line and cs line driver strength.
+			 default value is PHY_DRV_ODT_80.
+
+- phy_lpddr4_dq_drv :	 When dram type is LPDDR4, this parameter define the
+			 phy side DQ line(incluing DQS/DQ/DM line) driver
+			 strength. default value is PHY_DRV_ODT_80.
+
+- phy_lpddr4_odt :	 When dram type is LPDDR4, this parameter define the
+			 phy side odt strength, default value is PHY_DRV_ODT_60.
+
+Example:
+	dmc_opp_table: dmc_opp_table {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <666000000>;
+			opp-microvolt = <900000>;
+		};
+	};
+
+	dmc: dmc {
+		compatible = "rockchip,rk3399-dmc";
+		devfreq-events = <&dfi>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_DDRCLK>;
+		clock-names = "dmc_clk";
+		operating-points-v2 = <&dmc_opp_table>;
+		center-supply = <&ppvar_centerlogic>;
+		upthreshold = <15>;
+		downdifferential = <10>;
+		status = "disabled";
+	};
+
-- 
2.6.6

[PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Lin Huang]

This patch adds the documentation for rockchip rk3399 dmc driver.

Signed-off-by: Lin Huang <hl@rock-chips.com>
---
Changes in v8:
- add ddr timing properties

Changes in v7:
-None

Changes in v6:
-Add more detail in Documentation

Changes in v5:
-None

Changes in v4:
-None

Changes in v3:
-None

Changes in v2:
-None 

Changes in v1:
-None

 .../devicetree/bindings/devfreq/rk3399_dmc.txt     | 173 +++++++++++++++++++++
 1 file changed, 173 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt

diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
new file mode 100644
index 0000000..1f39b5cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
@@ -0,0 +1,173 @@
+* Rockchip rk3399 DMC(Dynamic Memory Controller) device
+
+Required properties:
+- compatible:		 Must be "rockchip,rk3399-dmc".
+- devfreq-events:	 Node to get DDR loading, Refer to
+			 Documentation/devicetree/bindings/devfreq/
+			 rockchip-dfi.txt
+- interrupts:		 The interrupt number to the CPU. The interrupt
+			 specifier format depends on the interrupt controller.
+			 It should be DCF interrupts, when DDR dvfs finish,
+			 it will happen.
+- clocks:		 Phandles for clock specified in "clock-names" property
+- clock-names :		 The name of clock used by the DFI, must be
+			 "pclk_ddr_mon";
+- operating-points-v2:	 Refer to Documentation/devicetree/bindings/power/opp.txt
+			 for details.
+- center-supply:	 DMC supply node.
+- status:		 Marks the node enabled/disabled.
+
+Following properties are ddr timing:
+
+- dram_speed_bin :	 Value is defined at include/dt-bindings/clock/ddr.h,
+			 it select ddr3 cl-trp-trcd type, default value
+			 "DDR3_DEFAULT".it must selected according to
+			 "Speed Bin" in ddr3 datasheet, DO NOT use smaller
+			 "Speed Bin" than ddr3 exactly is.
+
+- pd_idle :		 Config the PD_IDLE value, defined the power-down idle
+			 period, memories are places into power-down mode if
+			 bus is idle for PD_IDLE DFI clocks.
+
+- sr_idle :		 Configure the SR_IDLE value, defined the selfrefresh
+			 idle period, memories are places into self-refresh
+			 mode if bus is idle for SR_IDLE*1024 DFI clocks
+			 (DFI clocks freq is half of dram's clocks), defaule
+			 value is "0".
+
+- sr_mc_gate_idle :	 Defined the self-refresh with memory and controller
+			 clock gating idle period, memories are places into
+			 self-refresh mode and memory controller clock arg
+			 gating if bus is idle for sr_mc_gate_idle*1024 DFI
+			 clocks.
+
+- srpd_lite_idle :	 Defined the self-refresh power down idle period,
+			 memories are places into self-refresh power down
+			 mode if bus is idle for srpd_lite_idle*1024 DFI
+			 clocks. This parameter is for LPDDR4 only.
+
+- standby_idle :	 Defined the standby idle period, memories are places
+			 into self-refresh than controller, pi, phy and dram
+			 clock will gating if bus is idle for
+			 standby_idle * DFI clocks.
+
+- dram_dll_disb_freq :	 It's defined the DDR3 dll bypass frequency in MHz
+			 when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
+			 dll will bypssed note: if dll was bypassed, the
+			 odt also stop working.
+
+- phy_dll_disb_freq :	 Defined the PHY dll bypass frequency in MHz (Mega Hz),
+			 when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
+			 will bypssed. note: phy dll and phy odt are
+			 independent
+
+- ddr3_odt_disb_freq :	 When dram type is DDR3, this parameter defined the
+			 odt disable frequency in MHz (Mega Hz), when ddr
+			 frequency less then ddr3_odt_disb_freq, the odt
+			 on dram side and controller side are both disabled.
+
+- ddr3_drv :		 When dram type is DDR3, this parameter define the
+			 dram side driver stength in ohm, default value is
+			 DDR3_DS_40ohm.
+
+- ddr3_odt :		 When dram type is DDR3, this parameter define the
+			 dram side ODT stength in ohm, default value is
+			 DDR3_ODT_120ohm.
+
+- phy_ddr3_ca_drv :	 When dram type is DDR3, this parameter define the phy
+			 side CA line(incluing command line, address line and
+			 clock line) driver strength. default value is
+			 PHY_DRV_ODT_40.
+
+- phy_ddr3_dq_drv :	 When dram type is DDR3, this parameter define the phy
+			 side DQ line(incluing DQS/DQ/DM line) driver strength.
+			 default value is PHY_DRV_ODT_40.
+
+- phy_ddr3_odt : 	 When dram type is DDR3, this parameter define the
+			 phy side odt strength, default value is
+			 PHY_DRV_ODT_240.
+
+- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then
+			 odt disable frequency in MHz (Mega Hz), when ddr
+			 frequency less then ddr3_odt_disb_freq, the odt on
+			 dram side and controller side are both disabled.
+
+- lpddr3_drv :		 When dram type is LPDDR3, this parameter define the
+			 dram side driver stength in ohm, default value is
+			 LP3_DS_34ohm.
+
+- lpddr3_odt :		 When dram type is LPDDR3, this parameter define the
+			 dram side ODT stength in ohm, default value is
+			 LP3_ODT_240ohm.
+
+- phy_lpddr3_ca_drv :	 When dram type is LPDDR3, this parameter define the
+			 phy side CA line(incluing command line, address line
+			 and clock line) driver strength. default value is
+			 PHY_DRV_ODT_40.
+
+- phy_lpddr3_dq_drv :	 When dram type is LPDDR3, this parameter define the
+			 phy side DQ line(incluing DQS/DQ/DM line) driver
+			 strength. default value is PHY_DRV_ODT_40.
+
+- phy_lpddr3_odt : 	 When dram type is LPDDR3, this parameter define the phy
+			 side odt strength, default value is PHY_DRV_ODT_240.
+
+- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the
+			 odt disable frequency in MHz (Mega Hz), when ddr
+			 frequency less then ddr3_odt_disb_freq, the odt on
+			 dram side and controller side are both disabled.
+
+- lpddr4_drv :		 When dram type is LPDDR4, this parameter define the
+			 dram side driver stength in ohm, default value is
+			 LP4_PDDS_60ohm.
+
+- lpddr4_dq_odt : 	 When dram type is LPDDR4, this parameter define the
+			 dram side ODT on dqs/dq line stength in ohm, default
+			 value is LP4_DQ_ODT_40ohm.
+
+- lpddr4_ca_odt :	 When dram type is LPDDR4, this parameter define the
+			 dram side ODT on ca line stength in ohm, default value
+			 is LP4_CA_ODT_40ohm.
+
+- phy_lpddr4_ca_drv :	 When dram type is LPDDR4, this parameter define the
+			 phy side  CA line(incluing command address line)
+			 driver strength. default value is PHY_DRV_ODT_40.
+
+- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the
+			 phy side clock line and cs line driver strength.
+			 default value is PHY_DRV_ODT_80.
+
+- phy_lpddr4_dq_drv :	 When dram type is LPDDR4, this parameter define the
+			 phy side DQ line(incluing DQS/DQ/DM line) driver
+			 strength. default value is PHY_DRV_ODT_80.
+
+- phy_lpddr4_odt :	 When dram type is LPDDR4, this parameter define the
+			 phy side odt strength, default value is PHY_DRV_ODT_60.
+
+Example:
+	dmc_opp_table: dmc_opp_table {
+		compatible = "operating-points-v2";
+
+		opp00 {
+			opp-hz = /bits/ 64 <300000000>;
+			opp-microvolt = <900000>;
+		};
+		opp01 {
+			opp-hz = /bits/ 64 <666000000>;
+			opp-microvolt = <900000>;
+		};
+	};
+
+	dmc: dmc {
+		compatible = "rockchip,rk3399-dmc";
+		devfreq-events = <&dfi>;
+		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_DDRCLK>;
+		clock-names = "dmc_clk";
+		operating-points-v2 = <&dmc_opp_table>;
+		center-supply = <&ppvar_centerlogic>;
+		upthreshold = <15>;
+		downdifferential = <10>;
+		status = "disabled";
+	};
+
-- 
2.6.6

Re: [PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Chanwoo Choi]

On 2016년 09월 02일 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip rk3399 dmc driver.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> ---
> Changes in v8:
> - add ddr timing properties
> 
> Changes in v7:
> -None
> 
> Changes in v6:
> -Add more detail in Documentation
> 
> Changes in v5:
> -None
> 
> Changes in v4:
> -None
> 
> Changes in v3:
> -None
> 
> Changes in v2:
> -None 
> 
> Changes in v1:
> -None
> 
>  .../devicetree/bindings/devfreq/rk3399_dmc.txt     | 173 +++++++++++++++++++++
>  1 file changed, 173 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> new file mode 100644
> index 0000000..1f39b5cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -0,0 +1,173 @@
> +* Rockchip rk3399 DMC(Dynamic Memory Controller) device
> +
> +Required properties:
> +- compatible:		 Must be "rockchip,rk3399-dmc".
> +- devfreq-events:	 Node to get DDR loading, Refer to
> +			 Documentation/devicetree/bindings/devfreq/
> +			 rockchip-dfi.txt
> +- interrupts:		 The interrupt number to the CPU. The interrupt
> +			 specifier format depends on the interrupt controller.
> +			 It should be DCF interrupts, when DDR dvfs finish,
> +			 it will happen.
> +- clocks:		 Phandles for clock specified in "clock-names" property
> +- clock-names :		 The name of clock used by the DFI, must be
> +			 "pclk_ddr_mon";
> +- operating-points-v2:	 Refer to Documentation/devicetree/bindings/power/opp.txt
> +			 for details.
> +- center-supply:	 DMC supply node.
> +- status:		 Marks the node enabled/disabled.
> +
> +Following properties are ddr timing:
> +
> +- dram_speed_bin :	 Value is defined at include/dt-bindings/clock/ddr.h,
> +			 it select ddr3 cl-trp-trcd type, default value
> +			 "DDR3_DEFAULT".it must selected according to
> +			 "Speed Bin" in ddr3 datasheet, DO NOT use smaller
> +			 "Speed Bin" than ddr3 exactly is.
> +
> +- pd_idle :		 Config the PD_IDLE value, defined the power-down idle
> +			 period, memories are places into power-down mode if
> +			 bus is idle for PD_IDLE DFI clocks.
> +
> +- sr_idle :		 Configure the SR_IDLE value, defined the selfrefresh
> +			 idle period, memories are places into self-refresh
> +			 mode if bus is idle for SR_IDLE*1024 DFI clocks
> +			 (DFI clocks freq is half of dram's clocks), defaule
> +			 value is "0".
> +
> +- sr_mc_gate_idle :	 Defined the self-refresh with memory and controller
> +			 clock gating idle period, memories are places into
> +			 self-refresh mode and memory controller clock arg
> +			 gating if bus is idle for sr_mc_gate_idle*1024 DFI
> +			 clocks.
> +
> +- srpd_lite_idle :	 Defined the self-refresh power down idle period,
> +			 memories are places into self-refresh power down
> +			 mode if bus is idle for srpd_lite_idle*1024 DFI
> +			 clocks. This parameter is for LPDDR4 only.
> +
> +- standby_idle :	 Defined the standby idle period, memories are places
> +			 into self-refresh than controller, pi, phy and dram
> +			 clock will gating if bus is idle for
> +			 standby_idle * DFI clocks.
> +
> +- dram_dll_disb_freq :	 It's defined the DDR3 dll bypass frequency in MHz
> +			 when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
> +			 dll will bypssed note: if dll was bypassed, the
> +			 odt also stop working.
> +
> +- phy_dll_disb_freq :	 Defined the PHY dll bypass frequency in MHz (Mega Hz),
> +			 when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
> +			 will bypssed. note: phy dll and phy odt are
> +			 independent
> +
> +- ddr3_odt_disb_freq :	 When dram type is DDR3, this parameter defined the
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt
> +			 on dram side and controller side are both disabled.
> +
> +- ddr3_drv :		 When dram type is DDR3, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 DDR3_DS_40ohm.
> +
> +- ddr3_odt :		 When dram type is DDR3, this parameter define the
> +			 dram side ODT stength in ohm, default value is
> +			 DDR3_ODT_120ohm.
> +
> +- phy_ddr3_ca_drv :	 When dram type is DDR3, this parameter define the phy
> +			 side CA line(incluing command line, address line and
> +			 clock line) driver strength. default value is
> +			 PHY_DRV_ODT_40.
> +
> +- phy_ddr3_dq_drv :	 When dram type is DDR3, this parameter define the phy
> +			 side DQ line(incluing DQS/DQ/DM line) driver strength.
> +			 default value is PHY_DRV_ODT_40.
> +
> +- phy_ddr3_odt : 	 When dram type is DDR3, this parameter define the
> +			 phy side odt strength, default value is
> +			 PHY_DRV_ODT_240.
> +
> +- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt on
> +			 dram side and controller side are both disabled.
> +
> +- lpddr3_drv :		 When dram type is LPDDR3, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 LP3_DS_34ohm.
> +
> +- lpddr3_odt :		 When dram type is LPDDR3, this parameter define the
> +			 dram side ODT stength in ohm, default value is
> +			 LP3_ODT_240ohm.
> +
> +- phy_lpddr3_ca_drv :	 When dram type is LPDDR3, this parameter define the
> +			 phy side CA line(incluing command line, address line
> +			 and clock line) driver strength. default value is
> +			 PHY_DRV_ODT_40.
> +
> +- phy_lpddr3_dq_drv :	 When dram type is LPDDR3, this parameter define the
> +			 phy side DQ line(incluing DQS/DQ/DM line) driver
> +			 strength. default value is PHY_DRV_ODT_40.
> +
> +- phy_lpddr3_odt : 	 When dram type is LPDDR3, this parameter define the phy
> +			 side odt strength, default value is PHY_DRV_ODT_240.
> +
> +- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt on
> +			 dram side and controller side are both disabled.
> +
> +- lpddr4_drv :		 When dram type is LPDDR4, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 LP4_PDDS_60ohm.
> +
> +- lpddr4_dq_odt : 	 When dram type is LPDDR4, this parameter define the
> +			 dram side ODT on dqs/dq line stength in ohm, default
> +			 value is LP4_DQ_ODT_40ohm.
> +
> +- lpddr4_ca_odt :	 When dram type is LPDDR4, this parameter define the
> +			 dram side ODT on ca line stength in ohm, default value
> +			 is LP4_CA_ODT_40ohm.
> +
> +- phy_lpddr4_ca_drv :	 When dram type is LPDDR4, this parameter define the
> +			 phy side  CA line(incluing command address line)
> +			 driver strength. default value is PHY_DRV_ODT_40.
> +
> +- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the
> +			 phy side clock line and cs line driver strength.
> +			 default value is PHY_DRV_ODT_80.
> +
> +- phy_lpddr4_dq_drv :	 When dram type is LPDDR4, this parameter define the
> +			 phy side DQ line(incluing DQS/DQ/DM line) driver
> +			 strength. default value is PHY_DRV_ODT_80.
> +
> +- phy_lpddr4_odt :	 When dram type is LPDDR4, this parameter define the
> +			 phy side odt strength, default value is PHY_DRV_ODT_60.

It is good to explain the each field for ddr timing.
But, why you you drop the example for ddr timing values?
I think that you better to add the example for ddr timing values

> +
> +Example:
> +	dmc_opp_table: dmc_opp_table {
> +		compatible = "operating-points-v2";
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <666000000>;
> +			opp-microvolt = <900000>;
> +		};
> +	};
> +
> +	dmc: dmc {
> +		compatible = "rockchip,rk3399-dmc";
> +		devfreq-events = <&dfi>;
> +		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_DDRCLK>;
> +		clock-names = "dmc_clk";
> +		operating-points-v2 = <&dmc_opp_table>;
> +		center-supply = <&ppvar_centerlogic>;
> +		upthreshold = <15>;
> +		downdifferential = <10>;
> +		status = "disabled";
> +	};
> +
> 


-- 
Best Regards,
Chanwoo Choi

[PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Chanwoo Choi]

On 2016? 09? 02? 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip rk3399 dmc driver.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> ---
> Changes in v8:
> - add ddr timing properties
> 
> Changes in v7:
> -None
> 
> Changes in v6:
> -Add more detail in Documentation
> 
> Changes in v5:
> -None
> 
> Changes in v4:
> -None
> 
> Changes in v3:
> -None
> 
> Changes in v2:
> -None 
> 
> Changes in v1:
> -None
> 
>  .../devicetree/bindings/devfreq/rk3399_dmc.txt     | 173 +++++++++++++++++++++
>  1 file changed, 173 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> new file mode 100644
> index 0000000..1f39b5cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -0,0 +1,173 @@
> +* Rockchip rk3399 DMC(Dynamic Memory Controller) device
> +
> +Required properties:
> +- compatible:		 Must be "rockchip,rk3399-dmc".
> +- devfreq-events:	 Node to get DDR loading, Refer to
> +			 Documentation/devicetree/bindings/devfreq/
> +			 rockchip-dfi.txt
> +- interrupts:		 The interrupt number to the CPU. The interrupt
> +			 specifier format depends on the interrupt controller.
> +			 It should be DCF interrupts, when DDR dvfs finish,
> +			 it will happen.
> +- clocks:		 Phandles for clock specified in "clock-names" property
> +- clock-names :		 The name of clock used by the DFI, must be
> +			 "pclk_ddr_mon";
> +- operating-points-v2:	 Refer to Documentation/devicetree/bindings/power/opp.txt
> +			 for details.
> +- center-supply:	 DMC supply node.
> +- status:		 Marks the node enabled/disabled.
> +
> +Following properties are ddr timing:
> +
> +- dram_speed_bin :	 Value is defined at include/dt-bindings/clock/ddr.h,
> +			 it select ddr3 cl-trp-trcd type, default value
> +			 "DDR3_DEFAULT".it must selected according to
> +			 "Speed Bin" in ddr3 datasheet, DO NOT use smaller
> +			 "Speed Bin" than ddr3 exactly is.
> +
> +- pd_idle :		 Config the PD_IDLE value, defined the power-down idle
> +			 period, memories are places into power-down mode if
> +			 bus is idle for PD_IDLE DFI clocks.
> +
> +- sr_idle :		 Configure the SR_IDLE value, defined the selfrefresh
> +			 idle period, memories are places into self-refresh
> +			 mode if bus is idle for SR_IDLE*1024 DFI clocks
> +			 (DFI clocks freq is half of dram's clocks), defaule
> +			 value is "0".
> +
> +- sr_mc_gate_idle :	 Defined the self-refresh with memory and controller
> +			 clock gating idle period, memories are places into
> +			 self-refresh mode and memory controller clock arg
> +			 gating if bus is idle for sr_mc_gate_idle*1024 DFI
> +			 clocks.
> +
> +- srpd_lite_idle :	 Defined the self-refresh power down idle period,
> +			 memories are places into self-refresh power down
> +			 mode if bus is idle for srpd_lite_idle*1024 DFI
> +			 clocks. This parameter is for LPDDR4 only.
> +
> +- standby_idle :	 Defined the standby idle period, memories are places
> +			 into self-refresh than controller, pi, phy and dram
> +			 clock will gating if bus is idle for
> +			 standby_idle * DFI clocks.
> +
> +- dram_dll_disb_freq :	 It's defined the DDR3 dll bypass frequency in MHz
> +			 when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
> +			 dll will bypssed note: if dll was bypassed, the
> +			 odt also stop working.
> +
> +- phy_dll_disb_freq :	 Defined the PHY dll bypass frequency in MHz (Mega Hz),
> +			 when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
> +			 will bypssed. note: phy dll and phy odt are
> +			 independent
> +
> +- ddr3_odt_disb_freq :	 When dram type is DDR3, this parameter defined the
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt
> +			 on dram side and controller side are both disabled.
> +
> +- ddr3_drv :		 When dram type is DDR3, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 DDR3_DS_40ohm.
> +
> +- ddr3_odt :		 When dram type is DDR3, this parameter define the
> +			 dram side ODT stength in ohm, default value is
> +			 DDR3_ODT_120ohm.
> +
> +- phy_ddr3_ca_drv :	 When dram type is DDR3, this parameter define the phy
> +			 side CA line(incluing command line, address line and
> +			 clock line) driver strength. default value is
> +			 PHY_DRV_ODT_40.
> +
> +- phy_ddr3_dq_drv :	 When dram type is DDR3, this parameter define the phy
> +			 side DQ line(incluing DQS/DQ/DM line) driver strength.
> +			 default value is PHY_DRV_ODT_40.
> +
> +- phy_ddr3_odt : 	 When dram type is DDR3, this parameter define the
> +			 phy side odt strength, default value is
> +			 PHY_DRV_ODT_240.
> +
> +- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt on
> +			 dram side and controller side are both disabled.
> +
> +- lpddr3_drv :		 When dram type is LPDDR3, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 LP3_DS_34ohm.
> +
> +- lpddr3_odt :		 When dram type is LPDDR3, this parameter define the
> +			 dram side ODT stength in ohm, default value is
> +			 LP3_ODT_240ohm.
> +
> +- phy_lpddr3_ca_drv :	 When dram type is LPDDR3, this parameter define the
> +			 phy side CA line(incluing command line, address line
> +			 and clock line) driver strength. default value is
> +			 PHY_DRV_ODT_40.
> +
> +- phy_lpddr3_dq_drv :	 When dram type is LPDDR3, this parameter define the
> +			 phy side DQ line(incluing DQS/DQ/DM line) driver
> +			 strength. default value is PHY_DRV_ODT_40.
> +
> +- phy_lpddr3_odt : 	 When dram type is LPDDR3, this parameter define the phy
> +			 side odt strength, default value is PHY_DRV_ODT_240.
> +
> +- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt on
> +			 dram side and controller side are both disabled.
> +
> +- lpddr4_drv :		 When dram type is LPDDR4, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 LP4_PDDS_60ohm.
> +
> +- lpddr4_dq_odt : 	 When dram type is LPDDR4, this parameter define the
> +			 dram side ODT on dqs/dq line stength in ohm, default
> +			 value is LP4_DQ_ODT_40ohm.
> +
> +- lpddr4_ca_odt :	 When dram type is LPDDR4, this parameter define the
> +			 dram side ODT on ca line stength in ohm, default value
> +			 is LP4_CA_ODT_40ohm.
> +
> +- phy_lpddr4_ca_drv :	 When dram type is LPDDR4, this parameter define the
> +			 phy side  CA line(incluing command address line)
> +			 driver strength. default value is PHY_DRV_ODT_40.
> +
> +- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the
> +			 phy side clock line and cs line driver strength.
> +			 default value is PHY_DRV_ODT_80.
> +
> +- phy_lpddr4_dq_drv :	 When dram type is LPDDR4, this parameter define the
> +			 phy side DQ line(incluing DQS/DQ/DM line) driver
> +			 strength. default value is PHY_DRV_ODT_80.
> +
> +- phy_lpddr4_odt :	 When dram type is LPDDR4, this parameter define the
> +			 phy side odt strength, default value is PHY_DRV_ODT_60.

It is good to explain the each field for ddr timing.
But, why you you drop the example for ddr timing values?
I think that you better to add the example for ddr timing values

> +
> +Example:
> +	dmc_opp_table: dmc_opp_table {
> +		compatible = "operating-points-v2";
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <666000000>;
> +			opp-microvolt = <900000>;
> +		};
> +	};
> +
> +	dmc: dmc {
> +		compatible = "rockchip,rk3399-dmc";
> +		devfreq-events = <&dfi>;
> +		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_DDRCLK>;
> +		clock-names = "dmc_clk";
> +		operating-points-v2 = <&dmc_opp_table>;
> +		center-supply = <&ppvar_centerlogic>;
> +		upthreshold = <15>;
> +		downdifferential = <10>;
> +		status = "disabled";
> +	};
> +
> 


-- 
Best Regards,
Chanwoo Choi

Re: [PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc

[Chanwoo Choi]

On 2016년 09월 02일 07:31, Lin Huang wrote:
> This patch adds the documentation for rockchip rk3399 dmc driver.
> 
> Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
> Changes in v8:
> - add ddr timing properties
> 
> Changes in v7:
> -None
> 
> Changes in v6:
> -Add more detail in Documentation
> 
> Changes in v5:
> -None
> 
> Changes in v4:
> -None
> 
> Changes in v3:
> -None
> 
> Changes in v2:
> -None 
> 
> Changes in v1:
> -None
> 
>  .../devicetree/bindings/devfreq/rk3399_dmc.txt     | 173 +++++++++++++++++++++
>  1 file changed, 173 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> 
> diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> new file mode 100644
> index 0000000..1f39b5cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
> @@ -0,0 +1,173 @@
> +* Rockchip rk3399 DMC(Dynamic Memory Controller) device
> +
> +Required properties:
> +- compatible:		 Must be "rockchip,rk3399-dmc".
> +- devfreq-events:	 Node to get DDR loading, Refer to
> +			 Documentation/devicetree/bindings/devfreq/
> +			 rockchip-dfi.txt
> +- interrupts:		 The interrupt number to the CPU. The interrupt
> +			 specifier format depends on the interrupt controller.
> +			 It should be DCF interrupts, when DDR dvfs finish,
> +			 it will happen.
> +- clocks:		 Phandles for clock specified in "clock-names" property
> +- clock-names :		 The name of clock used by the DFI, must be
> +			 "pclk_ddr_mon";
> +- operating-points-v2:	 Refer to Documentation/devicetree/bindings/power/opp.txt
> +			 for details.
> +- center-supply:	 DMC supply node.
> +- status:		 Marks the node enabled/disabled.
> +
> +Following properties are ddr timing:
> +
> +- dram_speed_bin :	 Value is defined at include/dt-bindings/clock/ddr.h,
> +			 it select ddr3 cl-trp-trcd type, default value
> +			 "DDR3_DEFAULT".it must selected according to
> +			 "Speed Bin" in ddr3 datasheet, DO NOT use smaller
> +			 "Speed Bin" than ddr3 exactly is.
> +
> +- pd_idle :		 Config the PD_IDLE value, defined the power-down idle
> +			 period, memories are places into power-down mode if
> +			 bus is idle for PD_IDLE DFI clocks.
> +
> +- sr_idle :		 Configure the SR_IDLE value, defined the selfrefresh
> +			 idle period, memories are places into self-refresh
> +			 mode if bus is idle for SR_IDLE*1024 DFI clocks
> +			 (DFI clocks freq is half of dram's clocks), defaule
> +			 value is "0".
> +
> +- sr_mc_gate_idle :	 Defined the self-refresh with memory and controller
> +			 clock gating idle period, memories are places into
> +			 self-refresh mode and memory controller clock arg
> +			 gating if bus is idle for sr_mc_gate_idle*1024 DFI
> +			 clocks.
> +
> +- srpd_lite_idle :	 Defined the self-refresh power down idle period,
> +			 memories are places into self-refresh power down
> +			 mode if bus is idle for srpd_lite_idle*1024 DFI
> +			 clocks. This parameter is for LPDDR4 only.
> +
> +- standby_idle :	 Defined the standby idle period, memories are places
> +			 into self-refresh than controller, pi, phy and dram
> +			 clock will gating if bus is idle for
> +			 standby_idle * DFI clocks.
> +
> +- dram_dll_disb_freq :	 It's defined the DDR3 dll bypass frequency in MHz
> +			 when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3
> +			 dll will bypssed note: if dll was bypassed, the
> +			 odt also stop working.
> +
> +- phy_dll_disb_freq :	 Defined the PHY dll bypass frequency in MHz (Mega Hz),
> +			 when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll
> +			 will bypssed. note: phy dll and phy odt are
> +			 independent
> +
> +- ddr3_odt_disb_freq :	 When dram type is DDR3, this parameter defined the
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt
> +			 on dram side and controller side are both disabled.
> +
> +- ddr3_drv :		 When dram type is DDR3, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 DDR3_DS_40ohm.
> +
> +- ddr3_odt :		 When dram type is DDR3, this parameter define the
> +			 dram side ODT stength in ohm, default value is
> +			 DDR3_ODT_120ohm.
> +
> +- phy_ddr3_ca_drv :	 When dram type is DDR3, this parameter define the phy
> +			 side CA line(incluing command line, address line and
> +			 clock line) driver strength. default value is
> +			 PHY_DRV_ODT_40.
> +
> +- phy_ddr3_dq_drv :	 When dram type is DDR3, this parameter define the phy
> +			 side DQ line(incluing DQS/DQ/DM line) driver strength.
> +			 default value is PHY_DRV_ODT_40.
> +
> +- phy_ddr3_odt : 	 When dram type is DDR3, this parameter define the
> +			 phy side odt strength, default value is
> +			 PHY_DRV_ODT_240.
> +
> +- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt on
> +			 dram side and controller side are both disabled.
> +
> +- lpddr3_drv :		 When dram type is LPDDR3, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 LP3_DS_34ohm.
> +
> +- lpddr3_odt :		 When dram type is LPDDR3, this parameter define the
> +			 dram side ODT stength in ohm, default value is
> +			 LP3_ODT_240ohm.
> +
> +- phy_lpddr3_ca_drv :	 When dram type is LPDDR3, this parameter define the
> +			 phy side CA line(incluing command line, address line
> +			 and clock line) driver strength. default value is
> +			 PHY_DRV_ODT_40.
> +
> +- phy_lpddr3_dq_drv :	 When dram type is LPDDR3, this parameter define the
> +			 phy side DQ line(incluing DQS/DQ/DM line) driver
> +			 strength. default value is PHY_DRV_ODT_40.
> +
> +- phy_lpddr3_odt : 	 When dram type is LPDDR3, this parameter define the phy
> +			 side odt strength, default value is PHY_DRV_ODT_240.
> +
> +- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the
> +			 odt disable frequency in MHz (Mega Hz), when ddr
> +			 frequency less then ddr3_odt_disb_freq, the odt on
> +			 dram side and controller side are both disabled.
> +
> +- lpddr4_drv :		 When dram type is LPDDR4, this parameter define the
> +			 dram side driver stength in ohm, default value is
> +			 LP4_PDDS_60ohm.
> +
> +- lpddr4_dq_odt : 	 When dram type is LPDDR4, this parameter define the
> +			 dram side ODT on dqs/dq line stength in ohm, default
> +			 value is LP4_DQ_ODT_40ohm.
> +
> +- lpddr4_ca_odt :	 When dram type is LPDDR4, this parameter define the
> +			 dram side ODT on ca line stength in ohm, default value
> +			 is LP4_CA_ODT_40ohm.
> +
> +- phy_lpddr4_ca_drv :	 When dram type is LPDDR4, this parameter define the
> +			 phy side  CA line(incluing command address line)
> +			 driver strength. default value is PHY_DRV_ODT_40.
> +
> +- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the
> +			 phy side clock line and cs line driver strength.
> +			 default value is PHY_DRV_ODT_80.
> +
> +- phy_lpddr4_dq_drv :	 When dram type is LPDDR4, this parameter define the
> +			 phy side DQ line(incluing DQS/DQ/DM line) driver
> +			 strength. default value is PHY_DRV_ODT_80.
> +
> +- phy_lpddr4_odt :	 When dram type is LPDDR4, this parameter define the
> +			 phy side odt strength, default value is PHY_DRV_ODT_60.

It is good to explain the each field for ddr timing.
But, why you you drop the example for ddr timing values?
I think that you better to add the example for ddr timing values

> +
> +Example:
> +	dmc_opp_table: dmc_opp_table {
> +		compatible = "operating-points-v2";
> +
> +		opp00 {
> +			opp-hz = /bits/ 64 <300000000>;
> +			opp-microvolt = <900000>;
> +		};
> +		opp01 {
> +			opp-hz = /bits/ 64 <666000000>;
> +			opp-microvolt = <900000>;
> +		};
> +	};
> +
> +	dmc: dmc {
> +		compatible = "rockchip,rk3399-dmc";
> +		devfreq-events = <&dfi>;
> +		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&cru SCLK_DDRCLK>;
> +		clock-names = "dmc_clk";
> +		operating-points-v2 = <&dmc_opp_table>;
> +		center-supply = <&ppvar_centerlogic>;
> +		upthreshold = <15>;
> +		downdifferential = <10>;
> +		status = "disabled";
> +	};
> +
> 


-- 
Best Regards,
Chanwoo Choi
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[PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Lin Huang]

base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: MyngJoo Ham <myngjoo.ham@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Changes in v8:
- do not use ddr_timing node, get ddr timing directly

Changes in v7:
- remove a blank line

Changes in v6:
- fix some nit suggest by Chanwoo Choi

Changes in v5:
- improve dmc driver suggest by Chanwoo Choi

Changes in v4:
- use arm_smccc_smc() function talk to bl31
- delete rockchip_dmc.c file and config
- delete dmc_notify
- adjust probe order

Changes in v3:
- operate dram setting through sip call
- imporve set rate flow

Changes in v2:
- None

Changes in v1:
- move dfi controller to event
- fix set voltage sequence when set rate fail
- change Kconfig type from tristate to bool
- move unuse EXPORT_SYMBOL_GPL()

 drivers/devfreq/Kconfig      |  11 +
 drivers/devfreq/Makefile     |   1 +
 drivers/devfreq/rk3399_dmc.c | 480 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 492 insertions(+)
 create mode 100644 drivers/devfreq/rk3399_dmc.c

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index a5be56e..e848121 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -100,6 +100,17 @@ config ARM_TEGRA_DEVFREQ
          It reads ACTMON counters of memory controllers and adjusts the
          operating frequencies and voltages with OPP support.
 
+config ARM_RK3399_DMC_DEVFREQ
+	tristate "ARM RK3399 DMC DEVFREQ Driver"
+	depends on ARCH_ROCKCHIP
+	select DEVFREQ_EVENT_ROCKCHIP_DFI
+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select PM_OPP
+	help
+          This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
+          It sets the frequency for the memory controller and reads the usage counts
+          from hardware.
+
 source "drivers/devfreq/event/Kconfig"
 
 endif # PM_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 09f11d9..fbff40a 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE)	+= governor_passive.o
 
 # DEVFREQ Drivers
 obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o
+obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
 obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra-devfreq.o
 
 # DEVFREQ Event Drivers
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
new file mode 100644
index 0000000..54d65f2
--- /dev/null
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -0,0 +1,480 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Lin Huang <hl@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/rwsem.h>
+#include <linux/suspend.h>
+
+#include <soc/rockchip/rockchip_sip.h>
+
+struct dram_timing {
+	unsigned int ddr3_speed_bin;
+	unsigned int pd_idle;
+	unsigned int sr_idle;
+	unsigned int sr_mc_gate_idle;
+	unsigned int srpd_lite_idle;
+	unsigned int standby_idle;
+	unsigned int auto_pd_dis_freq;
+	unsigned int dram_dll_dis_freq;
+	unsigned int phy_dll_dis_freq;
+	unsigned int ddr3_odt_dis_freq;
+	unsigned int ddr3_drv;
+	unsigned int ddr3_odt;
+	unsigned int phy_ddr3_ca_drv;
+	unsigned int phy_ddr3_dq_drv;
+	unsigned int phy_ddr3_odt;
+	unsigned int lpddr3_odt_dis_freq;
+	unsigned int lpddr3_drv;
+	unsigned int lpddr3_odt;
+	unsigned int phy_lpddr3_ca_drv;
+	unsigned int phy_lpddr3_dq_drv;
+	unsigned int phy_lpddr3_odt;
+	unsigned int lpddr4_odt_dis_freq;
+	unsigned int lpddr4_drv;
+	unsigned int lpddr4_dq_odt;
+	unsigned int lpddr4_ca_odt;
+	unsigned int phy_lpddr4_ca_drv;
+	unsigned int phy_lpddr4_ck_cs_drv;
+	unsigned int phy_lpddr4_dq_drv;
+	unsigned int phy_lpddr4_odt;
+};
+
+struct rk3399_dmcfreq {
+	struct device *dev;
+	struct devfreq *devfreq;
+	struct devfreq_simple_ondemand_data ondemand_data;
+	struct clk *dmc_clk;
+	struct devfreq_event_dev *edev;
+	struct mutex lock;
+	struct dram_timing timing;
+
+	/*
+	 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
+	 * conversion without the participation of CPU, we will implement and
+	 * control it in arm trust firmware.
+	 */
+	wait_queue_head_t	wait_dcf_queue;
+	int irq;
+	int wait_dcf_flag;
+	struct regulator *vdd_center;
+	unsigned long rate, target_rate;
+	unsigned long volt, target_volt;
+	struct dev_pm_opp *curr_opp;
+};
+
+static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+				 u32 flags)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	struct dev_pm_opp *opp;
+	unsigned long old_clk_rate = dmcfreq->rate;
+	unsigned long target_volt, target_rate;
+	int err;
+
+	rcu_read_lock();
+	opp = devfreq_recommended_opp(dev, freq, flags);
+	if (IS_ERR(opp)) {
+		rcu_read_unlock();
+		return PTR_ERR(opp);
+	}
+
+	target_rate = dev_pm_opp_get_freq(opp);
+	target_volt = dev_pm_opp_get_voltage(opp);
+
+	dmcfreq->rate = dev_pm_opp_get_freq(dmcfreq->curr_opp);
+	dmcfreq->volt = dev_pm_opp_get_voltage(dmcfreq->curr_opp);
+
+	rcu_read_unlock();
+
+	if (dmcfreq->rate == target_rate)
+		return 0;
+
+	mutex_lock(&dmcfreq->lock);
+
+	/*
+	 * If frequency scaling from low to high, adjust voltage first.
+	 * If frequency scaling from high to low, adjust frequency first.
+	 */
+	if (old_clk_rate < target_rate) {
+		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+					    target_volt);
+		if (err) {
+			dev_err(dev, "Cannot to set voltage %lu uV\n",
+				target_volt);
+			goto out;
+		}
+	}
+	dmcfreq->wait_dcf_flag = 1;
+
+	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
+	if (err) {
+		dev_err(dev, "Cannot to set frequency %lu (%d)\n",
+			target_rate, err);
+		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+				      dmcfreq->volt);
+		goto out;
+	}
+
+	/*
+	 * Wait until bcf irq happen, it means freq scaling finish in
+	 * arm trust firmware, use 100ms as timeout time.
+	 */
+	if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
+				!dmcfreq->wait_dcf_flag, HZ / 10))
+		dev_warn(dev, "Timeout waiting for dcf interrupt\n");
+
+	/*
+	 * Check the dpll rate,
+	 * There only two result we will get,
+	 * 1. Ddr frequency scaling fail, we still get the old rate.
+	 * 2. Ddr frequency scaling sucessful, we get the rate we set.
+	 */
+	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
+
+	/* If get the incorrect rate, set voltage to old value. */
+	if (dmcfreq->rate != target_rate) {
+		dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
+			Current frequency %lu\n", target_rate, dmcfreq->rate);
+		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+				      dmcfreq->volt);
+		goto out;
+	} else if (old_clk_rate > target_rate)
+		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+					    target_volt);
+	if (err)
+		dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
+
+	dmcfreq->curr_opp = opp;
+out:
+	mutex_unlock(&dmcfreq->lock);
+	return err;
+}
+
+static int rk3399_dmcfreq_get_dev_status(struct device *dev,
+					 struct devfreq_dev_status *stat)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	struct devfreq_event_data edata;
+	int ret = 0;
+
+	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
+	if (ret < 0)
+		return ret;
+
+	stat->current_frequency = dmcfreq->rate;
+	stat->busy_time = edata.load_count;
+	stat->total_time = edata.total_count;
+
+	return ret;
+}
+
+static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+
+	*freq = dmcfreq->rate;
+
+	return 0;
+}
+
+static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
+	.polling_ms	= 200,
+	.target		= rk3399_dmcfreq_target,
+	.get_dev_status	= rk3399_dmcfreq_get_dev_status,
+	.get_cur_freq	= rk3399_dmcfreq_get_cur_freq,
+};
+
+static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = devfreq_event_disable_edev(dmcfreq->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to disable the devfreq-event devices\n");
+		return ret;
+	}
+
+	ret = devfreq_suspend_device(dmcfreq->devfreq);
+	if (ret < 0) {
+		dev_err(dev, "failed to suspend the devfreq devices\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = devfreq_event_enable_edev(dmcfreq->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable the devfreq-event devices\n");
+		return ret;
+	}
+
+	ret = devfreq_resume_device(dmcfreq->devfreq);
+	if (ret < 0) {
+		dev_err(dev, "failed to resume the devfreq devices\n");
+		return ret;
+	}
+	return ret;
+}
+
+static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
+			 rk3399_dmcfreq_resume);
+
+static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_id;
+	struct arm_smccc_res res;
+
+	dmcfreq->wait_dcf_flag = 0;
+	wake_up(&dmcfreq->wait_dcf_queue);
+
+	/* Clear the DCF interrupt */
+	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+		      ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
+		      0, 0, 0, 0, &res);
+
+	return IRQ_HANDLED;
+}
+
+static int of_get_ddr_timings(struct dram_timing *timing,
+			      struct device_node *np)
+{
+	int ret = 0;
+
+	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
+				   &timing->ddr3_speed_bin);
+	ret |= of_property_read_u32(np, "rockchip,pd_idle",
+				    &timing->pd_idle);
+	ret |= of_property_read_u32(np, "rockchip,sr_idle",
+				    &timing->sr_idle);
+	ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
+				    &timing->sr_mc_gate_idle);
+	ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
+				    &timing->srpd_lite_idle);
+	ret |= of_property_read_u32(np, "rockchip,standby_idle",
+				    &timing->standby_idle);
+	ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
+				    &timing->auto_pd_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
+				    &timing->dram_dll_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
+				    &timing->phy_dll_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
+				    &timing->ddr3_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
+				    &timing->ddr3_drv);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
+				    &timing->ddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
+				    &timing->phy_ddr3_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
+				    &timing->phy_ddr3_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
+				    &timing->phy_ddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
+				    &timing->lpddr3_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
+				    &timing->lpddr3_drv);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
+				    &timing->lpddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
+				    &timing->phy_lpddr3_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
+				    &timing->phy_lpddr3_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
+				    &timing->phy_lpddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
+				    &timing->lpddr4_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
+				    &timing->lpddr4_drv);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
+				    &timing->lpddr4_dq_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
+				    &timing->lpddr4_ca_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
+				    &timing->phy_lpddr4_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
+				    &timing->phy_lpddr4_ck_cs_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
+				    &timing->phy_lpddr4_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
+				    &timing->phy_lpddr4_odt);
+
+	return ret;
+}
+
+static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+{
+	struct arm_smccc_res res;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = pdev->dev.of_node;
+	struct rk3399_dmcfreq *data;
+	int ret, irq, index, size;
+	uint32_t *timing;
+	struct dev_pm_opp *opp;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
+		return -EINVAL;
+	}
+	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	mutex_init(&data->lock);
+
+	data->vdd_center = devm_regulator_get(dev, "center");
+	if (IS_ERR(data->vdd_center)) {
+		dev_err(dev, "Cannot get the regulator \"center\"\n");
+		return PTR_ERR(data->vdd_center);
+	}
+
+	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
+	if (IS_ERR(data->dmc_clk)) {
+		dev_err(dev, "Cannot get the clk dmc_clk\n");
+		return PTR_ERR(data->dmc_clk);
+	};
+
+	data->irq = irq;
+	ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
+			       dev_name(dev), data);
+	if (ret) {
+		dev_err(dev, "Failed to request dmc irq: %d\n", ret);
+		return ret;
+	}
+
+	init_waitqueue_head(&data->wait_dcf_queue);
+	data->wait_dcf_flag = 0;
+
+	data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
+	if (IS_ERR(data->edev))
+		return -EPROBE_DEFER;
+
+	ret = devfreq_event_enable_edev(data->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable devfreq-event devices\n");
+		return ret;
+	}
+
+	/*
+	 * Get dram timing and pass it to arm trust firmware,
+	 * the dram drvier in arm trust firmware will get these
+	 * timing and to do dram initial.
+	 */
+	if (!of_get_ddr_timings(&data->timing, np)) {
+		timing = &data->timing.ddr3_speed_bin;
+		size = sizeof(struct dram_timing) / 4;
+		for (index = 0; index < size; index++) {
+			arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
+				      ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
+				      0, 0, 0, 0, &res);
+			if (res.a0) {
+				dev_err(dev, "Failed to set dram param: %ld\n",
+					res.a0);
+				return -EINVAL;
+			}
+		}
+	}
+
+	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+		      ROCKCHIP_SIP_CONFIG_DRAM_INIT,
+		      0, 0, 0, 0, &res);
+
+	/*
+	 * We add a devfreq driver to our parent since it has a device tree node
+	 * with operating points.
+	 */
+	if (dev_pm_opp_of_add_table(dev)) {
+		dev_err(dev, "Invalid operating-points in device tree.\n");
+		rcu_read_unlock();
+		return -EINVAL;
+	}
+
+	of_property_read_u32(np, "upthreshold",
+			     &data->ondemand_data.upthreshold);
+	of_property_read_u32(np, "downdifferential",
+			     &data->ondemand_data.downdifferential);
+
+	data->rate = clk_get_rate(data->dmc_clk);
+
+	rcu_read_lock();
+	opp = devfreq_recommended_opp(dev, &data->rate, 0);
+	if (IS_ERR(opp)) {
+		rcu_read_unlock();
+		return PTR_ERR(opp);
+	}
+	rcu_read_unlock();
+	data->curr_opp = opp;
+
+	rk3399_devfreq_dmc_profile.initial_freq = data->rate;
+
+	data->devfreq = devfreq_add_device(dev,
+					   &rk3399_devfreq_dmc_profile,
+					   "simple_ondemand",
+					   &data->ondemand_data);
+	if (IS_ERR(data->devfreq))
+		return PTR_ERR(data->devfreq);
+	devm_devfreq_register_opp_notifier(dev, data->devfreq);
+
+	data->dev = dev;
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+}
+
+static int rk3399_dmcfreq_remove(struct platform_device *pdev)
+{
+	struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);
+
+	regulator_put(dmcfreq->vdd_center);
+
+	return 0;
+}
+
+static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
+	{ .compatible = "rockchip,rk3399-dmc" },
+	{ },
+};
+
+static struct platform_driver rk3399_dmcfreq_driver = {
+	.probe	= rk3399_dmcfreq_probe,
+	.remove	= rk3399_dmcfreq_remove,
+	.driver = {
+		.name	= "rk3399-dmc-freq",
+		.pm	= &rk3399_dmcfreq_pm,
+		.of_match_table = rk3399dmc_devfreq_of_match,
+	},
+};
+module_platform_driver(rk3399_dmcfreq_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
+MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
-- 
2.6.6

[PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Lin Huang]

base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: MyngJoo Ham <myngjoo.ham@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Changes in v8:
- do not use ddr_timing node, get ddr timing directly

Changes in v7:
- remove a blank line

Changes in v6:
- fix some nit suggest by Chanwoo Choi

Changes in v5:
- improve dmc driver suggest by Chanwoo Choi

Changes in v4:
- use arm_smccc_smc() function talk to bl31
- delete rockchip_dmc.c file and config
- delete dmc_notify
- adjust probe order

Changes in v3:
- operate dram setting through sip call
- imporve set rate flow

Changes in v2:
- None

Changes in v1:
- move dfi controller to event
- fix set voltage sequence when set rate fail
- change Kconfig type from tristate to bool
- move unuse EXPORT_SYMBOL_GPL()

 drivers/devfreq/Kconfig      |  11 +
 drivers/devfreq/Makefile     |   1 +
 drivers/devfreq/rk3399_dmc.c | 480 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 492 insertions(+)
 create mode 100644 drivers/devfreq/rk3399_dmc.c

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index a5be56e..e848121 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -100,6 +100,17 @@ config ARM_TEGRA_DEVFREQ
          It reads ACTMON counters of memory controllers and adjusts the
          operating frequencies and voltages with OPP support.
 
+config ARM_RK3399_DMC_DEVFREQ
+	tristate "ARM RK3399 DMC DEVFREQ Driver"
+	depends on ARCH_ROCKCHIP
+	select DEVFREQ_EVENT_ROCKCHIP_DFI
+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select PM_OPP
+	help
+          This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
+          It sets the frequency for the memory controller and reads the usage counts
+          from hardware.
+
 source "drivers/devfreq/event/Kconfig"
 
 endif # PM_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 09f11d9..fbff40a 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE)	+= governor_passive.o
 
 # DEVFREQ Drivers
 obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o
+obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
 obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra-devfreq.o
 
 # DEVFREQ Event Drivers
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
new file mode 100644
index 0000000..54d65f2
--- /dev/null
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -0,0 +1,480 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Lin Huang <hl@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/rwsem.h>
+#include <linux/suspend.h>
+
+#include <soc/rockchip/rockchip_sip.h>
+
+struct dram_timing {
+	unsigned int ddr3_speed_bin;
+	unsigned int pd_idle;
+	unsigned int sr_idle;
+	unsigned int sr_mc_gate_idle;
+	unsigned int srpd_lite_idle;
+	unsigned int standby_idle;
+	unsigned int auto_pd_dis_freq;
+	unsigned int dram_dll_dis_freq;
+	unsigned int phy_dll_dis_freq;
+	unsigned int ddr3_odt_dis_freq;
+	unsigned int ddr3_drv;
+	unsigned int ddr3_odt;
+	unsigned int phy_ddr3_ca_drv;
+	unsigned int phy_ddr3_dq_drv;
+	unsigned int phy_ddr3_odt;
+	unsigned int lpddr3_odt_dis_freq;
+	unsigned int lpddr3_drv;
+	unsigned int lpddr3_odt;
+	unsigned int phy_lpddr3_ca_drv;
+	unsigned int phy_lpddr3_dq_drv;
+	unsigned int phy_lpddr3_odt;
+	unsigned int lpddr4_odt_dis_freq;
+	unsigned int lpddr4_drv;
+	unsigned int lpddr4_dq_odt;
+	unsigned int lpddr4_ca_odt;
+	unsigned int phy_lpddr4_ca_drv;
+	unsigned int phy_lpddr4_ck_cs_drv;
+	unsigned int phy_lpddr4_dq_drv;
+	unsigned int phy_lpddr4_odt;
+};
+
+struct rk3399_dmcfreq {
+	struct device *dev;
+	struct devfreq *devfreq;
+	struct devfreq_simple_ondemand_data ondemand_data;
+	struct clk *dmc_clk;
+	struct devfreq_event_dev *edev;
+	struct mutex lock;
+	struct dram_timing timing;
+
+	/*
+	 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
+	 * conversion without the participation of CPU, we will implement and
+	 * control it in arm trust firmware.
+	 */
+	wait_queue_head_t	wait_dcf_queue;
+	int irq;
+	int wait_dcf_flag;
+	struct regulator *vdd_center;
+	unsigned long rate, target_rate;
+	unsigned long volt, target_volt;
+	struct dev_pm_opp *curr_opp;
+};
+
+static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+				 u32 flags)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	struct dev_pm_opp *opp;
+	unsigned long old_clk_rate = dmcfreq->rate;
+	unsigned long target_volt, target_rate;
+	int err;
+
+	rcu_read_lock();
+	opp = devfreq_recommended_opp(dev, freq, flags);
+	if (IS_ERR(opp)) {
+		rcu_read_unlock();
+		return PTR_ERR(opp);
+	}
+
+	target_rate = dev_pm_opp_get_freq(opp);
+	target_volt = dev_pm_opp_get_voltage(opp);
+
+	dmcfreq->rate = dev_pm_opp_get_freq(dmcfreq->curr_opp);
+	dmcfreq->volt = dev_pm_opp_get_voltage(dmcfreq->curr_opp);
+
+	rcu_read_unlock();
+
+	if (dmcfreq->rate == target_rate)
+		return 0;
+
+	mutex_lock(&dmcfreq->lock);
+
+	/*
+	 * If frequency scaling from low to high, adjust voltage first.
+	 * If frequency scaling from high to low, adjust frequency first.
+	 */
+	if (old_clk_rate < target_rate) {
+		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+					    target_volt);
+		if (err) {
+			dev_err(dev, "Cannot to set voltage %lu uV\n",
+				target_volt);
+			goto out;
+		}
+	}
+	dmcfreq->wait_dcf_flag = 1;
+
+	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
+	if (err) {
+		dev_err(dev, "Cannot to set frequency %lu (%d)\n",
+			target_rate, err);
+		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+				      dmcfreq->volt);
+		goto out;
+	}
+
+	/*
+	 * Wait until bcf irq happen, it means freq scaling finish in
+	 * arm trust firmware, use 100ms as timeout time.
+	 */
+	if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
+				!dmcfreq->wait_dcf_flag, HZ / 10))
+		dev_warn(dev, "Timeout waiting for dcf interrupt\n");
+
+	/*
+	 * Check the dpll rate,
+	 * There only two result we will get,
+	 * 1. Ddr frequency scaling fail, we still get the old rate.
+	 * 2. Ddr frequency scaling sucessful, we get the rate we set.
+	 */
+	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
+
+	/* If get the incorrect rate, set voltage to old value. */
+	if (dmcfreq->rate != target_rate) {
+		dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
+			Current frequency %lu\n", target_rate, dmcfreq->rate);
+		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+				      dmcfreq->volt);
+		goto out;
+	} else if (old_clk_rate > target_rate)
+		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+					    target_volt);
+	if (err)
+		dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
+
+	dmcfreq->curr_opp = opp;
+out:
+	mutex_unlock(&dmcfreq->lock);
+	return err;
+}
+
+static int rk3399_dmcfreq_get_dev_status(struct device *dev,
+					 struct devfreq_dev_status *stat)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	struct devfreq_event_data edata;
+	int ret = 0;
+
+	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
+	if (ret < 0)
+		return ret;
+
+	stat->current_frequency = dmcfreq->rate;
+	stat->busy_time = edata.load_count;
+	stat->total_time = edata.total_count;
+
+	return ret;
+}
+
+static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+
+	*freq = dmcfreq->rate;
+
+	return 0;
+}
+
+static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
+	.polling_ms	= 200,
+	.target		= rk3399_dmcfreq_target,
+	.get_dev_status	= rk3399_dmcfreq_get_dev_status,
+	.get_cur_freq	= rk3399_dmcfreq_get_cur_freq,
+};
+
+static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = devfreq_event_disable_edev(dmcfreq->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to disable the devfreq-event devices\n");
+		return ret;
+	}
+
+	ret = devfreq_suspend_device(dmcfreq->devfreq);
+	if (ret < 0) {
+		dev_err(dev, "failed to suspend the devfreq devices\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = devfreq_event_enable_edev(dmcfreq->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable the devfreq-event devices\n");
+		return ret;
+	}
+
+	ret = devfreq_resume_device(dmcfreq->devfreq);
+	if (ret < 0) {
+		dev_err(dev, "failed to resume the devfreq devices\n");
+		return ret;
+	}
+	return ret;
+}
+
+static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
+			 rk3399_dmcfreq_resume);
+
+static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_id;
+	struct arm_smccc_res res;
+
+	dmcfreq->wait_dcf_flag = 0;
+	wake_up(&dmcfreq->wait_dcf_queue);
+
+	/* Clear the DCF interrupt */
+	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+		      ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
+		      0, 0, 0, 0, &res);
+
+	return IRQ_HANDLED;
+}
+
+static int of_get_ddr_timings(struct dram_timing *timing,
+			      struct device_node *np)
+{
+	int ret = 0;
+
+	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
+				   &timing->ddr3_speed_bin);
+	ret |= of_property_read_u32(np, "rockchip,pd_idle",
+				    &timing->pd_idle);
+	ret |= of_property_read_u32(np, "rockchip,sr_idle",
+				    &timing->sr_idle);
+	ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
+				    &timing->sr_mc_gate_idle);
+	ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
+				    &timing->srpd_lite_idle);
+	ret |= of_property_read_u32(np, "rockchip,standby_idle",
+				    &timing->standby_idle);
+	ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
+				    &timing->auto_pd_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
+				    &timing->dram_dll_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
+				    &timing->phy_dll_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
+				    &timing->ddr3_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
+				    &timing->ddr3_drv);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
+				    &timing->ddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
+				    &timing->phy_ddr3_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
+				    &timing->phy_ddr3_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
+				    &timing->phy_ddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
+				    &timing->lpddr3_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
+				    &timing->lpddr3_drv);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
+				    &timing->lpddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
+				    &timing->phy_lpddr3_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
+				    &timing->phy_lpddr3_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
+				    &timing->phy_lpddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
+				    &timing->lpddr4_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
+				    &timing->lpddr4_drv);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
+				    &timing->lpddr4_dq_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
+				    &timing->lpddr4_ca_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
+				    &timing->phy_lpddr4_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
+				    &timing->phy_lpddr4_ck_cs_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
+				    &timing->phy_lpddr4_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
+				    &timing->phy_lpddr4_odt);
+
+	return ret;
+}
+
+static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+{
+	struct arm_smccc_res res;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = pdev->dev.of_node;
+	struct rk3399_dmcfreq *data;
+	int ret, irq, index, size;
+	uint32_t *timing;
+	struct dev_pm_opp *opp;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
+		return -EINVAL;
+	}
+	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	mutex_init(&data->lock);
+
+	data->vdd_center = devm_regulator_get(dev, "center");
+	if (IS_ERR(data->vdd_center)) {
+		dev_err(dev, "Cannot get the regulator \"center\"\n");
+		return PTR_ERR(data->vdd_center);
+	}
+
+	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
+	if (IS_ERR(data->dmc_clk)) {
+		dev_err(dev, "Cannot get the clk dmc_clk\n");
+		return PTR_ERR(data->dmc_clk);
+	};
+
+	data->irq = irq;
+	ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
+			       dev_name(dev), data);
+	if (ret) {
+		dev_err(dev, "Failed to request dmc irq: %d\n", ret);
+		return ret;
+	}
+
+	init_waitqueue_head(&data->wait_dcf_queue);
+	data->wait_dcf_flag = 0;
+
+	data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
+	if (IS_ERR(data->edev))
+		return -EPROBE_DEFER;
+
+	ret = devfreq_event_enable_edev(data->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable devfreq-event devices\n");
+		return ret;
+	}
+
+	/*
+	 * Get dram timing and pass it to arm trust firmware,
+	 * the dram drvier in arm trust firmware will get these
+	 * timing and to do dram initial.
+	 */
+	if (!of_get_ddr_timings(&data->timing, np)) {
+		timing = &data->timing.ddr3_speed_bin;
+		size = sizeof(struct dram_timing) / 4;
+		for (index = 0; index < size; index++) {
+			arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
+				      ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
+				      0, 0, 0, 0, &res);
+			if (res.a0) {
+				dev_err(dev, "Failed to set dram param: %ld\n",
+					res.a0);
+				return -EINVAL;
+			}
+		}
+	}
+
+	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+		      ROCKCHIP_SIP_CONFIG_DRAM_INIT,
+		      0, 0, 0, 0, &res);
+
+	/*
+	 * We add a devfreq driver to our parent since it has a device tree node
+	 * with operating points.
+	 */
+	if (dev_pm_opp_of_add_table(dev)) {
+		dev_err(dev, "Invalid operating-points in device tree.\n");
+		rcu_read_unlock();
+		return -EINVAL;
+	}
+
+	of_property_read_u32(np, "upthreshold",
+			     &data->ondemand_data.upthreshold);
+	of_property_read_u32(np, "downdifferential",
+			     &data->ondemand_data.downdifferential);
+
+	data->rate = clk_get_rate(data->dmc_clk);
+
+	rcu_read_lock();
+	opp = devfreq_recommended_opp(dev, &data->rate, 0);
+	if (IS_ERR(opp)) {
+		rcu_read_unlock();
+		return PTR_ERR(opp);
+	}
+	rcu_read_unlock();
+	data->curr_opp = opp;
+
+	rk3399_devfreq_dmc_profile.initial_freq = data->rate;
+
+	data->devfreq = devfreq_add_device(dev,
+					   &rk3399_devfreq_dmc_profile,
+					   "simple_ondemand",
+					   &data->ondemand_data);
+	if (IS_ERR(data->devfreq))
+		return PTR_ERR(data->devfreq);
+	devm_devfreq_register_opp_notifier(dev, data->devfreq);
+
+	data->dev = dev;
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+}
+
+static int rk3399_dmcfreq_remove(struct platform_device *pdev)
+{
+	struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);
+
+	regulator_put(dmcfreq->vdd_center);
+
+	return 0;
+}
+
+static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
+	{ .compatible = "rockchip,rk3399-dmc" },
+	{ },
+};
+
+static struct platform_driver rk3399_dmcfreq_driver = {
+	.probe	= rk3399_dmcfreq_probe,
+	.remove	= rk3399_dmcfreq_remove,
+	.driver = {
+		.name	= "rk3399-dmc-freq",
+		.pm	= &rk3399_dmcfreq_pm,
+		.of_match_table = rk3399dmc_devfreq_of_match,
+	},
+};
+module_platform_driver(rk3399_dmcfreq_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>");
+MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
-- 
2.6.6

[PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Lin Huang]

base on dfi result, we do ddr frequency scaling, register
dmc driver to devfreq framework, and use simple-ondemand
policy.

Signed-off-by: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: MyngJoo Ham <myngjoo.ham-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Reviewed-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
Changes in v8:
- do not use ddr_timing node, get ddr timing directly

Changes in v7:
- remove a blank line

Changes in v6:
- fix some nit suggest by Chanwoo Choi

Changes in v5:
- improve dmc driver suggest by Chanwoo Choi

Changes in v4:
- use arm_smccc_smc() function talk to bl31
- delete rockchip_dmc.c file and config
- delete dmc_notify
- adjust probe order

Changes in v3:
- operate dram setting through sip call
- imporve set rate flow

Changes in v2:
- None

Changes in v1:
- move dfi controller to event
- fix set voltage sequence when set rate fail
- change Kconfig type from tristate to bool
- move unuse EXPORT_SYMBOL_GPL()

 drivers/devfreq/Kconfig      |  11 +
 drivers/devfreq/Makefile     |   1 +
 drivers/devfreq/rk3399_dmc.c | 480 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 492 insertions(+)
 create mode 100644 drivers/devfreq/rk3399_dmc.c

diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index a5be56e..e848121 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -100,6 +100,17 @@ config ARM_TEGRA_DEVFREQ
          It reads ACTMON counters of memory controllers and adjusts the
          operating frequencies and voltages with OPP support.
 
+config ARM_RK3399_DMC_DEVFREQ
+	tristate "ARM RK3399 DMC DEVFREQ Driver"
+	depends on ARCH_ROCKCHIP
+	select DEVFREQ_EVENT_ROCKCHIP_DFI
+	select DEVFREQ_GOV_SIMPLE_ONDEMAND
+	select PM_OPP
+	help
+          This adds the DEVFREQ driver for the RK3399 DMC(Dynamic Memory Controller).
+          It sets the frequency for the memory controller and reads the usage counts
+          from hardware.
+
 source "drivers/devfreq/event/Kconfig"
 
 endif # PM_DEVFREQ
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 09f11d9..fbff40a 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE)	+= governor_passive.o
 
 # DEVFREQ Drivers
 obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ)	+= exynos-bus.o
+obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ)	+= rk3399_dmc.o
 obj-$(CONFIG_ARM_TEGRA_DEVFREQ)		+= tegra-devfreq.o
 
 # DEVFREQ Event Drivers
diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
new file mode 100644
index 0000000..54d65f2
--- /dev/null
+++ b/drivers/devfreq/rk3399_dmc.c
@@ -0,0 +1,480 @@
+/*
+ * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+#include <linux/rwsem.h>
+#include <linux/suspend.h>
+
+#include <soc/rockchip/rockchip_sip.h>
+
+struct dram_timing {
+	unsigned int ddr3_speed_bin;
+	unsigned int pd_idle;
+	unsigned int sr_idle;
+	unsigned int sr_mc_gate_idle;
+	unsigned int srpd_lite_idle;
+	unsigned int standby_idle;
+	unsigned int auto_pd_dis_freq;
+	unsigned int dram_dll_dis_freq;
+	unsigned int phy_dll_dis_freq;
+	unsigned int ddr3_odt_dis_freq;
+	unsigned int ddr3_drv;
+	unsigned int ddr3_odt;
+	unsigned int phy_ddr3_ca_drv;
+	unsigned int phy_ddr3_dq_drv;
+	unsigned int phy_ddr3_odt;
+	unsigned int lpddr3_odt_dis_freq;
+	unsigned int lpddr3_drv;
+	unsigned int lpddr3_odt;
+	unsigned int phy_lpddr3_ca_drv;
+	unsigned int phy_lpddr3_dq_drv;
+	unsigned int phy_lpddr3_odt;
+	unsigned int lpddr4_odt_dis_freq;
+	unsigned int lpddr4_drv;
+	unsigned int lpddr4_dq_odt;
+	unsigned int lpddr4_ca_odt;
+	unsigned int phy_lpddr4_ca_drv;
+	unsigned int phy_lpddr4_ck_cs_drv;
+	unsigned int phy_lpddr4_dq_drv;
+	unsigned int phy_lpddr4_odt;
+};
+
+struct rk3399_dmcfreq {
+	struct device *dev;
+	struct devfreq *devfreq;
+	struct devfreq_simple_ondemand_data ondemand_data;
+	struct clk *dmc_clk;
+	struct devfreq_event_dev *edev;
+	struct mutex lock;
+	struct dram_timing timing;
+
+	/*
+	 * DDR Converser of Frequency (DCF) is used to implement DDR frequency
+	 * conversion without the participation of CPU, we will implement and
+	 * control it in arm trust firmware.
+	 */
+	wait_queue_head_t	wait_dcf_queue;
+	int irq;
+	int wait_dcf_flag;
+	struct regulator *vdd_center;
+	unsigned long rate, target_rate;
+	unsigned long volt, target_volt;
+	struct dev_pm_opp *curr_opp;
+};
+
+static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq,
+				 u32 flags)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	struct dev_pm_opp *opp;
+	unsigned long old_clk_rate = dmcfreq->rate;
+	unsigned long target_volt, target_rate;
+	int err;
+
+	rcu_read_lock();
+	opp = devfreq_recommended_opp(dev, freq, flags);
+	if (IS_ERR(opp)) {
+		rcu_read_unlock();
+		return PTR_ERR(opp);
+	}
+
+	target_rate = dev_pm_opp_get_freq(opp);
+	target_volt = dev_pm_opp_get_voltage(opp);
+
+	dmcfreq->rate = dev_pm_opp_get_freq(dmcfreq->curr_opp);
+	dmcfreq->volt = dev_pm_opp_get_voltage(dmcfreq->curr_opp);
+
+	rcu_read_unlock();
+
+	if (dmcfreq->rate == target_rate)
+		return 0;
+
+	mutex_lock(&dmcfreq->lock);
+
+	/*
+	 * If frequency scaling from low to high, adjust voltage first.
+	 * If frequency scaling from high to low, adjust frequency first.
+	 */
+	if (old_clk_rate < target_rate) {
+		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+					    target_volt);
+		if (err) {
+			dev_err(dev, "Cannot to set voltage %lu uV\n",
+				target_volt);
+			goto out;
+		}
+	}
+	dmcfreq->wait_dcf_flag = 1;
+
+	err = clk_set_rate(dmcfreq->dmc_clk, target_rate);
+	if (err) {
+		dev_err(dev, "Cannot to set frequency %lu (%d)\n",
+			target_rate, err);
+		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+				      dmcfreq->volt);
+		goto out;
+	}
+
+	/*
+	 * Wait until bcf irq happen, it means freq scaling finish in
+	 * arm trust firmware, use 100ms as timeout time.
+	 */
+	if (!wait_event_timeout(dmcfreq->wait_dcf_queue,
+				!dmcfreq->wait_dcf_flag, HZ / 10))
+		dev_warn(dev, "Timeout waiting for dcf interrupt\n");
+
+	/*
+	 * Check the dpll rate,
+	 * There only two result we will get,
+	 * 1. Ddr frequency scaling fail, we still get the old rate.
+	 * 2. Ddr frequency scaling sucessful, we get the rate we set.
+	 */
+	dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk);
+
+	/* If get the incorrect rate, set voltage to old value. */
+	if (dmcfreq->rate != target_rate) {
+		dev_err(dev, "Get wrong ddr frequency, Request frequency %lu,\
+			Current frequency %lu\n", target_rate, dmcfreq->rate);
+		regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt,
+				      dmcfreq->volt);
+		goto out;
+	} else if (old_clk_rate > target_rate)
+		err = regulator_set_voltage(dmcfreq->vdd_center, target_volt,
+					    target_volt);
+	if (err)
+		dev_err(dev, "Cannot to set vol %lu uV\n", target_volt);
+
+	dmcfreq->curr_opp = opp;
+out:
+	mutex_unlock(&dmcfreq->lock);
+	return err;
+}
+
+static int rk3399_dmcfreq_get_dev_status(struct device *dev,
+					 struct devfreq_dev_status *stat)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	struct devfreq_event_data edata;
+	int ret = 0;
+
+	ret = devfreq_event_get_event(dmcfreq->edev, &edata);
+	if (ret < 0)
+		return ret;
+
+	stat->current_frequency = dmcfreq->rate;
+	stat->busy_time = edata.load_count;
+	stat->total_time = edata.total_count;
+
+	return ret;
+}
+
+static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+
+	*freq = dmcfreq->rate;
+
+	return 0;
+}
+
+static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = {
+	.polling_ms	= 200,
+	.target		= rk3399_dmcfreq_target,
+	.get_dev_status	= rk3399_dmcfreq_get_dev_status,
+	.get_cur_freq	= rk3399_dmcfreq_get_cur_freq,
+};
+
+static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = devfreq_event_disable_edev(dmcfreq->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to disable the devfreq-event devices\n");
+		return ret;
+	}
+
+	ret = devfreq_suspend_device(dmcfreq->devfreq);
+	if (ret < 0) {
+		dev_err(dev, "failed to suspend the devfreq devices\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev);
+	int ret = 0;
+
+	ret = devfreq_event_enable_edev(dmcfreq->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable the devfreq-event devices\n");
+		return ret;
+	}
+
+	ret = devfreq_resume_device(dmcfreq->devfreq);
+	if (ret < 0) {
+		dev_err(dev, "failed to resume the devfreq devices\n");
+		return ret;
+	}
+	return ret;
+}
+
+static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend,
+			 rk3399_dmcfreq_resume);
+
+static irqreturn_t rk3399_dmc_irq(int irq, void *dev_id)
+{
+	struct rk3399_dmcfreq *dmcfreq = dev_id;
+	struct arm_smccc_res res;
+
+	dmcfreq->wait_dcf_flag = 0;
+	wake_up(&dmcfreq->wait_dcf_queue);
+
+	/* Clear the DCF interrupt */
+	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+		      ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ,
+		      0, 0, 0, 0, &res);
+
+	return IRQ_HANDLED;
+}
+
+static int of_get_ddr_timings(struct dram_timing *timing,
+			      struct device_node *np)
+{
+	int ret = 0;
+
+	ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin",
+				   &timing->ddr3_speed_bin);
+	ret |= of_property_read_u32(np, "rockchip,pd_idle",
+				    &timing->pd_idle);
+	ret |= of_property_read_u32(np, "rockchip,sr_idle",
+				    &timing->sr_idle);
+	ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle",
+				    &timing->sr_mc_gate_idle);
+	ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle",
+				    &timing->srpd_lite_idle);
+	ret |= of_property_read_u32(np, "rockchip,standby_idle",
+				    &timing->standby_idle);
+	ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq",
+				    &timing->auto_pd_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq",
+				    &timing->dram_dll_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq",
+				    &timing->phy_dll_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq",
+				    &timing->ddr3_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_drv",
+				    &timing->ddr3_drv);
+	ret |= of_property_read_u32(np, "rockchip,ddr3_odt",
+				    &timing->ddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv",
+				    &timing->phy_ddr3_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv",
+				    &timing->phy_ddr3_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt",
+				    &timing->phy_ddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq",
+				    &timing->lpddr3_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_drv",
+				    &timing->lpddr3_drv);
+	ret |= of_property_read_u32(np, "rockchip,lpddr3_odt",
+				    &timing->lpddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv",
+				    &timing->phy_lpddr3_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv",
+				    &timing->phy_lpddr3_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt",
+				    &timing->phy_lpddr3_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq",
+				    &timing->lpddr4_odt_dis_freq);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_drv",
+				    &timing->lpddr4_drv);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt",
+				    &timing->lpddr4_dq_odt);
+	ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt",
+				    &timing->lpddr4_ca_odt);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv",
+				    &timing->phy_lpddr4_ca_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv",
+				    &timing->phy_lpddr4_ck_cs_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv",
+				    &timing->phy_lpddr4_dq_drv);
+	ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt",
+				    &timing->phy_lpddr4_odt);
+
+	return ret;
+}
+
+static int rk3399_dmcfreq_probe(struct platform_device *pdev)
+{
+	struct arm_smccc_res res;
+	struct device *dev = &pdev->dev;
+	struct device_node *np = pdev->dev.of_node;
+	struct rk3399_dmcfreq *data;
+	int ret, irq, index, size;
+	uint32_t *timing;
+	struct dev_pm_opp *opp;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "Cannot get the dmc interrupt resource\n");
+		return -EINVAL;
+	}
+	data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	mutex_init(&data->lock);
+
+	data->vdd_center = devm_regulator_get(dev, "center");
+	if (IS_ERR(data->vdd_center)) {
+		dev_err(dev, "Cannot get the regulator \"center\"\n");
+		return PTR_ERR(data->vdd_center);
+	}
+
+	data->dmc_clk = devm_clk_get(dev, "dmc_clk");
+	if (IS_ERR(data->dmc_clk)) {
+		dev_err(dev, "Cannot get the clk dmc_clk\n");
+		return PTR_ERR(data->dmc_clk);
+	};
+
+	data->irq = irq;
+	ret = devm_request_irq(dev, irq, rk3399_dmc_irq, 0,
+			       dev_name(dev), data);
+	if (ret) {
+		dev_err(dev, "Failed to request dmc irq: %d\n", ret);
+		return ret;
+	}
+
+	init_waitqueue_head(&data->wait_dcf_queue);
+	data->wait_dcf_flag = 0;
+
+	data->edev = devfreq_event_get_edev_by_phandle(dev, 0);
+	if (IS_ERR(data->edev))
+		return -EPROBE_DEFER;
+
+	ret = devfreq_event_enable_edev(data->edev);
+	if (ret < 0) {
+		dev_err(dev, "failed to enable devfreq-event devices\n");
+		return ret;
+	}
+
+	/*
+	 * Get dram timing and pass it to arm trust firmware,
+	 * the dram drvier in arm trust firmware will get these
+	 * timing and to do dram initial.
+	 */
+	if (!of_get_ddr_timings(&data->timing, np)) {
+		timing = &data->timing.ddr3_speed_bin;
+		size = sizeof(struct dram_timing) / 4;
+		for (index = 0; index < size; index++) {
+			arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index,
+				      ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM,
+				      0, 0, 0, 0, &res);
+			if (res.a0) {
+				dev_err(dev, "Failed to set dram param: %ld\n",
+					res.a0);
+				return -EINVAL;
+			}
+		}
+	}
+
+	arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0,
+		      ROCKCHIP_SIP_CONFIG_DRAM_INIT,
+		      0, 0, 0, 0, &res);
+
+	/*
+	 * We add a devfreq driver to our parent since it has a device tree node
+	 * with operating points.
+	 */
+	if (dev_pm_opp_of_add_table(dev)) {
+		dev_err(dev, "Invalid operating-points in device tree.\n");
+		rcu_read_unlock();
+		return -EINVAL;
+	}
+
+	of_property_read_u32(np, "upthreshold",
+			     &data->ondemand_data.upthreshold);
+	of_property_read_u32(np, "downdifferential",
+			     &data->ondemand_data.downdifferential);
+
+	data->rate = clk_get_rate(data->dmc_clk);
+
+	rcu_read_lock();
+	opp = devfreq_recommended_opp(dev, &data->rate, 0);
+	if (IS_ERR(opp)) {
+		rcu_read_unlock();
+		return PTR_ERR(opp);
+	}
+	rcu_read_unlock();
+	data->curr_opp = opp;
+
+	rk3399_devfreq_dmc_profile.initial_freq = data->rate;
+
+	data->devfreq = devfreq_add_device(dev,
+					   &rk3399_devfreq_dmc_profile,
+					   "simple_ondemand",
+					   &data->ondemand_data);
+	if (IS_ERR(data->devfreq))
+		return PTR_ERR(data->devfreq);
+	devm_devfreq_register_opp_notifier(dev, data->devfreq);
+
+	data->dev = dev;
+	platform_set_drvdata(pdev, data);
+
+	return 0;
+}
+
+static int rk3399_dmcfreq_remove(struct platform_device *pdev)
+{
+	struct rk3399_dmcfreq *dmcfreq = platform_get_drvdata(pdev);
+
+	regulator_put(dmcfreq->vdd_center);
+
+	return 0;
+}
+
+static const struct of_device_id rk3399dmc_devfreq_of_match[] = {
+	{ .compatible = "rockchip,rk3399-dmc" },
+	{ },
+};
+
+static struct platform_driver rk3399_dmcfreq_driver = {
+	.probe	= rk3399_dmcfreq_probe,
+	.remove	= rk3399_dmcfreq_remove,
+	.driver = {
+		.name	= "rk3399-dmc-freq",
+		.pm	= &rk3399_dmcfreq_pm,
+		.of_match_table = rk3399dmc_devfreq_of_match,
+	},
+};
+module_platform_driver(rk3399_dmcfreq_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Lin Huang <hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org>");
+MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework");
-- 
2.6.6

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Re: [PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Heiko Stübner]

Am Freitag, 2. September 2016, 06:31:24 schrieb Lin Huang:
> base on dfi result, we do ddr frequency scaling, register
> dmc driver to devfreq framework, and use simple-ondemand
> policy.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Signed-off-by: MyngJoo Ham <myngjoo.ham@samsung.com>
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---

[...]

> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
> new file mode 100644
> index 0000000..54d65f2
> --- /dev/null
> +++ b/drivers/devfreq/rk3399_dmc.c
> @@ -0,0 +1,480 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Lin Huang <hl@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> for + * more details.
> + */
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/devfreq.h>
> +#include <linux/devfreq-event.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/rwsem.h>
> +#include <linux/suspend.h>
> +
> +#include <soc/rockchip/rockchip_sip.h>

(Repeated from previous version)
For the shared sip-interface header I've prepared a signed, stable tag
which can be pulled from

The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:

  Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/rockchip-ddr-sip

for you to fetch changes up to 97dd82682f1a6174698fbea149a04b4cabc58c4f:

  soc: rockchip: add header for ddr rate SIP interface (2016-08-31 18:53:24 +0200)

----------------------------------------------------------------
Header file defining the SIP-interface to the ATF for DDR frequency changes

----------------------------------------------------------------
Lin Huang (1):
      soc: rockchip: add header for ddr rate SIP interface

 include/soc/rockchip/rockchip_sip.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 include/soc/rockchip/rockchip_sip.h

[PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Heiko Stübner]

Am Freitag, 2. September 2016, 06:31:24 schrieb Lin Huang:
> base on dfi result, we do ddr frequency scaling, register
> dmc driver to devfreq framework, and use simple-ondemand
> policy.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Signed-off-by: MyngJoo Ham <myngjoo.ham@samsung.com>
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---

[...]

> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
> new file mode 100644
> index 0000000..54d65f2
> --- /dev/null
> +++ b/drivers/devfreq/rk3399_dmc.c
> @@ -0,0 +1,480 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Lin Huang <hl@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> for + * more details.
> + */
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/devfreq.h>
> +#include <linux/devfreq-event.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/rwsem.h>
> +#include <linux/suspend.h>
> +
> +#include <soc/rockchip/rockchip_sip.h>

(Repeated from previous version)
For the shared sip-interface header I've prepared a signed, stable tag
which can be pulled from

The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:

  Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/rockchip-ddr-sip

for you to fetch changes up to 97dd82682f1a6174698fbea149a04b4cabc58c4f:

  soc: rockchip: add header for ddr rate SIP interface (2016-08-31 18:53:24 +0200)

----------------------------------------------------------------
Header file defining the SIP-interface to the ATF for DDR frequency changes

----------------------------------------------------------------
Lin Huang (1):
      soc: rockchip: add header for ddr rate SIP interface

 include/soc/rockchip/rockchip_sip.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 include/soc/rockchip/rockchip_sip.h

Re: [PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Heiko Stübner]

Am Freitag, 2. September 2016, 06:31:24 schrieb Lin Huang:
> base on dfi result, we do ddr frequency scaling, register
> dmc driver to devfreq framework, and use simple-ondemand
> policy.
> 
> Signed-off-by: Lin Huang <hl@rock-chips.com>
> Signed-off-by: MyngJoo Ham <myngjoo.ham@samsung.com>
> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---

[...]

> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
> new file mode 100644
> index 0000000..54d65f2
> --- /dev/null
> +++ b/drivers/devfreq/rk3399_dmc.c
> @@ -0,0 +1,480 @@
> +/*
> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Lin Huang <hl@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
> for + * more details.
> + */
> +
> +#include <linux/arm-smccc.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/devfreq.h>
> +#include <linux/devfreq-event.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/rwsem.h>
> +#include <linux/suspend.h>
> +
> +#include <soc/rockchip/rockchip_sip.h>

(Repeated from previous version)
For the shared sip-interface header I've prepared a signed, stable tag
which can be pulled from

The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:

  Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/rockchip-ddr-sip

for you to fetch changes up to 97dd82682f1a6174698fbea149a04b4cabc58c4f:

  soc: rockchip: add header for ddr rate SIP interface (2016-08-31 18:53:24 +0200)

----------------------------------------------------------------
Header file defining the SIP-interface to the ATF for DDR frequency changes

----------------------------------------------------------------
Lin Huang (1):
      soc: rockchip: add header for ddr rate SIP interface

 include/soc/rockchip/rockchip_sip.h | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 include/soc/rockchip/rockchip_sip.h
_______________________________________________
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dri-devel@lists.freedesktop.org
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Re: [PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Chanwoo Choi]

Hi Heiko,

On 2016년 09월 02일 08:17, Heiko Stübner wrote:
> Am Freitag, 2. September 2016, 06:31:24 schrieb Lin Huang:
>> base on dfi result, we do ddr frequency scaling, register
>> dmc driver to devfreq framework, and use simple-ondemand
>> policy.
>>
>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>> Signed-off-by: MyngJoo Ham <myngjoo.ham@samsung.com>
>> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
> 
> [...]
> 
>> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
>> new file mode 100644
>> index 0000000..54d65f2
>> --- /dev/null
>> +++ b/drivers/devfreq/rk3399_dmc.c
>> @@ -0,0 +1,480 @@
>> +/*
>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
>> + * Author: Lin Huang <hl@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
>> for + * more details.
>> + */
>> +
>> +#include <linux/arm-smccc.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/devfreq.h>
>> +#include <linux/devfreq-event.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_opp.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/rwsem.h>
>> +#include <linux/suspend.h>
>> +
>> +#include <soc/rockchip/rockchip_sip.h>
> 
> (Repeated from previous version)
> For the shared sip-interface header I've prepared a signed, stable tag
> which can be pulled from
> 
> The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
> 
>   Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/rockchip-ddr-sip
> 
> for you to fetch changes up to 97dd82682f1a6174698fbea149a04b4cabc58c4f:
> 
>   soc: rockchip: add header for ddr rate SIP interface (2016-08-31 18:53:24 +0200)
> 
> ----------------------------------------------------------------
> Header file defining the SIP-interface to the ATF for DDR frequency changes
> 
> ----------------------------------------------------------------
> Lin Huang (1):
>       soc: rockchip: add header for ddr rate SIP interface
> 
>  include/soc/rockchip/rockchip_sip.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>  create mode 100644 include/soc/rockchip/rockchip_sip.h
> 
> 
> 

Thanks for creating the immutable branch.

-- 
Best Regards,
Chanwoo Choi

[PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Chanwoo Choi]

Hi Heiko,

On 2016? 09? 02? 08:17, Heiko St?bner wrote:
> Am Freitag, 2. September 2016, 06:31:24 schrieb Lin Huang:
>> base on dfi result, we do ddr frequency scaling, register
>> dmc driver to devfreq framework, and use simple-ondemand
>> policy.
>>
>> Signed-off-by: Lin Huang <hl@rock-chips.com>
>> Signed-off-by: MyngJoo Ham <myngjoo.ham@samsung.com>
>> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
>> ---
> 
> [...]
> 
>> diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c
>> new file mode 100644
>> index 0000000..54d65f2
>> --- /dev/null
>> +++ b/drivers/devfreq/rk3399_dmc.c
>> @@ -0,0 +1,480 @@
>> +/*
>> + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd.
>> + * Author: Lin Huang <hl@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
>> for + * more details.
>> + */
>> +
>> +#include <linux/arm-smccc.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/devfreq.h>
>> +#include <linux/devfreq-event.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pm_opp.h>
>> +#include <linux/regulator/consumer.h>
>> +#include <linux/rwsem.h>
>> +#include <linux/suspend.h>
>> +
>> +#include <soc/rockchip/rockchip_sip.h>
> 
> (Repeated from previous version)
> For the shared sip-interface header I've prepared a signed, stable tag
> which can be pulled from
> 
> The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc:
> 
>   Linux 4.8-rc1 (2016-08-07 18:18:00 -0700)
> 
> are available in the git repository at:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/rockchip-ddr-sip
> 
> for you to fetch changes up to 97dd82682f1a6174698fbea149a04b4cabc58c4f:
> 
>   soc: rockchip: add header for ddr rate SIP interface (2016-08-31 18:53:24 +0200)
> 
> ----------------------------------------------------------------
> Header file defining the SIP-interface to the ATF for DDR frequency changes
> 
> ----------------------------------------------------------------
> Lin Huang (1):
>       soc: rockchip: add header for ddr rate SIP interface
> 
>  include/soc/rockchip/rockchip_sip.h | 27 +++++++++++++++++++++++++++
>  1 file changed, 27 insertions(+)
>  create mode 100644 include/soc/rockchip/rockchip_sip.h
> 
> 
> 

Thanks for creating the immutable branch.

-- 
Best Regards,
Chanwoo Choi

Re: [PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1676 bytes --]

Hi Lin,

[auto build test ERROR on next-20160825]
[also build test ERROR on v4.8-rc4]
[cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> drivers/devfreq/rk3399_dmc.c:29:39: fatal error: soc/rockchip/rockchip_sip.h: No such file or directory
   compilation terminated.

vim +29 drivers/devfreq/rk3399_dmc.c

    23	#include <linux/platform_device.h>
    24	#include <linux/pm_opp.h>
    25	#include <linux/regulator/consumer.h>
    26	#include <linux/rwsem.h>
    27	#include <linux/suspend.h>
    28	
  > 29	#include <soc/rockchip/rockchip_sip.h>
    30	
    31	struct dram_timing {
    32		unsigned int ddr3_speed_bin;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 58849 bytes --]

[PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[kbuild test robot]

Hi Lin,

[auto build test ERROR on next-20160825]
[also build test ERROR on v4.8-rc4]
[cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> drivers/devfreq/rk3399_dmc.c:29:39: fatal error: soc/rockchip/rockchip_sip.h: No such file or directory
   compilation terminated.

vim +29 drivers/devfreq/rk3399_dmc.c

    23	#include <linux/platform_device.h>
    24	#include <linux/pm_opp.h>
    25	#include <linux/regulator/consumer.h>
    26	#include <linux/rwsem.h>
    27	#include <linux/suspend.h>
    28	
  > 29	#include <soc/rockchip/rockchip_sip.h>
    30	
    31	struct dram_timing {
    32		unsigned int ddr3_speed_bin;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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Re: [PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 1676 bytes --]

Hi Lin,

[auto build test ERROR on next-20160825]
[also build test ERROR on v4.8-rc4]
[cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All errors (new ones prefixed by >>):

>> drivers/devfreq/rk3399_dmc.c:29:39: fatal error: soc/rockchip/rockchip_sip.h: No such file or directory
   compilation terminated.

vim +29 drivers/devfreq/rk3399_dmc.c

    23	#include <linux/platform_device.h>
    24	#include <linux/pm_opp.h>
    25	#include <linux/regulator/consumer.h>
    26	#include <linux/rwsem.h>
    27	#include <linux/suspend.h>
    28	
  > 29	#include <soc/rockchip/rockchip_sip.h>
    30	
    31	struct dram_timing {
    32		unsigned int ddr3_speed_bin;

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 58849 bytes --]

[-- Attachment #3: Type: text/plain, Size: 160 bytes --]

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Re: [PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Chanwoo Choi]

Dear all,

This patch rely on both rockchip.git and devfreq.git.
Already, Rockchip SoC Maintainer (Heiko Stuebner) created
the immutable branch[1]. When applying these patches
on devfreq.git with pulling the immutable branch[1],
It looks like that should not be a problem.

[1] http://www.spinics.net/lists/arm-kernel/msg528298.html

Best Regards,
Chanwoo Choi

On 2016년 09월 02일 10:23, kbuild test robot wrote:
> Hi Lin,
> 
> [auto build test ERROR on next-20160825]
> [also build test ERROR on v4.8-rc4]
> [cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
> [Check https://git-scm.com/docs/git-format-patch for more information]
> 
> url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
> reproduce:
>         wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # save the attached .config to linux build tree
>         make.cross ARCH=arm 
> 
> All errors (new ones prefixed by >>):
> 
>>> drivers/devfreq/rk3399_dmc.c:29:39: fatal error: soc/rockchip/rockchip_sip.h: No such file or directory
>    compilation terminated.
> 
> vim +29 drivers/devfreq/rk3399_dmc.c
> 
>     23	#include <linux/platform_device.h>
>     24	#include <linux/pm_opp.h>
>     25	#include <linux/regulator/consumer.h>
>     26	#include <linux/rwsem.h>
>     27	#include <linux/suspend.h>
>     28	
>   > 29	#include <soc/rockchip/rockchip_sip.h>
>     30	
>     31	struct dram_timing {
>     32		unsigned int ddr3_speed_bin;
> 
> ---
> 0-DAY kernel test infrastructure                Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
> 

[PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Chanwoo Choi]

Dear all,

This patch rely on both rockchip.git and devfreq.git.
Already, Rockchip SoC Maintainer (Heiko Stuebner) created
the immutable branch[1]. When applying these patches
on devfreq.git with pulling the immutable branch[1],
It looks like that should not be a problem.

[1] http://www.spinics.net/lists/arm-kernel/msg528298.html

Best Regards,
Chanwoo Choi

On 2016? 09? 02? 10:23, kbuild test robot wrote:
> Hi Lin,
> 
> [auto build test ERROR on next-20160825]
> [also build test ERROR on v4.8-rc4]
> [cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
> [Check https://git-scm.com/docs/git-format-patch for more information]
> 
> url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
> reproduce:
>         wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # save the attached .config to linux build tree
>         make.cross ARCH=arm 
> 
> All errors (new ones prefixed by >>):
> 
>>> drivers/devfreq/rk3399_dmc.c:29:39: fatal error: soc/rockchip/rockchip_sip.h: No such file or directory
>    compilation terminated.
> 
> vim +29 drivers/devfreq/rk3399_dmc.c
> 
>     23	#include <linux/platform_device.h>
>     24	#include <linux/pm_opp.h>
>     25	#include <linux/regulator/consumer.h>
>     26	#include <linux/rwsem.h>
>     27	#include <linux/suspend.h>
>     28	
>   > 29	#include <soc/rockchip/rockchip_sip.h>
>     30	
>     31	struct dram_timing {
>     32		unsigned int ddr3_speed_bin;
> 
> ---
> 0-DAY kernel test infrastructure                Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
> 

Re: [PATCH 4/5] PM / devfreq: rockchip: add devfreq driver for rk3399 dmc

[Chanwoo Choi]

Dear all,

This patch rely on both rockchip.git and devfreq.git.
Already, Rockchip SoC Maintainer (Heiko Stuebner) created
the immutable branch[1]. When applying these patches
on devfreq.git with pulling the immutable branch[1],
It looks like that should not be a problem.

[1] http://www.spinics.net/lists/arm-kernel/msg528298.html

Best Regards,
Chanwoo Choi

On 2016년 09월 02일 10:23, kbuild test robot wrote:
> Hi Lin,
> 
> [auto build test ERROR on next-20160825]
> [also build test ERROR on v4.8-rc4]
> [cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2]
> [if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
> [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
> [Check https://git-scm.com/docs/git-format-patch for more information]
> 
> url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
> config: arm-allmodconfig (attached as .config)
> compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
> reproduce:
>         wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # save the attached .config to linux build tree
>         make.cross ARCH=arm 
> 
> All errors (new ones prefixed by >>):
> 
>>> drivers/devfreq/rk3399_dmc.c:29:39: fatal error: soc/rockchip/rockchip_sip.h: No such file or directory
>    compilation terminated.
> 
> vim +29 drivers/devfreq/rk3399_dmc.c
> 
>     23	#include <linux/platform_device.h>
>     24	#include <linux/pm_opp.h>
>     25	#include <linux/regulator/consumer.h>
>     26	#include <linux/rwsem.h>
>     27	#include <linux/suspend.h>
>     28	
>   > 29	#include <soc/rockchip/rockchip_sip.h>
>     30	
>     31	struct dram_timing {
>     32		unsigned int ddr3_speed_bin;
> 
> ---
> 0-DAY kernel test infrastructure                Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
> 


_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip

[PATCH 5/5] drm/rockchip: Add dmc notifier in vop driver

[Lin Huang]

when in ddr frequency scaling process, vop can not do enable or
disable operation, since in dcf we check vop clock to see whether
vop work. If vop work, dcf do ddr frequency scaling when vop
in vblank status, and we need to read vop register to check whether
vop go into vblank status. If vop not work, dcf can do ddr frequency
any time. So when do ddr frequency scaling, you disabled or enable
vop, there may two bad thing happen: 1, the panel flicker(when vop from
disable status change to enable). 2, kernel hang (when vop from enable
status change to disable, dcf need to read vblank status, but if you disable
vop clock, it can not get the status, it will lead soc dead) So we need
register to devfreq notifier, and we can get the dmc status. Also, when
there have two vop enabled, we need to disable dmc, since dcf only base
on one vop vblank time, so the other panel will flicker when do ddr
frequency scaling.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Changes in v8:
- None

Changes in v7:
- None

Changes in v6:
- fix a build error

Changes in v5:
- improve some nits

Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and DEVFREQ_POSTCHANGE to get dmc status
- when two vop enable, disable dmc
- when two vop back to one vop, enable dmc

Changes in v3:
- when do vop eanble/disable, dmc will wait until it finish

Changes in v2:
- None

Changes in v1:
- use wait_event instead usleep

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 116 ++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index efbc41a..a73f3aa 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -19,6 +19,8 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_plane_helper.h>
 
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -118,6 +120,13 @@ struct vop {
 
 	const struct vop_data *data;
 
+	struct devfreq *devfreq;
+	struct devfreq_event_dev *devfreq_event_dev;
+	struct notifier_block dmc_nb;
+	int dmc_in_process;
+	int vop_switch_status;
+	wait_queue_head_t wait_dmc_queue;
+	wait_queue_head_t wait_vop_switch_queue;
 	uint32_t *regsbak;
 	void __iomem *regs;
 
@@ -428,11 +437,47 @@ static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 	spin_unlock_irqrestore(&vop->irq_lock, flags);
 }
 
+static int dmc_notify(struct notifier_block *nb, unsigned long event,
+		      void *data)
+{
+	struct vop *vop = container_of(nb, struct vop, dmc_nb);
+
+	if (event == DEVFREQ_PRECHANGE) {
+		/*
+		 * check if vop in enable or disable process,
+		 * if yes, wait until it finishes, use 200ms as
+		 * timeout.
+		 */
+		if (!wait_event_timeout(vop->wait_vop_switch_queue,
+					!vop->vop_switch_status, HZ / 5))
+			dev_warn(vop->dev,
+				 "Timeout waiting for vop swtich status\n");
+		vop->dmc_in_process = 1;
+	} else if (event == DEVFREQ_POSTCHANGE) {
+		vop->dmc_in_process = 0;
+		wake_up(&vop->wait_dmc_queue);
+	}
+
+	return NOTIFY_OK;
+}
+
 static int vop_enable(struct drm_crtc *crtc)
 {
 	struct vop *vop = to_vop(crtc);
+	int num_enabled_crtc = 0;
 	int ret;
 
+	/*
+	 * if in dmc scaling frequency process, wait until it finishes
+	 * use 200ms as timeout time.
+	 */
+	if (!wait_event_timeout(vop->wait_dmc_queue,
+				!vop->dmc_in_process, HZ / 5))
+		dev_warn(vop->dev,
+			 "Timeout waiting for dmc when vop enable\n");
+
+	vop->vop_switch_status = 1;
+
 	ret = pm_runtime_get_sync(vop->dev);
 	if (ret < 0) {
 		dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
@@ -479,6 +524,21 @@ static int vop_enable(struct drm_crtc *crtc)
 
 	drm_crtc_vblank_on(crtc);
 
+	vop->vop_switch_status = 0;
+	wake_up(&vop->wait_vop_switch_queue);
+
+	/* check how many VOPs in use now */
+	drm_for_each_crtc(crtc, vop->drm_dev) {
+		if (crtc->state->enable)
+			num_enabled_crtc++;
+	}
+
+	/* if enable two vop, need to disable dmc */
+	if ((num_enabled_crtc > 1) && vop->devfreq) {
+		if (vop->devfreq_event_dev)
+			devfreq_event_disable_edev(vop->devfreq_event_dev);
+		devfreq_suspend_device(vop->devfreq);
+	}
 	return 0;
 
 err_disable_aclk:
@@ -489,17 +549,31 @@ err_disable_hclk:
 	clk_disable(vop->hclk);
 err_put_pm_runtime:
 	pm_runtime_put_sync(vop->dev);
+	vop->vop_switch_status = 0;
+	wake_up(&vop->wait_vop_switch_queue);
 	return ret;
 }
 
 static void vop_crtc_disable(struct drm_crtc *crtc)
 {
 	struct vop *vop = to_vop(crtc);
+	int num_enabled_crtc = 0;
 	int i;
 
 	WARN_ON(vop->event);
 
 	/*
+	 * if in dmc scaling frequency process, wait until it finish
+	 * use 200ms as timeout time.
+	 */
+	if (!wait_event_timeout(vop->wait_dmc_queue,
+				!vop->dmc_in_process, HZ / 5))
+		dev_warn(vop->dev,
+			 "Timeout waiting for dmc when vop disable\n");
+
+	vop->vop_switch_status = 1;
+
+	/*
 	 * We need to make sure that all windows are disabled before we
 	 * disable that crtc. Otherwise we might try to scan from a destroyed
 	 * buffer later.
@@ -555,6 +629,24 @@ static void vop_crtc_disable(struct drm_crtc *crtc)
 		spin_unlock_irq(&crtc->dev->event_lock);
 
 		crtc->state->event = NULL;
+
+	vop->vop_switch_status = 0;
+	wake_up(&vop->wait_vop_switch_queue);
+
+	/* check how many VOPs in use now */
+	drm_for_each_crtc(crtc, vop->drm_dev) {
+		if (crtc->state->enable)
+			num_enabled_crtc++;
+	}
+
+	/*
+	 * if num_enabled_crtc = 1 now, it means 2 vop enabled
+	 * change to 1 vop enabled  need to enable dmc again.
+	 */
+	if ((num_enabled_crtc == 1) && vop->devfreq) {
+		if (vop->devfreq_event_dev)
+			devfreq_event_enable_edev(vop->devfreq_event_dev);
+		devfreq_resume_device(vop->devfreq);
 	}
 }
 
@@ -1413,6 +1505,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
 	struct drm_device *drm_dev = data;
 	struct vop *vop;
 	struct resource *res;
+	struct devfreq *devfreq;
+	struct devfreq_event_dev *event_dev;
 	size_t alloc_size;
 	int ret, irq;
 
@@ -1474,6 +1568,28 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
 		return ret;
 
 	pm_runtime_enable(&pdev->dev);
+
+	init_waitqueue_head(&vop->wait_vop_switch_queue);
+	vop->vop_switch_status = 0;
+	init_waitqueue_head(&vop->wait_dmc_queue);
+	vop->dmc_in_process = 0;
+
+	devfreq = devfreq_get_devfreq_by_phandle(dev, 0);
+	if (IS_ERR(devfreq))
+		goto out;
+
+	vop->devfreq = devfreq;
+	vop->dmc_nb.notifier_call = dmc_notify;
+	devfreq_register_notifier(vop->devfreq, &vop->dmc_nb,
+				  DEVFREQ_TRANSITION_NOTIFIER);
+
+	event_dev = devfreq_event_get_edev_by_phandle(vop->devfreq->dev.parent,
+						      0);
+	if (IS_ERR(event_dev))
+		goto out;
+
+	vop->devfreq_event_dev = event_dev;
+out:
 	return 0;
 }
 
-- 
2.6.6

[PATCH 5/5] drm/rockchip: Add dmc notifier in vop driver

[Lin Huang]

when in ddr frequency scaling process, vop can not do enable or
disable operation, since in dcf we check vop clock to see whether
vop work. If vop work, dcf do ddr frequency scaling when vop
in vblank status, and we need to read vop register to check whether
vop go into vblank status. If vop not work, dcf can do ddr frequency
any time. So when do ddr frequency scaling, you disabled or enable
vop, there may two bad thing happen: 1, the panel flicker(when vop from
disable status change to enable). 2, kernel hang (when vop from enable
status change to disable, dcf need to read vblank status, but if you disable
vop clock, it can not get the status, it will lead soc dead) So we need
register to devfreq notifier, and we can get the dmc status. Also, when
there have two vop enabled, we need to disable dmc, since dcf only base
on one vop vblank time, so the other panel will flicker when do ddr
frequency scaling.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Changes in v8:
- None

Changes in v7:
- None

Changes in v6:
- fix a build error

Changes in v5:
- improve some nits

Changes in v4:
- register notifier to devfreq_register_notifier
- use DEVFREQ_PRECHANGE and DEVFREQ_POSTCHANGE to get dmc status
- when two vop enable, disable dmc
- when two vop back to one vop, enable dmc

Changes in v3:
- when do vop eanble/disable, dmc will wait until it finish

Changes in v2:
- None

Changes in v1:
- use wait_event instead usleep

 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 116 ++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index efbc41a..a73f3aa 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -19,6 +19,8 @@
 #include <drm/drm_crtc_helper.h>
 #include <drm/drm_plane_helper.h>
 
+#include <linux/devfreq.h>
+#include <linux/devfreq-event.h>
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
@@ -118,6 +120,13 @@ struct vop {
 
 	const struct vop_data *data;
 
+	struct devfreq *devfreq;
+	struct devfreq_event_dev *devfreq_event_dev;
+	struct notifier_block dmc_nb;
+	int dmc_in_process;
+	int vop_switch_status;
+	wait_queue_head_t wait_dmc_queue;
+	wait_queue_head_t wait_vop_switch_queue;
 	uint32_t *regsbak;
 	void __iomem *regs;
 
@@ -428,11 +437,47 @@ static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
 	spin_unlock_irqrestore(&vop->irq_lock, flags);
 }
 
+static int dmc_notify(struct notifier_block *nb, unsigned long event,
+		      void *data)
+{
+	struct vop *vop = container_of(nb, struct vop, dmc_nb);
+
+	if (event == DEVFREQ_PRECHANGE) {
+		/*
+		 * check if vop in enable or disable process,
+		 * if yes, wait until it finishes, use 200ms as
+		 * timeout.
+		 */
+		if (!wait_event_timeout(vop->wait_vop_switch_queue,
+					!vop->vop_switch_status, HZ / 5))
+			dev_warn(vop->dev,
+				 "Timeout waiting for vop swtich status\n");
+		vop->dmc_in_process = 1;
+	} else if (event == DEVFREQ_POSTCHANGE) {
+		vop->dmc_in_process = 0;
+		wake_up(&vop->wait_dmc_queue);
+	}
+
+	return NOTIFY_OK;
+}
+
 static int vop_enable(struct drm_crtc *crtc)
 {
 	struct vop *vop = to_vop(crtc);
+	int num_enabled_crtc = 0;
 	int ret;
 
+	/*
+	 * if in dmc scaling frequency process, wait until it finishes
+	 * use 200ms as timeout time.
+	 */
+	if (!wait_event_timeout(vop->wait_dmc_queue,
+				!vop->dmc_in_process, HZ / 5))
+		dev_warn(vop->dev,
+			 "Timeout waiting for dmc when vop enable\n");
+
+	vop->vop_switch_status = 1;
+
 	ret = pm_runtime_get_sync(vop->dev);
 	if (ret < 0) {
 		dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
@@ -479,6 +524,21 @@ static int vop_enable(struct drm_crtc *crtc)
 
 	drm_crtc_vblank_on(crtc);
 
+	vop->vop_switch_status = 0;
+	wake_up(&vop->wait_vop_switch_queue);
+
+	/* check how many VOPs in use now */
+	drm_for_each_crtc(crtc, vop->drm_dev) {
+		if (crtc->state->enable)
+			num_enabled_crtc++;
+	}
+
+	/* if enable two vop, need to disable dmc */
+	if ((num_enabled_crtc > 1) && vop->devfreq) {
+		if (vop->devfreq_event_dev)
+			devfreq_event_disable_edev(vop->devfreq_event_dev);
+		devfreq_suspend_device(vop->devfreq);
+	}
 	return 0;
 
 err_disable_aclk:
@@ -489,17 +549,31 @@ err_disable_hclk:
 	clk_disable(vop->hclk);
 err_put_pm_runtime:
 	pm_runtime_put_sync(vop->dev);
+	vop->vop_switch_status = 0;
+	wake_up(&vop->wait_vop_switch_queue);
 	return ret;
 }
 
 static void vop_crtc_disable(struct drm_crtc *crtc)
 {
 	struct vop *vop = to_vop(crtc);
+	int num_enabled_crtc = 0;
 	int i;
 
 	WARN_ON(vop->event);
 
 	/*
+	 * if in dmc scaling frequency process, wait until it finish
+	 * use 200ms as timeout time.
+	 */
+	if (!wait_event_timeout(vop->wait_dmc_queue,
+				!vop->dmc_in_process, HZ / 5))
+		dev_warn(vop->dev,
+			 "Timeout waiting for dmc when vop disable\n");
+
+	vop->vop_switch_status = 1;
+
+	/*
 	 * We need to make sure that all windows are disabled before we
 	 * disable that crtc. Otherwise we might try to scan from a destroyed
 	 * buffer later.
@@ -555,6 +629,24 @@ static void vop_crtc_disable(struct drm_crtc *crtc)
 		spin_unlock_irq(&crtc->dev->event_lock);
 
 		crtc->state->event = NULL;
+
+	vop->vop_switch_status = 0;
+	wake_up(&vop->wait_vop_switch_queue);
+
+	/* check how many VOPs in use now */
+	drm_for_each_crtc(crtc, vop->drm_dev) {
+		if (crtc->state->enable)
+			num_enabled_crtc++;
+	}
+
+	/*
+	 * if num_enabled_crtc = 1 now, it means 2 vop enabled
+	 * change to 1 vop enabled  need to enable dmc again.
+	 */
+	if ((num_enabled_crtc == 1) && vop->devfreq) {
+		if (vop->devfreq_event_dev)
+			devfreq_event_enable_edev(vop->devfreq_event_dev);
+		devfreq_resume_device(vop->devfreq);
 	}
 }
 
@@ -1413,6 +1505,8 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
 	struct drm_device *drm_dev = data;
 	struct vop *vop;
 	struct resource *res;
+	struct devfreq *devfreq;
+	struct devfreq_event_dev *event_dev;
 	size_t alloc_size;
 	int ret, irq;
 
@@ -1474,6 +1568,28 @@ static int vop_bind(struct device *dev, struct device *master, void *data)
 		return ret;
 
 	pm_runtime_enable(&pdev->dev);
+
+	init_waitqueue_head(&vop->wait_vop_switch_queue);
+	vop->vop_switch_status = 0;
+	init_waitqueue_head(&vop->wait_dmc_queue);
+	vop->dmc_in_process = 0;
+
+	devfreq = devfreq_get_devfreq_by_phandle(dev, 0);
+	if (IS_ERR(devfreq))
+		goto out;
+
+	vop->devfreq = devfreq;
+	vop->dmc_nb.notifier_call = dmc_notify;
+	devfreq_register_notifier(vop->devfreq, &vop->dmc_nb,
+				  DEVFREQ_TRANSITION_NOTIFIER);
+
+	event_dev = devfreq_event_get_edev_by_phandle(vop->devfreq->dev.parent,
+						      0);
+	if (IS_ERR(event_dev))
+		goto out;
+
+	vop->devfreq_event_dev = event_dev;
+out:
 	return 0;
 }
 
-- 
2.6.6

Re: [PATCH 5/5] drm/rockchip: Add dmc notifier in vop driver

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 17809 bytes --]

Hi Lin,

[auto build test ERROR on next-20160825]
[cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2 v4.8-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/rockchip/rockchip_drm_vop.c:23:0:
   include/linux/devfreq-event.h:190:21: error: redefinition of 'devfreq_event_get_drvdata'
    static inline void *devfreq_event_get_drvdata(struct devfreq_event_dev *edev)
                        ^
   include/linux/devfreq-event.h:151:21: note: previous definition of 'devfreq_event_get_drvdata' was here
    static inline void *devfreq_event_get_drvdata(struct devfreq_event_dev *edev)
                        ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c: In function 'vop_crtc_disable':
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:653:13: error: invalid storage class for function 'vop_plane_destroy'
    static void vop_plane_destroy(struct drm_plane *plane)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:653:1: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
    static void vop_plane_destroy(struct drm_plane *plane)
    ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:658:12: error: invalid storage class for function 'vop_plane_prepare_fb'
    static int vop_plane_prepare_fb(struct drm_plane *plane,
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:667:13: error: invalid storage class for function 'vop_plane_cleanup_fb'
    static void vop_plane_cleanup_fb(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:674:12: error: invalid storage class for function 'vop_plane_atomic_check'
    static int vop_plane_atomic_check(struct drm_plane *plane,
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:731:13: error: invalid storage class for function 'vop_plane_atomic_disable'
    static void vop_plane_atomic_disable(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:756:13: error: invalid storage class for function 'vop_plane_atomic_update'
    static void vop_plane_atomic_update(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:866:16: error: initializer element is not constant
     .prepare_fb = vop_plane_prepare_fb,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:866:16: note: (near initialization for 'plane_helper_funcs.prepare_fb')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:867:16: error: initializer element is not constant
     .cleanup_fb = vop_plane_cleanup_fb,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:867:16: note: (near initialization for 'plane_helper_funcs.cleanup_fb')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:868:18: error: initializer element is not constant
     .atomic_check = vop_plane_atomic_check,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:868:18: note: (near initialization for 'plane_helper_funcs.atomic_check')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:869:19: error: initializer element is not constant
     .atomic_update = vop_plane_atomic_update,
                      ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:869:19: note: (near initialization for 'plane_helper_funcs.atomic_update')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:870:20: error: initializer element is not constant
     .atomic_disable = vop_plane_atomic_disable,
                       ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:870:20: note: (near initialization for 'plane_helper_funcs.atomic_disable')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:873:13: error: invalid storage class for function 'vop_atomic_plane_reset'
    static void vop_atomic_plane_reset(struct drm_plane *plane)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:891:1: error: invalid storage class for function 'vop_atomic_plane_duplicate_state'
    vop_atomic_plane_duplicate_state(struct drm_plane *plane)
    ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:911:13: error: invalid storage class for function 'vop_atomic_plane_destroy_state'
    static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:924:13: error: initializer element is not constant
     .destroy = vop_plane_destroy,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:924:13: note: (near initialization for 'vop_plane_funcs.destroy')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:925:11: error: initializer element is not constant
     .reset = vop_atomic_plane_reset,
              ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:925:11: note: (near initialization for 'vop_plane_funcs.reset')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:926:28: error: initializer element is not constant
     .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
                               ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:926:28: note: (near initialization for 'vop_plane_funcs.atomic_duplicate_state')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:927:26: error: initializer element is not constant
     .atomic_destroy_state = vop_atomic_plane_destroy_state,
                             ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:927:26: note: (near initialization for 'vop_plane_funcs.atomic_destroy_state')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:930:12: error: invalid storage class for function 'vop_crtc_enable_vblank'
    static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:947:13: error: invalid storage class for function 'vop_crtc_disable_vblank'
    static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:962:13: error: invalid storage class for function 'vop_crtc_wait_for_update'
    static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:971:19: error: initializer element is not constant
     .enable_vblank = vop_crtc_enable_vblank,
                      ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:971:19: note: (near initialization for 'private_crtc_funcs.enable_vblank')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:972:20: error: initializer element is not constant
     .disable_vblank = vop_crtc_disable_vblank,
                       ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:972:20: note: (near initialization for 'private_crtc_funcs.disable_vblank')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:973:21: error: initializer element is not constant
     .wait_for_update = vop_crtc_wait_for_update,
                        ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:973:21: note: (near initialization for 'private_crtc_funcs.wait_for_update')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:976:13: error: invalid storage class for function 'vop_crtc_mode_fixup'
    static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:988:13: error: invalid storage class for function 'vop_crtc_enable'
    static void vop_crtc_enable(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1090:13: error: invalid storage class for function 'vop_crtc_atomic_flush'
    static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1105:13: error: invalid storage class for function 'vop_crtc_atomic_begin'
    static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1122:12: error: initializer element is not constant
     .enable = vop_crtc_enable,
               ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1122:12: note: (near initialization for 'vop_crtc_helper_funcs.enable')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1124:16: error: initializer element is not constant
     .mode_fixup = vop_crtc_mode_fixup,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1124:16: note: (near initialization for 'vop_crtc_helper_funcs.mode_fixup')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1125:18: error: initializer element is not constant
     .atomic_flush = vop_crtc_atomic_flush,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1125:18: note: (near initialization for 'vop_crtc_helper_funcs.atomic_flush')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1126:18: error: initializer element is not constant
     .atomic_begin = vop_crtc_atomic_begin,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1126:18: note: (near initialization for 'vop_crtc_helper_funcs.atomic_begin')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1129:13: error: invalid storage class for function 'vop_crtc_destroy'
    static void vop_crtc_destroy(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1134:13: error: invalid storage class for function 'vop_crtc_reset'
    static void vop_crtc_reset(struct drm_crtc *crtc)
                ^

vim +/vop_plane_destroy +653 drivers/gpu/drm/rockchip/rockchip_drm_vop.c

4bb85264 Lin Huang     2016-09-02  647  		if (vop->devfreq_event_dev)
4bb85264 Lin Huang     2016-09-02  648  			devfreq_event_enable_edev(vop->devfreq_event_dev);
4bb85264 Lin Huang     2016-09-02  649  		devfreq_resume_device(vop->devfreq);
893b6cad Daniel Vetter 2016-06-08  650  	}
2048e328 Mark Yao      2014-08-22  651  }
2048e328 Mark Yao      2014-08-22  652  
63ebb9fa Mark Yao      2015-11-30 @653  static void vop_plane_destroy(struct drm_plane *plane)
2048e328 Mark Yao      2014-08-22  654  {
63ebb9fa Mark Yao      2015-11-30  655  	drm_plane_cleanup(plane);
2048e328 Mark Yao      2014-08-22  656  }
2048e328 Mark Yao      2014-08-22  657  
44d0237a Mark Yao      2016-04-29 @658  static int vop_plane_prepare_fb(struct drm_plane *plane,
1832040d Chris Wilson  2016-08-18  659  				struct drm_plane_state *new_state)
44d0237a Mark Yao      2016-04-29  660  {
44d0237a Mark Yao      2016-04-29  661  	if (plane->state->fb)
44d0237a Mark Yao      2016-04-29  662  		drm_framebuffer_reference(plane->state->fb);
44d0237a Mark Yao      2016-04-29  663  
44d0237a Mark Yao      2016-04-29  664  	return 0;
44d0237a Mark Yao      2016-04-29  665  }
44d0237a Mark Yao      2016-04-29  666  
44d0237a Mark Yao      2016-04-29 @667  static void vop_plane_cleanup_fb(struct drm_plane *plane,
1832040d Chris Wilson  2016-08-18  668  				 struct drm_plane_state *old_state)
44d0237a Mark Yao      2016-04-29  669  {
44d0237a Mark Yao      2016-04-29  670  	if (old_state->fb)
44d0237a Mark Yao      2016-04-29  671  		drm_framebuffer_unreference(old_state->fb);
44d0237a Mark Yao      2016-04-29  672  }
44d0237a Mark Yao      2016-04-29  673  
63ebb9fa Mark Yao      2015-11-30 @674  static int vop_plane_atomic_check(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  675  			   struct drm_plane_state *state)
2048e328 Mark Yao      2014-08-22  676  {
63ebb9fa Mark Yao      2015-11-30  677  	struct drm_crtc *crtc = state->crtc;
92915da6 John Keeping  2016-03-04  678  	struct drm_crtc_state *crtc_state;
63ebb9fa Mark Yao      2015-11-30  679  	struct drm_framebuffer *fb = state->fb;
2048e328 Mark Yao      2014-08-22  680  	struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa Mark Yao      2015-11-30  681  	struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
2048e328 Mark Yao      2014-08-22  682  	const struct vop_win_data *win = vop_win->data;
2048e328 Mark Yao      2014-08-22  683  	int ret;
63ebb9fa Mark Yao      2015-11-30  684  	struct drm_rect clip;
4c156c21 Mark Yao      2015-06-26  685  	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
4c156c21 Mark Yao      2015-06-26  686  					DRM_PLANE_HELPER_NO_SCALING;
4c156c21 Mark Yao      2015-06-26  687  	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
4c156c21 Mark Yao      2015-06-26  688  					DRM_PLANE_HELPER_NO_SCALING;
2048e328 Mark Yao      2014-08-22  689  
63ebb9fa Mark Yao      2015-11-30  690  	if (!crtc || !fb)
63ebb9fa Mark Yao      2015-11-30  691  		goto out_disable;
92915da6 John Keeping  2016-03-04  692  
92915da6 John Keeping  2016-03-04  693  	crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
92915da6 John Keeping  2016-03-04  694  	if (WARN_ON(!crtc_state))
92915da6 John Keeping  2016-03-04  695  		return -EINVAL;
92915da6 John Keeping  2016-03-04  696  
63ebb9fa Mark Yao      2015-11-30  697  	clip.x1 = 0;
63ebb9fa Mark Yao      2015-11-30  698  	clip.y1 = 0;
92915da6 John Keeping  2016-03-04  699  	clip.x2 = crtc_state->adjusted_mode.hdisplay;
92915da6 John Keeping  2016-03-04  700  	clip.y2 = crtc_state->adjusted_mode.vdisplay;
63ebb9fa Mark Yao      2015-11-30  701  
f9b96be0 Ville Syrjälä 2016-07-26  702  	ret = drm_plane_helper_check_state(state, &clip,
f9b96be0 Ville Syrjälä 2016-07-26  703  					   min_scale, max_scale,
f9b96be0 Ville Syrjälä 2016-07-26  704  					   true, true);
2048e328 Mark Yao      2014-08-22  705  	if (ret)
2048e328 Mark Yao      2014-08-22  706  		return ret;
2048e328 Mark Yao      2014-08-22  707  
f9b96be0 Ville Syrjälä 2016-07-26  708  	if (!state->visible)
63ebb9fa Mark Yao      2015-11-30  709  		goto out_disable;
84c7f8ca Mark Yao      2015-07-20  710  
63ebb9fa Mark Yao      2015-11-30  711  	vop_plane_state->format = vop_convert_format(fb->pixel_format);
63ebb9fa Mark Yao      2015-11-30  712  	if (vop_plane_state->format < 0)
63ebb9fa Mark Yao      2015-11-30  713  		return vop_plane_state->format;
2048e328 Mark Yao      2014-08-22  714  
84c7f8ca Mark Yao      2015-07-20  715  	/*
84c7f8ca Mark Yao      2015-07-20  716  	 * Src.x1 can be odd when do clip, but yuv plane start point
84c7f8ca Mark Yao      2015-07-20  717  	 * need align with 2 pixel.
84c7f8ca Mark Yao      2015-07-20  718  	 */
f9b96be0 Ville Syrjälä 2016-07-26  719  	if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2))
63ebb9fa Mark Yao      2015-11-30  720  		return -EINVAL;
84c7f8ca Mark Yao      2015-07-20  721  
63ebb9fa Mark Yao      2015-11-30  722  	vop_plane_state->enable = true;
2048e328 Mark Yao      2014-08-22  723  
63ebb9fa Mark Yao      2015-11-30  724  	return 0;
2048e328 Mark Yao      2014-08-22  725  
63ebb9fa Mark Yao      2015-11-30  726  out_disable:
63ebb9fa Mark Yao      2015-11-30  727  	vop_plane_state->enable = false;
63ebb9fa Mark Yao      2015-11-30  728  	return 0;
63ebb9fa Mark Yao      2015-11-30  729  }
2048e328 Mark Yao      2014-08-22  730  
63ebb9fa Mark Yao      2015-11-30 @731  static void vop_plane_atomic_disable(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  732  				     struct drm_plane_state *old_state)
63ebb9fa Mark Yao      2015-11-30  733  {
63ebb9fa Mark Yao      2015-11-30  734  	struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
63ebb9fa Mark Yao      2015-11-30  735  	struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa Mark Yao      2015-11-30  736  	const struct vop_win_data *win = vop_win->data;
63ebb9fa Mark Yao      2015-11-30  737  	struct vop *vop = to_vop(old_state->crtc);
2048e328 Mark Yao      2014-08-22  738  
63ebb9fa Mark Yao      2015-11-30  739  	if (!old_state->crtc)
63ebb9fa Mark Yao      2015-11-30  740  		return;
84c7f8ca Mark Yao      2015-07-20  741  
4f9d39a7 Daniel Vetter 2016-06-08  742  	spin_lock_irq(&plane->dev->event_lock);
4f9d39a7 Daniel Vetter 2016-06-08  743  	vop_win->enable = false;
4f9d39a7 Daniel Vetter 2016-06-08  744  	vop_win->yrgb_mst = 0;
4f9d39a7 Daniel Vetter 2016-06-08  745  	spin_unlock_irq(&plane->dev->event_lock);
4f9d39a7 Daniel Vetter 2016-06-08  746  
63ebb9fa Mark Yao      2015-11-30  747  	spin_lock(&vop->reg_lock);
63ebb9fa Mark Yao      2015-11-30  748  
63ebb9fa Mark Yao      2015-11-30  749  	VOP_WIN_SET(vop, win, enable, 0);
84c7f8ca Mark Yao      2015-07-20  750  
63ebb9fa Mark Yao      2015-11-30  751  	spin_unlock(&vop->reg_lock);
84c7f8ca Mark Yao      2015-07-20  752  
63ebb9fa Mark Yao      2015-11-30  753  	vop_plane_state->enable = false;
84c7f8ca Mark Yao      2015-07-20  754  }
84c7f8ca Mark Yao      2015-07-20  755  
63ebb9fa Mark Yao      2015-11-30 @756  static void vop_plane_atomic_update(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  757  		struct drm_plane_state *old_state)
63ebb9fa Mark Yao      2015-11-30  758  {
63ebb9fa Mark Yao      2015-11-30  759  	struct drm_plane_state *state = plane->state;

:::::: The code at line 653 was first introduced by commit
:::::: 63ebb9fa7ff06d194362ed4a5d0a31ac7612a89c drm/rockchip: Convert to support atomic API

:::::: TO: Mark Yao <mark.yao@rock-chips.com>
:::::: CC: Mark Yao <mark.yao@rock-chips.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[-- Attachment #2: .config.gz --]
[-- Type: application/octet-stream, Size: 38827 bytes --]

[PATCH 5/5] drm/rockchip: Add dmc notifier in vop driver

[kbuild test robot]

Hi Lin,

[auto build test ERROR on next-20160825]
[cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2 v4.8-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/rockchip/rockchip_drm_vop.c:23:0:
   include/linux/devfreq-event.h:190:21: error: redefinition of 'devfreq_event_get_drvdata'
    static inline void *devfreq_event_get_drvdata(struct devfreq_event_dev *edev)
                        ^
   include/linux/devfreq-event.h:151:21: note: previous definition of 'devfreq_event_get_drvdata' was here
    static inline void *devfreq_event_get_drvdata(struct devfreq_event_dev *edev)
                        ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c: In function 'vop_crtc_disable':
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:653:13: error: invalid storage class for function 'vop_plane_destroy'
    static void vop_plane_destroy(struct drm_plane *plane)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:653:1: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
    static void vop_plane_destroy(struct drm_plane *plane)
    ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:658:12: error: invalid storage class for function 'vop_plane_prepare_fb'
    static int vop_plane_prepare_fb(struct drm_plane *plane,
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:667:13: error: invalid storage class for function 'vop_plane_cleanup_fb'
    static void vop_plane_cleanup_fb(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:674:12: error: invalid storage class for function 'vop_plane_atomic_check'
    static int vop_plane_atomic_check(struct drm_plane *plane,
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:731:13: error: invalid storage class for function 'vop_plane_atomic_disable'
    static void vop_plane_atomic_disable(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:756:13: error: invalid storage class for function 'vop_plane_atomic_update'
    static void vop_plane_atomic_update(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:866:16: error: initializer element is not constant
     .prepare_fb = vop_plane_prepare_fb,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:866:16: note: (near initialization for 'plane_helper_funcs.prepare_fb')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:867:16: error: initializer element is not constant
     .cleanup_fb = vop_plane_cleanup_fb,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:867:16: note: (near initialization for 'plane_helper_funcs.cleanup_fb')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:868:18: error: initializer element is not constant
     .atomic_check = vop_plane_atomic_check,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:868:18: note: (near initialization for 'plane_helper_funcs.atomic_check')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:869:19: error: initializer element is not constant
     .atomic_update = vop_plane_atomic_update,
                      ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:869:19: note: (near initialization for 'plane_helper_funcs.atomic_update')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:870:20: error: initializer element is not constant
     .atomic_disable = vop_plane_atomic_disable,
                       ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:870:20: note: (near initialization for 'plane_helper_funcs.atomic_disable')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:873:13: error: invalid storage class for function 'vop_atomic_plane_reset'
    static void vop_atomic_plane_reset(struct drm_plane *plane)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:891:1: error: invalid storage class for function 'vop_atomic_plane_duplicate_state'
    vop_atomic_plane_duplicate_state(struct drm_plane *plane)
    ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:911:13: error: invalid storage class for function 'vop_atomic_plane_destroy_state'
    static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:924:13: error: initializer element is not constant
     .destroy = vop_plane_destroy,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:924:13: note: (near initialization for 'vop_plane_funcs.destroy')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:925:11: error: initializer element is not constant
     .reset = vop_atomic_plane_reset,
              ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:925:11: note: (near initialization for 'vop_plane_funcs.reset')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:926:28: error: initializer element is not constant
     .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
                               ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:926:28: note: (near initialization for 'vop_plane_funcs.atomic_duplicate_state')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:927:26: error: initializer element is not constant
     .atomic_destroy_state = vop_atomic_plane_destroy_state,
                             ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:927:26: note: (near initialization for 'vop_plane_funcs.atomic_destroy_state')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:930:12: error: invalid storage class for function 'vop_crtc_enable_vblank'
    static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:947:13: error: invalid storage class for function 'vop_crtc_disable_vblank'
    static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:962:13: error: invalid storage class for function 'vop_crtc_wait_for_update'
    static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:971:19: error: initializer element is not constant
     .enable_vblank = vop_crtc_enable_vblank,
                      ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:971:19: note: (near initialization for 'private_crtc_funcs.enable_vblank')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:972:20: error: initializer element is not constant
     .disable_vblank = vop_crtc_disable_vblank,
                       ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:972:20: note: (near initialization for 'private_crtc_funcs.disable_vblank')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:973:21: error: initializer element is not constant
     .wait_for_update = vop_crtc_wait_for_update,
                        ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:973:21: note: (near initialization for 'private_crtc_funcs.wait_for_update')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:976:13: error: invalid storage class for function 'vop_crtc_mode_fixup'
    static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:988:13: error: invalid storage class for function 'vop_crtc_enable'
    static void vop_crtc_enable(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1090:13: error: invalid storage class for function 'vop_crtc_atomic_flush'
    static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1105:13: error: invalid storage class for function 'vop_crtc_atomic_begin'
    static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1122:12: error: initializer element is not constant
     .enable = vop_crtc_enable,
               ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1122:12: note: (near initialization for 'vop_crtc_helper_funcs.enable')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1124:16: error: initializer element is not constant
     .mode_fixup = vop_crtc_mode_fixup,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1124:16: note: (near initialization for 'vop_crtc_helper_funcs.mode_fixup')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1125:18: error: initializer element is not constant
     .atomic_flush = vop_crtc_atomic_flush,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1125:18: note: (near initialization for 'vop_crtc_helper_funcs.atomic_flush')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1126:18: error: initializer element is not constant
     .atomic_begin = vop_crtc_atomic_begin,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1126:18: note: (near initialization for 'vop_crtc_helper_funcs.atomic_begin')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1129:13: error: invalid storage class for function 'vop_crtc_destroy'
    static void vop_crtc_destroy(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1134:13: error: invalid storage class for function 'vop_crtc_reset'
    static void vop_crtc_reset(struct drm_crtc *crtc)
                ^

vim +/vop_plane_destroy +653 drivers/gpu/drm/rockchip/rockchip_drm_vop.c

4bb85264 Lin Huang     2016-09-02  647  		if (vop->devfreq_event_dev)
4bb85264 Lin Huang     2016-09-02  648  			devfreq_event_enable_edev(vop->devfreq_event_dev);
4bb85264 Lin Huang     2016-09-02  649  		devfreq_resume_device(vop->devfreq);
893b6cad Daniel Vetter 2016-06-08  650  	}
2048e328 Mark Yao      2014-08-22  651  }
2048e328 Mark Yao      2014-08-22  652  
63ebb9fa Mark Yao      2015-11-30 @653  static void vop_plane_destroy(struct drm_plane *plane)
2048e328 Mark Yao      2014-08-22  654  {
63ebb9fa Mark Yao      2015-11-30  655  	drm_plane_cleanup(plane);
2048e328 Mark Yao      2014-08-22  656  }
2048e328 Mark Yao      2014-08-22  657  
44d0237a Mark Yao      2016-04-29 @658  static int vop_plane_prepare_fb(struct drm_plane *plane,
1832040d Chris Wilson  2016-08-18  659  				struct drm_plane_state *new_state)
44d0237a Mark Yao      2016-04-29  660  {
44d0237a Mark Yao      2016-04-29  661  	if (plane->state->fb)
44d0237a Mark Yao      2016-04-29  662  		drm_framebuffer_reference(plane->state->fb);
44d0237a Mark Yao      2016-04-29  663  
44d0237a Mark Yao      2016-04-29  664  	return 0;
44d0237a Mark Yao      2016-04-29  665  }
44d0237a Mark Yao      2016-04-29  666  
44d0237a Mark Yao      2016-04-29 @667  static void vop_plane_cleanup_fb(struct drm_plane *plane,
1832040d Chris Wilson  2016-08-18  668  				 struct drm_plane_state *old_state)
44d0237a Mark Yao      2016-04-29  669  {
44d0237a Mark Yao      2016-04-29  670  	if (old_state->fb)
44d0237a Mark Yao      2016-04-29  671  		drm_framebuffer_unreference(old_state->fb);
44d0237a Mark Yao      2016-04-29  672  }
44d0237a Mark Yao      2016-04-29  673  
63ebb9fa Mark Yao      2015-11-30 @674  static int vop_plane_atomic_check(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  675  			   struct drm_plane_state *state)
2048e328 Mark Yao      2014-08-22  676  {
63ebb9fa Mark Yao      2015-11-30  677  	struct drm_crtc *crtc = state->crtc;
92915da6 John Keeping  2016-03-04  678  	struct drm_crtc_state *crtc_state;
63ebb9fa Mark Yao      2015-11-30  679  	struct drm_framebuffer *fb = state->fb;
2048e328 Mark Yao      2014-08-22  680  	struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa Mark Yao      2015-11-30  681  	struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
2048e328 Mark Yao      2014-08-22  682  	const struct vop_win_data *win = vop_win->data;
2048e328 Mark Yao      2014-08-22  683  	int ret;
63ebb9fa Mark Yao      2015-11-30  684  	struct drm_rect clip;
4c156c21 Mark Yao      2015-06-26  685  	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
4c156c21 Mark Yao      2015-06-26  686  					DRM_PLANE_HELPER_NO_SCALING;
4c156c21 Mark Yao      2015-06-26  687  	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
4c156c21 Mark Yao      2015-06-26  688  					DRM_PLANE_HELPER_NO_SCALING;
2048e328 Mark Yao      2014-08-22  689  
63ebb9fa Mark Yao      2015-11-30  690  	if (!crtc || !fb)
63ebb9fa Mark Yao      2015-11-30  691  		goto out_disable;
92915da6 John Keeping  2016-03-04  692  
92915da6 John Keeping  2016-03-04  693  	crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
92915da6 John Keeping  2016-03-04  694  	if (WARN_ON(!crtc_state))
92915da6 John Keeping  2016-03-04  695  		return -EINVAL;
92915da6 John Keeping  2016-03-04  696  
63ebb9fa Mark Yao      2015-11-30  697  	clip.x1 = 0;
63ebb9fa Mark Yao      2015-11-30  698  	clip.y1 = 0;
92915da6 John Keeping  2016-03-04  699  	clip.x2 = crtc_state->adjusted_mode.hdisplay;
92915da6 John Keeping  2016-03-04  700  	clip.y2 = crtc_state->adjusted_mode.vdisplay;
63ebb9fa Mark Yao      2015-11-30  701  
f9b96be0 Ville Syrj?l? 2016-07-26  702  	ret = drm_plane_helper_check_state(state, &clip,
f9b96be0 Ville Syrj?l? 2016-07-26  703  					   min_scale, max_scale,
f9b96be0 Ville Syrj?l? 2016-07-26  704  					   true, true);
2048e328 Mark Yao      2014-08-22  705  	if (ret)
2048e328 Mark Yao      2014-08-22  706  		return ret;
2048e328 Mark Yao      2014-08-22  707  
f9b96be0 Ville Syrj?l? 2016-07-26  708  	if (!state->visible)
63ebb9fa Mark Yao      2015-11-30  709  		goto out_disable;
84c7f8ca Mark Yao      2015-07-20  710  
63ebb9fa Mark Yao      2015-11-30  711  	vop_plane_state->format = vop_convert_format(fb->pixel_format);
63ebb9fa Mark Yao      2015-11-30  712  	if (vop_plane_state->format < 0)
63ebb9fa Mark Yao      2015-11-30  713  		return vop_plane_state->format;
2048e328 Mark Yao      2014-08-22  714  
84c7f8ca Mark Yao      2015-07-20  715  	/*
84c7f8ca Mark Yao      2015-07-20  716  	 * Src.x1 can be odd when do clip, but yuv plane start point
84c7f8ca Mark Yao      2015-07-20  717  	 * need align with 2 pixel.
84c7f8ca Mark Yao      2015-07-20  718  	 */
f9b96be0 Ville Syrj?l? 2016-07-26  719  	if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2))
63ebb9fa Mark Yao      2015-11-30  720  		return -EINVAL;
84c7f8ca Mark Yao      2015-07-20  721  
63ebb9fa Mark Yao      2015-11-30  722  	vop_plane_state->enable = true;
2048e328 Mark Yao      2014-08-22  723  
63ebb9fa Mark Yao      2015-11-30  724  	return 0;
2048e328 Mark Yao      2014-08-22  725  
63ebb9fa Mark Yao      2015-11-30  726  out_disable:
63ebb9fa Mark Yao      2015-11-30  727  	vop_plane_state->enable = false;
63ebb9fa Mark Yao      2015-11-30  728  	return 0;
63ebb9fa Mark Yao      2015-11-30  729  }
2048e328 Mark Yao      2014-08-22  730  
63ebb9fa Mark Yao      2015-11-30 @731  static void vop_plane_atomic_disable(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  732  				     struct drm_plane_state *old_state)
63ebb9fa Mark Yao      2015-11-30  733  {
63ebb9fa Mark Yao      2015-11-30  734  	struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
63ebb9fa Mark Yao      2015-11-30  735  	struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa Mark Yao      2015-11-30  736  	const struct vop_win_data *win = vop_win->data;
63ebb9fa Mark Yao      2015-11-30  737  	struct vop *vop = to_vop(old_state->crtc);
2048e328 Mark Yao      2014-08-22  738  
63ebb9fa Mark Yao      2015-11-30  739  	if (!old_state->crtc)
63ebb9fa Mark Yao      2015-11-30  740  		return;
84c7f8ca Mark Yao      2015-07-20  741  
4f9d39a7 Daniel Vetter 2016-06-08  742  	spin_lock_irq(&plane->dev->event_lock);
4f9d39a7 Daniel Vetter 2016-06-08  743  	vop_win->enable = false;
4f9d39a7 Daniel Vetter 2016-06-08  744  	vop_win->yrgb_mst = 0;
4f9d39a7 Daniel Vetter 2016-06-08  745  	spin_unlock_irq(&plane->dev->event_lock);
4f9d39a7 Daniel Vetter 2016-06-08  746  
63ebb9fa Mark Yao      2015-11-30  747  	spin_lock(&vop->reg_lock);
63ebb9fa Mark Yao      2015-11-30  748  
63ebb9fa Mark Yao      2015-11-30  749  	VOP_WIN_SET(vop, win, enable, 0);
84c7f8ca Mark Yao      2015-07-20  750  
63ebb9fa Mark Yao      2015-11-30  751  	spin_unlock(&vop->reg_lock);
84c7f8ca Mark Yao      2015-07-20  752  
63ebb9fa Mark Yao      2015-11-30  753  	vop_plane_state->enable = false;
84c7f8ca Mark Yao      2015-07-20  754  }
84c7f8ca Mark Yao      2015-07-20  755  
63ebb9fa Mark Yao      2015-11-30 @756  static void vop_plane_atomic_update(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  757  		struct drm_plane_state *old_state)
63ebb9fa Mark Yao      2015-11-30  758  {
63ebb9fa Mark Yao      2015-11-30  759  	struct drm_plane_state *state = plane->state;

:::::: The code at line 653 was first introduced by commit
:::::: 63ebb9fa7ff06d194362ed4a5d0a31ac7612a89c drm/rockchip: Convert to support atomic API

:::::: TO: Mark Yao <mark.yao@rock-chips.com>
:::::: CC: Mark Yao <mark.yao@rock-chips.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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Re: [PATCH 5/5] drm/rockchip: Add dmc notifier in vop driver

[kbuild test robot]

[-- Attachment #1: Type: text/plain, Size: 17809 bytes --]

Hi Lin,

[auto build test ERROR on next-20160825]
[cannot apply to rockchip/for-next devfreq/for-rafael linus/master v4.8-rc4 v4.8-rc3 v4.8-rc2 v4.8-rc4]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Lin-Huang/rk3399-support-ddr-frequency-scaling/20160902-063701
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 5.4.0-6) 5.4.0 20160609
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

All error/warnings (new ones prefixed by >>):

   In file included from drivers/gpu/drm/rockchip/rockchip_drm_vop.c:23:0:
   include/linux/devfreq-event.h:190:21: error: redefinition of 'devfreq_event_get_drvdata'
    static inline void *devfreq_event_get_drvdata(struct devfreq_event_dev *edev)
                        ^
   include/linux/devfreq-event.h:151:21: note: previous definition of 'devfreq_event_get_drvdata' was here
    static inline void *devfreq_event_get_drvdata(struct devfreq_event_dev *edev)
                        ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c: In function 'vop_crtc_disable':
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:653:13: error: invalid storage class for function 'vop_plane_destroy'
    static void vop_plane_destroy(struct drm_plane *plane)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:653:1: warning: ISO C90 forbids mixed declarations and code [-Wdeclaration-after-statement]
    static void vop_plane_destroy(struct drm_plane *plane)
    ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:658:12: error: invalid storage class for function 'vop_plane_prepare_fb'
    static int vop_plane_prepare_fb(struct drm_plane *plane,
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:667:13: error: invalid storage class for function 'vop_plane_cleanup_fb'
    static void vop_plane_cleanup_fb(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:674:12: error: invalid storage class for function 'vop_plane_atomic_check'
    static int vop_plane_atomic_check(struct drm_plane *plane,
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:731:13: error: invalid storage class for function 'vop_plane_atomic_disable'
    static void vop_plane_atomic_disable(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:756:13: error: invalid storage class for function 'vop_plane_atomic_update'
    static void vop_plane_atomic_update(struct drm_plane *plane,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:866:16: error: initializer element is not constant
     .prepare_fb = vop_plane_prepare_fb,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:866:16: note: (near initialization for 'plane_helper_funcs.prepare_fb')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:867:16: error: initializer element is not constant
     .cleanup_fb = vop_plane_cleanup_fb,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:867:16: note: (near initialization for 'plane_helper_funcs.cleanup_fb')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:868:18: error: initializer element is not constant
     .atomic_check = vop_plane_atomic_check,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:868:18: note: (near initialization for 'plane_helper_funcs.atomic_check')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:869:19: error: initializer element is not constant
     .atomic_update = vop_plane_atomic_update,
                      ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:869:19: note: (near initialization for 'plane_helper_funcs.atomic_update')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:870:20: error: initializer element is not constant
     .atomic_disable = vop_plane_atomic_disable,
                       ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:870:20: note: (near initialization for 'plane_helper_funcs.atomic_disable')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:873:13: error: invalid storage class for function 'vop_atomic_plane_reset'
    static void vop_atomic_plane_reset(struct drm_plane *plane)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:891:1: error: invalid storage class for function 'vop_atomic_plane_duplicate_state'
    vop_atomic_plane_duplicate_state(struct drm_plane *plane)
    ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:911:13: error: invalid storage class for function 'vop_atomic_plane_destroy_state'
    static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:924:13: error: initializer element is not constant
     .destroy = vop_plane_destroy,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:924:13: note: (near initialization for 'vop_plane_funcs.destroy')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:925:11: error: initializer element is not constant
     .reset = vop_atomic_plane_reset,
              ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:925:11: note: (near initialization for 'vop_plane_funcs.reset')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:926:28: error: initializer element is not constant
     .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
                               ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:926:28: note: (near initialization for 'vop_plane_funcs.atomic_duplicate_state')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:927:26: error: initializer element is not constant
     .atomic_destroy_state = vop_atomic_plane_destroy_state,
                             ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:927:26: note: (near initialization for 'vop_plane_funcs.atomic_destroy_state')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:930:12: error: invalid storage class for function 'vop_crtc_enable_vblank'
    static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
               ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:947:13: error: invalid storage class for function 'vop_crtc_disable_vblank'
    static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:962:13: error: invalid storage class for function 'vop_crtc_wait_for_update'
    static void vop_crtc_wait_for_update(struct drm_crtc *crtc)
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:971:19: error: initializer element is not constant
     .enable_vblank = vop_crtc_enable_vblank,
                      ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:971:19: note: (near initialization for 'private_crtc_funcs.enable_vblank')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:972:20: error: initializer element is not constant
     .disable_vblank = vop_crtc_disable_vblank,
                       ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:972:20: note: (near initialization for 'private_crtc_funcs.disable_vblank')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:973:21: error: initializer element is not constant
     .wait_for_update = vop_crtc_wait_for_update,
                        ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:973:21: note: (near initialization for 'private_crtc_funcs.wait_for_update')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:976:13: error: invalid storage class for function 'vop_crtc_mode_fixup'
    static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:988:13: error: invalid storage class for function 'vop_crtc_enable'
    static void vop_crtc_enable(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1090:13: error: invalid storage class for function 'vop_crtc_atomic_flush'
    static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1105:13: error: invalid storage class for function 'vop_crtc_atomic_begin'
    static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
                ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1122:12: error: initializer element is not constant
     .enable = vop_crtc_enable,
               ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1122:12: note: (near initialization for 'vop_crtc_helper_funcs.enable')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1124:16: error: initializer element is not constant
     .mode_fixup = vop_crtc_mode_fixup,
                   ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1124:16: note: (near initialization for 'vop_crtc_helper_funcs.mode_fixup')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1125:18: error: initializer element is not constant
     .atomic_flush = vop_crtc_atomic_flush,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1125:18: note: (near initialization for 'vop_crtc_helper_funcs.atomic_flush')
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1126:18: error: initializer element is not constant
     .atomic_begin = vop_crtc_atomic_begin,
                     ^
   drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1126:18: note: (near initialization for 'vop_crtc_helper_funcs.atomic_begin')
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1129:13: error: invalid storage class for function 'vop_crtc_destroy'
    static void vop_crtc_destroy(struct drm_crtc *crtc)
                ^
>> drivers/gpu/drm/rockchip/rockchip_drm_vop.c:1134:13: error: invalid storage class for function 'vop_crtc_reset'
    static void vop_crtc_reset(struct drm_crtc *crtc)
                ^

vim +/vop_plane_destroy +653 drivers/gpu/drm/rockchip/rockchip_drm_vop.c

4bb85264 Lin Huang     2016-09-02  647  		if (vop->devfreq_event_dev)
4bb85264 Lin Huang     2016-09-02  648  			devfreq_event_enable_edev(vop->devfreq_event_dev);
4bb85264 Lin Huang     2016-09-02  649  		devfreq_resume_device(vop->devfreq);
893b6cad Daniel Vetter 2016-06-08  650  	}
2048e328 Mark Yao      2014-08-22  651  }
2048e328 Mark Yao      2014-08-22  652  
63ebb9fa Mark Yao      2015-11-30 @653  static void vop_plane_destroy(struct drm_plane *plane)
2048e328 Mark Yao      2014-08-22  654  {
63ebb9fa Mark Yao      2015-11-30  655  	drm_plane_cleanup(plane);
2048e328 Mark Yao      2014-08-22  656  }
2048e328 Mark Yao      2014-08-22  657  
44d0237a Mark Yao      2016-04-29 @658  static int vop_plane_prepare_fb(struct drm_plane *plane,
1832040d Chris Wilson  2016-08-18  659  				struct drm_plane_state *new_state)
44d0237a Mark Yao      2016-04-29  660  {
44d0237a Mark Yao      2016-04-29  661  	if (plane->state->fb)
44d0237a Mark Yao      2016-04-29  662  		drm_framebuffer_reference(plane->state->fb);
44d0237a Mark Yao      2016-04-29  663  
44d0237a Mark Yao      2016-04-29  664  	return 0;
44d0237a Mark Yao      2016-04-29  665  }
44d0237a Mark Yao      2016-04-29  666  
44d0237a Mark Yao      2016-04-29 @667  static void vop_plane_cleanup_fb(struct drm_plane *plane,
1832040d Chris Wilson  2016-08-18  668  				 struct drm_plane_state *old_state)
44d0237a Mark Yao      2016-04-29  669  {
44d0237a Mark Yao      2016-04-29  670  	if (old_state->fb)
44d0237a Mark Yao      2016-04-29  671  		drm_framebuffer_unreference(old_state->fb);
44d0237a Mark Yao      2016-04-29  672  }
44d0237a Mark Yao      2016-04-29  673  
63ebb9fa Mark Yao      2015-11-30 @674  static int vop_plane_atomic_check(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  675  			   struct drm_plane_state *state)
2048e328 Mark Yao      2014-08-22  676  {
63ebb9fa Mark Yao      2015-11-30  677  	struct drm_crtc *crtc = state->crtc;
92915da6 John Keeping  2016-03-04  678  	struct drm_crtc_state *crtc_state;
63ebb9fa Mark Yao      2015-11-30  679  	struct drm_framebuffer *fb = state->fb;
2048e328 Mark Yao      2014-08-22  680  	struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa Mark Yao      2015-11-30  681  	struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
2048e328 Mark Yao      2014-08-22  682  	const struct vop_win_data *win = vop_win->data;
2048e328 Mark Yao      2014-08-22  683  	int ret;
63ebb9fa Mark Yao      2015-11-30  684  	struct drm_rect clip;
4c156c21 Mark Yao      2015-06-26  685  	int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
4c156c21 Mark Yao      2015-06-26  686  					DRM_PLANE_HELPER_NO_SCALING;
4c156c21 Mark Yao      2015-06-26  687  	int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
4c156c21 Mark Yao      2015-06-26  688  					DRM_PLANE_HELPER_NO_SCALING;
2048e328 Mark Yao      2014-08-22  689  
63ebb9fa Mark Yao      2015-11-30  690  	if (!crtc || !fb)
63ebb9fa Mark Yao      2015-11-30  691  		goto out_disable;
92915da6 John Keeping  2016-03-04  692  
92915da6 John Keeping  2016-03-04  693  	crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
92915da6 John Keeping  2016-03-04  694  	if (WARN_ON(!crtc_state))
92915da6 John Keeping  2016-03-04  695  		return -EINVAL;
92915da6 John Keeping  2016-03-04  696  
63ebb9fa Mark Yao      2015-11-30  697  	clip.x1 = 0;
63ebb9fa Mark Yao      2015-11-30  698  	clip.y1 = 0;
92915da6 John Keeping  2016-03-04  699  	clip.x2 = crtc_state->adjusted_mode.hdisplay;
92915da6 John Keeping  2016-03-04  700  	clip.y2 = crtc_state->adjusted_mode.vdisplay;
63ebb9fa Mark Yao      2015-11-30  701  
f9b96be0 Ville Syrjälä 2016-07-26  702  	ret = drm_plane_helper_check_state(state, &clip,
f9b96be0 Ville Syrjälä 2016-07-26  703  					   min_scale, max_scale,
f9b96be0 Ville Syrjälä 2016-07-26  704  					   true, true);
2048e328 Mark Yao      2014-08-22  705  	if (ret)
2048e328 Mark Yao      2014-08-22  706  		return ret;
2048e328 Mark Yao      2014-08-22  707  
f9b96be0 Ville Syrjälä 2016-07-26  708  	if (!state->visible)
63ebb9fa Mark Yao      2015-11-30  709  		goto out_disable;
84c7f8ca Mark Yao      2015-07-20  710  
63ebb9fa Mark Yao      2015-11-30  711  	vop_plane_state->format = vop_convert_format(fb->pixel_format);
63ebb9fa Mark Yao      2015-11-30  712  	if (vop_plane_state->format < 0)
63ebb9fa Mark Yao      2015-11-30  713  		return vop_plane_state->format;
2048e328 Mark Yao      2014-08-22  714  
84c7f8ca Mark Yao      2015-07-20  715  	/*
84c7f8ca Mark Yao      2015-07-20  716  	 * Src.x1 can be odd when do clip, but yuv plane start point
84c7f8ca Mark Yao      2015-07-20  717  	 * need align with 2 pixel.
84c7f8ca Mark Yao      2015-07-20  718  	 */
f9b96be0 Ville Syrjälä 2016-07-26  719  	if (is_yuv_support(fb->pixel_format) && ((state->src.x1 >> 16) % 2))
63ebb9fa Mark Yao      2015-11-30  720  		return -EINVAL;
84c7f8ca Mark Yao      2015-07-20  721  
63ebb9fa Mark Yao      2015-11-30  722  	vop_plane_state->enable = true;
2048e328 Mark Yao      2014-08-22  723  
63ebb9fa Mark Yao      2015-11-30  724  	return 0;
2048e328 Mark Yao      2014-08-22  725  
63ebb9fa Mark Yao      2015-11-30  726  out_disable:
63ebb9fa Mark Yao      2015-11-30  727  	vop_plane_state->enable = false;
63ebb9fa Mark Yao      2015-11-30  728  	return 0;
63ebb9fa Mark Yao      2015-11-30  729  }
2048e328 Mark Yao      2014-08-22  730  
63ebb9fa Mark Yao      2015-11-30 @731  static void vop_plane_atomic_disable(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  732  				     struct drm_plane_state *old_state)
63ebb9fa Mark Yao      2015-11-30  733  {
63ebb9fa Mark Yao      2015-11-30  734  	struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
63ebb9fa Mark Yao      2015-11-30  735  	struct vop_win *vop_win = to_vop_win(plane);
63ebb9fa Mark Yao      2015-11-30  736  	const struct vop_win_data *win = vop_win->data;
63ebb9fa Mark Yao      2015-11-30  737  	struct vop *vop = to_vop(old_state->crtc);
2048e328 Mark Yao      2014-08-22  738  
63ebb9fa Mark Yao      2015-11-30  739  	if (!old_state->crtc)
63ebb9fa Mark Yao      2015-11-30  740  		return;
84c7f8ca Mark Yao      2015-07-20  741  
4f9d39a7 Daniel Vetter 2016-06-08  742  	spin_lock_irq(&plane->dev->event_lock);
4f9d39a7 Daniel Vetter 2016-06-08  743  	vop_win->enable = false;
4f9d39a7 Daniel Vetter 2016-06-08  744  	vop_win->yrgb_mst = 0;
4f9d39a7 Daniel Vetter 2016-06-08  745  	spin_unlock_irq(&plane->dev->event_lock);
4f9d39a7 Daniel Vetter 2016-06-08  746  
63ebb9fa Mark Yao      2015-11-30  747  	spin_lock(&vop->reg_lock);
63ebb9fa Mark Yao      2015-11-30  748  
63ebb9fa Mark Yao      2015-11-30  749  	VOP_WIN_SET(vop, win, enable, 0);
84c7f8ca Mark Yao      2015-07-20  750  
63ebb9fa Mark Yao      2015-11-30  751  	spin_unlock(&vop->reg_lock);
84c7f8ca Mark Yao      2015-07-20  752  
63ebb9fa Mark Yao      2015-11-30  753  	vop_plane_state->enable = false;
84c7f8ca Mark Yao      2015-07-20  754  }
84c7f8ca Mark Yao      2015-07-20  755  
63ebb9fa Mark Yao      2015-11-30 @756  static void vop_plane_atomic_update(struct drm_plane *plane,
63ebb9fa Mark Yao      2015-11-30  757  		struct drm_plane_state *old_state)
63ebb9fa Mark Yao      2015-11-30  758  {
63ebb9fa Mark Yao      2015-11-30  759  	struct drm_plane_state *state = plane->state;

:::::: The code at line 653 was first introduced by commit
:::::: 63ebb9fa7ff06d194362ed4a5d0a31ac7612a89c drm/rockchip: Convert to support atomic API

:::::: TO: Mark Yao <mark.yao@rock-chips.com>
:::::: CC: Mark Yao <mark.yao@rock-chips.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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