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From: "Jan Beulich" <JBeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Xen-devel <xen-devel@lists.xen.org>
Subject: Re: [PATCH v9 08/11] x86/entry: Clobber the Return Stack Buffer/Return Address Stack on entry to Xen
Date: Fri, 19 Jan 2018 08:02:13 -0700	[thread overview]
Message-ID: <5A62168502000078001A06BD@prv-mh.provo.novell.com> (raw)
In-Reply-To: <b36fffad-b6ab-3ea7-c4e1-34097b9a5161@citrix.com>

>>> On 19.01.18 at 15:24, <andrew.cooper3@citrix.com> wrote:
> On 19/01/18 12:47, Jan Beulich wrote:
>>>>> On 18.01.18 at 16:46, <andrew.cooper3@citrix.com> wrote:
>>> @@ -265,6 +265,10 @@ On hardware supporting IBRS, the `ibrs=` option can be 
>>> used to force or
>>>  prevent Xen using the feature itself.  If Xen is not using IBRS itself,
>>>  functionality is still set up so IBRS can be virtualised for guests.
>>>  
>>> +The `rsb_vmexit=` and `rsb_native=` options can be used to fine tune when the
>>> +RSB gets overwritten.  There are individual controls for an entry from HVM
>>> +context, and an entry from a native (PV or Xen) context.
>> Would you mind adding a sentence or two to the description making
>> clear what use this fine grained control is? I can't really figure why I
>> might need to be concerned about one of the two cases, but not the
>> other.
> 
> I though I'd covered that in the commit message, but I'm not sure this
> is a suitable place to discuss the details.  PV and HVM guests have
> different reasoning for why we need to overwrite the RSB.
> 
> In the past, there used to be a default interaction of rsb_native and
> SMEP, but that proved to be insufficient and rsb_native is now
> unconditionally enabled.  In principle however, it should fall within
> CONFIG_PV.

Thanks for the explanation, but I'm afraid I'm none the wiser as
to why the two separate options are needed (or even just wanted).

>>> --- a/xen/include/asm-x86/spec_ctrl_asm.h
>>> +++ b/xen/include/asm-x86/spec_ctrl_asm.h
>>> @@ -73,6 +73,40 @@
>>>   *  - SPEC_CTRL_EXIT_TO_GUEST
>>>   */
>>>  
>>> +.macro DO_OVERWRITE_RSB
>>> +/*
>>> + * Requires nothing
>>> + * Clobbers %rax, %rcx
>>> + *
>>> + * Requires 256 bytes of stack space, but %rsp has no net change. Based on
>>> + * Google's performance numbers, the loop is unrolled to 16 iterations and two
>>> + * calls per iteration.
>>> + *
>>> + * The call filling the RSB needs a nonzero displacement, but we use "1:
>>> + * pause, jmp 1b" to safely contains any ret-based speculation, even if the
>>> + * loop is speculatively executed prematurely.
>> I'm struggling to understand why you use "but" here. Maybe just a
>> lack of English skills on my part?
> 
> "displacement.  A nop would do, but" ?
> 
> It is a justification for why we are putting more than a single byte in
> the middle.

Oh, I see, but only with the addition you suggest.

>>> + * %rsp is preserved by using an extra GPR because a) we've got plenty spare,
>>> + * b) the two movs are shorter to encode than `add $32*8, %rsp`, and c) can be
>>> + * optimised with mov-elimination in modern cores.
>>> + */
>>> +    mov $16, %ecx   /* 16 iterations, two calls per loop */
>>> +    mov %rsp, %rax  /* Store the current %rsp */
>>> +
>>> +.L\@_fill_rsb_loop:
>>> +
>>> +    .rept 2         /* Unrolled twice. */
>>> +    call 2f         /* Create an RSB entry. */
>>> +1:  pause
>>> +    jmp 1b          /* Capture rogue speculation. */
>>> +2:
>> I won't further insist on changing away from numeric labels here, but
>> I'd still like to point out an example of a high risk use of such labels in
>> mainline code: There's a "jz 1b" soon after
>> exception_with_ints_disabled, leading across _two_ other labels and
>> quite a few insns and macro invocations. May I at the very least
>> suggest that you don't use 1 and 2 here?
> 
> I spent ages trying to get .L labels working here, but they don't
> function inside a rept, as you end up with duplicate local symbols.
> 
> Even using irp to inject a unique number into the loop doesn't appear to
> work, because the \ escape gets interpreted as a token separator. 
> AFAICT, \@ is special by virtue of the fact that it doesn't count as a
> token separator.
> 
> If you've got a better suggestion then I'm all ears.
> 
> Alternatively, I could manually unroll the loop, or pick some arbitrary
> other numbers to use.

Since the unroll number is just 2, this is what I would have
suggested primarily. .rept of course won't work, as it's not a
macro invocation, and hence doesn't increment the internal
counter. With .irp I can get things to work:

	.macro m
	.irp n, 1, 2
.Lxyz_\@_\n:	mov	$\@, %eax
	.endr
	.endm

Jan

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  reply	other threads:[~2018-01-19 15:02 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-18 15:45 [PATCH v9 00/11] x86: Mitigations for SP2/CVE-2017-5715/Branch Target Injection Andrew Cooper
2018-01-18 15:46 ` [PATCH v9 01/11] x86/thunk: Fix GEN_INDIRECT_THUNK comment Andrew Cooper
2018-01-18 16:06   ` Jan Beulich
2018-01-18 15:46 ` [PATCH v9 02/11] x86/cpuid: Handling of IBRS/IBPB, STIBP and IBRS for guests Andrew Cooper
2018-01-19 10:40   ` Jan Beulich
2018-01-19 10:53     ` Andrew Cooper
2018-01-19 11:46       ` Jan Beulich
2018-01-19 12:01         ` Andrew Cooper
2018-01-19 12:11           ` Jan Beulich
2018-01-19 12:36             ` Andrew Cooper
2018-01-19 12:52               ` Jan Beulich
2018-01-19 13:06                 ` Andrew Cooper
2018-01-19 13:33                   ` Jan Beulich
2018-01-19 15:00                     ` Andrew Cooper
2018-01-19 15:09                       ` Jan Beulich
2018-01-18 15:46 ` [PATCH v9 03/11] x86/msr: Emulation of MSR_{SPEC_CTRL, PRED_CMD} " Andrew Cooper
2018-01-19 10:45   ` Jan Beulich
2018-01-19 11:05     ` Andrew Cooper
2018-01-22 14:50     ` Andrew Cooper
2018-01-18 15:46 ` [PATCH v9 04/11] x86/migrate: Move MSR_SPEC_CTRL on migrate Andrew Cooper
2018-01-18 15:46 ` [PATCH v9 05/11] x86/hvm: Permit guests direct access to MSR_{SPEC_CTRL, PRED_CMD} Andrew Cooper
2018-01-18 18:04   ` Boris Ostrovsky
2018-01-19 10:52   ` Jan Beulich
2018-01-19 10:54     ` Andrew Cooper
2018-01-22  1:47   ` Tian, Kevin
2018-01-18 15:46 ` [PATCH v9 06/11] x86/entry: Organise the use of MSR_SPEC_CTRL at each entry/exit point Andrew Cooper
2018-01-19 10:39   ` Andrew Cooper
2018-01-19 11:43   ` Jan Beulich
2018-01-19 13:36     ` Andrew Cooper
2018-01-19 13:51       ` Jan Beulich
2018-01-22 11:42         ` Andrew Cooper
2018-01-22 12:06           ` Jan Beulich
2018-01-22 13:52             ` Andrew Cooper
2018-01-22 22:27       ` Boris Ostrovsky
2018-01-23  0:17         ` Andrew Cooper
2018-01-23  2:19           ` Boris Ostrovsky
2018-01-23 20:00             ` Andrew Cooper
2018-01-18 15:46 ` [PATCH v9 07/11] x86/boot: Calculate the most appropriate BTI mitigation to use Andrew Cooper
2018-01-19 12:06   ` Jan Beulich
2018-01-19 13:48     ` Andrew Cooper
2018-01-19 14:01   ` Jan Beulich
2018-01-22 15:11     ` Andrew Cooper
2018-01-18 15:46 ` [PATCH v9 08/11] x86/entry: Clobber the Return Stack Buffer/Return Address Stack on entry to Xen Andrew Cooper
2018-01-19 12:47   ` Jan Beulich
2018-01-19 14:24     ` Andrew Cooper
2018-01-19 15:02       ` Jan Beulich [this message]
2018-01-19 16:10         ` Andrew Cooper
2018-01-19 16:19           ` Jan Beulich
2018-01-19 16:43             ` Andrew Cooper
2018-01-22 15:51         ` Andrew Cooper
2018-01-22 16:49           ` Jan Beulich
2018-01-22 17:04             ` Andrew Cooper
2018-01-18 15:46 ` [PATCH v9 09/11] x86/ctxt: Issue a speculation barrier between vcpu contexts Andrew Cooper
2018-01-19 13:25   ` Jan Beulich
2018-01-19 14:48     ` Andrew Cooper
2018-01-19 15:07       ` Jan Beulich
2018-01-20 11:10         ` David Woodhouse
2018-01-22 10:15           ` Jan Beulich
2018-01-18 15:46 ` [PATCH v9 10/11] x86/cpuid: Offer Indirect Branch Controls to guests Andrew Cooper
2018-01-18 15:46 ` [PATCH v9 11/11] x86/idle: Clear SPEC_CTRL while idle Andrew Cooper

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