From: <Conor.Dooley@microchip.com> To: <andrew@lunn.ch> Cc: <palmer@rivosinc.com>, <apatel@ventanamicro.com>, <netdev@vger.kernel.org>, <Nicolas.Ferre@microchip.com>, <Claudiu.Beznea@microchip.com>, <linux@armlinux.org.uk>, <hkallweit1@gmail.com>, <linux-riscv@lists.infradead.org> Subject: Re: riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1 Date: Tue, 5 Apr 2022 14:41:00 +0000 [thread overview] Message-ID: <60fd1eb7-a2ce-9084-c567-721e975e7e86@microchip.com> (raw) In-Reply-To: <98b571fb-993e-9fe1-1cf9-dc09651feb0b@microchip.com> On 05/04/2022 14:17, Conor Dooley wrote: > > > On 05/04/2022 13:25, Andrew Lunn wrote: >> On Tue, Apr 05, 2022 at 01:05:12PM +0000, Conor.Dooley@microchip.com wrote: >>> [ 2.818894] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL) >> >> Hi Conor >> >> In general, it is better to use the specific PHY driver for the PHY >> then rely on the generic PHY driver. I think the Icicle Kit has a >> VSC8662? So i would suggest you enable the Vitesse PHYs. > > Hi Andrew, thanks for the quick reply. > It does indeed have a Vitesse VSC8662, but the link never seems to > come up for me [1] so I have been using Generic PHY. I'll try look > at why that is. Either way would like to know what's gone wrong in > the Generic PHY case since that's what's available in the riscv > defconfig. I think I put this badly - without the reversion of the CONFIG_PM addition, the link doesn't come up for the Vitesse driver but there is no validation failure: [ 1.521768] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (00:04:a3:4d:4c:dc) [ 3.206274] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) [ 3.216641] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode (and then nothing) If I revert the CONFIG_PM addition: [ 1.508882] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (00:04:a3:4d:4c:dc) [ 2.879617] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) [ 2.890010] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode [ 6.981823] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off [ 6.989657] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready > > Thanks, > Conor. > > [1]: > >> >> Andrew >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: <Conor.Dooley@microchip.com> To: <andrew@lunn.ch> Cc: <palmer@rivosinc.com>, <apatel@ventanamicro.com>, <netdev@vger.kernel.org>, <Nicolas.Ferre@microchip.com>, <Claudiu.Beznea@microchip.com>, <linux@armlinux.org.uk>, <hkallweit1@gmail.com>, <linux-riscv@lists.infradead.org> Subject: Re: riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1 Date: Tue, 5 Apr 2022 14:41:00 +0000 [thread overview] Message-ID: <60fd1eb7-a2ce-9084-c567-721e975e7e86@microchip.com> (raw) In-Reply-To: <98b571fb-993e-9fe1-1cf9-dc09651feb0b@microchip.com> On 05/04/2022 14:17, Conor Dooley wrote: > > > On 05/04/2022 13:25, Andrew Lunn wrote: >> On Tue, Apr 05, 2022 at 01:05:12PM +0000, Conor.Dooley@microchip.com wrote: >>> [ 2.818894] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL) >> >> Hi Conor >> >> In general, it is better to use the specific PHY driver for the PHY >> then rely on the generic PHY driver. I think the Icicle Kit has a >> VSC8662? So i would suggest you enable the Vitesse PHYs. > > Hi Andrew, thanks for the quick reply. > It does indeed have a Vitesse VSC8662, but the link never seems to > come up for me [1] so I have been using Generic PHY. I'll try look > at why that is. Either way would like to know what's gone wrong in > the Generic PHY case since that's what's available in the riscv > defconfig. I think I put this badly - without the reversion of the CONFIG_PM addition, the link doesn't come up for the Vitesse driver but there is no validation failure: [ 1.521768] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (00:04:a3:4d:4c:dc) [ 3.206274] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) [ 3.216641] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode (and then nothing) If I revert the CONFIG_PM addition: [ 1.508882] macb 20112000.ethernet eth0: Cadence GEM rev 0x0107010c at 0x20112000 irq 17 (00:04:a3:4d:4c:dc) [ 2.879617] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Vitesse VSC8662] (irq=POLL) [ 2.890010] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode [ 6.981823] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off [ 6.989657] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready > > Thanks, > Conor. > > [1]: > >> >> Andrew >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-04-05 14:41 UTC|newest] Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-05 13:05 riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1 Conor.Dooley 2022-04-05 13:05 ` Conor.Dooley 2022-04-05 13:25 ` Andrew Lunn 2022-04-05 13:25 ` Andrew Lunn 2022-04-05 14:18 ` Conor.Dooley 2022-04-05 14:18 ` Conor.Dooley 2022-04-05 14:41 ` Conor.Dooley [this message] 2022-04-05 14:41 ` Conor.Dooley 2022-04-05 14:49 ` Andrew Lunn 2022-04-05 14:49 ` Andrew Lunn 2022-04-05 14:56 ` Andrew Lunn 2022-04-05 14:56 ` Andrew Lunn 2022-04-05 15:04 ` Andrew Lunn 2022-04-05 15:04 ` Andrew Lunn 2022-04-05 16:25 ` Conor Dooley 2022-04-05 16:25 ` Conor Dooley 2022-04-06 8:36 ` Conor.Dooley 2022-04-06 8:36 ` Conor.Dooley 2022-04-07 14:30 ` Conor.Dooley 2022-04-07 14:30 ` Conor.Dooley 2022-04-05 15:53 ` Russell King (Oracle) 2022-04-05 15:53 ` Russell King (Oracle) 2022-04-05 16:56 ` Palmer Dabbelt 2022-04-05 16:56 ` Palmer Dabbelt 2022-04-05 17:23 ` Conor Dooley 2022-04-05 17:23 ` Conor Dooley 2022-04-05 18:06 ` Andrew Lunn 2022-04-05 18:06 ` Andrew Lunn 2022-04-05 18:35 ` Conor Dooley 2022-04-05 18:35 ` Conor Dooley 2022-04-05 16:58 ` Conor Dooley 2022-04-05 16:58 ` Conor Dooley 2022-04-05 18:55 ` Russell King (Oracle) 2022-04-05 18:55 ` Russell King (Oracle)
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