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From: Conor Dooley <mail@conchuod.ie>
To: Andrew Lunn <andrew@lunn.ch>, Conor.Dooley@microchip.com
Cc: palmer@rivosinc.com, apatel@ventanamicro.com,
	netdev@vger.kernel.org, Nicolas.Ferre@microchip.com,
	Claudiu.Beznea@microchip.com, linux@armlinux.org.uk,
	hkallweit1@gmail.com, linux-riscv@lists.infradead.org
Subject: Re: riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1
Date: Tue, 5 Apr 2022 17:25:00 +0100	[thread overview]
Message-ID: <e445af29-4354-69c3-fa9a-c5b99d90a9a5@conchuod.ie> (raw)
In-Reply-To: <YkxaiEbHwduhS2+p@lunn.ch>

On 05/04/2022 16:04, Andrew Lunn wrote:
>> [ 2.818894] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL)
>> [ 2.828915] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
>> [11.045411] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
>> [11.053247] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> 
> You have a multi-part link. You need that the PHY reports the line
> side is up. Put some printk in genphy_update_link() and look at
> phydev->link. You also need that the SGMII link between the PHY and
> the SoC is up. That is a bit harder to see, but try adding #define
> DEBUG at the top of phylink.c and phy.c so you get additional debug
> prints for the state machines.

Sure, will give it a go tomorrow.

> 
>         Andrew
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <mail@conchuod.ie>
To: Andrew Lunn <andrew@lunn.ch>, Conor.Dooley@microchip.com
Cc: palmer@rivosinc.com, apatel@ventanamicro.com,
	netdev@vger.kernel.org, Nicolas.Ferre@microchip.com,
	Claudiu.Beznea@microchip.com, linux@armlinux.org.uk,
	hkallweit1@gmail.com, linux-riscv@lists.infradead.org
Subject: Re: riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1
Date: Tue, 5 Apr 2022 17:25:00 +0100	[thread overview]
Message-ID: <e445af29-4354-69c3-fa9a-c5b99d90a9a5@conchuod.ie> (raw)
In-Reply-To: <YkxaiEbHwduhS2+p@lunn.ch>

On 05/04/2022 16:04, Andrew Lunn wrote:
>> [ 2.818894] macb 20112000.ethernet eth0: PHY [20112000.ethernet-ffffffff:09] driver [Generic PHY] (irq=POLL)
>> [ 2.828915] macb 20112000.ethernet eth0: configuring for phy/sgmii link mode
>> [11.045411] macb 20112000.ethernet eth0: Link is Up - 1Gbps/Full - flow control off
>> [11.053247] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> 
> You have a multi-part link. You need that the PHY reports the line
> side is up. Put some printk in genphy_update_link() and look at
> phydev->link. You also need that the SGMII link between the PHY and
> the SoC is up. That is a bit harder to see, but try adding #define
> DEBUG at the top of phylink.c and phy.c so you get additional debug
> prints for the state machines.

Sure, will give it a go tomorrow.

> 
>         Andrew
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2022-04-05 16:25 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-05 13:05 riscv defconfig CONFIG_PM/macb/generic PHY regression in v5.18-rc1 Conor.Dooley
2022-04-05 13:05 ` Conor.Dooley
2022-04-05 13:25 ` Andrew Lunn
2022-04-05 13:25   ` Andrew Lunn
2022-04-05 14:18   ` Conor.Dooley
2022-04-05 14:18     ` Conor.Dooley
2022-04-05 14:41     ` Conor.Dooley
2022-04-05 14:41       ` Conor.Dooley
2022-04-05 14:49     ` Andrew Lunn
2022-04-05 14:49       ` Andrew Lunn
2022-04-05 14:56 ` Andrew Lunn
2022-04-05 14:56   ` Andrew Lunn
2022-04-05 15:04 ` Andrew Lunn
2022-04-05 15:04   ` Andrew Lunn
2022-04-05 16:25   ` Conor Dooley [this message]
2022-04-05 16:25     ` Conor Dooley
2022-04-06  8:36   ` Conor.Dooley
2022-04-06  8:36     ` Conor.Dooley
2022-04-07 14:30     ` Conor.Dooley
2022-04-07 14:30       ` Conor.Dooley
2022-04-05 15:53 ` Russell King (Oracle)
2022-04-05 15:53   ` Russell King (Oracle)
2022-04-05 16:56   ` Palmer Dabbelt
2022-04-05 16:56     ` Palmer Dabbelt
2022-04-05 17:23     ` Conor Dooley
2022-04-05 17:23       ` Conor Dooley
2022-04-05 18:06       ` Andrew Lunn
2022-04-05 18:06         ` Andrew Lunn
2022-04-05 18:35         ` Conor Dooley
2022-04-05 18:35           ` Conor Dooley
2022-04-05 16:58   ` Conor Dooley
2022-04-05 16:58     ` Conor Dooley
2022-04-05 18:55     ` Russell King (Oracle)
2022-04-05 18:55       ` Russell King (Oracle)

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