* [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
@ 2018-10-23 3:29 Rex Zhu
[not found] ` <1540265370-23923-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 10+ messages in thread
From: Rex Zhu @ 2018-10-23 3:29 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
jerry.zhang-5C7GfCeVMHo, alexander.deucher-5C7GfCeVMHo,
christian.koenig-5C7GfCeVMHo
Cc: Rex Zhu
when the VA address located in the last PD entries,
the alloc_pts will faile.
Use the right PD mask instand of hardcode, suggested
by jerry.zhang.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 054633b..3939013 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -202,8 +202,11 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
unsigned int level)
{
+ unsigned shift = amdgpu_vm_level_shift(adev,
+ adev->vm_manager.root_level);
+
if (level <= adev->vm_manager.root_level)
- return 0xffffffff;
+ return (round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift) - 1;
else if (level != AMDGPU_VM_PTB)
return 0x1ff;
else
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <1540265370-23923-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-23 5:12 ` Zhang, Jerry(Junwei)
[not found] ` <7b50f2a1-791e-8eab-6777-e7fff572565c-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 10+ messages in thread
From: Zhang, Jerry(Junwei) @ 2018-10-23 5:12 UTC (permalink / raw)
To: Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
alexander.deucher-5C7GfCeVMHo, christian.koenig-5C7GfCeVMHo
On 10/23/2018 11:29 AM, Rex Zhu wrote:
> when the VA address located in the last PD entries,
> the alloc_pts will faile.
>
> Use the right PD mask instand of hardcode, suggested
> by jerry.zhang.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Thanks to verify that.
Feel free to add
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Also like to get to know some background about these two functions from
Christian.
Perhaps we may make it more simple, e.g. merging them together.
Regards,
Jerry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 054633b..3939013 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -202,8 +202,11 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
> static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
> unsigned int level)
> {
> + unsigned shift = amdgpu_vm_level_shift(adev,
> + adev->vm_manager.root_level);
> +
> if (level <= adev->vm_manager.root_level)
> - return 0xffffffff;
> + return (round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift) - 1;
> else if (level != AMDGPU_VM_PTB)
> return 0x1ff;
> else
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <7b50f2a1-791e-8eab-6777-e7fff572565c-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-23 5:29 ` Zhang, Jerry(Junwei)
2018-10-23 5:42 ` Zhu, Rex
1 sibling, 0 replies; 10+ messages in thread
From: Zhang, Jerry(Junwei) @ 2018-10-23 5:29 UTC (permalink / raw)
To: Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
alexander.deucher-5C7GfCeVMHo, christian.koenig-5C7GfCeVMHo
On 10/23/2018 01:12 PM, Zhang, Jerry(Junwei) wrote:
> On 10/23/2018 11:29 AM, Rex Zhu wrote:
>> when the VA address located in the last PD entries,
>> the alloc_pts will faile.
>>
>> Use the right PD mask instand of hardcode, suggested
>> by jerry.zhang.
>>
>> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
>
> Thanks to verify that.
> Feel free to add
> Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
>
> Also like to get to know some background about these two functions
> from Christian.
> Perhaps we may make it more simple, e.g. merging them together.
If we really needs them all, we may simplify that like:
```
amdgpu_vm_entries_mask(struct amdgpu_device *adev, unsigned int level)
{
return amdgpu_vm_num_entries(adev, level) - 1;
}
```
Jerry
>
> Regards,
> Jerry
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 054633b..3939013 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -202,8 +202,11 @@ static unsigned amdgpu_vm_num_entries(struct
>> amdgpu_device *adev,
>> static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
>> unsigned int level)
>> {
>> + unsigned shift = amdgpu_vm_level_shift(adev,
>> + adev->vm_manager.root_level);
>> +
>> if (level <= adev->vm_manager.root_level)
>> - return 0xffffffff;
>> + return (round_up(adev->vm_manager.max_pfn, 1 << shift) >>
>> shift) - 1;
>> else if (level != AMDGPU_VM_PTB)
>> return 0x1ff;
>> else
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <7b50f2a1-791e-8eab-6777-e7fff572565c-5C7GfCeVMHo@public.gmane.org>
2018-10-23 5:29 ` Zhang, Jerry(Junwei)
@ 2018-10-23 5:42 ` Zhu, Rex
[not found] ` <BYAPR12MB2775C0F7BCA52B2969C9D16EFBF50-ZGDeBxoHBPmJeBUhB162ZQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
1 sibling, 1 reply; 10+ messages in thread
From: Zhu, Rex @ 2018-10-23 5:42 UTC (permalink / raw)
To: Zhang, Jerry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Deucher,
Alexander, Koenig, Christian
[-- Attachment #1.1: Type: text/plain, Size: 3085 bytes --]
No, if the vm size is small, there may only on root pd entry.
we need to make sure the mask >= 0;
Maybe this change revert Christian's commit:
commit 72af632549b97ead9251bb155f08fefd1fb6f5c3
Author: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
Date: Sat Sep 15 10:02:13 2018 +0200
drm/amdgpu: add amdgpu_vm_entries_mask v2
We can't get the mask for the root directory from the number of entries.
So add a new function to avoid that problem.
Best Regards
Rex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Zhang, Jerry(Junwei) <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
Sent: Tuesday, October 23, 2018 1:12 PM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Deucher, Alexander; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
On 10/23/2018 11:29 AM, Rex Zhu wrote:
> when the VA address located in the last PD entries,
> the alloc_pts will faile.
>
> Use the right PD mask instand of hardcode, suggested
> by jerry.zhang.
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Thanks to verify that.
Feel free to add
Reviewed-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
Also like to get to know some background about these two functions from
Christian.
Perhaps we may make it more simple, e.g. merging them together.
Regards,
Jerry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 054633b..3939013 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -202,8 +202,11 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
> static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
> unsigned int level)
> {
> + unsigned shift = amdgpu_vm_level_shift(adev,
> + adev->vm_manager.root_level);
> +
> if (level <= adev->vm_manager.root_level)
> - return 0xffffffff;
> + return (round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift) - 1;
> else if (level != AMDGPU_VM_PTB)
> return 0x1ff;
> else
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <BYAPR12MB2775C0F7BCA52B2969C9D16EFBF50-ZGDeBxoHBPmJeBUhB162ZQdYzm3356FpvxpqHgZTriW3zl9H0oFU5g@public.gmane.org>
@ 2018-10-23 9:01 ` Christian König
[not found] ` <62aee584-d4b1-dd9b-234e-8ca7d7a23a29-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
0 siblings, 1 reply; 10+ messages in thread
From: Christian König @ 2018-10-23 9:01 UTC (permalink / raw)
To: Zhu, Rex, Zhang, Jerry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
Deucher, Alexander, Koenig, Christian
[-- Attachment #1.1: Type: text/plain, Size: 3737 bytes --]
Hi guys,
yeah the root PD doesn't necessarily have a power of two entries.
But what exactly was the problem with the original code? Why does
0xffffffff doesn't work?
The only possible explanation I can see is that somebody tried to use an
address which is above max_pfn, or how did that trigger?
Thanks,
Christian.
Am 23.10.18 um 07:42 schrieb Zhu, Rex:
>
> No, if the vm size is small, there may only on root pd entry.
>
> we need to make sure the mask >= 0;
>
>
> Maybe this change revert Christian's commit:
>
>
> commit 72af632549b97ead9251bb155f08fefd1fb6f5c3
> Author: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org>
> Date: Sat Sep 15 10:02:13 2018 +0200
>
> drm/amdgpu: add amdgpu_vm_entries_mask v2
>
> We can't get the mask for the root directory from the number of
> entries.
>
> So add a new function to avoid that problem.
>
>
> Best Regards
>
> Rex
>
>
>
> ------------------------------------------------------------------------
> *From:* amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of
> Zhang, Jerry(Junwei) <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
> *Sent:* Tuesday, October 23, 2018 1:12 PM
> *To:* Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Deucher, Alexander;
> Koenig, Christian
> *Subject:* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
> On 10/23/2018 11:29 AM, Rex Zhu wrote:
> > when the VA address located in the last PD entries,
> > the alloc_pts will faile.
> >
> > Use the right PD mask instand of hardcode, suggested
> > by jerry.zhang.
> >
> > Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
>
> Thanks to verify that.
> Feel free to add
> Reviewed-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
>
> Also like to get to know some background about these two functions from
> Christian.
> Perhaps we may make it more simple, e.g. merging them together.
>
> Regards,
> Jerry
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > index 054633b..3939013 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> > @@ -202,8 +202,11 @@ static unsigned amdgpu_vm_num_entries(struct
> amdgpu_device *adev,
> > static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
> > unsigned int level)
> > {
> > + unsigned shift = amdgpu_vm_level_shift(adev,
> > + adev->vm_manager.root_level);
> > +
> > if (level <= adev->vm_manager.root_level)
> > - return 0xffffffff;
> > + return (round_up(adev->vm_manager.max_pfn, 1 << shift)
> >> shift) - 1;
> > else if (level != AMDGPU_VM_PTB)
> > return 0x1ff;
> > else
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> amd-gfx Info Page - freedesktop.org
> <https://lists.freedesktop.org/mailman/listinfo/amd-gfx>
> lists.freedesktop.org
> To see the collection of prior postings to the list, visit the amd-gfx
> Archives.. Using amd-gfx: To post a message to all the list members,
> send email to amd-gfx-PD4FTy7X32lNgt0PjOBp9xlNPtJONSTn@public.gmane.org You can subscribe to the
> list, or change your existing subscription, in the sections below.
>
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <62aee584-d4b1-dd9b-234e-8ca7d7a23a29-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
@ 2018-10-23 9:08 ` Zhu, Rex
0 siblings, 0 replies; 10+ messages in thread
From: Zhu, Rex @ 2018-10-23 9:08 UTC (permalink / raw)
To: Zhang, Jerry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Deucher,
Alexander, Koenig, Christian
[-- Attachment #1.1: Type: text/plain, Size: 4660 bytes --]
Hi Christian,
You can reproduce this issue by allocate CSA buffer in baremetal and map them to reserved VM address.
Please see the attached patch.
Best Regards
Rex
________________________________
From: Christian König <ckoenig.leichtzumerken-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sent: Tuesday, October 23, 2018 5:01 PM
To: Zhu, Rex; Zhang, Jerry; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Deucher, Alexander; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
Hi guys,
yeah the root PD doesn't necessarily have a power of two entries.
But what exactly was the problem with the original code? Why does 0xffffffff doesn't work?
The only possible explanation I can see is that somebody tried to use an address which is above max_pfn, or how did that trigger?
Thanks,
Christian.
Am 23.10.18 um 07:42 schrieb Zhu, Rex:
No, if the vm size is small, there may only on root pd entry.
we need to make sure the mask >= 0;
Maybe this change revert Christian's commit:
commit 72af632549b97ead9251bb155f08fefd1fb6f5c3
Author: Christian König <christian.koenig-5C7GfCeVMHo@public.gmane.org><mailto:christian.koenig@amd.com>
Date: Sat Sep 15 10:02:13 2018 +0200
drm/amdgpu: add amdgpu_vm_entries_mask v2
We can't get the mask for the root directory from the number of entries.
So add a new function to avoid that problem.
Best Regards
Rex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org><mailto:amd-gfx-bounces@lists.freedesktop.org> on behalf of Zhang, Jerry(Junwei) <Jerry.Zhang@amd.com><mailto:Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
Sent: Tuesday, October 23, 2018 1:12 PM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org<mailto:amd-gfx-PD4FTy7X32lNgt0PjOBp9w@public.gmane.orgp.org>; Deucher, Alexander; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
On 10/23/2018 11:29 AM, Rex Zhu wrote:
> when the VA address located in the last PD entries,
> the alloc_pts will faile.
>
> Use the right PD mask instand of hardcode, suggested
> by jerry.zhang.
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org><mailto:Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Thanks to verify that.
Feel free to add
Reviewed-by: Junwei Zhang <Jerry.Zhang-5C7GfCeVMHo@public.gmane.org><mailto:Jerry.Zhang-5C7GfCeVMHo@public.gmane.org>
Also like to get to know some background about these two functions from
Christian.
Perhaps we may make it more simple, e.g. merging them together.
Regards,
Jerry
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 054633b..3939013 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -202,8 +202,11 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
> static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
> unsigned int level)
> {
> + unsigned shift = amdgpu_vm_level_shift(adev,
> + adev->vm_manager.root_level);
> +
> if (level <= adev->vm_manager.root_level)
> - return 0xffffffff;
> + return (round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift) - 1;
> else if (level != AMDGPU_VM_PTB)
> return 0x1ff;
> else
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From a68c029e2bc5f60fd26d1b0705fee2be80b6f604 Mon Sep 17 00:00:00 2001
From: Rex Zhu <Rex.Zhu@amd.com>
Date: Tue, 23 Oct 2018 17:07:12 +0800
Subject: [PATCH] debug: create and map csa buffer
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 450b0b7..e0d46b9 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1658,7 +1658,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
adev->ip_blocks[i].status.hw = true;
/* right after GMC hw init, we create CSA */
- if (amdgpu_sriov_vf(adev)) {
+// if (amdgpu_sriov_vf(adev)) {
r = amdgpu_allocate_static_csa(adev, &adev->virt.csa_obj,
AMDGPU_GEM_DOMAIN_VRAM,
AMDGPU_CSA_SIZE);
@@ -1666,7 +1666,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
DRM_ERROR("allocate CSA failed %d\n", r);
return r;
}
- }
+// }
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index f2ef9a1..b332262 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -977,13 +977,13 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
goto error_vm;
}
- if (amdgpu_sriov_vf(adev)) {
+// if (amdgpu_sriov_vf(adev)) {
uint64_t csa_addr = amdgpu_csa_vaddr(adev, 1) & AMDGPU_GMC_HOLE_MASK;
r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
&fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
if (r)
goto error_vm;
- }
+// }
mutex_init(&fpriv->bo_list_lock);
idr_init(&fpriv->bo_list_handles);
@@ -1043,13 +1043,13 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev,
amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
- if (amdgpu_sriov_vf(adev)) {
+// if (amdgpu_sriov_vf(adev)) {
/* TODO: how to handle reserve failure */
BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
fpriv->csa_va = NULL;
amdgpu_bo_unreserve(adev->virt.csa_obj);
- }
+// }
pasid = fpriv->vm.pasid;
pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
--
1.9.1
[-- Attachment #3: Type: text/plain, Size: 154 bytes --]
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <7eb4b4ef-c72a-9a58-2c99-0bfbe6109f69-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-23 3:31 ` Zhu, Rex
0 siblings, 0 replies; 10+ messages in thread
From: Zhu, Rex @ 2018-10-23 3:31 UTC (permalink / raw)
To: Zhang, Jerry, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Koenig,
Christian
[-- Attachment #1.1: Type: text/plain, Size: 4229 bytes --]
Thanks Jerry.
Good suggestion.
Use the right mask for PD instand of hardcode.
so don't need to revert the whole patch.
Best Regards
Rex
________________________________
From: Zhang, Jerry
Sent: Tuesday, October 23, 2018 10:02 AM
To: Zhu, Rex; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Koenig, Christian
Subject: Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
On 10/23/2018 12:09 AM, Rex Zhu wrote:
> When the va address located in the last pd entry,
Do you mean the root PD?
maybe we need roundup root PD in amdgpu_vm_entries_mask() like
amdgpu_vm_num_entries().
BTW, looks amdgpu_vm_entries_mask() is going to replace the
amdgpu_vm_num_entries()
Jerry
> the alloc_pts will failed.
> caused by
> "drm/amdgpu: add amdgpu_vm_entries_mask v2"
> commit 72af632549b97ead9251bb155f08fefd1fb6f5c3.
>
> Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++++++---------------------------
> 1 file changed, 7 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 054633b..1a3af72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -191,26 +191,6 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
> }
>
> /**
> - * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
> - *
> - * @adev: amdgpu_device pointer
> - * @level: VMPT level
> - *
> - * Returns:
> - * The mask to extract the entry number of a PD/PT from an address.
> - */
> -static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
> - unsigned int level)
> -{
> - if (level <= adev->vm_manager.root_level)
> - return 0xffffffff;
> - else if (level != AMDGPU_VM_PTB)
> - return 0x1ff;
> - else
> - return AMDGPU_VM_PTE_COUNT(adev) - 1;
> -}
> -
> -/**
> * amdgpu_vm_bo_size - returns the size of the BOs in bytes
> *
> * @adev: amdgpu_device pointer
> @@ -419,17 +399,17 @@ static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
> static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
> struct amdgpu_vm_pt_cursor *cursor)
> {
> - unsigned mask, shift, idx;
> + unsigned num_entries, shift, idx;
>
> if (!cursor->entry->entries)
> return false;
>
> BUG_ON(!cursor->entry->base.bo);
> - mask = amdgpu_vm_entries_mask(adev, cursor->level);
> + num_entries = amdgpu_vm_num_entries(adev, cursor->level);
> shift = amdgpu_vm_level_shift(adev, cursor->level);
>
> ++cursor->level;
> - idx = (cursor->pfn >> shift) & mask;
> + idx = (cursor->pfn >> shift) % num_entries;
> cursor->parent = cursor->entry;
> cursor->entry = &cursor->entry->entries[idx];
> return true;
> @@ -1618,7 +1598,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
> amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
> while (cursor.pfn < end) {
> struct amdgpu_bo *pt = cursor.entry->base.bo;
> - unsigned shift, parent_shift, mask;
> + unsigned shift, parent_shift, num_entries;
> uint64_t incr, entry_end, pe_start;
>
> if (!pt)
> @@ -1673,9 +1653,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
>
> /* Looks good so far, calculate parameters for the update */
> incr = AMDGPU_GPU_PAGE_SIZE << shift;
> - mask = amdgpu_vm_entries_mask(adev, cursor.level);
> - pe_start = ((cursor.pfn >> shift) & mask) * 8;
> - entry_end = (mask + 1) << shift;
> + num_entries = amdgpu_vm_num_entries(adev, cursor.level);
> + pe_start = ((cursor.pfn >> shift) & (num_entries - 1)) * 8;
> + entry_end = num_entries << shift;
> entry_end += cursor.pfn & ~(entry_end - 1);
> entry_end = min(entry_end, end);
>
[-- Attachment #1.2: Type: text/html, Size: 8470 bytes --]
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <1540224561-4728-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-10-22 17:42 ` Deucher, Alexander
@ 2018-10-23 2:02 ` Zhang, Jerry(Junwei)
[not found] ` <7eb4b4ef-c72a-9a58-2c99-0bfbe6109f69-5C7GfCeVMHo@public.gmane.org>
1 sibling, 1 reply; 10+ messages in thread
From: Zhang, Jerry(Junwei) @ 2018-10-23 2:02 UTC (permalink / raw)
To: Rex Zhu, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
christian.koenig-5C7GfCeVMHo
On 10/23/2018 12:09 AM, Rex Zhu wrote:
> When the va address located in the last pd entry,
Do you mean the root PD?
maybe we need roundup root PD in amdgpu_vm_entries_mask() like
amdgpu_vm_num_entries().
BTW, looks amdgpu_vm_entries_mask() is going to replace the
amdgpu_vm_num_entries()
Jerry
> the alloc_pts will failed.
> caused by
> "drm/amdgpu: add amdgpu_vm_entries_mask v2"
> commit 72af632549b97ead9251bb155f08fefd1fb6f5c3.
>
> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++++++---------------------------
> 1 file changed, 7 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 054633b..1a3af72 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -191,26 +191,6 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
> }
>
> /**
> - * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
> - *
> - * @adev: amdgpu_device pointer
> - * @level: VMPT level
> - *
> - * Returns:
> - * The mask to extract the entry number of a PD/PT from an address.
> - */
> -static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
> - unsigned int level)
> -{
> - if (level <= adev->vm_manager.root_level)
> - return 0xffffffff;
> - else if (level != AMDGPU_VM_PTB)
> - return 0x1ff;
> - else
> - return AMDGPU_VM_PTE_COUNT(adev) - 1;
> -}
> -
> -/**
> * amdgpu_vm_bo_size - returns the size of the BOs in bytes
> *
> * @adev: amdgpu_device pointer
> @@ -419,17 +399,17 @@ static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
> static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
> struct amdgpu_vm_pt_cursor *cursor)
> {
> - unsigned mask, shift, idx;
> + unsigned num_entries, shift, idx;
>
> if (!cursor->entry->entries)
> return false;
>
> BUG_ON(!cursor->entry->base.bo);
> - mask = amdgpu_vm_entries_mask(adev, cursor->level);
> + num_entries = amdgpu_vm_num_entries(adev, cursor->level);
> shift = amdgpu_vm_level_shift(adev, cursor->level);
>
> ++cursor->level;
> - idx = (cursor->pfn >> shift) & mask;
> + idx = (cursor->pfn >> shift) % num_entries;
> cursor->parent = cursor->entry;
> cursor->entry = &cursor->entry->entries[idx];
> return true;
> @@ -1618,7 +1598,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
> amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
> while (cursor.pfn < end) {
> struct amdgpu_bo *pt = cursor.entry->base.bo;
> - unsigned shift, parent_shift, mask;
> + unsigned shift, parent_shift, num_entries;
> uint64_t incr, entry_end, pe_start;
>
> if (!pt)
> @@ -1673,9 +1653,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
>
> /* Looks good so far, calculate parameters for the update */
> incr = AMDGPU_GPU_PAGE_SIZE << shift;
> - mask = amdgpu_vm_entries_mask(adev, cursor.level);
> - pe_start = ((cursor.pfn >> shift) & mask) * 8;
> - entry_end = (mask + 1) << shift;
> + num_entries = amdgpu_vm_num_entries(adev, cursor.level);
> + pe_start = ((cursor.pfn >> shift) & (num_entries - 1)) * 8;
> + entry_end = num_entries << shift;
> entry_end += cursor.pfn & ~(entry_end - 1);
> entry_end = min(entry_end, end);
>
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
[not found] ` <1540224561-4728-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
@ 2018-10-22 17:42 ` Deucher, Alexander
2018-10-23 2:02 ` Zhang, Jerry(Junwei)
1 sibling, 0 replies; 10+ messages in thread
From: Deucher, Alexander @ 2018-10-22 17:42 UTC (permalink / raw)
To: Zhu, Rex, amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Koenig, Christian
[-- Attachment #1.1: Type: text/plain, Size: 4143 bytes --]
This re-introduces a 64 division that is not handled correctly with the % operator.
Alex
________________________________
From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
Sent: Monday, October 22, 2018 12:09:21 PM
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org; Koenig, Christian
Cc: Zhu, Rex
Subject: [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
When the va address located in the last pd entry,
the alloc_pts will failed.
caused by
"drm/amdgpu: add amdgpu_vm_entries_mask v2"
commit 72af632549b97ead9251bb155f08fefd1fb6f5c3.
Signed-off-by: Rex Zhu <Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++++++---------------------------
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 054633b..1a3af72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -191,26 +191,6 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
}
/**
- * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
- *
- * @adev: amdgpu_device pointer
- * @level: VMPT level
- *
- * Returns:
- * The mask to extract the entry number of a PD/PT from an address.
- */
-static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
- unsigned int level)
-{
- if (level <= adev->vm_manager.root_level)
- return 0xffffffff;
- else if (level != AMDGPU_VM_PTB)
- return 0x1ff;
- else
- return AMDGPU_VM_PTE_COUNT(adev) - 1;
-}
-
-/**
* amdgpu_vm_bo_size - returns the size of the BOs in bytes
*
* @adev: amdgpu_device pointer
@@ -419,17 +399,17 @@ static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
struct amdgpu_vm_pt_cursor *cursor)
{
- unsigned mask, shift, idx;
+ unsigned num_entries, shift, idx;
if (!cursor->entry->entries)
return false;
BUG_ON(!cursor->entry->base.bo);
- mask = amdgpu_vm_entries_mask(adev, cursor->level);
+ num_entries = amdgpu_vm_num_entries(adev, cursor->level);
shift = amdgpu_vm_level_shift(adev, cursor->level);
++cursor->level;
- idx = (cursor->pfn >> shift) & mask;
+ idx = (cursor->pfn >> shift) % num_entries;
cursor->parent = cursor->entry;
cursor->entry = &cursor->entry->entries[idx];
return true;
@@ -1618,7 +1598,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
while (cursor.pfn < end) {
struct amdgpu_bo *pt = cursor.entry->base.bo;
- unsigned shift, parent_shift, mask;
+ unsigned shift, parent_shift, num_entries;
uint64_t incr, entry_end, pe_start;
if (!pt)
@@ -1673,9 +1653,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
/* Looks good so far, calculate parameters for the update */
incr = AMDGPU_GPU_PAGE_SIZE << shift;
- mask = amdgpu_vm_entries_mask(adev, cursor.level);
- pe_start = ((cursor.pfn >> shift) & mask) * 8;
- entry_end = (mask + 1) << shift;
+ num_entries = amdgpu_vm_num_entries(adev, cursor.level);
+ pe_start = ((cursor.pfn >> shift) & (num_entries - 1)) * 8;
+ entry_end = num_entries << shift;
entry_end += cursor.pfn & ~(entry_end - 1);
entry_end = min(entry_end, end);
--
1.9.1
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[-- Attachment #1.2: Type: text/html, Size: 8171 bytes --]
[-- Attachment #2: Type: text/plain, Size: 154 bytes --]
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed
@ 2018-10-22 16:09 Rex Zhu
[not found] ` <1540224561-4728-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 10+ messages in thread
From: Rex Zhu @ 2018-10-22 16:09 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, christian.koenig-5C7GfCeVMHo
Cc: Rex Zhu
When the va address located in the last pd entry,
the alloc_pts will failed.
caused by
"drm/amdgpu: add amdgpu_vm_entries_mask v2"
commit 72af632549b97ead9251bb155f08fefd1fb6f5c3.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 34 +++++++---------------------------
1 file changed, 7 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 054633b..1a3af72 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -191,26 +191,6 @@ static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
}
/**
- * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
- *
- * @adev: amdgpu_device pointer
- * @level: VMPT level
- *
- * Returns:
- * The mask to extract the entry number of a PD/PT from an address.
- */
-static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
- unsigned int level)
-{
- if (level <= adev->vm_manager.root_level)
- return 0xffffffff;
- else if (level != AMDGPU_VM_PTB)
- return 0x1ff;
- else
- return AMDGPU_VM_PTE_COUNT(adev) - 1;
-}
-
-/**
* amdgpu_vm_bo_size - returns the size of the BOs in bytes
*
* @adev: amdgpu_device pointer
@@ -419,17 +399,17 @@ static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
struct amdgpu_vm_pt_cursor *cursor)
{
- unsigned mask, shift, idx;
+ unsigned num_entries, shift, idx;
if (!cursor->entry->entries)
return false;
BUG_ON(!cursor->entry->base.bo);
- mask = amdgpu_vm_entries_mask(adev, cursor->level);
+ num_entries = amdgpu_vm_num_entries(adev, cursor->level);
shift = amdgpu_vm_level_shift(adev, cursor->level);
++cursor->level;
- idx = (cursor->pfn >> shift) & mask;
+ idx = (cursor->pfn >> shift) % num_entries;
cursor->parent = cursor->entry;
cursor->entry = &cursor->entry->entries[idx];
return true;
@@ -1618,7 +1598,7 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
while (cursor.pfn < end) {
struct amdgpu_bo *pt = cursor.entry->base.bo;
- unsigned shift, parent_shift, mask;
+ unsigned shift, parent_shift, num_entries;
uint64_t incr, entry_end, pe_start;
if (!pt)
@@ -1673,9 +1653,9 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
/* Looks good so far, calculate parameters for the update */
incr = AMDGPU_GPU_PAGE_SIZE << shift;
- mask = amdgpu_vm_entries_mask(adev, cursor.level);
- pe_start = ((cursor.pfn >> shift) & mask) * 8;
- entry_end = (mask + 1) << shift;
+ num_entries = amdgpu_vm_num_entries(adev, cursor.level);
+ pe_start = ((cursor.pfn >> shift) & (num_entries - 1)) * 8;
+ entry_end = num_entries << shift;
entry_end += cursor.pfn & ~(entry_end - 1);
entry_end = min(entry_end, end);
--
1.9.1
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^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-10-23 9:08 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2018-10-23 3:29 [PATCH] drm/amdgpu: Fix amdgpu_vm_alloc_pts failed Rex Zhu
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2018-10-23 5:12 ` Zhang, Jerry(Junwei)
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2018-10-23 5:29 ` Zhang, Jerry(Junwei)
2018-10-23 5:42 ` Zhu, Rex
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2018-10-23 9:01 ` Christian König
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2018-10-23 9:08 ` Zhu, Rex
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2018-10-22 16:09 Rex Zhu
[not found] ` <1540224561-4728-1-git-send-email-Rex.Zhu-5C7GfCeVMHo@public.gmane.org>
2018-10-22 17:42 ` Deucher, Alexander
2018-10-23 2:02 ` Zhang, Jerry(Junwei)
[not found] ` <7eb4b4ef-c72a-9a58-2c99-0bfbe6109f69-5C7GfCeVMHo@public.gmane.org>
2018-10-23 3:31 ` Zhu, Rex
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