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From: Mauro Carvalho Chehab <mchehab@kernel.org>
To: unlisted-recipients:; (no To-header on input)
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>,
	Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org,
	Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Subject: [PATCH 15/21] drm/i915: Add platform macro for selective tlb flush
Date: Wed, 13 Jul 2022 10:30:12 +0100	[thread overview]
Message-ID: <62c27558f7add68cc60fcf765e591f8886a195f9.1657703926.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657703926.git.mchehab@kernel.org>

From: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

Add support for selective TLB invalidation, which is a platform
feature supported on XeHP.

Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/i915_drv.h          | 3 +++
 drivers/gpu/drm/i915/i915_pci.c          | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1f70257dbe0..73494960a3a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1312,6 +1312,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
 
+#define HAS_SELECTIVE_TLB_INVALIDATION(dev_priv) \
+	(INTEL_INFO(dev_priv)->has_selective_tlb_invalidation)
+
 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
 
 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index aacc10f2e73f..30d945fe384b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1022,6 +1022,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
+	.has_selective_tlb_invalidation = 1, \
 	.ppgtt_size = 48, \
 	.ppgtt_type = INTEL_PPGTT_FULL
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 23bf230aa104..92a38b8f7c47 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -170,6 +170,7 @@ enum intel_ppgtt_type {
 	func(has_rc6p); \
 	func(has_rps); \
 	func(has_runtime_pm); \
+	func(has_selective_tlb_invalidation); \
 	func(has_snoop); \
 	func(has_coherent_ggtt); \
 	func(unfenced_needs_alignment); \
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	David Airlie <airlied@linux.ie>,
	intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Subject: [PATCH 15/21] drm/i915: Add platform macro for selective tlb flush
Date: Wed, 13 Jul 2022 10:30:12 +0100	[thread overview]
Message-ID: <62c27558f7add68cc60fcf765e591f8886a195f9.1657703926.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657703926.git.mchehab@kernel.org>

From: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

Add support for selective TLB invalidation, which is a platform
feature supported on XeHP.

Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/i915_drv.h          | 3 +++
 drivers/gpu/drm/i915/i915_pci.c          | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1f70257dbe0..73494960a3a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1312,6 +1312,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
 
+#define HAS_SELECTIVE_TLB_INVALIDATION(dev_priv) \
+	(INTEL_INFO(dev_priv)->has_selective_tlb_invalidation)
+
 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
 
 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index aacc10f2e73f..30d945fe384b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1022,6 +1022,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
+	.has_selective_tlb_invalidation = 1, \
 	.ppgtt_size = 48, \
 	.ppgtt_type = INTEL_PPGTT_FULL
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 23bf230aa104..92a38b8f7c47 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -170,6 +170,7 @@ enum intel_ppgtt_type {
 	func(has_rc6p); \
 	func(has_rps); \
 	func(has_runtime_pm); \
+	func(has_selective_tlb_invalidation); \
 	func(has_snoop); \
 	func(has_coherent_ggtt); \
 	func(unfenced_needs_alignment); \
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: David Airlie <airlied@linux.ie>,
	intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>
Subject: [Intel-gfx] [PATCH 15/21] drm/i915: Add platform macro for selective tlb flush
Date: Wed, 13 Jul 2022 10:30:12 +0100	[thread overview]
Message-ID: <62c27558f7add68cc60fcf765e591f8886a195f9.1657703926.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657703926.git.mchehab@kernel.org>

From: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

Add support for selective TLB invalidation, which is a platform
feature supported on XeHP.

Signed-off-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/i915_drv.h          | 3 +++
 drivers/gpu/drm/i915/i915_pci.c          | 1 +
 drivers/gpu/drm/i915/intel_device_info.h | 1 +
 3 files changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f1f70257dbe0..73494960a3a8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1312,6 +1312,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 
 #define HAS_GT_UC(dev_priv)	(INTEL_INFO(dev_priv)->has_gt_uc)
 
+#define HAS_SELECTIVE_TLB_INVALIDATION(dev_priv) \
+	(INTEL_INFO(dev_priv)->has_selective_tlb_invalidation)
+
 #define HAS_POOLED_EU(dev_priv)	(INTEL_INFO(dev_priv)->has_pooled_eu)
 
 #define HAS_GLOBAL_MOCS_REGISTERS(dev_priv)	(INTEL_INFO(dev_priv)->has_global_mocs)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index aacc10f2e73f..30d945fe384b 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -1022,6 +1022,7 @@ static const struct intel_device_info adl_p_info = {
 	.has_reset_engine = 1, \
 	.has_rps = 1, \
 	.has_runtime_pm = 1, \
+	.has_selective_tlb_invalidation = 1, \
 	.ppgtt_size = 48, \
 	.ppgtt_type = INTEL_PPGTT_FULL
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 23bf230aa104..92a38b8f7c47 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -170,6 +170,7 @@ enum intel_ppgtt_type {
 	func(has_rc6p); \
 	func(has_rps); \
 	func(has_runtime_pm); \
+	func(has_selective_tlb_invalidation); \
 	func(has_snoop); \
 	func(has_coherent_ggtt); \
 	func(unfenced_needs_alignment); \
-- 
2.36.1


  parent reply	other threads:[~2022-07-13  9:30 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-13  9:29 [PATCH 00/21] Fix performance regressions with TLB and add GuC support Mauro Carvalho Chehab
2022-07-13  9:29 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:29 ` Mauro Carvalho Chehab
2022-07-13  9:29 ` [PATCH 01/21] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-07-13  9:29   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:29   ` Mauro Carvalho Chehab
2022-07-13  9:29 ` [PATCH 02/21] drm/i915/gt: document with_intel_gt_pm_if_awake() Mauro Carvalho Chehab
2022-07-13  9:29   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:29   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 03/21] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 05/21] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 06/21] drm/i915/gt: Batch TLB invalidations Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 07/21] drm/i915/gt: describe the new tlb parameter at i915_vma_resource Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 08/21] drm/i915/gt: Move TLB invalidation to its own file Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 09/21] drm/i915/guc: Define CTB based TLB invalidation routines Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 10/21] drm/i915/guc: use kernel-doc for enum intel_guc_tlb_inval_mode Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 11/21] drm/i915/guc: document the TLB invalidation struct members Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 12/21] drm/i915/guc: Introduce TLB_INVALIDATION_ALL action Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 13/21] drm/i915: Invalidate the TLBs on each GT Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 14/21] drm/i915: document tlb field at struct drm_i915_gem_object Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` Mauro Carvalho Chehab [this message]
2022-07-13  9:30   ` [Intel-gfx] [PATCH 15/21] drm/i915: Add platform macro for selective tlb flush Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 16/21] drm/i915: Define GuC Based TLB invalidation routines Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 17/21] drm/i915: Add generic interface for tlb invalidation for XeHP Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 18/21] drm/i915: Use selective tlb invalidations where supported Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 19/21] drm/i915/gt: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 20/21] drm/i915/guc: describe enum intel_guc_tlb_invalidation_type Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 21/21] drm/i915/guc: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support Patchwork
2022-07-13 13:13 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support (rev2) Patchwork

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