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From: Mauro Carvalho Chehab <mchehab@kernel.org>
To: unlisted-recipients:; (no To-header on input)
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>,
	Alan Previn <alan.previn.teres.alexis@intel.com>,
	Daniel Vetter <daniel@ffwll.ch>,
	Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	David Airlie <airlied@linux.ie>,
	Jani Nikula <jani.nikula@linux.intel.com>,
	John Harrison <John.C.Harrison@Intel.com>,
	Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	Matthew Brost <matthew.brost@intel.com>,
	Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org
Subject: [PATCH 11/21] drm/i915/guc: document the TLB invalidation struct members
Date: Wed, 13 Jul 2022 10:30:08 +0100	[thread overview]
Message-ID: <b2475a1e10f643124c2bd60747051eb319fa15b4.1657703926.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657703926.git.mchehab@kernel.org>

Add documentation for the 3 new members of struct intel_guc
that are used to handle TLB cache invalidation logic.

Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/uc/intel_guc.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f82a121b0838..73c46d405dc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -76,11 +76,23 @@ struct intel_guc {
 	 */
 	atomic_t outstanding_submission_g2h;
 
-	/** @interrupts: pointers to GuC interrupt-managing functions. */
+	/**
+	 * @tlb_lookup: TLB cache invalidation lookup table.
+	 */
 	struct xarray tlb_lookup;
+
+	/**
+	 * @serial_slot: index to the latest allocated element at the
+	 * @tlb_lookup xarray.
+	 */
 	u32 serial_slot;
+
+	/**
+	 * @next_seqno: next index to be allocated at the @tlb_lookup xarray.
+	 */
 	u32 next_seqno;
 
+	/** @interrupts: pointers to GuC interrupt-managing functions. */
 	struct {
 		void (*reset)(struct intel_guc *guc);
 		void (*enable)(struct intel_guc *guc);
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Matthew Brost <matthew.brost@intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
	Alan Previn <alan.previn.teres.alexis@intel.com>,
	David Airlie <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	linux-kernel@vger.kernel.org,
	Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>,
	intel-gfx@lists.freedesktop.org,
	John Harrison <John.C.Harrison@Intel.com>
Subject: [PATCH 11/21] drm/i915/guc: document the TLB invalidation struct members
Date: Wed, 13 Jul 2022 10:30:08 +0100	[thread overview]
Message-ID: <b2475a1e10f643124c2bd60747051eb319fa15b4.1657703926.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657703926.git.mchehab@kernel.org>

Add documentation for the 3 new members of struct intel_guc
that are used to handle TLB cache invalidation logic.

Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/uc/intel_guc.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f82a121b0838..73c46d405dc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -76,11 +76,23 @@ struct intel_guc {
 	 */
 	atomic_t outstanding_submission_g2h;
 
-	/** @interrupts: pointers to GuC interrupt-managing functions. */
+	/**
+	 * @tlb_lookup: TLB cache invalidation lookup table.
+	 */
 	struct xarray tlb_lookup;
+
+	/**
+	 * @serial_slot: index to the latest allocated element at the
+	 * @tlb_lookup xarray.
+	 */
 	u32 serial_slot;
+
+	/**
+	 * @next_seqno: next index to be allocated at the @tlb_lookup xarray.
+	 */
 	u32 next_seqno;
 
+	/** @interrupts: pointers to GuC interrupt-managing functions. */
 	struct {
 		void (*reset)(struct intel_guc *guc);
 		void (*enable)(struct intel_guc *guc);
-- 
2.36.1


WARNING: multiple messages have this Message-ID (diff)
From: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>,
	David Airlie <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org,
	Lucas De Marchi <lucas.demarchi@intel.com>,
	linux-kernel@vger.kernel.org,
	Rodrigo Vivi <rodrigo.vivi@intel.com>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 11/21] drm/i915/guc: document the TLB invalidation struct members
Date: Wed, 13 Jul 2022 10:30:08 +0100	[thread overview]
Message-ID: <b2475a1e10f643124c2bd60747051eb319fa15b4.1657703926.git.mchehab@kernel.org> (raw)
In-Reply-To: <cover.1657703926.git.mchehab@kernel.org>

Add documentation for the 3 new members of struct intel_guc
that are used to handle TLB cache invalidation logic.

Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
---

See [PATCH 00/21] at: https://lore.kernel.org/all/cover.1657703926.git.mchehab@kernel.org/

 drivers/gpu/drm/i915/gt/uc/intel_guc.h | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index f82a121b0838..73c46d405dc4 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -76,11 +76,23 @@ struct intel_guc {
 	 */
 	atomic_t outstanding_submission_g2h;
 
-	/** @interrupts: pointers to GuC interrupt-managing functions. */
+	/**
+	 * @tlb_lookup: TLB cache invalidation lookup table.
+	 */
 	struct xarray tlb_lookup;
+
+	/**
+	 * @serial_slot: index to the latest allocated element at the
+	 * @tlb_lookup xarray.
+	 */
 	u32 serial_slot;
+
+	/**
+	 * @next_seqno: next index to be allocated at the @tlb_lookup xarray.
+	 */
 	u32 next_seqno;
 
+	/** @interrupts: pointers to GuC interrupt-managing functions. */
 	struct {
 		void (*reset)(struct intel_guc *guc);
 		void (*enable)(struct intel_guc *guc);
-- 
2.36.1


  parent reply	other threads:[~2022-07-13  9:30 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-13  9:29 [PATCH 00/21] Fix performance regressions with TLB and add GuC support Mauro Carvalho Chehab
2022-07-13  9:29 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:29 ` Mauro Carvalho Chehab
2022-07-13  9:29 ` [PATCH 01/21] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-07-13  9:29   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:29   ` Mauro Carvalho Chehab
2022-07-13  9:29 ` [PATCH 02/21] drm/i915/gt: document with_intel_gt_pm_if_awake() Mauro Carvalho Chehab
2022-07-13  9:29   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:29   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 03/21] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 04/21] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 05/21] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 06/21] drm/i915/gt: Batch TLB invalidations Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 07/21] drm/i915/gt: describe the new tlb parameter at i915_vma_resource Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 08/21] drm/i915/gt: Move TLB invalidation to its own file Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 09/21] drm/i915/guc: Define CTB based TLB invalidation routines Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 10/21] drm/i915/guc: use kernel-doc for enum intel_guc_tlb_inval_mode Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` Mauro Carvalho Chehab [this message]
2022-07-13  9:30   ` [Intel-gfx] [PATCH 11/21] drm/i915/guc: document the TLB invalidation struct members Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 12/21] drm/i915/guc: Introduce TLB_INVALIDATION_ALL action Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 13/21] drm/i915: Invalidate the TLBs on each GT Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 14/21] drm/i915: document tlb field at struct drm_i915_gem_object Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 15/21] drm/i915: Add platform macro for selective tlb flush Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 16/21] drm/i915: Define GuC Based TLB invalidation routines Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 17/21] drm/i915: Add generic interface for tlb invalidation for XeHP Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 18/21] drm/i915: Use selective tlb invalidations where supported Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 19/21] drm/i915/gt: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 20/21] drm/i915/guc: describe enum intel_guc_tlb_invalidation_type Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:30 ` [PATCH 21/21] drm/i915/guc: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-07-13  9:30   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-13  9:30   ` Mauro Carvalho Chehab
2022-07-13  9:48 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support Patchwork
2022-07-13 13:13 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Fix performance regressions with TLB and add GuC support (rev2) Patchwork

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