* [PATCH v7 01/12] drm/i915/perf: ensure we keep a reference on the driver
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
@ 2019-07-09 9:31 ` Lionel Landwerlin
2019-07-09 9:35 ` Chris Wilson
2019-07-09 9:31 ` [PATCH v7 02/12] drm/i915/perf: add missing delay for OA muxes configuration Lionel Landwerlin
` (10 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:31 UTC (permalink / raw)
To: intel-gfx
The i915 perf stream has its own file descriptor and is tied to
reference of the driver. We haven't taken care of keep the driver
alive.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Fixes: eec688e1420da5 ("drm/i915: Add i915 perf infrastructure")
---
drivers/gpu/drm/i915/i915_perf.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 357e63beb373..27842e7bcfed 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -2517,6 +2517,9 @@ static int i915_perf_release(struct inode *inode, struct file *file)
i915_perf_destroy_locked(stream);
mutex_unlock(&dev_priv->perf.lock);
+ /* Release the reference the perf stream kept on the driver. */
+ drm_dev_put(&dev_priv->drm);
+
return 0;
}
@@ -2652,6 +2655,11 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
if (!(param->flags & I915_PERF_FLAG_DISABLED))
i915_perf_enable_locked(stream);
+ /* Take a reference on the driver that will be kept with stream_fd
+ * until its release.
+ */
+ drm_dev_get(&dev_priv->drm);
+
return stream_fd;
err_open:
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 02/12] drm/i915/perf: add missing delay for OA muxes configuration
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
2019-07-09 9:31 ` [PATCH v7 01/12] drm/i915/perf: ensure we keep a reference on the driver Lionel Landwerlin
@ 2019-07-09 9:31 ` Lionel Landwerlin
2019-07-09 9:36 ` Chris Wilson
2019-07-09 9:31 ` [PATCH v7 03/12] drm/i915/perf: introduce a versioning of the i915-perf uapi Lionel Landwerlin
` (9 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:31 UTC (permalink / raw)
To: intel-gfx
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 19f81df2859eb1 ("drm/i915/perf: Add OA unit support for Gen 8+")
---
drivers/gpu/drm/i915/i915_perf.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 27842e7bcfed..545d3adaf341 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1838,6 +1838,29 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream)
config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
+ /* It apparently takes a fairly long time for a new MUX
+ * configuration to be be applied after these register writes.
+ * This delay duration was derived empirically based on the
+ * render_basic config but hopefully it covers the maximum
+ * configuration latency.
+ *
+ * As a fallback, the checks in _append_oa_reports() to skip
+ * invalid OA reports do also seem to work to discard reports
+ * generated before this config has completed - albeit not
+ * silently.
+ *
+ * Unfortunately this is essentially a magic number, since we
+ * don't currently know of a reliable mechanism for predicting
+ * how long the MUX config will take to apply and besides
+ * seeing invalid reports we don't know of a reliable way to
+ * explicitly check that the MUX config has landed.
+ *
+ * It's even possible we've miss characterized the underlying
+ * problem - it just seems like the simplest explanation why
+ * a delay at this location would mitigate any invalid reports.
+ */
+ usleep_range(15000, 20000);
+
config_oa_regs(dev_priv, oa_config->b_counter_regs,
oa_config->b_counter_regs_len);
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 03/12] drm/i915/perf: introduce a versioning of the i915-perf uapi
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
2019-07-09 9:31 ` [PATCH v7 01/12] drm/i915/perf: ensure we keep a reference on the driver Lionel Landwerlin
2019-07-09 9:31 ` [PATCH v7 02/12] drm/i915/perf: add missing delay for OA muxes configuration Lionel Landwerlin
@ 2019-07-09 9:31 ` Lionel Landwerlin
2019-07-09 9:37 ` Chris Wilson
2019-07-09 9:32 ` [PATCH v7 04/12] drm/i915/perf: allow for CS OA configs to be created lazily Lionel Landwerlin
` (8 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:31 UTC (permalink / raw)
To: intel-gfx
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 +++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_perf.c | 10 ++++++++++
include/uapi/drm/i915_drm.h | 21 +++++++++++++++++++++
4 files changed, 35 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 794c6814a6d0..f70ad7adaea5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -483,6 +483,9 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_MMAP_GTT_COHERENT:
value = INTEL_INFO(dev_priv)->has_coherent_ggtt;
break;
+ case I915_PARAM_PERF_REVISION:
+ value = i915_perf_ioctl_version();
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f9878cbef4d9..e4b010085f2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2673,6 +2673,7 @@ extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
+int i915_perf_ioctl_version(void);
/* i915_suspend.c */
extern int i915_save_state(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 545d3adaf341..fed959181773 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3570,3 +3570,13 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
dev_priv->perf.initialized = false;
}
+
+/**
+ * i915_perf_ioctl_version - Version of the i915-perf subsystem
+ *
+ * This version number is used by userspace to detect available features.
+ */
+int i915_perf_ioctl_version(void)
+{
+ return 1;
+}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 469dc512cca3..ea02b168ac3a 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -611,6 +611,13 @@ typedef struct drm_i915_irq_wait {
* See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
*/
#define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
+
+/*
+ * Revision of the i915-perf uAPI. The value returned helps determine what
+ * i915-perf features are available. See drm_i915_perf_property_id.
+ */
+#define I915_PARAM_PERF_REVISION 54
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1844,23 +1851,31 @@ enum drm_i915_perf_property_id {
* Open the stream for a specific context handle (as used with
* execbuffer2). A stream opened for a specific context this way
* won't typically require root privileges.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_CTX_HANDLE = 1,
/**
* A value of 1 requests the inclusion of raw OA unit reports as
* part of stream samples.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_SAMPLE_OA,
/**
* The value specifies which set of OA unit metrics should be
* be configured, defining the contents of any OA unit reports.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_METRICS_SET,
/**
* The value specifies the size and layout of OA unit reports.
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_FORMAT,
@@ -1870,6 +1885,8 @@ enum drm_i915_perf_property_id {
* from this exponent as follows:
*
* 80ns * 2^(period_exponent + 1)
+ *
+ * This property is available in perf revision 1.
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
@@ -1901,6 +1918,8 @@ struct drm_i915_perf_open_param {
* to close and re-open a stream with the same configuration.
*
* It's undefined whether any pending data for the stream will be lost.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
@@ -1908,6 +1927,8 @@ struct drm_i915_perf_open_param {
* Disable data capture for a stream.
*
* It is an error to try and read a stream that is disabled.
+ *
+ * This ioctl is available in perf revision 1.
*/
#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 04/12] drm/i915/perf: allow for CS OA configs to be created lazily
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (2 preceding siblings ...)
2019-07-09 9:31 ` [PATCH v7 03/12] drm/i915/perf: introduce a versioning of the i915-perf uapi Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 9:32 ` [PATCH v7 05/12] drm/i915: enumerate scratch fields Lionel Landwerlin
` (7 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particular user batchbuffer be
executed with a given OA configuration.
This mechanism essentially allows the userspace driver to go through
several OA configuration without having to open/close the i915/perf
stream.
v2: No need for locking on object OA config object creation (Chris)
Flush cpu mapping of OA config (Chris)
v3: Properly deal with the perf_metric lock (Chris/Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/i915_drv.h | 24 ++-
drivers/gpu/drm/i915/i915_perf.c | 186 +++++++++++++++----
3 files changed, 175 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index eec31e36aca7..e7eff9db343e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -126,6 +126,7 @@
*/
#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1)
#define MI_LRI_FORCE_POSTED (1<<12)
+#define MI_LOAD_REGISTER_IMM_MAX_REGS (126)
#define MI_STORE_REGISTER_MEM MI_INSTR(0x24, 1)
#define MI_STORE_REGISTER_MEM_GEN8 MI_INSTR(0x24, 2)
#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e4b010085f2d..0419dfd0dea3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1096,6 +1096,8 @@ struct i915_oa_reg {
};
struct i915_oa_config {
+ struct drm_i915_private *i915;
+
char uuid[UUID_STRING_LEN + 1];
int id;
@@ -1110,6 +1112,10 @@ struct i915_oa_config {
struct attribute *attrs[2];
struct device_attribute sysfs_metric_id;
+ struct drm_i915_gem_object *obj;
+
+ struct list_head vma_link;
+
atomic_t ref_count;
};
@@ -1693,11 +1699,21 @@ struct drm_i915_private {
struct mutex metrics_lock;
/*
- * List of dynamic configurations, you need to hold
- * dev_priv->perf.metrics_lock to access it.
+ * List of dynamic configurations (struct i915_oa_config), you
+ * need to hold dev_priv->perf.metrics_lock to access it.
*/
struct idr metrics_idr;
+ /*
+ * List of dynamic configurations (struct i915_oa_config)
+ * which have an allocated buffer in GGTT for reconfiguration,
+ * you need to hold dev_priv->perf.metrics_lock to access it.
+ * Elements are added to the list lazilly on execbuf (when a
+ * particular configuration is requested). The list is freed
+ * upon closing the perf stream.
+ */
+ struct list_head metrics_buffers;
+
/*
* Lock associated with anything below within this structure
* except exclusive_stream.
@@ -2586,6 +2602,10 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
struct intel_context *ce,
u32 *reg_state);
+int i915_perf_get_oa_config(struct drm_i915_private *i915,
+ int metrics_set,
+ struct i915_oa_config **out_config,
+ struct drm_i915_gem_object **out_obj);
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index fed959181773..882d7056aec3 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -366,9 +366,20 @@ struct perf_open_properties {
int oa_period_exponent;
};
-static void free_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+static void put_oa_config(struct i915_oa_config *oa_config)
{
+ if (!atomic_dec_and_test(&oa_config->ref_count))
+ return;
+
+ if (oa_config->obj) {
+ struct drm_i915_private *i915 = oa_config->i915;
+
+ mutex_lock(&i915->perf.metrics_lock);
+ list_del(&oa_config->vma_link);
+ i915_gem_object_put(oa_config->obj);
+ mutex_unlock(&i915->perf.metrics_lock);
+ }
+
if (!PTR_ERR(oa_config->flex_regs))
kfree(oa_config->flex_regs);
if (!PTR_ERR(oa_config->b_counter_regs))
@@ -378,38 +389,124 @@ static void free_oa_config(struct drm_i915_private *dev_priv,
kfree(oa_config);
}
-static void put_oa_config(struct drm_i915_private *dev_priv,
- struct i915_oa_config *oa_config)
+static u32 *write_cs_mi_lri(u32 *cs, const struct i915_oa_reg *reg_data, u32 n_regs)
{
- if (!atomic_dec_and_test(&oa_config->ref_count))
- return;
+ u32 i;
+
+ for (i = 0; i < n_regs; i++) {
+ if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
+ u32 n_lri = min(n_regs - i,
+ (u32) MI_LOAD_REGISTER_IMM_MAX_REGS);
+
+ *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
+ }
+ *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
+ *cs++ = reg_data[i].value;
+ }
- free_oa_config(dev_priv, oa_config);
+ return cs;
}
-static int get_oa_config(struct drm_i915_private *dev_priv,
- int metrics_set,
- struct i915_oa_config **out_config)
+static int alloc_oa_config_buffer(struct drm_i915_private *i915,
+ struct i915_oa_config *oa_config)
{
- int ret;
+ struct drm_i915_gem_object *bo;
+ size_t config_length = 0;
+ u32 *cs;
- if (metrics_set == 1) {
- *out_config = &dev_priv->perf.oa.test_config;
- atomic_inc(&dev_priv->perf.oa.test_config.ref_count);
- return 0;
+ if (oa_config->mux_regs_len > 0) {
+ config_length += DIV_ROUND_UP(oa_config->mux_regs_len,
+ MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
+ config_length += oa_config->mux_regs_len * 8;
+ }
+ if (oa_config->b_counter_regs_len > 0) {
+ config_length += DIV_ROUND_UP(oa_config->b_counter_regs_len,
+ MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
+ config_length += oa_config->b_counter_regs_len * 8;
+ }
+ if (oa_config->flex_regs_len > 0) {
+ config_length += DIV_ROUND_UP(oa_config->flex_regs_len,
+ MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
+ config_length += oa_config->flex_regs_len * 8;
}
+ config_length += 4; /* MI_BATCH_BUFFER_END */
+ config_length = ALIGN(config_length, I915_GTT_PAGE_SIZE);
- ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock);
+ bo = i915_gem_object_create_shmem(i915, config_length);
+ if (IS_ERR(bo))
+ return PTR_ERR(bo);
+
+ cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
+ if (IS_ERR(cs)) {
+ i915_gem_object_put(bo);
+ return PTR_ERR(cs);
+ }
+
+ cs = write_cs_mi_lri(cs, oa_config->mux_regs, oa_config->mux_regs_len);
+ cs = write_cs_mi_lri(cs, oa_config->b_counter_regs, oa_config->b_counter_regs_len);
+ cs = write_cs_mi_lri(cs, oa_config->flex_regs, oa_config->flex_regs_len);
+
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ i915_gem_object_flush_map(bo);
+ i915_gem_object_unpin_map(bo);
+
+ oa_config->obj = bo;
+
+ return 0;
+}
+
+int i915_perf_get_oa_config(struct drm_i915_private *i915,
+ int metrics_set,
+ struct i915_oa_config **out_config,
+ struct drm_i915_gem_object **out_obj)
+{
+ int ret = 0;
+ struct i915_oa_config *oa_config;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
if (ret)
return ret;
- *out_config = idr_find(&dev_priv->perf.metrics_idr, metrics_set);
- if (!*out_config)
- ret = -EINVAL;
- else
- atomic_inc(&(*out_config)->ref_count);
+ if (metrics_set == 1) {
+ oa_config = &i915->perf.oa.test_config;
+ } else {
+ oa_config = idr_find(&i915->perf.metrics_idr, metrics_set);
+ if (!oa_config) {
+ ret = -EINVAL;
+ goto err_unlock;
+ }
+ }
+
+ if (out_config) {
+ atomic_inc(&oa_config->ref_count);
+ *out_config = oa_config;
+ }
- mutex_unlock(&dev_priv->perf.metrics_lock);
+ if (out_obj) {
+ if (oa_config->obj) {
+ *out_obj = i915_gem_object_get(oa_config->obj);
+ } else {
+ ret = alloc_oa_config_buffer(i915, oa_config);
+ if (ret)
+ goto err_unlock;
+
+ list_add(&oa_config->vma_link,
+ &i915->perf.metrics_buffers);
+ *out_obj = i915_gem_object_get(oa_config->obj);
+ }
+ }
+
+err_unlock:
+ mutex_unlock(&i915->perf.metrics_lock);
+
+ if (ret && out_config) {
+ put_oa_config(oa_config);
+ *out_config = NULL;
+ }
return ret;
}
@@ -1380,7 +1477,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
if (stream->ctx)
oa_put_render_ctx_id(stream);
- put_oa_config(dev_priv, stream->oa_config);
+ put_oa_config(stream->oa_config);
if (dev_priv->perf.oa.spurious_report_rs.missed) {
DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n",
@@ -2117,7 +2214,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
}
}
- ret = get_oa_config(dev_priv, props->metrics_set, &stream->oa_config);
+ ret = i915_perf_get_oa_config(dev_priv, props->metrics_set,
+ &stream->oa_config, NULL);
if (ret) {
DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
goto err_config;
@@ -2155,6 +2253,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
goto err_enable;
}
+ DRM_DEBUG("opening stream oa config uuid=%s\n", stream->oa_config->uuid);
+
mutex_unlock(&dev_priv->drm.struct_mutex);
return 0;
@@ -2168,7 +2268,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
free_oa_buffer(dev_priv);
err_oa_buf_alloc:
- put_oa_config(dev_priv, stream->oa_config);
+ put_oa_config(stream->oa_config);
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref);
@@ -2535,9 +2635,21 @@ static int i915_perf_release(struct inode *inode, struct file *file)
{
struct i915_perf_stream *stream = file->private_data;
struct drm_i915_private *dev_priv = stream->dev_priv;
+ struct i915_oa_config *oa_config, *next;
mutex_lock(&dev_priv->perf.lock);
+
i915_perf_destroy_locked(stream);
+
+ /* Dispose of all oa config batch buffers. */
+ mutex_lock(&dev_priv->perf.metrics_lock);
+ list_for_each_entry_safe(oa_config, next, &dev_priv->perf.metrics_buffers, vma_link) {
+ list_del(&oa_config->vma_link);
+ i915_gem_object_put(oa_config->obj);
+ oa_config->obj = NULL;
+ }
+ mutex_unlock(&dev_priv->perf.metrics_lock);
+
mutex_unlock(&dev_priv->perf.lock);
/* Release the reference the perf stream kept on the driver. */
@@ -2973,6 +3085,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
if (ret)
goto sysfs_error;
+ dev_priv->perf.oa.test_config.i915 = dev_priv;
atomic_set(&dev_priv->perf.oa.test_config.ref_count, 1);
goto exit;
@@ -3229,6 +3342,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
return -ENOMEM;
}
+ oa_config->i915 = dev_priv;
atomic_set(&oa_config->ref_count, 1);
if (!uuid_is_valid(args->uuid)) {
@@ -3328,7 +3442,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
sysfs_err:
mutex_unlock(&dev_priv->perf.metrics_lock);
reg_err:
- put_oa_config(dev_priv, oa_config);
+ put_oa_config(oa_config);
DRM_DEBUG("Failed to add new OA config\n");
return err;
}
@@ -3364,13 +3478,13 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
ret = mutex_lock_interruptible(&dev_priv->perf.metrics_lock);
if (ret)
- goto lock_err;
+ return ret;
oa_config = idr_find(&dev_priv->perf.metrics_idr, *arg);
if (!oa_config) {
DRM_DEBUG("Failed to remove unknown OA config\n");
ret = -ENOENT;
- goto config_err;
+ goto err_unlock;
}
GEM_BUG_ON(*arg != oa_config->id);
@@ -3380,13 +3494,16 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
idr_remove(&dev_priv->perf.metrics_idr, *arg);
+ mutex_unlock(&dev_priv->perf.metrics_lock);
+
DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
- put_oa_config(dev_priv, oa_config);
+ put_oa_config(oa_config);
+
+ return 0;
-config_err:
+err_unlock:
mutex_unlock(&dev_priv->perf.metrics_lock);
-lock_err:
return ret;
}
@@ -3528,6 +3645,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
init_waitqueue_head(&dev_priv->perf.oa.poll_wq);
INIT_LIST_HEAD(&dev_priv->perf.streams);
+ INIT_LIST_HEAD(&dev_priv->perf.metrics_buffers);
+
mutex_init(&dev_priv->perf.lock);
spin_lock_init(&dev_priv->perf.oa.oa_buffer.ptr_lock);
@@ -3544,10 +3663,9 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
static int destroy_config(int id, void *p, void *data)
{
- struct drm_i915_private *dev_priv = data;
struct i915_oa_config *oa_config = p;
- put_oa_config(dev_priv, oa_config);
+ put_oa_config(oa_config);
return 0;
}
@@ -3561,7 +3679,7 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
if (!dev_priv->perf.initialized)
return;
- idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, dev_priv);
+ idr_for_each(&dev_priv->perf.metrics_idr, destroy_config, NULL);
idr_destroy(&dev_priv->perf.metrics_idr);
unregister_sysctl_table(dev_priv->perf.sysctl_header);
--
2.21.0.392.gf8f6787159e
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 05/12] drm/i915: enumerate scratch fields
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (3 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 04/12] drm/i915/perf: allow for CS OA configs to be created lazily Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 9:32 ` [PATCH v7 06/12] drm/i915/perf: implement active wait for noa configurations Lionel Landwerlin
` (6 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
We have a bunch of offsets in the scratch buffer. As we're about to
add some more, let's group all of the offsets in a common location.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/intel_gt.h | 6 +++--
drivers/gpu/drm/i915/gt/intel_gt_types.h | 15 +++++++++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 24 ++++++++++-------
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 31 +++++++++++++++-------
4 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.h b/drivers/gpu/drm/i915/gt/intel_gt.h
index cf3c6cecc8ee..d9ce1775be53 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt.h
@@ -24,9 +24,11 @@ void intel_gt_chipset_flush(struct intel_gt *gt);
int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size);
void intel_gt_fini_scratch(struct intel_gt *gt);
-static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt)
+static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
+ enum intel_gt_scratch_field field)
{
- return i915_ggtt_offset(gt->scratch);
+
+ return i915_ggtt_offset(gt->scratch) + field;
}
#endif /* __INTEL_GT_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 37da428bef62..3563ce970102 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -60,4 +60,19 @@ struct intel_gt {
u32 pm_ier;
};
+enum intel_gt_scratch_field {
+ /* 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_DEFAULT = 0,
+
+ /* 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA = 128,
+
+ /* 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH = 128,
+
+ /* 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+
+};
+
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index e1ae1399c72b..87d263f92cf4 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1782,7 +1782,8 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
/* NB no one else is allowed to scribble over scratch + 256! */
*batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
- *batch++ = intel_gt_scratch_offset(engine->gt) + 256;
+ *batch++ = intel_gt_scratch_offset(engine->gt,
+ INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
*batch++ = 0;
*batch++ = MI_LOAD_REGISTER_IMM(1);
@@ -1796,7 +1797,8 @@ gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
*batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
*batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
- *batch++ = intel_gt_scratch_offset(engine->gt) + 256;
+ *batch++ = intel_gt_scratch_offset(engine->gt,
+ INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
*batch++ = 0;
return batch;
@@ -1828,13 +1830,14 @@ static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
/* Actual scratch location is at 128 bytes offset */
- batch = gen8_emit_pipe_control(batch,
- PIPE_CONTROL_FLUSH_L3 |
- PIPE_CONTROL_GLOBAL_GTT_IVB |
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_QW_WRITE,
- intel_gt_scratch_offset(engine->gt) +
- 2 * CACHELINE_BYTES);
+ batch = gen8_emit_pipe_control(
+ batch,
+ PIPE_CONTROL_FLUSH_L3 |
+ PIPE_CONTROL_GLOBAL_GTT_IVB |
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_QW_WRITE,
+ intel_gt_scratch_offset(engine->gt,
+ INTEL_GT_SCRATCH_FIELD_CLEAR_SLM_WA));
*batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
@@ -2528,7 +2531,8 @@ static int gen8_emit_flush_render(struct i915_request *request,
{
struct intel_engine_cs *engine = request->engine;
u32 scratch_addr =
- intel_gt_scratch_offset(engine->gt) + 2 * CACHELINE_BYTES;
+ intel_gt_scratch_offset(engine->gt,
+ INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
bool vf_flush_wa = false, dc_flush_wa = false;
u32 *cs, flags = 0;
int len;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index b33cfc56f623..a98652e4055c 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -76,7 +76,8 @@ gen2_render_ring_flush(struct i915_request *rq, u32 mode)
*cs++ = cmd;
while (num_store_dw--) {
*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
- *cs++ = intel_gt_scratch_offset(rq->engine->gt);
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_DEFAULT);
*cs++ = 0;
}
*cs++ = MI_FLUSH | MI_NO_WRITE_FLUSH;
@@ -149,7 +150,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
*/
if (mode & EMIT_INVALIDATE) {
*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
- *cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_DEFAULT) |
PIPE_CONTROL_GLOBAL_GTT;
*cs++ = 0;
*cs++ = 0;
@@ -158,7 +160,8 @@ gen4_render_ring_flush(struct i915_request *rq, u32 mode)
*cs++ = MI_FLUSH;
*cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE;
- *cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_DEFAULT) |
PIPE_CONTROL_GLOBAL_GTT;
*cs++ = 0;
*cs++ = 0;
@@ -212,7 +215,8 @@ static int
gen6_emit_post_sync_nonzero_flush(struct i915_request *rq)
{
u32 scratch_addr =
- intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
+ intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
u32 *cs;
cs = intel_ring_begin(rq, 6);
@@ -246,7 +250,8 @@ static int
gen6_render_ring_flush(struct i915_request *rq, u32 mode)
{
u32 scratch_addr =
- intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
+ intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
u32 *cs, flags = 0;
int ret;
@@ -304,7 +309,8 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs)
*cs++ = GFX_OP_PIPE_CONTROL(4);
*cs++ = PIPE_CONTROL_QW_WRITE;
- *cs++ = intel_gt_scratch_offset(rq->engine->gt) |
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_DEFAULT) |
PIPE_CONTROL_GLOBAL_GTT;
*cs++ = 0;
@@ -349,7 +355,8 @@ static int
gen7_render_ring_flush(struct i915_request *rq, u32 mode)
{
u32 scratch_addr =
- intel_gt_scratch_offset(rq->engine->gt) + 2 * CACHELINE_BYTES;
+ intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_RENDER_FLUSH);
u32 *cs, flags = 0;
/*
@@ -1078,7 +1085,9 @@ i830_emit_bb_start(struct i915_request *rq,
u64 offset, u32 len,
unsigned int dispatch_flags)
{
- u32 *cs, cs_offset = intel_gt_scratch_offset(rq->engine->gt);
+ u32 *cs, cs_offset =
+ intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_DEFAULT);
GEM_BUG_ON(rq->engine->gt->scratch->size < I830_WA_SIZE);
@@ -1522,7 +1531,8 @@ static int flush_pd_dir(struct i915_request *rq)
/* Stall until the page table load is complete */
*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base));
- *cs++ = intel_gt_scratch_offset(rq->engine->gt);
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_DEFAULT);
*cs++ = MI_NOOP;
intel_ring_advance(rq, cs);
@@ -1638,7 +1648,8 @@ static inline int mi_set_context(struct i915_request *rq, u32 flags)
/* Insert a delay before the next switch! */
*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
*cs++ = i915_mmio_reg_offset(last_reg);
- *cs++ = intel_gt_scratch_offset(rq->engine->gt);
+ *cs++ = intel_gt_scratch_offset(rq->engine->gt,
+ INTEL_GT_SCRATCH_FIELD_DEFAULT);
*cs++ = MI_NOOP;
}
*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
--
2.21.0.392.gf8f6787159e
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 06/12] drm/i915/perf: implement active wait for noa configurations
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (4 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 05/12] drm/i915: enumerate scratch fields Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 9:53 ` Chris Wilson
2019-07-09 9:32 ` [PATCH v7 07/12] drm/i915: introduce a mechanism to extend execbuf2 Lionel Landwerlin
` (5 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should be over the required amount of
time (according to HW architects).
v2: Don't forget to save/restore registers used for the wait (Chris)
v3: Name used CS_GPR registers (Chris)
Fix compile issue due to rebase (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 ++
drivers/gpu/drm/i915/gt/intel_gt_types.h | 5 +
drivers/gpu/drm/i915/i915_debugfs.c | 31 +++
drivers/gpu/drm/i915/i915_drv.h | 8 +
drivers/gpu/drm/i915/i915_perf.c | 227 ++++++++++++++++++-
drivers/gpu/drm/i915/i915_reg.h | 4 +-
6 files changed, 296 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index e7eff9db343e..4a66af38c87b 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -151,6 +151,7 @@
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
#define MI_BATCH_RESOURCE_STREAMER (1<<10)
+#define MI_BATCH_PREDICATE (1 << 15) /* HSW+ on RCS only*/
/*
* 3D instructions used by the kernel
@@ -226,6 +227,29 @@
#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+#define MI_MATH(x) MI_INSTR(0x1a, (x)-1)
+#define MI_ALU_OP(op, src1, src2) (((op) << 20) | ((src1) << 10) | (src2))
+/* operands */
+#define MI_ALU_OP_NOOP 0
+#define MI_ALU_OP_LOAD 128
+#define MI_ALU_OP_LOADINV 1152
+#define MI_ALU_OP_LOAD0 129
+#define MI_ALU_OP_LOAD1 1153
+#define MI_ALU_OP_ADD 256
+#define MI_ALU_OP_SUB 257
+#define MI_ALU_OP_AND 258
+#define MI_ALU_OP_OR 259
+#define MI_ALU_OP_XOR 260
+#define MI_ALU_OP_STORE 384
+#define MI_ALU_OP_STOREINV 1408
+/* sources */
+#define MI_ALU_SRC_REG(x) (x) /* 0 -> 15 */
+#define MI_ALU_SRC_SRCA 32
+#define MI_ALU_SRC_SRCB 33
+#define MI_ALU_SRC_ACCU 49
+#define MI_ALU_SRC_ZF 50
+#define MI_ALU_SRC_CF 51
+
/*
* Commands used only by the command parser
*/
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_types.h b/drivers/gpu/drm/i915/gt/intel_gt_types.h
index 3563ce970102..a3141b79d344 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_types.h
@@ -73,6 +73,11 @@ enum intel_gt_scratch_field {
/* 8 bytes */
INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA = 256,
+ /* 6 * 8 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR = 2048,
+
+ /* 4 bytes */
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1 = 2096,
};
#endif /* __INTEL_GT_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e4f58f19362..46fca53dfbda 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -3653,6 +3653,36 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
i915_wedged_get, i915_wedged_set,
"%llu\n");
+static int
+i915_perf_noa_delay_set(void *data, u64 val)
+{
+ struct drm_i915_private *i915 = data;
+
+ /* This would lead to infinite waits as we're doing timestamp
+ * difference on the CS with only 32bits.
+ */
+ if (val > ((1ul << 32) - 1) * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz)
+ return -EINVAL;
+
+ atomic64_set(&i915->perf.oa.noa_programming_delay, val);
+ return 0;
+}
+
+static int
+i915_perf_noa_delay_get(void *data, u64 *val)
+{
+ struct drm_i915_private *i915 = data;
+
+ *val = atomic64_read(&i915->perf.oa.noa_programming_delay);
+ return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
+ i915_perf_noa_delay_get,
+ i915_perf_noa_delay_set,
+ "%llu\n");
+
+
#define DROP_UNBOUND BIT(0)
#define DROP_BOUND BIT(1)
#define DROP_RETIRE BIT(2)
@@ -4418,6 +4448,7 @@ static const struct i915_debugfs_files {
const char *name;
const struct file_operations *fops;
} i915_debugfs_files[] = {
+ {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
{"i915_wedged", &i915_wedged_fops},
{"i915_cache_sharing", &i915_cache_sharing_fops},
{"i915_gem_drop_caches", &i915_drop_caches_fops},
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0419dfd0dea3..b3c6dd72c7a1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1834,6 +1834,14 @@ struct drm_i915_private {
struct i915_oa_ops ops;
const struct i915_oa_format *oa_formats;
+
+ /**
+ * A batch buffer doing a wait on the GPU for the NOA
+ * logic to be reprogrammed.
+ */
+ struct i915_vma *noa_wait;
+
+ atomic64_t noa_programming_delay;
} oa;
} perf;
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 882d7056aec3..18a8f38839ba 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_gt.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -429,7 +430,7 @@ static int alloc_oa_config_buffer(struct drm_i915_private *i915,
MI_LOAD_REGISTER_IMM_MAX_REGS) * 4;
config_length += oa_config->flex_regs_len * 8;
}
- config_length += 4; /* MI_BATCH_BUFFER_END */
+ config_length += 12; /* MI_BATCH_BUFFER_START into noa_wait loop */
config_length = ALIGN(config_length, I915_GTT_PAGE_SIZE);
bo = i915_gem_object_create_shmem(i915, config_length);
@@ -446,7 +447,12 @@ static int alloc_oa_config_buffer(struct drm_i915_private *i915,
cs = write_cs_mi_lri(cs, oa_config->b_counter_regs, oa_config->b_counter_regs_len);
cs = write_cs_mi_lri(cs, oa_config->flex_regs, oa_config->flex_regs_len);
- *cs++ = MI_BATCH_BUFFER_END;
+
+ /* Jump into the NOA wait busy loop. */
+ *cs++ = (INTEL_GEN(i915) < 8 ?
+ MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8);
+ *cs++ = i915_ggtt_offset(i915->perf.oa.noa_wait);
+ *cs++ = 0;
i915_gem_object_flush_map(bo);
i915_gem_object_unpin_map(bo);
@@ -1467,6 +1473,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
mutex_lock(&dev_priv->drm.struct_mutex);
dev_priv->perf.oa.exclusive_stream = NULL;
dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
+ i915_vma_unpin_and_release(&dev_priv->perf.oa.noa_wait, 0);
mutex_unlock(&dev_priv->drm.struct_mutex);
free_oa_buffer(dev_priv);
@@ -1653,6 +1660,206 @@ static int alloc_oa_buffer(struct drm_i915_private *dev_priv)
return ret;
}
+static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
+ i915_reg_t reg, u32 offset, u32 dword_count)
+{
+ uint32_t d;
+
+ for (d = 0; d < dword_count; d++) {
+ *cs++ = INTEL_GEN(i915) >= 8 ?
+ MI_STORE_REGISTER_MEM_GEN8 : MI_STORE_REGISTER_MEM;
+ *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
+ *cs++ = intel_gt_scratch_offset(&i915->gt, offset) + 4 * d;
+ if (INTEL_GEN(i915) >= 8)
+ *cs++ = 0;
+ }
+
+ return cs;
+}
+
+static u32 *restore_register(struct drm_i915_private *i915, u32 *cs,
+ i915_reg_t reg, u32 offset, u32 dword_count)
+{
+ uint32_t d;
+
+ for (d = 0; d < dword_count; d++) {
+ *cs++ = INTEL_GEN(i915) >= 8 ?
+ MI_LOAD_REGISTER_MEM_GEN8 : MI_LOAD_REGISTER_MEM;
+ *cs++ = i915_mmio_reg_offset(reg);
+ *cs++ = intel_gt_scratch_offset(&i915->gt, offset);
+ *cs++ = 0;
+ }
+
+ return cs;
+}
+
+static int alloc_noa_wait(struct drm_i915_private *i915)
+{
+ struct drm_i915_gem_object *bo;
+ struct i915_vma *vma;
+ u64 delay_ns = atomic64_read(&i915->perf.oa.noa_programming_delay), delay_ticks;
+ u32 *batch, *ts0, *cs, *jump;
+ int ret, i;
+ enum { START_TS, NOW_TS, DELTA_TS, JUMP_PREDICATE, DELTA_TARGET, N_CS_GPR };
+
+ bo = i915_gem_object_create_internal(i915, 4096);
+ if (IS_ERR(bo)) {
+ DRM_ERROR("Failed to allocate NOA wait batchbuffer\n");
+ return PTR_ERR(bo);
+ }
+
+ /*
+ * We pin in GGTT because we jump into this buffer now because
+ * multiple OA config BOs will have a jump to this address and it
+ * needs to be fixed during the lifetime of the i915/perf stream.
+ */
+ vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 4096, 0);
+ if (IS_ERR(vma)) {
+ ret = PTR_ERR(vma);
+ goto err_unref;
+ }
+
+ batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
+ if (IS_ERR(batch)) {
+ ret = PTR_ERR(batch);
+ goto err_unpin;
+ }
+
+ /* Save registers. */
+ for (i = 0; i < N_CS_GPR; i++) {
+ cs = save_register(i915, cs, HSW_CS_GPR(i),
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ }
+ cs = save_register(i915, cs, MI_PREDICATE_RESULT_1,
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+
+ /* First timestamp snapshot location. */
+ ts0 = cs;
+
+ /*
+ * Initial snapshot of the timestamp register to implement the wait.
+ * We work with 32b values, so clear out the top 32b bits of the
+ * register because the ALU works 64bits.
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS)) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS));
+
+ /*
+ * This is the location we're going to jump back into until the
+ * required amount of time has passed.
+ */
+ jump = cs;
+
+ /*
+ * Take another snapshot of the timestamp register. Take care to clear
+ * up the top 32bits of CS_GPR(1) as we're using it for other
+ * operations below.
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS)) + 4;
+ *cs++ = 0;
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS));
+
+ /*
+ * Do a diff between the 2 timestamps and store the result back into
+ * CS_GPR(1).
+ */
+ *cs++ = MI_MATH(5);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(NOW_TS));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(START_TS));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_SUB, 0, 0);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(DELTA_TS), MI_ALU_SRC_ACCU);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
+
+ /*
+ * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
+ * timestamp have rolled over the 32bits) into the predicate register
+ * to be used for the predicated jump.
+ */
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
+ *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
+
+ /* Restart from the beginning if we had timestamps roll over. */
+ *cs++ = (INTEL_GEN(i915) < 8 ?
+ MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
+ MI_BATCH_PREDICATE;
+ *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
+ *cs++ = 0;
+
+ /*
+ * Now add the diff between to previous timestamps and add it to :
+ * (((1 * << 64) - 1) - delay_ns)
+ *
+ * When the Carry Flag contains 1 this means the elapsed time is
+ * longer than the expected delay, and we can exit the wait loop.
+ */
+ delay_ticks = 0xffffffffffffffff -
+ DIV64_U64_ROUND_UP(delay_ns *
+ RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
+ 1000000ull);
+ *cs++ = MI_LOAD_REGISTER_IMM(2);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET));
+ *cs++ = lower_32_bits(delay_ticks);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET)) + 4;
+ *cs++ = upper_32_bits(delay_ticks);
+
+ *cs++ = MI_MATH(4);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(DELTA_TS));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(DELTA_TARGET));
+ *cs++ = MI_ALU_OP(MI_ALU_OP_ADD, 0, 0);
+ *cs++ = MI_ALU_OP(MI_ALU_OP_STOREINV, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
+
+ /*
+ * Transfer the result into the predicate register to be used for the
+ * predicated jump.
+ */
+ *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
+ *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
+ *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
+
+ /* Predicate the jump. */
+ *cs++ = (INTEL_GEN(i915) < 8 ?
+ MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
+ MI_BATCH_PREDICATE;
+ *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
+ *cs++ = 0;
+
+ /* Restore registers. */
+ for (i = 0; i < N_CS_GPR; i++) {
+ cs = restore_register(i915, cs, HSW_CS_GPR(i),
+ INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
+ }
+ cs = restore_register(i915, cs, MI_PREDICATE_RESULT_1,
+ INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
+
+ /* And return to the ring. */
+ *cs++ = MI_BATCH_BUFFER_END;
+
+ GEM_BUG_ON((cs - batch) > (PAGE_SIZE / sizeof(*batch)));
+
+ i915_gem_object_flush_map(bo);
+ i915_gem_object_unpin_map(bo);
+
+ i915->perf.oa.noa_wait = vma;
+
+ return 0;
+
+err_unpin:
+ __i915_vma_unpin(vma);
+
+err_unref:
+ i915_gem_object_put(bo);
+
+ return ret;
+}
+
static void config_oa_regs(struct drm_i915_private *dev_priv,
const struct i915_oa_reg *regs,
u32 n_regs)
@@ -2221,6 +2428,12 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
goto err_config;
}
+ ret = alloc_noa_wait(dev_priv);
+ if (ret) {
+ DRM_DEBUG("Unable to allocate NOA wait batch buffer\n");
+ goto err_noa_wait_alloc;
+ }
+
/* PRM - observability performance counters:
*
* OACONTROL, performance counter enable, note:
@@ -2273,6 +2486,13 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref);
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ i915_vma_unpin_and_release(&dev_priv->perf.oa.noa_wait, 0);
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+
+err_noa_wait_alloc:
+ put_oa_config(stream->oa_config);
+
err_config:
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -3657,6 +3877,9 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->perf.metrics_lock);
idr_init(&dev_priv->perf.metrics_idr);
+ atomic64_set(&dev_priv->perf.oa.noa_programming_delay,
+ 500 * 1000 /* 500us */);
+
dev_priv->perf.initialized = true;
}
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5898f59e3dd7..a73464dd5e91 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -567,7 +567,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MI_PREDICATE_SRC0_UDW _MMIO(0x2400 + 4)
#define MI_PREDICATE_SRC1 _MMIO(0x2408)
#define MI_PREDICATE_SRC1_UDW _MMIO(0x2408 + 4)
-
+#define MI_PREDICATE_DATA _MMIO(0x2410)
+#define MI_PREDICATE_RESULT _MMIO(0x2418)
+#define MI_PREDICATE_RESULT_1 _MMIO(0x241c)
#define MI_PREDICATE_RESULT_2 _MMIO(0x2214)
#define LOWER_SLICE_ENABLED (1 << 0)
#define LOWER_SLICE_DISABLED (0 << 0)
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v7 06/12] drm/i915/perf: implement active wait for noa configurations
2019-07-09 9:32 ` [PATCH v7 06/12] drm/i915/perf: implement active wait for noa configurations Lionel Landwerlin
@ 2019-07-09 9:53 ` Chris Wilson
2019-07-09 10:44 ` Lionel Landwerlin
0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-07-09 9:53 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-07-09 10:32:02)
> +static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
> + i915_reg_t reg, u32 offset, u32 dword_count)
> +{
> + uint32_t d;
> +
> + for (d = 0; d < dword_count; d++) {
> + *cs++ = INTEL_GEN(i915) >= 8 ?
> + MI_STORE_REGISTER_MEM_GEN8 : MI_STORE_REGISTER_MEM;
> + *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
> + *cs++ = intel_gt_scratch_offset(&i915->gt, offset) + 4 * d;
> + if (INTEL_GEN(i915) >= 8)
> + *cs++ = 0;
restore_register doesn't care about the extra MI_NOOP :)
> + }
> +
> + return cs;
> +}
> +
> +static u32 *restore_register(struct drm_i915_private *i915, u32 *cs,
> + i915_reg_t reg, u32 offset, u32 dword_count)
> +{
> + uint32_t d;
> +
> + for (d = 0; d < dword_count; d++) {
> + *cs++ = INTEL_GEN(i915) >= 8 ?
> + MI_LOAD_REGISTER_MEM_GEN8 : MI_LOAD_REGISTER_MEM;
> + *cs++ = i915_mmio_reg_offset(reg);
> + *cs++ = intel_gt_scratch_offset(&i915->gt, offset);
> + *cs++ = 0;
> + }
> +
> + return cs;
> +}
> +
> +static int alloc_noa_wait(struct drm_i915_private *i915)
> +{
> + struct drm_i915_gem_object *bo;
> + struct i915_vma *vma;
> + u64 delay_ns = atomic64_read(&i915->perf.oa.noa_programming_delay), delay_ticks;
I would const u64 delay_ticks = foo(i915);
That would save the distraction later in the middle of CS.
> + u32 *batch, *ts0, *cs, *jump;
> + int ret, i;
> + enum { START_TS, NOW_TS, DELTA_TS, JUMP_PREDICATE, DELTA_TARGET, N_CS_GPR };
> +
> + bo = i915_gem_object_create_internal(i915, 4096);
> + if (IS_ERR(bo)) {
> + DRM_ERROR("Failed to allocate NOA wait batchbuffer\n");
> + return PTR_ERR(bo);
> + }
> +
> + /*
> + * We pin in GGTT because we jump into this buffer now because
> + * multiple OA config BOs will have a jump to this address and it
> + * needs to be fixed during the lifetime of the i915/perf stream.
> + */
> + vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 4096, 0);
> + if (IS_ERR(vma)) {
> + ret = PTR_ERR(vma);
> + goto err_unref;
> + }
> +
> + batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
> + if (IS_ERR(batch)) {
> + ret = PTR_ERR(batch);
> + goto err_unpin;
> + }
> +
> + /* Save registers. */
> + for (i = 0; i < N_CS_GPR; i++) {
> + cs = save_register(i915, cs, HSW_CS_GPR(i),
> + INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
> + }
> + cs = save_register(i915, cs, MI_PREDICATE_RESULT_1,
> + INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
> +
> + /* First timestamp snapshot location. */
> + ts0 = cs;
> +
> + /*
> + * Initial snapshot of the timestamp register to implement the wait.
> + * We work with 32b values, so clear out the top 32b bits of the
> + * register because the ALU works 64bits.
> + */
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS)) + 4;
> + *cs++ = 0;
> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
> + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS));
> +
> + /*
> + * This is the location we're going to jump back into until the
> + * required amount of time has passed.
> + */
> + jump = cs;
> +
> + /*
> + * Take another snapshot of the timestamp register. Take care to clear
> + * up the top 32bits of CS_GPR(1) as we're using it for other
> + * operations below.
> + */
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS)) + 4;
> + *cs++ = 0;
> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
> + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS));
> +
> + /*
> + * Do a diff between the 2 timestamps and store the result back into
> + * CS_GPR(1).
> + */
> + *cs++ = MI_MATH(5);
> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(NOW_TS));
> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(START_TS));
> + *cs++ = MI_ALU_OP(MI_ALU_OP_SUB, 0, 0);
> + *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(DELTA_TS), MI_ALU_SRC_ACCU);
> + *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
> +
> + /*
> + * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
> + * timestamp have rolled over the 32bits) into the predicate register
> + * to be used for the predicated jump.
> + */
> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
> + *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
> +
> + /* Restart from the beginning if we had timestamps roll over. */
> + *cs++ = (INTEL_GEN(i915) < 8 ?
> + MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
> + MI_BATCH_PREDICATE;
> + *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
> + *cs++ = 0;
> +
> + /*
> + * Now add the diff between to previous timestamps and add it to :
> + * (((1 * << 64) - 1) - delay_ns)
> + *
> + * When the Carry Flag contains 1 this means the elapsed time is
> + * longer than the expected delay, and we can exit the wait loop.
> + */
> + delay_ticks = 0xffffffffffffffff -
> + DIV64_U64_ROUND_UP(delay_ns *
> + RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
> + 1000000ull);
> + *cs++ = MI_LOAD_REGISTER_IMM(2);
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET));
> + *cs++ = lower_32_bits(delay_ticks);
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET)) + 4;
> + *cs++ = upper_32_bits(delay_ticks);
> +
> + *cs++ = MI_MATH(4);
> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(DELTA_TS));
> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(DELTA_TARGET));
> + *cs++ = MI_ALU_OP(MI_ALU_OP_ADD, 0, 0);
> + *cs++ = MI_ALU_OP(MI_ALU_OP_STOREINV, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
> +
> + /*
> + * Transfer the result into the predicate register to be used for the
> + * predicated jump.
> + */
> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
> + *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
> +
> + /* Predicate the jump. */
> + *cs++ = (INTEL_GEN(i915) < 8 ?
> + MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
> + MI_BATCH_PREDICATE;
> + *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
> + *cs++ = 0;
> +
> + /* Restore registers. */
> + for (i = 0; i < N_CS_GPR; i++) {
> + cs = restore_register(i915, cs, HSW_CS_GPR(i),
> + INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
> + }
> + cs = restore_register(i915, cs, MI_PREDICATE_RESULT_1,
> + INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
> +
> + /* And return to the ring. */
> + *cs++ = MI_BATCH_BUFFER_END;
> +
> + GEM_BUG_ON((cs - batch) > (PAGE_SIZE / sizeof(*batch)));
> +
> + i915_gem_object_flush_map(bo);
> + i915_gem_object_unpin_map(bo);
> +
> + i915->perf.oa.noa_wait = vma;
> +
> + return 0;
> +
> +err_unpin:
> + __i915_vma_unpin(vma);
> +
> +err_unref:
> + i915_gem_object_put(bo);
> +
> + return ret;
> +}
Preferably with the nit above,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 06/12] drm/i915/perf: implement active wait for noa configurations
2019-07-09 9:53 ` Chris Wilson
@ 2019-07-09 10:44 ` Lionel Landwerlin
0 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 10:44 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 09/07/2019 12:53, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-07-09 10:32:02)
>> +static u32 *save_register(struct drm_i915_private *i915, u32 *cs,
>> + i915_reg_t reg, u32 offset, u32 dword_count)
>> +{
>> + uint32_t d;
>> +
>> + for (d = 0; d < dword_count; d++) {
>> + *cs++ = INTEL_GEN(i915) >= 8 ?
>> + MI_STORE_REGISTER_MEM_GEN8 : MI_STORE_REGISTER_MEM;
>> + *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
>> + *cs++ = intel_gt_scratch_offset(&i915->gt, offset) + 4 * d;
>> + if (INTEL_GEN(i915) >= 8)
>> + *cs++ = 0;
> restore_register doesn't care about the extra MI_NOOP :)
>
>> + }
>> +
>> + return cs;
>> +}
>> +
>> +static u32 *restore_register(struct drm_i915_private *i915, u32 *cs,
>> + i915_reg_t reg, u32 offset, u32 dword_count)
>> +{
>> + uint32_t d;
>> +
>> + for (d = 0; d < dword_count; d++) {
>> + *cs++ = INTEL_GEN(i915) >= 8 ?
>> + MI_LOAD_REGISTER_MEM_GEN8 : MI_LOAD_REGISTER_MEM;
>> + *cs++ = i915_mmio_reg_offset(reg);
>> + *cs++ = intel_gt_scratch_offset(&i915->gt, offset);
>> + *cs++ = 0;
>> + }
>> +
>> + return cs;
>> +}
>> +
>> +static int alloc_noa_wait(struct drm_i915_private *i915)
>> +{
>> + struct drm_i915_gem_object *bo;
>> + struct i915_vma *vma;
>> + u64 delay_ns = atomic64_read(&i915->perf.oa.noa_programming_delay), delay_ticks;
> I would const u64 delay_ticks = foo(i915);
>
> That would save the distraction later in the middle of CS.
>
>> + u32 *batch, *ts0, *cs, *jump;
>> + int ret, i;
>> + enum { START_TS, NOW_TS, DELTA_TS, JUMP_PREDICATE, DELTA_TARGET, N_CS_GPR };
>> +
>> + bo = i915_gem_object_create_internal(i915, 4096);
>> + if (IS_ERR(bo)) {
>> + DRM_ERROR("Failed to allocate NOA wait batchbuffer\n");
>> + return PTR_ERR(bo);
>> + }
>> +
>> + /*
>> + * We pin in GGTT because we jump into this buffer now because
>> + * multiple OA config BOs will have a jump to this address and it
>> + * needs to be fixed during the lifetime of the i915/perf stream.
>> + */
>> + vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 4096, 0);
>> + if (IS_ERR(vma)) {
>> + ret = PTR_ERR(vma);
>> + goto err_unref;
>> + }
>> +
>> + batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
>> + if (IS_ERR(batch)) {
>> + ret = PTR_ERR(batch);
>> + goto err_unpin;
>> + }
>> +
>> + /* Save registers. */
>> + for (i = 0; i < N_CS_GPR; i++) {
>> + cs = save_register(i915, cs, HSW_CS_GPR(i),
>> + INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
>> + }
>> + cs = save_register(i915, cs, MI_PREDICATE_RESULT_1,
>> + INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
>> +
>> + /* First timestamp snapshot location. */
>> + ts0 = cs;
>> +
>> + /*
>> + * Initial snapshot of the timestamp register to implement the wait.
>> + * We work with 32b values, so clear out the top 32b bits of the
>> + * register because the ALU works 64bits.
>> + */
>> + *cs++ = MI_LOAD_REGISTER_IMM(1);
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS)) + 4;
>> + *cs++ = 0;
>> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
>> + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(START_TS));
>> +
>> + /*
>> + * This is the location we're going to jump back into until the
>> + * required amount of time has passed.
>> + */
>> + jump = cs;
>> +
>> + /*
>> + * Take another snapshot of the timestamp register. Take care to clear
>> + * up the top 32bits of CS_GPR(1) as we're using it for other
>> + * operations below.
>> + */
>> + *cs++ = MI_LOAD_REGISTER_IMM(1);
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS)) + 4;
>> + *cs++ = 0;
>> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
>> + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(RENDER_RING_BASE));
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(NOW_TS));
>> +
>> + /*
>> + * Do a diff between the 2 timestamps and store the result back into
>> + * CS_GPR(1).
>> + */
>> + *cs++ = MI_MATH(5);
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(NOW_TS));
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(START_TS));
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_SUB, 0, 0);
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(DELTA_TS), MI_ALU_SRC_ACCU);
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_STORE, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
>> +
>> + /*
>> + * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
>> + * timestamp have rolled over the 32bits) into the predicate register
>> + * to be used for the predicated jump.
>> + */
>> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
>> + *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
>> +
>> + /* Restart from the beginning if we had timestamps roll over. */
>> + *cs++ = (INTEL_GEN(i915) < 8 ?
>> + MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
>> + MI_BATCH_PREDICATE;
>> + *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
>> + *cs++ = 0;
>> +
>> + /*
>> + * Now add the diff between to previous timestamps and add it to :
>> + * (((1 * << 64) - 1) - delay_ns)
>> + *
>> + * When the Carry Flag contains 1 this means the elapsed time is
>> + * longer than the expected delay, and we can exit the wait loop.
>> + */
>> + delay_ticks = 0xffffffffffffffff -
>> + DIV64_U64_ROUND_UP(delay_ns *
>> + RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
>> + 1000000ull);
>> + *cs++ = MI_LOAD_REGISTER_IMM(2);
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET));
>> + *cs++ = lower_32_bits(delay_ticks);
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(DELTA_TARGET)) + 4;
>> + *cs++ = upper_32_bits(delay_ticks);
>> +
>> + *cs++ = MI_MATH(4);
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCA, MI_ALU_SRC_REG(DELTA_TS));
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_LOAD, MI_ALU_SRC_SRCB, MI_ALU_SRC_REG(DELTA_TARGET));
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_ADD, 0, 0);
>> + *cs++ = MI_ALU_OP(MI_ALU_OP_STOREINV, MI_ALU_SRC_REG(JUMP_PREDICATE), MI_ALU_SRC_CF);
>> +
>> + /*
>> + * Transfer the result into the predicate register to be used for the
>> + * predicated jump.
>> + */
>> + *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
>> + *cs++ = i915_mmio_reg_offset(HSW_CS_GPR(JUMP_PREDICATE));
>> + *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1);
>> +
>> + /* Predicate the jump. */
>> + *cs++ = (INTEL_GEN(i915) < 8 ?
>> + MI_BATCH_BUFFER_START : MI_BATCH_BUFFER_START_GEN8) |
>> + MI_BATCH_PREDICATE;
>> + *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
>> + *cs++ = 0;
>> +
>> + /* Restore registers. */
>> + for (i = 0; i < N_CS_GPR; i++) {
>> + cs = restore_register(i915, cs, HSW_CS_GPR(i),
>> + INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
>> + }
>> + cs = restore_register(i915, cs, MI_PREDICATE_RESULT_1,
>> + INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
>> +
>> + /* And return to the ring. */
>> + *cs++ = MI_BATCH_BUFFER_END;
>> +
>> + GEM_BUG_ON((cs - batch) > (PAGE_SIZE / sizeof(*batch)));
>> +
>> + i915_gem_object_flush_map(bo);
>> + i915_gem_object_unpin_map(bo);
>> +
>> + i915->perf.oa.noa_wait = vma;
>> +
>> + return 0;
>> +
>> +err_unpin:
>> + __i915_vma_unpin(vma);
>> +
>> +err_unref:
>> + i915_gem_object_put(bo);
>> +
>> + return ret;
>> +}
> Preferably with the nit above,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
>
Thanks, added the 2 nis locally.
-Lionel
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^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v7 07/12] drm/i915: introduce a mechanism to extend execbuf2
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (5 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 06/12] drm/i915/perf: implement active wait for noa configurations Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 9:32 ` [PATCH v7 08/12] drm/i915: add syncobj timeline support Lionel Landwerlin
` (4 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 32 ++++++++++++++++++-
include/uapi/drm/i915_drm.h | 25 +++++++++++++--
2 files changed, 53 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 1c5dfbfad71b..9887fa9e3ac8 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -23,6 +23,7 @@
#include "i915_gem_clflush.h"
#include "i915_gem_context.h"
#include "i915_trace.h"
+#include "i915_user_extensions.h"
#include "intel_drv.h"
enum {
@@ -271,6 +272,10 @@ struct i915_execbuffer {
*/
int lut_size;
struct hlist_head *buckets; /** ht for relocation handles */
+
+ struct {
+ u64 flags; /** Available extensions parameters */
+ } extensions;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1969,7 +1974,7 @@ static bool i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
return false;
/* Kernel clipping was a DRI1 misfeature */
- if (!(exec->flags & I915_EXEC_FENCE_ARRAY)) {
+ if (!(exec->flags & (I915_EXEC_FENCE_ARRAY | I915_EXEC_EXT))) {
if (exec->num_cliprects || exec->cliprects_ptr)
return false;
}
@@ -2347,6 +2352,27 @@ signal_fence_array(struct i915_execbuffer *eb,
}
}
+static const i915_user_extension_fn execbuf_extensions[] = {
+};
+
+static int
+parse_execbuf2_extensions(struct drm_i915_gem_execbuffer2 *args,
+ struct i915_execbuffer *eb)
+{
+ eb->extensions.flags = 0;
+
+ if (!(args->flags & I915_EXEC_EXT))
+ return 0;
+
+ if (args->num_cliprects != 0)
+ return -EINVAL;
+
+ return i915_user_extensions(u64_to_user_ptr(args->cliprects_ptr),
+ execbuf_extensions,
+ ARRAY_SIZE(execbuf_extensions),
+ eb);
+}
+
static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
@@ -2393,6 +2419,10 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (args->flags & I915_EXEC_IS_PINNED)
eb.batch_flags |= I915_DISPATCH_PINNED;
+ err = parse_execbuf2_extensions(args, &eb);
+ if (err)
+ return err;
+
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
if (!in_fence)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index ea02b168ac3a..7d61f53a1c15 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1014,6 +1014,10 @@ struct drm_i915_gem_exec_fence {
__u32 flags;
};
+enum drm_i915_gem_execbuffer_ext {
+ DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
@@ -1030,8 +1034,14 @@ struct drm_i915_gem_execbuffer2 {
__u32 num_cliprects;
/**
* This is a struct drm_clip_rect *cliprects if I915_EXEC_FENCE_ARRAY
- * is not set. If I915_EXEC_FENCE_ARRAY is set, then this is a
- * struct drm_i915_gem_exec_fence *fences.
+ * & I915_EXEC_EXT are not set.
+ *
+ * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
+ * of struct drm_i915_gem_exec_fence and num_cliprects is the length
+ * of the array.
+ *
+ * If I915_EXEC_EXT is set, then this is a pointer to a single struct
+ * drm_i915_gem_base_execbuffer_ext and num_cliprects is 0.
*/
__u64 cliprects_ptr;
#define I915_EXEC_RING_MASK (0x3f)
@@ -1149,7 +1159,16 @@ struct drm_i915_gem_execbuffer2 {
*/
#define I915_EXEC_FENCE_SUBMIT (1 << 20)
-#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SUBMIT << 1))
+/*
+ * Setting I915_EXEC_EXT implies that drm_i915_gem_execbuffer2.cliprects_ptr
+ * is treated as a pointer to an linked list of i915_user_extension. Each
+ * i915_user_extension node is the base of a larger structure. The list of
+ * supported structures are listed in the drm_i915_gem_execbuffer_ext
+ * enum.
+ */
+#define I915_EXEC_EXT (1 << 21)
+
+#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_EXT<<1))
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
#define i915_execbuffer2_set_context_id(eb2, context) \
--
2.21.0.392.gf8f6787159e
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 08/12] drm/i915: add syncobj timeline support
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (6 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 07/12] drm/i915: introduce a mechanism to extend execbuf2 Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 9:32 ` [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter Lionel Landwerlin
` (3 subsequent siblings)
11 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_ULL (Chris)
v6: Fix issue with already signaled timeline points,
dma_fence_chain_find_seqno() setting fence to NULL (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 297 ++++++++++++++----
drivers/gpu/drm/i915/i915_drv.c | 4 +-
include/uapi/drm/i915_drm.h | 38 +++
3 files changed, 282 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 9887fa9e3ac8..fc5108b8f8ef 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -213,6 +213,13 @@ enum {
* the batchbuffer in trusted mode, otherwise the ioctl is rejected.
*/
+struct i915_eb_fences {
+ struct drm_syncobj *syncobj; /* Use with ptr_mask_bits() */
+ struct dma_fence *dma_fence;
+ u64 value;
+ struct dma_fence_chain *chain_fence;
+};
+
struct i915_execbuffer {
struct drm_i915_private *i915; /** i915 backpointer */
struct drm_file *file; /** per-file lookup tables and limits */
@@ -275,6 +282,7 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
+ struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
} extensions;
};
@@ -2224,67 +2232,207 @@ eb_select_engine(struct i915_execbuffer *eb,
}
static void
-__free_fence_array(struct drm_syncobj **fences, unsigned int n)
+__free_fence_array(struct i915_eb_fences *fences, unsigned int n)
{
- while (n--)
- drm_syncobj_put(ptr_mask_bits(fences[n], 2));
+ while (n--) {
+ drm_syncobj_put(ptr_mask_bits(fences[n].syncobj, 2));
+ dma_fence_put(fences[n].dma_fence);
+ kfree(fences[n].chain_fence);
+ }
kvfree(fences);
}
-static struct drm_syncobj **
-get_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_file *file)
+static struct i915_eb_fences *
+get_timeline_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
+{
+ struct drm_i915_gem_execbuffer_ext_timeline_fences *timeline_fences =
+ &eb->extensions.timeline_fences;
+ struct drm_i915_gem_exec_fence __user *user_fences;
+ struct i915_eb_fences *fences;
+ u64 __user *user_values;
+ u64 num_fences, num_user_fences = timeline_fences->fence_count;
+ unsigned long n;
+ int err;
+
+ /* Check multiplication overflow for access_ok() and kvmalloc_array() */
+ BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
+ if (num_user_fences > min_t(unsigned long,
+ ULONG_MAX / sizeof(*user_fences),
+ SIZE_MAX / sizeof(*fences)))
+ return ERR_PTR(-EINVAL);
+
+ user_fences = u64_to_user_ptr(timeline_fences->handles_ptr);
+ if (!access_ok(user_fences, num_user_fences * sizeof(*user_fences)))
+ return ERR_PTR(-EFAULT);
+
+ user_values = u64_to_user_ptr(timeline_fences->values_ptr);
+ if (!access_ok(user_values, num_user_fences * sizeof(*user_values)))
+ return ERR_PTR(-EFAULT);
+
+ fences = kvmalloc_array(num_user_fences, sizeof(*fences),
+ __GFP_NOWARN | GFP_KERNEL);
+ if (!fences)
+ return ERR_PTR(-ENOMEM);
+
+ BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
+ ~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
+
+ for (n = 0, num_fences = 0; n < timeline_fences->fence_count; n++) {
+ struct drm_i915_gem_exec_fence user_fence;
+ struct drm_syncobj *syncobj;
+ struct dma_fence *fence = NULL;
+ u64 point;
+
+ if (__copy_from_user(&user_fence, user_fences++, sizeof(user_fence))) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ err = -EINVAL;
+ goto err;
+ }
+
+ if (__get_user(point, user_values++)) {
+ err = -EFAULT;
+ goto err;
+ }
+
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
+ if (!syncobj) {
+ DRM_DEBUG("Invalid syncobj handle provided\n");
+ err = -EINVAL;
+ goto err;
+ }
+
+ if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
+ fence = drm_syncobj_fence_get(syncobj);
+ if (!fence) {
+ DRM_DEBUG("Syncobj handle has no fence\n");
+ drm_syncobj_put(syncobj);
+ err = -EINVAL;
+ goto err;
+ }
+
+ err = dma_fence_chain_find_seqno(&fence, point);
+ if (err) {
+ DRM_DEBUG("Syncobj handle missing requested point %llu\n", point);
+ drm_syncobj_put(syncobj);
+ goto err;
+ }
+
+ /* A point might have been signaled already and
+ * garbage collected from the timeline. In this case
+ * just ignore the point and carry on.
+ */
+ if (!fence) {
+ drm_syncobj_put(syncobj);
+ continue;
+ }
+ }
+
+ /*
+ * For timeline syncobjs we need to preallocate chains for
+ * later signaling.
+ */
+ if (point != 0 && user_fence.flags & I915_EXEC_FENCE_SIGNAL) {
+ fences[num_fences].chain_fence =
+ kmalloc(sizeof(*fences[num_fences].chain_fence),
+ GFP_KERNEL);
+ if (!fences[num_fences].chain_fence) {
+ dma_fence_put(fence);
+ drm_syncobj_put(syncobj);
+ err = -ENOMEM;
+ DRM_DEBUG("Unable to alloc chain_fence\n");
+ goto err;
+ }
+ } else {
+ fences[num_fences].chain_fence = NULL;
+ }
+
+ fences[num_fences].syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
+ fences[num_fences].dma_fence = fence;
+ fences[num_fences].value = point;
+ num_fences++;
+ }
+
+ *out_n_fences = num_fences;
+
+ return fences;
+
+err:
+ __free_fence_array(fences, num_fences);
+ return ERR_PTR(err);
+}
+
+static struct i915_eb_fences *
+get_legacy_fence_array(struct i915_execbuffer *eb,
+ int *out_n_fences)
{
- const unsigned long nfences = args->num_cliprects;
+ struct drm_i915_gem_execbuffer2 *args = eb->args;
struct drm_i915_gem_exec_fence __user *user;
- struct drm_syncobj **fences;
+ struct i915_eb_fences *fences;
+ const u32 num_fences = args->num_cliprects;
unsigned long n;
int err;
- if (!(args->flags & I915_EXEC_FENCE_ARRAY))
- return NULL;
+ *out_n_fences = num_fences;
/* Check multiplication overflow for access_ok() and kvmalloc_array() */
BUILD_BUG_ON(sizeof(size_t) > sizeof(unsigned long));
- if (nfences > min_t(unsigned long,
- ULONG_MAX / sizeof(*user),
- SIZE_MAX / sizeof(*fences)))
+ if (*out_n_fences > min_t(unsigned long,
+ ULONG_MAX / sizeof(*user),
+ SIZE_MAX / sizeof(*fences)))
return ERR_PTR(-EINVAL);
user = u64_to_user_ptr(args->cliprects_ptr);
- if (!access_ok(user, nfences * sizeof(*user)))
+ if (!access_ok(user, *out_n_fences * sizeof(*user)))
return ERR_PTR(-EFAULT);
- fences = kvmalloc_array(nfences, sizeof(*fences),
+ fences = kvmalloc_array(*out_n_fences, sizeof(*fences),
__GFP_NOWARN | GFP_KERNEL);
if (!fences)
return ERR_PTR(-ENOMEM);
- for (n = 0; n < nfences; n++) {
- struct drm_i915_gem_exec_fence fence;
+ for (n = 0; n < *out_n_fences; n++) {
+ struct drm_i915_gem_exec_fence user_fence;
struct drm_syncobj *syncobj;
+ struct dma_fence *fence = NULL;
- if (__copy_from_user(&fence, user++, sizeof(fence))) {
+ if (__copy_from_user(&user_fence, user++, sizeof(user_fence))) {
err = -EFAULT;
goto err;
}
- if (fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
+ if (user_fence.flags & __I915_EXEC_FENCE_UNKNOWN_FLAGS) {
err = -EINVAL;
goto err;
}
- syncobj = drm_syncobj_find(file, fence.handle);
+ syncobj = drm_syncobj_find(eb->file, user_fence.handle);
if (!syncobj) {
DRM_DEBUG("Invalid syncobj handle provided\n");
err = -ENOENT;
goto err;
}
+ if (user_fence.flags & I915_EXEC_FENCE_WAIT) {
+ fence = drm_syncobj_fence_get(syncobj);
+ if (!fence) {
+ DRM_DEBUG("Syncobj handle has no fence\n");
+ drm_syncobj_put(syncobj);
+ err = -EINVAL;
+ goto err;
+ }
+ }
+
BUILD_BUG_ON(~(ARCH_KMALLOC_MINALIGN - 1) &
~__I915_EXEC_FENCE_UNKNOWN_FLAGS);
- fences[n] = ptr_pack_bits(syncobj, fence.flags, 2);
+ fences[n].syncobj = ptr_pack_bits(syncobj, user_fence.flags, 2);
+ fences[n].dma_fence = fence;
+ fences[n].value = 0;
+ fences[n].chain_fence = NULL;
}
return fences;
@@ -2294,37 +2442,44 @@ get_fence_array(struct drm_i915_gem_execbuffer2 *args,
return ERR_PTR(err);
}
+static struct i915_eb_fences *
+get_fence_array(struct i915_execbuffer *eb, int *out_n_fences)
+{
+ if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
+ return get_legacy_fence_array(eb, out_n_fences);
+
+ if (eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES))
+ return get_timeline_fence_array(eb, out_n_fences);
+
+ *out_n_fences = 0;
+ return NULL;
+}
+
static void
-put_fence_array(struct drm_i915_gem_execbuffer2 *args,
- struct drm_syncobj **fences)
+put_fence_array(struct i915_eb_fences *fences, int nfences)
{
if (fences)
- __free_fence_array(fences, args->num_cliprects);
+ __free_fence_array(fences, nfences);
}
static int
await_fence_array(struct i915_execbuffer *eb,
- struct drm_syncobj **fences)
+ struct i915_eb_fences *fences,
+ int nfences)
{
- const unsigned int nfences = eb->args->num_cliprects;
unsigned int n;
int err;
for (n = 0; n < nfences; n++) {
struct drm_syncobj *syncobj;
- struct dma_fence *fence;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n].syncobj, &flags, 2);
if (!(flags & I915_EXEC_FENCE_WAIT))
continue;
- fence = drm_syncobj_fence_get(syncobj);
- if (!fence)
- return -EINVAL;
-
- err = i915_request_await_dma_fence(eb->request, fence);
- dma_fence_put(fence);
+ err = i915_request_await_dma_fence(eb->request,
+ fences[n].dma_fence);
if (err < 0)
return err;
}
@@ -2334,9 +2489,9 @@ await_fence_array(struct i915_execbuffer *eb,
static void
signal_fence_array(struct i915_execbuffer *eb,
- struct drm_syncobj **fences)
+ struct i915_eb_fences *fences,
+ int nfences)
{
- const unsigned int nfences = eb->args->num_cliprects;
struct dma_fence * const fence = &eb->request->fence;
unsigned int n;
@@ -2344,15 +2499,46 @@ signal_fence_array(struct i915_execbuffer *eb,
struct drm_syncobj *syncobj;
unsigned int flags;
- syncobj = ptr_unpack_bits(fences[n], &flags, 2);
+ syncobj = ptr_unpack_bits(fences[n].syncobj, &flags, 2);
if (!(flags & I915_EXEC_FENCE_SIGNAL))
continue;
- drm_syncobj_replace_fence(syncobj, fence);
+ if (fences[n].chain_fence) {
+ drm_syncobj_add_point(syncobj, fences[n].chain_fence,
+ fence, fences[n].value);
+ /*
+ * The chain's ownership is transfered to the
+ * timeline.
+ */
+ fences[n].chain_fence = NULL;
+ } else {
+ drm_syncobj_replace_fence(syncobj, fence);
+ }
}
}
+static int parse_timeline_fences(struct i915_user_extension __user *ext, void *data)
+{
+ struct i915_execbuffer *eb = data;
+
+ /* Timeline fences are incompatible with the fence array flag. */
+ if (eb->args->flags & I915_EXEC_FENCE_ARRAY)
+ return -EINVAL;
+
+ if (eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES))
+ return -EINVAL;
+
+ if (copy_from_user(&eb->extensions.timeline_fences, ext,
+ sizeof(eb->extensions.timeline_fences)))
+ return -EFAULT;
+
+ eb->extensions.flags |= BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES);
+
+ return 0;
+}
+
static const i915_user_extension_fn execbuf_extensions[] = {
+ [DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
};
static int
@@ -2377,14 +2563,15 @@ static int
i915_gem_do_execbuffer(struct drm_device *dev,
struct drm_file *file,
struct drm_i915_gem_execbuffer2 *args,
- struct drm_i915_gem_exec_object2 *exec,
- struct drm_syncobj **fences)
+ struct drm_i915_gem_exec_object2 *exec)
{
struct i915_execbuffer eb;
struct dma_fence *in_fence = NULL;
struct dma_fence *exec_fence = NULL;
struct sync_file *out_fence = NULL;
+ struct i915_eb_fences *fences = NULL;
int out_fence_fd = -1;
+ int nfences = 0;
int err;
BUILD_BUG_ON(__EXEC_INTERNAL_FLAGS & ~__I915_EXEC_ILLEGAL_FLAGS);
@@ -2423,10 +2610,16 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (err)
return err;
+ fences = get_fence_array(&eb, &nfences);
+ if (IS_ERR(fences))
+ return PTR_ERR(fences);
+
if (args->flags & I915_EXEC_FENCE_IN) {
in_fence = sync_file_get_fence(lower_32_bits(args->rsvd2));
- if (!in_fence)
- return -EINVAL;
+ if (!in_fence) {
+ err = -EINVAL;
+ goto err_fences;
+ }
}
if (args->flags & I915_EXEC_FENCE_SUBMIT) {
@@ -2584,7 +2777,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
if (fences) {
- err = await_fence_array(&eb, fences);
+ err = await_fence_array(&eb, fences, nfences);
if (err)
goto err_request;
}
@@ -2613,7 +2806,7 @@ i915_gem_do_execbuffer(struct drm_device *dev,
i915_request_add(eb.request);
if (fences)
- signal_fence_array(&eb, fences);
+ signal_fence_array(&eb, fences, nfences);
if (out_fence) {
if (err == 0) {
@@ -2648,6 +2841,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
dma_fence_put(exec_fence);
err_in_fence:
dma_fence_put(in_fence);
+err_fences:
+ put_fence_array(fences, nfences);
return err;
}
@@ -2741,7 +2936,7 @@ i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data,
exec2_list[i].flags = 0;
}
- err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list, NULL);
+ err = i915_gem_do_execbuffer(dev, file, &exec2, exec2_list);
if (exec2.flags & __EXEC_HAS_RELOC) {
struct drm_i915_gem_exec_object __user *user_exec_list =
u64_to_user_ptr(args->buffers_ptr);
@@ -2772,7 +2967,6 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
{
struct drm_i915_gem_execbuffer2 *args = data;
struct drm_i915_gem_exec_object2 *exec2_list;
- struct drm_syncobj **fences = NULL;
const size_t count = args->buffer_count;
int err;
@@ -2800,15 +2994,7 @@ i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data,
return -EFAULT;
}
- if (args->flags & I915_EXEC_FENCE_ARRAY) {
- fences = get_fence_array(args, file);
- if (IS_ERR(fences)) {
- kvfree(exec2_list);
- return PTR_ERR(fences);
- }
- }
-
- err = i915_gem_do_execbuffer(dev, file, args, exec2_list, fences);
+ err = i915_gem_do_execbuffer(dev, file, args, exec2_list);
/*
* Now that we have begun execution of the batchbuffer, we ignore
@@ -2848,7 +3034,6 @@ end:;
}
args->flags &= ~__I915_EXEC_UNKNOWN_FLAGS;
- put_fence_array(args, fences);
kvfree(exec2_list);
return err;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index f70ad7adaea5..94062188c523 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -457,6 +457,7 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_HAS_EXEC_BATCH_FIRST:
case I915_PARAM_HAS_EXEC_FENCE_ARRAY:
case I915_PARAM_HAS_EXEC_SUBMIT_FENCE:
+ case I915_PARAM_HAS_EXEC_TIMELINE_FENCES:
/* For the time being all of these are always true;
* if some supported hardware does not have one of these
* features this value needs to be provided from
@@ -3220,7 +3221,8 @@ static struct drm_driver driver = {
*/
.driver_features =
DRIVER_GEM |
- DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ,
+ DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
+ DRIVER_SYNCOBJ_TIMELINE,
.release = i915_driver_release,
.open = i915_driver_open,
.lastclose = i915_driver_lastclose,
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 7d61f53a1c15..e5ac1174c01e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -618,6 +618,12 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_PERF_REVISION 54
+/* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
+ * timeline syncobj through drm_i915_gem_execbuf_ext_timeline_fences. See
+ * I915_EXEC_EXT.
+ */
+#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1015,9 +1021,41 @@ struct drm_i915_gem_exec_fence {
};
enum drm_i915_gem_execbuffer_ext {
+ /**
+ * See drm_i915_gem_execbuf_ext_timeline_fences.
+ */
+ DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES = 0,
+
DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
};
+/**
+ * This structure describes an array of drm_syncobj and associated points for
+ * timeline variants of drm_syncobj. It is invalid to append this structure to
+ * the execbuf if I915_EXEC_FENCE_ARRAY is set.
+ */
+struct drm_i915_gem_execbuffer_ext_timeline_fences {
+ struct i915_user_extension base;
+
+ /**
+ * Number of element in the handles_ptr & value_ptr arrays.
+ */
+ __u64 fence_count;
+
+ /**
+ * Pointer to an array of struct drm_i915_gem_exec_fence of length
+ * fence_count.
+ */
+ __u64 handles_ptr;
+
+ /**
+ * Pointer to an array of u64 values of length fence_count. Values
+ * must be 0 for a binary drm_syncobj. A Value of 0 for a timeline
+ * drm_syncobj is invalid as it turns a drm_syncobj into a binary one.
+ */
+ __u64 values_ptr;
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
--
2.21.0.392.gf8f6787159e
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (7 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 08/12] drm/i915: add syncobj timeline support Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 9:58 ` Chris Wilson
2019-07-09 9:32 ` [PATCH v7 10/12] drm/i915/perf: allow holding preemption on filtered ctx Lionel Landwerlin
` (2 subsequent siblings)
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process making the execbuf with this flag to
also own the perf fd at the time of execbuf.
v2: Add a emit_oa_config() vfunc in the intel_engine_cs (Chris)
Move oa_config vma to active (Chris)
v3: Don't drop the lock for engine lookup (Chris)
Move OA config vma to active before writing the ringbuffer (Chris)
v4: Reuse i915_user_extension_fn
Serialize requests with OA config updates
v5: Check that the chained extension is only present once (Chris)
Unpin oa_vma in main path (Chris)
v6: Use BIT_ULL (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 124 +++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_ringbuffer.c | 4 +-
drivers/gpu/drm/i915/i915_drv.c | 4 +
drivers/gpu/drm/i915/i915_drv.h | 8 +-
drivers/gpu/drm/i915/i915_perf.c | 25 ++--
include/uapi/drm/i915_drm.h | 37 ++++++
9 files changed, 197 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index fc5108b8f8ef..af62441ae3f1 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -283,7 +283,12 @@ struct i915_execbuffer {
struct {
u64 flags; /** Available extensions parameters */
struct drm_i915_gem_execbuffer_ext_timeline_fences timeline_fences;
+ struct drm_i915_gem_execbuffer_ext_perf perf_config;
} extensions;
+
+ struct i915_oa_config *oa_config; /** HW configuration for OA, NULL is not needed. */
+ struct drm_i915_gem_object *oa_bo;
+ struct i915_vma *oa_vma;
};
#define exec_entry(EB, VMA) (&(EB)->exec[(VMA)->exec_flags - (EB)->flags])
@@ -1210,6 +1215,21 @@ static int reloc_move_to_gpu(struct i915_request *rq, struct i915_vma *vma)
return err;
}
+
+static int
+get_execbuf_oa_config(struct i915_execbuffer *eb)
+{
+ eb->oa_config = NULL;
+ eb->oa_vma = NULL;
+ eb->oa_bo = NULL;
+
+ if ((eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF)) == 0)
+ return 0;
+
+ return i915_perf_get_oa_config(eb->i915, eb->extensions.perf_config.oa_config,
+ &eb->oa_config, &eb->oa_bo);
+}
+
static int __reloc_gpu_alloc(struct i915_execbuffer *eb,
struct i915_vma *vma,
unsigned int len)
@@ -2072,6 +2092,40 @@ add_to_client(struct i915_request *rq, struct drm_file *file)
list_add_tail(&rq->client_link, &rq->file_priv->mm.request_list);
}
+static int eb_oa_config(struct i915_execbuffer *eb)
+{
+ int err;
+
+ if (!eb->oa_config)
+ return 0;
+
+ err = i915_active_request_set(&eb->engine->last_oa_config,
+ eb->request);
+ if (err)
+ return err;
+
+ /*
+ * If the config hasn't changed, skip reconfiguring the HW (this is
+ * subject to a delay we want to avoid has much as possible).
+ */
+ if (eb->oa_config == eb->i915->perf.oa.exclusive_stream->oa_config)
+ return 0;
+
+ err = i915_vma_move_to_active(eb->oa_vma, eb->request, 0);
+ if (err)
+ return err;
+
+ err = eb->engine->emit_bb_start(eb->request,
+ eb->oa_vma->node.start,
+ 0, I915_DISPATCH_SECURE);
+ if (err)
+ return err;
+
+ swap(eb->oa_config, eb->i915->perf.oa.exclusive_stream->oa_config);
+
+ return 0;
+}
+
static int eb_submit(struct i915_execbuffer *eb)
{
int err;
@@ -2098,6 +2152,10 @@ static int eb_submit(struct i915_execbuffer *eb)
return err;
}
+ err = eb_oa_config(eb);
+ if (err)
+ return err;
+
err = eb->engine->emit_bb_start(eb->request,
eb->batch->node.start +
eb->batch_start_offset,
@@ -2537,8 +2595,25 @@ static int parse_timeline_fences(struct i915_user_extension __user *ext, void *d
return 0;
}
+static int parse_perf_config(struct i915_user_extension __user *ext, void *data)
+{
+ struct i915_execbuffer *eb = data;
+
+ if (eb->extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF))
+ return -EINVAL;
+
+ if (copy_from_user(&eb->extensions.perf_config, ext,
+ sizeof(eb->extensions.perf_config)))
+ return -EFAULT;
+
+ eb->extensions.flags |= BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF);
+
+ return 0;
+}
+
static const i915_user_extension_fn execbuf_extensions[] = {
[DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES] = parse_timeline_fences,
+ [DRM_I915_GEM_EXECBUFFER_EXT_PERF] = parse_perf_config,
};
static int
@@ -2643,9 +2718,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
}
+ err = get_execbuf_oa_config(&eb);
+ if (err)
+ goto err_oa_config;
+
err = eb_create(&eb);
if (err)
- goto err_out_fence;
+ goto err_oa_config;
GEM_BUG_ON(!eb.lut_size);
@@ -2670,6 +2749,27 @@ i915_gem_do_execbuffer(struct drm_device *dev,
if (unlikely(err))
goto err_unlock;
+ if (eb.extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF)) {
+ struct file *perf_file;
+
+ if (!intel_engine_has_oa(eb.engine)) {
+ err = -ENODEV;
+ goto err_engine;
+ }
+
+ perf_file = fget(eb.extensions.perf_config.perf_fd);
+ if (!perf_file)
+ goto err_engine;
+
+ if (perf_file->private_data != eb.i915->perf.oa.exclusive_stream)
+ err = -EINVAL;
+
+ fput(perf_file);
+
+ if (unlikely(err))
+ goto err_engine;
+ }
+
err = eb_wait_for_ring(&eb); /* may temporarily drop struct_mutex */
if (unlikely(err))
goto err_engine;
@@ -2790,6 +2890,20 @@ i915_gem_do_execbuffer(struct drm_device *dev,
}
}
+ if (eb.extensions.flags & BIT_ULL(DRM_I915_GEM_EXECBUFFER_EXT_PERF)) {
+ eb.oa_vma = i915_vma_instance(eb.oa_bo,
+ &eb.engine->i915->ggtt.vm, NULL);
+ if (unlikely(IS_ERR(eb.oa_vma))) {
+ err = PTR_ERR(eb.oa_vma);
+ eb.oa_vma = NULL;
+ goto err_request;
+ }
+
+ err = i915_vma_pin(eb.oa_vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ goto err_request;
+ }
+
/*
* Whilst this request exists, batch_obj will be on the
* active_list, and so will hold the active reference. Only when this
@@ -2834,7 +2948,13 @@ i915_gem_do_execbuffer(struct drm_device *dev,
i915_gem_context_put(eb.gem_context);
err_destroy:
eb_destroy(&eb);
-err_out_fence:
+err_oa_config:
+ if (eb.oa_config) {
+ i915_gem_object_put(eb.oa_bo);
+ i915_oa_config_put(eb.oa_config);
+ }
+ if (eb.oa_vma)
+ i915_vma_unpin(eb.oa_vma);
if (out_fence_fd != -1)
put_unused_fd(out_fence_fd);
err_exec_fence:
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index df5932f5f578..25ef0107d7f5 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -864,6 +864,8 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
engine->set_default_submission(engine);
+ INIT_ACTIVE_REQUEST(&engine->last_oa_config);
+
return 0;
err_unpin:
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 7e056114344e..39da40937e7f 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -363,6 +363,8 @@ struct intel_engine_cs {
struct i915_wa_list wa_list;
struct i915_wa_list whitelist;
+ struct i915_active_request last_oa_config;
+
u32 irq_keep_mask; /* always keep these interrupts */
u32 irq_enable_mask; /* bitmask to enable ring interrupt */
void (*irq_enable)(struct intel_engine_cs *engine);
@@ -446,6 +448,7 @@ struct intel_engine_cs {
#define I915_ENGINE_HAS_SEMAPHORES BIT(3)
#define I915_ENGINE_NEEDS_BREADCRUMB_TASKLET BIT(4)
#define I915_ENGINE_IS_VIRTUAL BIT(5)
+#define I915_ENGINE_HAS_OA BIT(6)
unsigned int flags;
/*
@@ -541,6 +544,12 @@ intel_engine_is_virtual(const struct intel_engine_cs *engine)
return engine->flags & I915_ENGINE_IS_VIRTUAL;
}
+static inline bool
+intel_engine_has_oa(const struct intel_engine_cs *engine)
+{
+ return engine->flags & I915_ENGINE_HAS_OA;
+}
+
#define instdone_slice_mask(dev_priv__) \
(IS_GEN(dev_priv__, 7) ? \
1 : RUNTIME_INFO(dev_priv__)->sseu.slice_mask)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 87d263f92cf4..30782af8f4bc 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2794,6 +2794,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
engine->init_context = gen8_init_rcs_context;
engine->emit_flush = gen8_emit_flush_render;
engine->emit_fini_breadcrumb = gen8_emit_fini_breadcrumb_rcs;
+ engine->flags |= I915_ENGINE_HAS_OA;
}
return 0;
diff --git a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
index a98652e4055c..0d1334ab447b 100644
--- a/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/gt/intel_ringbuffer.c
@@ -2205,8 +2205,10 @@ static void setup_rcs(struct intel_engine_cs *engine)
engine->irq_enable_mask = I915_USER_INTERRUPT;
}
- if (IS_HASWELL(i915))
+ if (IS_HASWELL(i915)) {
engine->emit_bb_start = hsw_emit_bb_start;
+ engine->flags |= I915_ENGINE_HAS_OA;
+ }
engine->resume = rcs_resume;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 94062188c523..f767753ccf51 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -487,6 +487,10 @@ static int i915_getparam_ioctl(struct drm_device *dev, void *data,
case I915_PARAM_PERF_REVISION:
value = i915_perf_ioctl_version();
break;
+ case I915_PARAM_HAS_EXEC_PERF_CONFIG:
+ /* Obviously requires perf support. */
+ value = dev_priv->perf.initialized;
+ break;
default:
DRM_DEBUG("Unknown parameter %d\n", param->param);
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b3c6dd72c7a1..e898a3593b8a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1116,7 +1116,7 @@ struct i915_oa_config {
struct list_head vma_link;
- atomic_t ref_count;
+ struct kref ref;
};
struct i915_perf_stream;
@@ -2614,6 +2614,12 @@ int i915_perf_get_oa_config(struct drm_i915_private *i915,
int metrics_set,
struct i915_oa_config **out_config,
struct drm_i915_gem_object **out_obj);
+void i915_oa_config_release(struct kref *ref);
+
+static inline void i915_oa_config_put(struct i915_oa_config *oa_config)
+{
+ kref_put(&oa_config->ref, i915_oa_config_release);
+}
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 18a8f38839ba..decbec43d66d 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -367,10 +367,9 @@ struct perf_open_properties {
int oa_period_exponent;
};
-static void put_oa_config(struct i915_oa_config *oa_config)
+void i915_oa_config_release(struct kref *ref)
{
- if (!atomic_dec_and_test(&oa_config->ref_count))
- return;
+ struct i915_oa_config *oa_config = container_of(ref, typeof(*oa_config), ref);
if (oa_config->obj) {
struct drm_i915_private *i915 = oa_config->i915;
@@ -488,7 +487,7 @@ int i915_perf_get_oa_config(struct drm_i915_private *i915,
}
if (out_config) {
- atomic_inc(&oa_config->ref_count);
+ kref_get(&oa_config->ref);
*out_config = oa_config;
}
@@ -510,7 +509,7 @@ int i915_perf_get_oa_config(struct drm_i915_private *i915,
mutex_unlock(&i915->perf.metrics_lock);
if (ret && out_config) {
- put_oa_config(oa_config);
+ i915_oa_config_put(oa_config);
*out_config = NULL;
}
@@ -1484,7 +1483,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
if (stream->ctx)
oa_put_render_ctx_id(stream);
- put_oa_config(stream->oa_config);
+ i915_oa_config_put(stream->oa_config);
if (dev_priv->perf.oa.spurious_report_rs.missed) {
DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n",
@@ -2481,7 +2480,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
free_oa_buffer(dev_priv);
err_oa_buf_alloc:
- put_oa_config(stream->oa_config);
+ i915_oa_config_put(stream->oa_config);
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref);
@@ -2491,7 +2490,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
mutex_unlock(&dev_priv->drm.struct_mutex);
err_noa_wait_alloc:
- put_oa_config(stream->oa_config);
+ i915_oa_config_put(stream->oa_config);
err_config:
if (stream->ctx)
@@ -3306,7 +3305,7 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
goto sysfs_error;
dev_priv->perf.oa.test_config.i915 = dev_priv;
- atomic_set(&dev_priv->perf.oa.test_config.ref_count, 1);
+ kref_init(&dev_priv->perf.oa.test_config.ref);
goto exit;
@@ -3563,7 +3562,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
}
oa_config->i915 = dev_priv;
- atomic_set(&oa_config->ref_count, 1);
+ kref_init(&oa_config->ref);
if (!uuid_is_valid(args->uuid)) {
DRM_DEBUG("Invalid uuid format for OA config\n");
@@ -3662,7 +3661,7 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
sysfs_err:
mutex_unlock(&dev_priv->perf.metrics_lock);
reg_err:
- put_oa_config(oa_config);
+ i915_oa_config_put(oa_config);
DRM_DEBUG("Failed to add new OA config\n");
return err;
}
@@ -3718,7 +3717,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
DRM_DEBUG("Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
- put_oa_config(oa_config);
+ i915_oa_config_put(oa_config);
return 0;
@@ -3888,7 +3887,7 @@ static int destroy_config(int id, void *p, void *data)
{
struct i915_oa_config *oa_config = p;
- put_oa_config(oa_config);
+ i915_oa_config_put(oa_config);
return 0;
}
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e5ac1174c01e..e6f7f738490e 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -624,6 +624,16 @@ typedef struct drm_i915_irq_wait {
*/
#define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
+/*
+ * Request an i915/perf performance configuration change before running the
+ * commands given in an execbuf.
+ *
+ * Performance configuration ID and the file descriptor of the i915 perf
+ * stream are given through drm_i915_gem_execbuffer_ext_perf. See
+ * I915_EXEC_EXT.
+ */
+#define I915_PARAM_HAS_EXEC_PERF_CONFIG 56
+
/* Must be kept compact -- no holes and well documented */
typedef struct drm_i915_getparam {
@@ -1026,6 +1036,12 @@ enum drm_i915_gem_execbuffer_ext {
*/
DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES = 0,
+ /**
+ * This identifier is associated with
+ * drm_i915_gem_execbuffer_perf_ext.
+ */
+ DRM_I915_GEM_EXECBUFFER_EXT_PERF,
+
DRM_I915_GEM_EXECBUFFER_EXT_MAX /* non-ABI */
};
@@ -1056,6 +1072,27 @@ struct drm_i915_gem_execbuffer_ext_timeline_fences {
__u64 values_ptr;
};
+struct drm_i915_gem_execbuffer_ext_perf {
+ struct i915_user_extension base;
+
+ /**
+ * Performance file descriptor returned by DRM_IOCTL_I915_PERF_OPEN.
+ * This is used to identify that the application
+ */
+ __s32 perf_fd;
+
+ /**
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 pad;
+
+ /**
+ * OA configuration ID to switch to before executing the commands
+ * associated to the execbuf.
+ */
+ __u64 oa_config;
+};
+
struct drm_i915_gem_execbuffer2 {
/**
* List of gem_exec_object2 structs
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter
2019-07-09 9:32 ` [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter Lionel Landwerlin
@ 2019-07-09 9:58 ` Chris Wilson
2019-07-09 10:59 ` Lionel Landwerlin
0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-07-09 9:58 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-07-09 10:32:05)
> +static int eb_oa_config(struct i915_execbuffer *eb)
> +{
> + int err;
> +
> + if (!eb->oa_config)
> + return 0;
> +
> + err = i915_active_request_set(&eb->engine->last_oa_config,
> + eb->request);
This is outside of the eb->request->timeline->mutex and needs a mutex.
> + if (err)
> + return err;
> +
> + /*
> + * If the config hasn't changed, skip reconfiguring the HW (this is
> + * subject to a delay we want to avoid has much as possible).
> + */
> + if (eb->oa_config == eb->i915->perf.oa.exclusive_stream->oa_config)
> + return 0;
> +
> + err = i915_vma_move_to_active(eb->oa_vma, eb->request, 0);
> + if (err)
> + return err;
> +
> + err = eb->engine->emit_bb_start(eb->request,
> + eb->oa_vma->node.start,
> + 0, I915_DISPATCH_SECURE);
> + if (err)
> + return err;
> +
> + swap(eb->oa_config, eb->i915->perf.oa.exclusive_stream->oa_config);
As does this this. So which mutex is to guard
i915->perf.oa.exclusive_stream->oa_config ?
Is i915->perf.metrics_locks sensible to guard [data within] this function?
-Chris
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter
2019-07-09 9:58 ` Chris Wilson
@ 2019-07-09 10:59 ` Lionel Landwerlin
2019-07-09 11:06 ` Chris Wilson
0 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 10:59 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 09/07/2019 12:58, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-07-09 10:32:05)
>> +static int eb_oa_config(struct i915_execbuffer *eb)
>> +{
>> + int err;
>> +
>> + if (!eb->oa_config)
>> + return 0;
>> +
>> + err = i915_active_request_set(&eb->engine->last_oa_config,
>> + eb->request);
> This is outside of the eb->request->timeline->mutex and needs a mutex.
Can I do this inside i915_request_add() when rq->flags &
I915_REQUEST_FLAGS_PERF ?
>
>> + if (err)
>> + return err;
>> +
>> + /*
>> + * If the config hasn't changed, skip reconfiguring the HW (this is
>> + * subject to a delay we want to avoid has much as possible).
>> + */
>> + if (eb->oa_config == eb->i915->perf.oa.exclusive_stream->oa_config)
>> + return 0;
>> +
>> + err = i915_vma_move_to_active(eb->oa_vma, eb->request, 0);
>> + if (err)
>> + return err;
>> +
>> + err = eb->engine->emit_bb_start(eb->request,
>> + eb->oa_vma->node.start,
>> + 0, I915_DISPATCH_SECURE);
>> + if (err)
>> + return err;
>> +
>> + swap(eb->oa_config, eb->i915->perf.oa.exclusive_stream->oa_config);
> As does this this. So which mutex is to guard
> i915->perf.oa.exclusive_stream->oa_config ?
>
> Is i915->perf.metrics_locks sensible to guard [data within] this function?
> -Chris
>
Oh sorry, I missed that again...
At the moment it would be i915->drm.struct_mutex but this could be a bit
finer on the engine.
-Lionel
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter
2019-07-09 10:59 ` Lionel Landwerlin
@ 2019-07-09 11:06 ` Chris Wilson
2019-07-09 11:10 ` Lionel Landwerlin
0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-07-09 11:06 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-07-09 11:59:31)
> On 09/07/2019 12:58, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-07-09 10:32:05)
> >> +static int eb_oa_config(struct i915_execbuffer *eb)
> >> +{
> >> + int err;
> >> +
> >> + if (!eb->oa_config)
> >> + return 0;
> >> +
> >> + err = i915_active_request_set(&eb->engine->last_oa_config,
> >> + eb->request);
> > This is outside of the eb->request->timeline->mutex and needs a mutex.
>
>
> Can I do this inside i915_request_add() when rq->flags &
> I915_REQUEST_FLAGS_PERF ?
No. Because it is still being accessed without the appropriate locks.
(Multiple callers trying to modify eb->engine->last_oa_config all using
their own timeline->mutex.) You already need a lock to serialise
oa_config, that seems adequate to cover last_oa_config as well.
Oh, don't call the flag _PERF but something like FLAGS_NOPREEMPT so
it indicates the mechanism. Come to think of this don't include _FLAGS_
as we don't need to disambiguate yet :)
-Chris
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter
2019-07-09 11:06 ` Chris Wilson
@ 2019-07-09 11:10 ` Lionel Landwerlin
0 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 11:10 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 09/07/2019 14:06, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-07-09 11:59:31)
>> On 09/07/2019 12:58, Chris Wilson wrote:
>>> Quoting Lionel Landwerlin (2019-07-09 10:32:05)
>>>> +static int eb_oa_config(struct i915_execbuffer *eb)
>>>> +{
>>>> + int err;
>>>> +
>>>> + if (!eb->oa_config)
>>>> + return 0;
>>>> +
>>>> + err = i915_active_request_set(&eb->engine->last_oa_config,
>>>> + eb->request);
>>> This is outside of the eb->request->timeline->mutex and needs a mutex.
>>
>> Can I do this inside i915_request_add() when rq->flags &
>> I915_REQUEST_FLAGS_PERF ?
> No. Because it is still being accessed without the appropriate locks.
> (Multiple callers trying to modify eb->engine->last_oa_config all using
> their own timeline->mutex.) You already need a lock to serialise
> oa_config, that seems adequate to cover last_oa_config as well.
>
> Oh, don't call the flag _PERF but something like FLAGS_NOPREEMPT so
> it indicates the mechanism. Come to think of this don't include _FLAGS_
> as we don't need to disambiguate yet :)
> -Chris
>
Aligns perfectly ;)
-Lionel
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^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v7 10/12] drm/i915/perf: allow holding preemption on filtered ctx
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (8 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 09/12] drm/i915: add a new perf configuration execbuf parameter Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 10:00 ` Chris Wilson
2019-07-09 9:32 ` [PATCH v7 11/12] drm/i915/perf: execute OA configuration from command stream Lionel Landwerlin
2019-07-09 9:32 ` [PATCH v7 12/12] drm/i915: add support for perf configuration queries Lionel Landwerlin
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of command buffer concept meant that
queries' duration could span multiple command buffers.
With that restriction gone in Vulkan, we would like to simplify
measuring performance just by measuring the deltas between the counter
snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
more complex scheme we currently have in the GL driver, using 2
MI_RECORD_PERF_COUNT commands and doing some post processing on the
stream of OA reports, coming from the global OA buffer, to remove any
unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
Disabling preemption only apply to a single context with which want to
query performance counters for and is considered a privileged
operation, by default protected by CAP_SYS_ADMIN. It is possible to
enable it for a normal user by disabling the paranoid stream setting.
v2: Store preemption setting in intel_context (Chris)
v3: Use priorities to avoid preemption rather than the HW mechanism
v4: Just modify the port priority reporting function
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c | 8 +++++
drivers/gpu/drm/i915/gt/intel_lrc.c | 7 ++++-
drivers/gpu/drm/i915/i915_drv.h | 8 +++++
drivers/gpu/drm/i915/i915_perf.c | 31 +++++++++++++++++--
drivers/gpu/drm/i915/i915_priolist_types.h | 7 +++++
drivers/gpu/drm/i915/i915_request.c | 4 +--
drivers/gpu/drm/i915/i915_request.h | 14 ++++++++-
drivers/gpu/drm/i915/intel_guc_submission.c | 10 +++++-
drivers/gpu/drm/i915/intel_pm.c | 5 +--
include/uapi/drm/i915_drm.h | 11 +++++++
10 files changed, 95 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index af62441ae3f1..76453043781c 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2104,6 +2104,14 @@ static int eb_oa_config(struct i915_execbuffer *eb)
if (err)
return err;
+ /*
+ * If the perf stream was opened with hold preemption, flag the
+ * request properly so that the priority of the request is bumped once
+ * it reaches the execlist ports.
+ */
+ if (eb->i915->perf.oa.exclusive_stream->hold_preemption)
+ eb->request->flags |= I915_REQUEST_FLAGS_PERF;
+
/*
* If the config hasn't changed, skip reconfiguring the HW (this is
* subject to a delay we want to avoid has much as possible).
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 30782af8f4bc..6c35d33f9647 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -256,7 +256,12 @@ static inline int rq_prio(const struct i915_request *rq)
static int effective_prio(const struct i915_request *rq)
{
- int prio = rq_prio(rq);
+ int prio;
+
+ if (i915_request_has_perf(rq))
+ prio = I915_USER_PRIORITY(I915_PRIORITY_PERF);
+ else
+ prio = rq_prio(rq);
/*
* On unwinding the active request, we give it a priority bump
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e898a3593b8a..dc0e4982c672 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1232,6 +1232,14 @@ struct i915_perf_stream {
*/
bool enabled;
+ /**
+ * @hold_preemption: Whether preemption is put on hold for command
+ * submissions done on the @ctx. This is useful for some drivers that
+ * cannot easily post process the OA buffer context to subtract delta
+ * of performance counters not associated with @ctx.
+ */
+ bool hold_preemption;
+
/**
* @ops: The callbacks providing the implementation of this specific
* type of configured stream.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index decbec43d66d..1e5011d4cdae 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -344,6 +344,8 @@ static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* struct perf_open_properties - for validated properties given to open a stream
* @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
* @single_context: Whether a single or all gpu contexts should be monitored
+ * @hold_preemption: Whether the preemption is disabled for the filtered
+ * context
* @ctx_handle: A gem ctx handle for use with @single_context
* @metrics_set: An ID for an OA unit metric set advertised via sysfs
* @oa_format: An OA unit HW report format
@@ -358,6 +360,7 @@ struct perf_open_properties {
u32 sample_flags;
u64 single_context:1;
+ u64 hold_preemption:1;
u64 ctx_handle;
/* OA sampling state */
@@ -2401,6 +2404,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
stream->sample_flags |= SAMPLE_OA_REPORT;
stream->sample_size += format_size;
+ stream->hold_preemption = props->hold_preemption;
+
dev_priv->perf.oa.oa_buffer.format_size = format_size;
if (WARN_ON(dev_priv->perf.oa.oa_buffer.format_size == 0))
return -EINVAL;
@@ -2942,6 +2947,15 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
}
}
+ if (props->hold_preemption) {
+ if (!props->single_context) {
+ DRM_DEBUG("preemption disable with no context\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ privileged_op = true;
+ }
+
/*
* On Haswell the OA unit supports clock gating off for a specific
* context and in this mode there's no visibility of metrics for the
@@ -2956,8 +2970,9 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
* MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
* enable the OA unit by default.
*/
- if (IS_HASWELL(dev_priv) && specific_ctx)
+ if (IS_HASWELL(dev_priv) && specific_ctx && !props->hold_preemption) {
privileged_op = false;
+ }
/* Similar to perf's kernel.perf_paranoid_cpu sysctl option
* we check a dev.i915.perf_stream_paranoid sysctl option
@@ -2966,7 +2981,7 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
*/
if (privileged_op &&
i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) {
- DRM_DEBUG("Insufficient privileges to open system-wide i915 perf stream\n");
+ DRM_DEBUG("Insufficient privileges to open i915 perf stream\n");
ret = -EACCES;
goto err_ctx;
}
@@ -3163,6 +3178,9 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
props->oa_periodic = true;
props->oa_period_exponent = value;
break;
+ case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
+ props->hold_preemption = !!value;
+ break;
case DRM_I915_PERF_PROP_MAX:
MISSING_CASE(id);
return -EINVAL;
@@ -3918,5 +3936,12 @@ void i915_perf_fini(struct drm_i915_private *dev_priv)
*/
int i915_perf_ioctl_version(void)
{
- return 1;
+ /* 1: initial version
+ *
+ * 2: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
+ * preemption on a particular context so that performance data is
+ * accessible from a delta of MI_RPC reports without looking at the
+ * OA buffer.
+ */
+ return 2;
}
diff --git a/drivers/gpu/drm/i915/i915_priolist_types.h b/drivers/gpu/drm/i915/i915_priolist_types.h
index 49709de69875..bb9d1e1fb94a 100644
--- a/drivers/gpu/drm/i915/i915_priolist_types.h
+++ b/drivers/gpu/drm/i915/i915_priolist_types.h
@@ -17,6 +17,13 @@ enum {
I915_PRIORITY_NORMAL = I915_CONTEXT_DEFAULT_PRIORITY,
I915_PRIORITY_MAX = I915_CONTEXT_MAX_USER_PRIORITY + 1,
+ /* Requests containing performance queries must not be preempted by
+ * another context. They get scheduled with their default priority and
+ * once they reach the execlist ports we bump them to
+ * I915_PRIORITY_PERF so that they stick to the HW until they finish.
+ */
+ I915_PRIORITY_PERF,
+
I915_PRIORITY_INVALID = INT_MIN
};
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index 5ff87c4a0cd5..222c9c56e9de 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -292,7 +292,7 @@ static bool i915_request_retire(struct i915_request *rq)
dma_fence_signal_locked(&rq->fence);
if (test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &rq->fence.flags))
i915_request_cancel_breadcrumb(rq);
- if (rq->waitboost) {
+ if (i915_request_has_waitboost(rq)) {
GEM_BUG_ON(!atomic_read(&rq->i915->gt_pm.rps.num_waiters));
atomic_dec(&rq->i915->gt_pm.rps.num_waiters);
}
@@ -684,7 +684,7 @@ __i915_request_create(struct intel_context *ce, gfp_t gfp)
rq->file_priv = NULL;
rq->batch = NULL;
rq->capture_list = NULL;
- rq->waitboost = false;
+ rq->flags = 0;
rq->execution_mask = ALL_ENGINES;
INIT_LIST_HEAD(&rq->active_list);
diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h
index b58ceef92e20..3bc2a3b8b9ca 100644
--- a/drivers/gpu/drm/i915/i915_request.h
+++ b/drivers/gpu/drm/i915/i915_request.h
@@ -216,7 +216,9 @@ struct i915_request {
/** Time at which this request was emitted, in jiffies. */
unsigned long emitted_jiffies;
- bool waitboost;
+#define I915_REQUEST_FLAGS_WAITBOOST BIT(0)
+#define I915_REQUEST_FLAGS_PERF BIT(1)
+ u32 flags;
/** timeline->request entry for this request */
struct list_head link;
@@ -430,6 +432,16 @@ static inline void i915_request_mark_complete(struct i915_request *rq)
rq->hwsp_seqno = (u32 *)&rq->fence.seqno; /* decouple from HWSP */
}
+static inline bool i915_request_has_waitboost(const struct i915_request *rq)
+{
+ return rq->flags & I915_REQUEST_FLAGS_WAITBOOST;
+}
+
+static inline bool i915_request_has_perf(const struct i915_request *rq)
+{
+ return rq->flags & I915_REQUEST_FLAGS_PERF;
+}
+
bool i915_retire_requests(struct drm_i915_private *i915);
#endif /* I915_REQUEST_H */
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 12c22359fdac..48e7ae3d67a2 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -707,6 +707,14 @@ static inline int rq_prio(const struct i915_request *rq)
return rq->sched.attr.priority | __NO_PREEMPTION;
}
+static inline int effective_prio(const struct i915_request *rq)
+{
+ if (i915_request_has_perf(rq))
+ return I915_USER_PRIORITY(I915_PRIORITY_PERF) | __NO_PREEMPTION;
+
+ return rq_prio(rq);
+}
+
static struct i915_request *schedule_in(struct i915_request *rq, int idx)
{
trace_i915_request_in(rq, idx);
@@ -747,7 +755,7 @@ static void __guc_dequeue(struct intel_engine_cs *engine)
&engine->i915->guc.preempt_work[engine->id];
int prio = execlists->queue_priority_hint;
- if (i915_scheduler_need_preempt(prio, rq_prio(last))) {
+ if (i915_scheduler_need_preempt(prio, effective_prio(last))) {
intel_write_status_page(engine,
I915_GEM_HWS_PREEMPT,
GUC_PREEMPT_INPROGRESS);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 87244d8215a7..1489e401129d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6876,9 +6876,10 @@ void gen6_rps_boost(struct i915_request *rq)
/* Serializes with i915_request_retire() */
boost = false;
spin_lock_irqsave(&rq->lock, flags);
- if (!rq->waitboost && !dma_fence_is_signaled_locked(&rq->fence)) {
+ if (!i915_request_has_waitboost(rq) &&
+ !dma_fence_is_signaled_locked(&rq->fence)) {
boost = !atomic_fetch_inc(&rps->num_waiters);
- rq->waitboost = true;
+ rq->flags |= I915_REQUEST_FLAGS_WAITBOOST;
}
spin_unlock_irqrestore(&rq->lock, flags);
if (!boost)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index e6f7f738490e..7359f190728c 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1984,6 +1984,17 @@ enum drm_i915_perf_property_id {
*/
DRM_I915_PERF_PROP_OA_EXPONENT,
+ /**
+ * Specifying this property is only valid when specify a context to
+ * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
+ * will hold preemption of the particular context we want to gather
+ * performance data about. The execbuf2 submissions must include a
+ * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
+ *
+ * This property is available in perf revision 2.
+ */
+ DRM_I915_PERF_PROP_HOLD_PREEMPTION,
+
DRM_I915_PERF_PROP_MAX /* non-ABI */
};
--
2.21.0.392.gf8f6787159e
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v7 10/12] drm/i915/perf: allow holding preemption on filtered ctx
2019-07-09 9:32 ` [PATCH v7 10/12] drm/i915/perf: allow holding preemption on filtered ctx Lionel Landwerlin
@ 2019-07-09 10:00 ` Chris Wilson
2019-07-09 10:45 ` Lionel Landwerlin
0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-07-09 10:00 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-07-09 10:32:06)
> We would like to make use of perf in Vulkan. The Vulkan API is much
> lower level than OpenGL, with applications directly exposed to the
> concept of command buffers (pretty much equivalent to our batch
> buffers). In Vulkan, queries are always limited in scope to a command
> buffer. In OpenGL, the lack of command buffer concept meant that
> queries' duration could span multiple command buffers.
>
> With that restriction gone in Vulkan, we would like to simplify
> measuring performance just by measuring the deltas between the counter
> snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
> more complex scheme we currently have in the GL driver, using 2
> MI_RECORD_PERF_COUNT commands and doing some post processing on the
> stream of OA reports, coming from the global OA buffer, to remove any
> unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
>
> Disabling preemption only apply to a single context with which want to
> query performance counters for and is considered a privileged
> operation, by default protected by CAP_SYS_ADMIN. It is possible to
> enable it for a normal user by disabling the paranoid stream setting.
>
> v2: Store preemption setting in intel_context (Chris)
>
> v3: Use priorities to avoid preemption rather than the HW mechanism
>
> v4: Just modify the port priority reporting function
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Could you split this into two -- separate the backend mechanism from
perf setting the flag? I want to add a selftest and apply.
-Chris
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^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v7 10/12] drm/i915/perf: allow holding preemption on filtered ctx
2019-07-09 10:00 ` Chris Wilson
@ 2019-07-09 10:45 ` Lionel Landwerlin
0 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 10:45 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 09/07/2019 13:00, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-07-09 10:32:06)
>> We would like to make use of perf in Vulkan. The Vulkan API is much
>> lower level than OpenGL, with applications directly exposed to the
>> concept of command buffers (pretty much equivalent to our batch
>> buffers). In Vulkan, queries are always limited in scope to a command
>> buffer. In OpenGL, the lack of command buffer concept meant that
>> queries' duration could span multiple command buffers.
>>
>> With that restriction gone in Vulkan, we would like to simplify
>> measuring performance just by measuring the deltas between the counter
>> snapshots written by 2 MI_RECORD_PERF_COUNT commands, rather than the
>> more complex scheme we currently have in the GL driver, using 2
>> MI_RECORD_PERF_COUNT commands and doing some post processing on the
>> stream of OA reports, coming from the global OA buffer, to remove any
>> unrelated deltas in between the 2 MI_RECORD_PERF_COUNT.
>>
>> Disabling preemption only apply to a single context with which want to
>> query performance counters for and is considered a privileged
>> operation, by default protected by CAP_SYS_ADMIN. It is possible to
>> enable it for a normal user by disabling the paranoid stream setting.
>>
>> v2: Store preemption setting in intel_context (Chris)
>>
>> v3: Use priorities to avoid preemption rather than the HW mechanism
>>
>> v4: Just modify the port priority reporting function
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Could you split this into two -- separate the backend mechanism from
> perf setting the flag? I want to add a selftest and apply.
> -Chris
>
Sure.
-Lionel
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v7 11/12] drm/i915/perf: execute OA configuration from command stream
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (9 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 10/12] drm/i915/perf: allow holding preemption on filtered ctx Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 10:02 ` Chris Wilson
2019-07-09 9:32 ` [PATCH v7 12/12] drm/i915: add support for perf configuration queries Lionel Landwerlin
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer.
Since we have a command buffer prepared for the execbuffer side of
things, we can reuse that approach here too.
This also allows us to significantly reduce the amount of time we hold
the main lock.
v2: Drop the global lock as much as possible
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 7 +
drivers/gpu/drm/i915/i915_perf.c | 261 ++++++++++++++++++-------------
2 files changed, 161 insertions(+), 107 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index dc0e4982c672..c72e7c746b57 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1205,6 +1205,13 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+ * @initial_config_rq: First request run at the opening of the i915
+ * perf stream to configure the HW. Should be NULL after the perf
+ * stream has been opened successfully.
+ */
+ struct i915_request *initial_config_rq;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1e5011d4cdae..048a9abad26a 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -392,6 +392,19 @@ void i915_oa_config_release(struct kref *ref)
kfree(oa_config);
}
+static void i915_oa_config_dispose_buffers(struct drm_i915_private *i915)
+{
+ struct i915_oa_config *oa_config, *next;
+
+ mutex_lock(&i915->perf.metrics_lock);
+ list_for_each_entry_safe(oa_config, next, &i915->perf.metrics_buffers, vma_link) {
+ list_del(&oa_config->vma_link);
+ i915_gem_object_put(oa_config->obj);
+ oa_config->obj = NULL;
+ }
+ mutex_unlock(&i915->perf.metrics_lock);
+}
+
static u32 *write_cs_mi_lri(u32 *cs, const struct i915_oa_reg *reg_data, u32 n_regs)
{
u32 i;
@@ -1449,6 +1462,14 @@ static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
}
}
+static void free_noa_wait(struct drm_i915_private *i915)
+{
+ mutex_lock(&i915->drm.struct_mutex);
+ i915_vma_unpin_and_release(&i915->perf.oa.noa_wait,
+ I915_VMA_RELEASE_MAP);
+ mutex_unlock(&i915->drm.struct_mutex);
+}
+
static void
free_oa_buffer(struct drm_i915_private *i915)
{
@@ -1468,16 +1489,17 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
BUG_ON(stream != dev_priv->perf.oa.exclusive_stream);
+ dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
+
/*
* Unset exclusive_stream first, it will be checked while disabling
* the metric set on gen8+.
*/
mutex_lock(&dev_priv->drm.struct_mutex);
dev_priv->perf.oa.exclusive_stream = NULL;
- dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
- i915_vma_unpin_and_release(&dev_priv->perf.oa.noa_wait, 0);
mutex_unlock(&dev_priv->drm.struct_mutex);
+ free_noa_wait(dev_priv);
free_oa_buffer(dev_priv);
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
@@ -1710,6 +1732,10 @@ static int alloc_noa_wait(struct drm_i915_private *i915)
return PTR_ERR(bo);
}
+ ret = i915_mutex_lock_interruptible(&i915->drm);
+ if (ret)
+ goto err_unref;
+
/*
* We pin in GGTT because we jump into this buffer now because
* multiple OA config BOs will have a jump to this address and it
@@ -1717,10 +1743,13 @@ static int alloc_noa_wait(struct drm_i915_private *i915)
*/
vma = i915_gem_object_ggtt_pin(bo, NULL, 0, 4096, 0);
if (IS_ERR(vma)) {
+ mutex_unlock(&i915->drm.struct_mutex);
ret = PTR_ERR(vma);
goto err_unref;
}
+ mutex_unlock(&i915->drm.struct_mutex);
+
batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
if (IS_ERR(batch)) {
ret = PTR_ERR(batch);
@@ -1854,7 +1883,11 @@ static int alloc_noa_wait(struct drm_i915_private *i915)
return 0;
err_unpin:
- __i915_vma_unpin(vma);
+ mutex_lock(&i915->drm.struct_mutex);
+ i915_vma_unpin_and_release(&i915->perf.oa.noa_wait, 0);
+ mutex_unlock(&i915->drm.struct_mutex);
+
+ return ret;
err_unref:
i915_gem_object_put(bo);
@@ -1862,23 +1895,55 @@ static int alloc_noa_wait(struct drm_i915_private *i915)
return ret;
}
-static void config_oa_regs(struct drm_i915_private *dev_priv,
- const struct i915_oa_reg *regs,
- u32 n_regs)
+static int emit_oa_config(struct drm_i915_private *i915,
+ struct i915_perf_stream *stream)
{
- u32 i;
+ struct i915_oa_config *oa_config = stream->oa_config;
+ struct i915_request *rq = stream->initial_config_rq;
+ struct i915_vma *vma;
+ u32 *cs;
+ int err;
- for (i = 0; i < n_regs; i++) {
- const struct i915_oa_reg *reg = regs + i;
+ vma = i915_vma_instance(oa_config->obj, &i915->ggtt.vm, NULL);
+ if (unlikely(IS_ERR(vma)))
+ return PTR_ERR(vma);
+
+ err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
+ if (err)
+ return err;
- I915_WRITE(reg->addr, reg->value);
+ err = i915_vma_move_to_active(vma, rq, 0);
+ if (err) {
+ i915_vma_unpin(vma);
+ return err;
}
+
+ cs = intel_ring_begin(rq, INTEL_GEN(i915) >= 8 ? 4 : 2);
+ if (IS_ERR(cs)) {
+ i915_vma_unpin(vma);
+ return PTR_ERR(cs);
+ }
+
+ if (INTEL_GEN(i915) > 8) {
+ *cs++ = MI_BATCH_BUFFER_START_GEN8;
+ *cs++ = lower_32_bits(vma->node.start);
+ *cs++ = upper_32_bits(vma->node.start);
+ *cs++ = MI_NOOP;
+ } else {
+ *cs++ = MI_BATCH_BUFFER_START;
+ *cs++ = vma->node.start;
+ }
+
+ intel_ring_advance(rq, cs);
+
+ i915_vma_unpin(vma);
+
+ return 0;
}
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
- const struct i915_oa_config *oa_config = stream->oa_config;
/* PRM:
*
@@ -1894,35 +1959,7 @@ static int hsw_enable_metric_set(struct i915_perf_stream *stream)
I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) |
GEN6_CSUNIT_CLOCK_GATE_DISABLE));
- config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
-
- /* It apparently takes a fairly long time for a new MUX
- * configuration to be be applied after these register writes.
- * This delay duration was derived empirically based on the
- * render_basic config but hopefully it covers the maximum
- * configuration latency.
- *
- * As a fallback, the checks in _append_oa_reports() to skip
- * invalid OA reports do also seem to work to discard reports
- * generated before this config has completed - albeit not
- * silently.
- *
- * Unfortunately this is essentially a magic number, since we
- * don't currently know of a reliable mechanism for predicting
- * how long the MUX config will take to apply and besides
- * seeing invalid reports we don't know of a reliable way to
- * explicitly check that the MUX config has landed.
- *
- * It's even possible we've miss characterized the underlying
- * problem - it just seems like the simplest explanation why
- * a delay at this location would mitigate any invalid reports.
- */
- usleep_range(15000, 20000);
-
- config_oa_regs(dev_priv, oa_config->b_counter_regs,
- oa_config->b_counter_regs_len);
-
- return 0;
+ return emit_oa_config(dev_priv, stream);
}
static void hsw_disable_metric_set(struct drm_i915_private *dev_priv)
@@ -2027,10 +2064,18 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
{
unsigned int map_type = i915_coherent_map_type(dev_priv);
struct i915_gem_context *ctx;
- struct i915_request *rq;
int ret;
- lockdep_assert_held(&dev_priv->drm.struct_mutex);
+ /* When calling without a configuration, we're tearing down the i915
+ * perf stream. Don't be interruptible in that case.
+ */
+ if (oa_config) {
+ ret = i915_mutex_lock_interruptible(&dev_priv->drm);
+ if (ret)
+ return ret;
+ } else {
+ mutex_lock(&dev_priv->drm.struct_mutex);
+ }
/*
* The OA register config is setup through the context image. This image
@@ -2049,7 +2094,7 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
I915_WAIT_LOCKED,
MAX_SCHEDULE_TIMEOUT);
if (ret)
- return ret;
+ goto unlock;
/* Update all contexts now that we've stalled the submission. */
list_for_each_entry(ctx, &dev_priv->contexts.list, link) {
@@ -2072,7 +2117,8 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
map_type);
if (IS_ERR(regs)) {
i915_gem_context_unlock_engines(ctx);
- return PTR_ERR(regs);
+ ret = PTR_ERR(regs);
+ goto unlock;
}
ce->state->obj->mm.dirty = true;
@@ -2086,16 +2132,14 @@ static int gen8_configure_all_contexts(struct drm_i915_private *dev_priv,
}
/*
- * Apply the configuration by doing one context restore of the edited
- * context image.
+ * The above configuration will be applied when called
+ * config_oa_regs().
*/
- rq = i915_request_create(dev_priv->engine[RCS0]->kernel_context);
- if (IS_ERR(rq))
- return PTR_ERR(rq);
- i915_request_add(rq);
+unlock:
+ mutex_unlock(&dev_priv->drm.struct_mutex);
- return 0;
+ return ret;
}
static int gen8_enable_metric_set(struct i915_perf_stream *stream)
@@ -2142,35 +2186,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream)
if (ret)
return ret;
- config_oa_regs(dev_priv, oa_config->mux_regs, oa_config->mux_regs_len);
-
- /* It apparently takes a fairly long time for a new MUX
- * configuration to be be applied after these register writes.
- * This delay duration was derived empirically based on the
- * render_basic config but hopefully it covers the maximum
- * configuration latency.
- *
- * As a fallback, the checks in _append_oa_reports() to skip
- * invalid OA reports do also seem to work to discard reports
- * generated before this config has completed - albeit not
- * silently.
- *
- * Unfortunately this is essentially a magic number, since we
- * don't currently know of a reliable mechanism for predicting
- * how long the MUX config will take to apply and besides
- * seeing invalid reports we don't know of a reliable way to
- * explicitly check that the MUX config has landed.
- *
- * It's even possible we've miss characterized the underlying
- * problem - it just seems like the simplest explanation why
- * a delay at this location would mitigate any invalid reports.
- */
- usleep_range(15000, 20000);
-
- config_oa_regs(dev_priv, oa_config->b_counter_regs,
- oa_config->b_counter_regs_len);
-
- return 0;
+ return emit_oa_config(dev_priv, stream);
}
static void gen8_disable_metric_set(struct drm_i915_private *dev_priv)
@@ -2341,7 +2357,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
struct perf_open_properties *props)
{
struct drm_i915_private *dev_priv = stream->dev_priv;
+ struct drm_i915_gem_object *obj;
int format_size;
+ long timeout;
int ret;
/* If the sysfs metrics/ directory wasn't registered for some
@@ -2425,13 +2443,6 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
}
}
- ret = i915_perf_get_oa_config(dev_priv, props->metrics_set,
- &stream->oa_config, NULL);
- if (ret) {
- DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
- goto err_config;
- }
-
ret = alloc_noa_wait(dev_priv);
if (ret) {
DRM_DEBUG("Unable to allocate NOA wait batch buffer\n");
@@ -2457,47 +2468,90 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
if (ret)
goto err_oa_buf_alloc;
+ ret = i915_perf_get_oa_config(dev_priv, props->metrics_set,
+ &stream->oa_config, &obj);
+ if (ret) {
+ DRM_DEBUG("Invalid OA config id=%i\n", props->metrics_set);
+ goto err_config;
+ }
+
+ /*
+ * We just need the buffer to be created, but not our own reference on
+ * it as the oa_config already has one.
+ */
+ i915_gem_object_put(obj);
+
+ stream->initial_config_rq =
+ i915_request_create(dev_priv->engine[RCS0]->kernel_context);
+ if (IS_ERR(stream->initial_config_rq)) {
+ ret = PTR_ERR(stream->initial_config_rq);
+ goto err_initial_config;
+ }
+
+ stream->ops = &i915_oa_stream_ops;
+
ret = i915_mutex_lock_interruptible(&dev_priv->drm);
if (ret)
goto err_lock;
- stream->ops = &i915_oa_stream_ops;
+ ret = i915_active_request_set(&dev_priv->engine[RCS0]->last_oa_config,
+ stream->initial_config_rq);
+ if (ret) {
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+ goto err_lock;
+ }
+
dev_priv->perf.oa.exclusive_stream = stream;
+ mutex_unlock(&dev_priv->drm.struct_mutex);
+
ret = dev_priv->perf.oa.ops.enable_metric_set(stream);
if (ret) {
DRM_DEBUG("Unable to enable metric set\n");
goto err_enable;
}
- DRM_DEBUG("opening stream oa config uuid=%s\n", stream->oa_config->uuid);
+ i915_request_get(stream->initial_config_rq);
- mutex_unlock(&dev_priv->drm.struct_mutex);
+ i915_request_add(stream->initial_config_rq);
+
+ timeout = i915_request_wait(stream->initial_config_rq,
+ I915_WAIT_INTERRUPTIBLE,
+ MAX_SCHEDULE_TIMEOUT);
+ i915_request_put(stream->initial_config_rq);
+ stream->initial_config_rq = NULL;
+
+ ret = timeout < 0 ? timeout : 0;
+ if (ret)
+ goto err_enable;
+
+ DRM_DEBUG("opening stream oa config uuid=%s\n", stream->oa_config->uuid);
return 0;
err_enable:
+ mutex_lock(&dev_priv->drm.struct_mutex);
dev_priv->perf.oa.exclusive_stream = NULL;
- dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
mutex_unlock(&dev_priv->drm.struct_mutex);
+ dev_priv->perf.oa.ops.disable_metric_set(dev_priv);
err_lock:
- free_oa_buffer(dev_priv);
+ i915_request_add(stream->initial_config_rq);
-err_oa_buf_alloc:
+err_initial_config:
i915_oa_config_put(stream->oa_config);
+ i915_oa_config_dispose_buffers(dev_priv);
+
+err_config:
+ free_oa_buffer(dev_priv);
+err_oa_buf_alloc:
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
intel_runtime_pm_put(&dev_priv->runtime_pm, stream->wakeref);
- mutex_lock(&dev_priv->drm.struct_mutex);
- i915_vma_unpin_and_release(&dev_priv->perf.oa.noa_wait, 0);
- mutex_unlock(&dev_priv->drm.struct_mutex);
+ free_noa_wait(dev_priv);
err_noa_wait_alloc:
- i915_oa_config_put(stream->oa_config);
-
-err_config:
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -2859,20 +2913,13 @@ static int i915_perf_release(struct inode *inode, struct file *file)
{
struct i915_perf_stream *stream = file->private_data;
struct drm_i915_private *dev_priv = stream->dev_priv;
- struct i915_oa_config *oa_config, *next;
mutex_lock(&dev_priv->perf.lock);
i915_perf_destroy_locked(stream);
/* Dispose of all oa config batch buffers. */
- mutex_lock(&dev_priv->perf.metrics_lock);
- list_for_each_entry_safe(oa_config, next, &dev_priv->perf.metrics_buffers, vma_link) {
- list_del(&oa_config->vma_link);
- i915_gem_object_put(oa_config->obj);
- oa_config->obj = NULL;
- }
- mutex_unlock(&dev_priv->perf.metrics_lock);
+ i915_oa_config_dispose_buffers(dev_priv);
mutex_unlock(&dev_priv->perf.lock);
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v7 11/12] drm/i915/perf: execute OA configuration from command stream
2019-07-09 9:32 ` [PATCH v7 11/12] drm/i915/perf: execute OA configuration from command stream Lionel Landwerlin
@ 2019-07-09 10:02 ` Chris Wilson
2019-07-09 11:04 ` Lionel Landwerlin
0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-07-09 10:02 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-07-09 10:32:07)
> +static int emit_oa_config(struct drm_i915_private *i915,
> + struct i915_perf_stream *stream)
> {
> - u32 i;
> + struct i915_oa_config *oa_config = stream->oa_config;
> + struct i915_request *rq = stream->initial_config_rq;
> + struct i915_vma *vma;
> + u32 *cs;
> + int err;
>
> - for (i = 0; i < n_regs; i++) {
> - const struct i915_oa_reg *reg = regs + i;
> + vma = i915_vma_instance(oa_config->obj, &i915->ggtt.vm, NULL);
> + if (unlikely(IS_ERR(vma)))
> + return PTR_ERR(vma);
> +
> + err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
> + if (err)
> + return err;
Hmm, still a lock inversion here as we will not be allowed to pin from
underneath rq->timeline->mutex.
-Chris
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 11/12] drm/i915/perf: execute OA configuration from command stream
2019-07-09 10:02 ` Chris Wilson
@ 2019-07-09 11:04 ` Lionel Landwerlin
2019-07-09 11:16 ` Lionel Landwerlin
0 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 11:04 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 09/07/2019 13:02, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-07-09 10:32:07)
>> +static int emit_oa_config(struct drm_i915_private *i915,
>> + struct i915_perf_stream *stream)
>> {
>> - u32 i;
>> + struct i915_oa_config *oa_config = stream->oa_config;
>> + struct i915_request *rq = stream->initial_config_rq;
>> + struct i915_vma *vma;
>> + u32 *cs;
>> + int err;
>>
>> - for (i = 0; i < n_regs; i++) {
>> - const struct i915_oa_reg *reg = regs + i;
>> + vma = i915_vma_instance(oa_config->obj, &i915->ggtt.vm, NULL);
>> + if (unlikely(IS_ERR(vma)))
>> + return PTR_ERR(vma);
>> +
>> + err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
>> + if (err)
>> + return err;
> Hmm, still a lock inversion here as we will not be allowed to pin from
> underneath rq->timeline->mutex.
> -Chris
>
I can put this function back under the i915->drm.struct_mutex.
We still drop the lock to do the wait.
Sounds ok?
-Lionel
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 11/12] drm/i915/perf: execute OA configuration from command stream
2019-07-09 11:04 ` Lionel Landwerlin
@ 2019-07-09 11:16 ` Lionel Landwerlin
0 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 11:16 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 09/07/2019 14:04, Lionel Landwerlin wrote:
> On 09/07/2019 13:02, Chris Wilson wrote:
>> Quoting Lionel Landwerlin (2019-07-09 10:32:07)
>>> +static int emit_oa_config(struct drm_i915_private *i915,
>>> + struct i915_perf_stream *stream)
>>> {
>>> - u32 i;
>>> + struct i915_oa_config *oa_config = stream->oa_config;
>>> + struct i915_request *rq = stream->initial_config_rq;
>>> + struct i915_vma *vma;
>>> + u32 *cs;
>>> + int err;
>>> - for (i = 0; i < n_regs; i++) {
>>> - const struct i915_oa_reg *reg = regs + i;
>>> + vma = i915_vma_instance(oa_config->obj, &i915->ggtt.vm, NULL);
>>> + if (unlikely(IS_ERR(vma)))
>>> + return PTR_ERR(vma);
>>> +
>>> + err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL);
>>> + if (err)
>>> + return err;
>> Hmm, still a lock inversion here as we will not be allowed to pin from
>> underneath rq->timeline->mutex.
>> -Chris
>>
> I can put this function back under the i915->drm.struct_mutex.
>
> We still drop the lock to do the wait.
>
>
> Sounds ok?
>
>
> -Lionel
When with locking around the global pin.
-Lionel
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^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v7 12/12] drm/i915: add support for perf configuration queries
2019-07-09 9:31 [PATCH v7 00/12] drm/i915: Vulkan performance query support Lionel Landwerlin
` (10 preceding siblings ...)
2019-07-09 9:32 ` [PATCH v7 11/12] drm/i915/perf: execute OA configuration from command stream Lionel Landwerlin
@ 2019-07-09 9:32 ` Lionel Landwerlin
2019-07-09 10:07 ` Chris Wilson
11 siblings, 1 reply; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 9:32 UTC (permalink / raw)
To: intel-gfx
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v2: Fix sparse warnings (Lionel)
Add support to query configuration using uuid (Lionel)
v3: Fix some inconsistency in uapi header (Lionel)
Fix unlocking when not locked issue (Lionel)
Add debug messages (Lionel)
v4: Fix missing unlock (Dan)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 +
drivers/gpu/drm/i915/i915_perf.c | 3 +
drivers/gpu/drm/i915/i915_query.c | 279 ++++++++++++++++++++++++++++++
include/uapi/drm/i915_drm.h | 65 ++++++-
4 files changed, 350 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c72e7c746b57..28f0f490b7b1 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1729,6 +1729,12 @@ struct drm_i915_private {
*/
struct list_head metrics_buffers;
+ /*
+ * Number of dynamic configurations, you need to hold
+ * dev_priv->perf.metrics_lock to access it.
+ */
+ u32 n_metrics;
+
/*
* Lock associated with anything below within this structure
* except exclusive_stream.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 048a9abad26a..f51674a61742 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3717,6 +3717,8 @@ int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
goto sysfs_err;
}
+ dev_priv->perf.n_metrics++;
+
mutex_unlock(&dev_priv->perf.metrics_lock);
DRM_DEBUG("Added config %s id=%i\n", oa_config->uuid, oa_config->id);
@@ -3777,6 +3779,7 @@ int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
&oa_config->sysfs_metric);
idr_remove(&dev_priv->perf.metrics_idr, *arg);
+ dev_priv->perf.n_metrics--;
mutex_unlock(&dev_priv->perf.metrics_lock);
diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c
index 7b7016171057..c1e203c7b2c2 100644
--- a/drivers/gpu/drm/i915/i915_query.c
+++ b/drivers/gpu/drm/i915/i915_query.c
@@ -143,10 +143,289 @@ query_engine_info(struct drm_i915_private *i915,
return len;
}
+static int can_copy_perf_config_registers_or_number(u32 user_n_regs,
+ u64 user_regs_ptr,
+ u32 kernel_n_regs)
+{
+ /*
+ * We'll just put the number of registers, and won't copy the
+ * register.
+ */
+ if (user_n_regs == 0)
+ return 0;
+
+ if (user_n_regs < kernel_n_regs)
+ return -EINVAL;
+
+ if (!access_ok(u64_to_user_ptr(user_regs_ptr),
+ 2 * sizeof(u32) * kernel_n_regs))
+ return -EFAULT;
+
+ return 0;
+}
+
+static int copy_perf_config_registers_or_number(const struct i915_oa_reg *kernel_regs,
+ u32 kernel_n_regs,
+ u64 user_regs_ptr,
+ u32 *user_n_regs)
+{
+ u32 r;
+
+ if (*user_n_regs == 0) {
+ *user_n_regs = kernel_n_regs;
+ return 0;
+ }
+
+ *user_n_regs = kernel_n_regs;
+
+ for (r = 0; r < kernel_n_regs; r++) {
+ u32 __user *user_reg_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2);
+ u32 __user *user_val_ptr =
+ u64_to_user_ptr(user_regs_ptr + sizeof(u32) * r * 2 +
+ sizeof(u32));
+ int ret;
+
+ ret = __put_user(i915_mmio_reg_offset(kernel_regs[r].addr),
+ user_reg_ptr);
+ if (ret)
+ return -EFAULT;
+
+ ret = __put_user(kernel_regs[r].value, user_val_ptr);
+ if (ret)
+ return -EFAULT;
+ }
+
+ return 0;
+}
+
+static int query_perf_config_data(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item,
+ bool use_uuid)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct drm_i915_perf_oa_config __user *user_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config));
+ struct drm_i915_perf_oa_config user_config;
+ struct i915_oa_config *oa_config = NULL;
+ u32 flags, total_size;
+ int ret;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ total_size = sizeof(struct drm_i915_query_perf_config) +
+ sizeof(struct drm_i915_perf_oa_config);
+
+ if (query_item->length == 0)
+ return total_size;
+
+ if (query_item->length < total_size) {
+ DRM_DEBUG("Invalid query config data item size=%u expected=%u\n",
+ query_item->length, total_size);
+ return -EINVAL;
+ }
+
+ if (!access_ok(user_query_config_ptr, total_size))
+ return -EFAULT;
+
+ if (__get_user(flags, &user_query_config_ptr->flags))
+ return -EFAULT;
+
+ if (flags != 0)
+ return -EINVAL;
+
+ ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
+ if (ret)
+ return ret;
+
+ if (use_uuid) {
+ char uuid[UUID_STRING_LEN + 1] = { 0, };
+ struct i915_oa_config *tmp;
+ int id;
+
+ BUILD_BUG_ON(sizeof(user_query_config_ptr->uuid) >= sizeof(uuid));
+
+ if (__copy_from_user(uuid, user_query_config_ptr->uuid,
+ sizeof(user_query_config_ptr->uuid))) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ idr_for_each_entry(&i915->perf.metrics_idr, tmp, id) {
+ if (!strcmp(tmp->uuid, uuid)) {
+ oa_config = tmp;
+ break;
+ }
+ }
+ } else {
+ u64 config_id;
+
+ if (__get_user(config_id, &user_query_config_ptr->config)) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ if (config_id == 1)
+ oa_config = &i915->perf.oa.test_config;
+ else
+ oa_config = idr_find(&i915->perf.metrics_idr, config_id);
+ }
+
+ if (!oa_config) {
+ ret = -ENOENT;
+ goto out;
+ }
+
+ if (__copy_from_user(&user_config, user_config_ptr,
+ sizeof(user_config))) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ ret = can_copy_perf_config_registers_or_number(user_config.n_boolean_regs,
+ user_config.boolean_regs_ptr,
+ oa_config->b_counter_regs_len);
+ if (ret)
+ goto out;
+
+ ret = can_copy_perf_config_registers_or_number(user_config.n_flex_regs,
+ user_config.flex_regs_ptr,
+ oa_config->flex_regs_len);
+ if (ret)
+ goto out;
+
+ ret = can_copy_perf_config_registers_or_number(user_config.n_mux_regs,
+ user_config.mux_regs_ptr,
+ oa_config->mux_regs_len);
+ if (ret)
+ goto out;
+
+ ret = copy_perf_config_registers_or_number(oa_config->b_counter_regs,
+ oa_config->b_counter_regs_len,
+ user_config.boolean_regs_ptr,
+ &user_config.n_boolean_regs);
+ if (ret)
+ goto out;
+
+ ret = copy_perf_config_registers_or_number(oa_config->flex_regs,
+ oa_config->flex_regs_len,
+ user_config.flex_regs_ptr,
+ &user_config.n_flex_regs);
+ if (ret)
+ goto out;
+
+ ret = copy_perf_config_registers_or_number(oa_config->mux_regs,
+ oa_config->mux_regs_len,
+ user_config.mux_regs_ptr,
+ &user_config.n_mux_regs);
+ if (ret)
+ goto out;
+
+ memcpy(user_config.uuid, oa_config->uuid, sizeof(user_config.uuid));
+
+ if (__copy_to_user(user_config_ptr, &user_config,
+ sizeof(user_config))) {
+ ret = -EFAULT;
+ goto out;
+ }
+
+ ret = total_size;
+
+out:
+ mutex_unlock(&i915->perf.metrics_lock);
+ return ret;
+}
+
+static int query_perf_config_list(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item)
+{
+ struct drm_i915_query_perf_config __user *user_query_config_ptr =
+ u64_to_user_ptr(query_item->data_ptr);
+ struct i915_oa_config *oa_config;
+ u32 flags, total_size;
+ u64 n_configs;
+ int ret, id;
+
+ if (!i915->perf.initialized)
+ return -ENODEV;
+
+ /* Count the default test configuration */
+ n_configs = i915->perf.n_metrics + 1;
+ total_size = sizeof(struct drm_i915_query_perf_config) +
+ sizeof(u64) * n_configs;
+
+ if (query_item->length == 0)
+ return total_size;
+
+ if (query_item->length < total_size) {
+ DRM_DEBUG("Invalid query config list item size=%u expected=%u\n",
+ query_item->length, total_size);
+ return -EINVAL;
+ }
+
+ if (!access_ok(user_query_config_ptr, total_size))
+ return -EFAULT;
+
+ if (__get_user(flags, &user_query_config_ptr->flags))
+ return -EFAULT;
+
+ if (flags != 0)
+ return -EINVAL;
+
+ if (__put_user(n_configs, &user_query_config_ptr->config))
+ return -EFAULT;
+
+ if (__put_user((u64)1ULL, &user_query_config_ptr->data[0]))
+ return -EFAULT;
+
+ ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
+ if (ret)
+ return ret;
+
+ n_configs = 1;
+ idr_for_each_entry(&i915->perf.metrics_idr, oa_config, id) {
+ u64 __user *item =
+ u64_to_user_ptr(query_item->data_ptr +
+ sizeof(struct drm_i915_query_perf_config) +
+ n_configs * sizeof(u64));
+
+ if (__put_user((u64)id, item)) {
+ ret = -EFAULT;
+ goto out;
+ }
+ n_configs++;
+ }
+
+ ret = total_size;
+
+out:
+ mutex_unlock(&i915->perf.metrics_lock);
+ return ret;
+}
+
+static int query_perf_config(struct drm_i915_private *i915,
+ struct drm_i915_query_item *query_item)
+{
+ switch (query_item->flags) {
+ case DRM_I915_QUERY_PERF_CONFIG_LIST:
+ return query_perf_config_list(i915, query_item);
+ case DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID:
+ return query_perf_config_data(i915, query_item, true);
+ case DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID:
+ return query_perf_config_data(i915, query_item, false);
+ default:
+ return -EINVAL;
+ }
+}
+
static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv,
struct drm_i915_query_item *query_item) = {
query_topology_info,
query_engine_info,
+ query_perf_config,
};
int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file)
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 7359f190728c..545d87a722b4 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -1037,8 +1037,7 @@ enum drm_i915_gem_execbuffer_ext {
DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES = 0,
/**
- * This identifier is associated with
- * drm_i915_gem_execbuffer_perf_ext.
+ * See drm_i915_gem_execbuffer_perf_ext.
*/
DRM_I915_GEM_EXECBUFFER_EXT_PERF,
@@ -2110,6 +2109,7 @@ struct drm_i915_query_item {
__u64 query_id;
#define DRM_I915_QUERY_TOPOLOGY_INFO 1
#define DRM_I915_QUERY_ENGINE_INFO 2
+#define DRM_I915_QUERY_PERF_CONFIG 3
/* Must be kept compact -- no holes and well documented */
/*
@@ -2121,9 +2121,18 @@ struct drm_i915_query_item {
__s32 length;
/*
- * Unused for now. Must be cleared to zero.
+ * When query_id == DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
+ *
+ * When query_id == DRM_I915_QUERY_PERF_CONFIG, must be one of the
+ * following :
+ * - DRM_I915_QUERY_PERF_CONFIG_LIST
+ * - DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
+ * - DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
*/
__u32 flags;
+#define DRM_I915_QUERY_PERF_CONFIG_LIST 1
+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
+#define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
/*
* Data will be written at the location pointed by data_ptr when the
@@ -2249,6 +2258,56 @@ struct drm_i915_query_engine_info {
struct drm_i915_engine_info engines[];
};
+/*
+ * Data written by the kernel with query DRM_I915_QUERY_PERF_CONFIG.
+ */
+struct drm_i915_query_perf_config {
+ union {
+ /*
+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets
+ * this fields to the number of configurations available.
+ */
+ __u64 n_configs;
+
+ /*
+ * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID,
+ * i915 will use the value in this field as configuration
+ * identifier to decide what data to write into config_ptr.
+ */
+ __u64 config;
+
+ /*
+ * When query_id == DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID,
+ * i915 will use the value in this field as configuration
+ * identifier to decide what data to write into config_ptr.
+ *
+ * String formatted like "%08x-%04x-%04x-%04x-%012x"
+ */
+ char uuid[36];
+ };
+
+ /*
+ * Unused for now. Must be cleared to zero.
+ */
+ __u32 flags;
+
+ /*
+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_LIST, i915 will
+ * write an array of __u64 of configuration identifiers.
+ *
+ * When query_item.flags == DRM_I915_QUERY_PERF_CONFIG_DATA, i915 will
+ * write a struct drm_i915_perf_oa_config. If the following fields of
+ * drm_i915_perf_oa_config are set not set to 0, i915 will write into
+ * the associated pointers the values of submitted when the
+ * configuration was created :
+ *
+ * - n_mux_regs
+ * - n_boolean_regs
+ * - n_flex_regs
+ */
+ __u8 data[];
+};
+
#if defined(__cplusplus)
}
#endif
--
2.21.0.392.gf8f6787159e
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^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [PATCH v7 12/12] drm/i915: add support for perf configuration queries
2019-07-09 9:32 ` [PATCH v7 12/12] drm/i915: add support for perf configuration queries Lionel Landwerlin
@ 2019-07-09 10:07 ` Chris Wilson
2019-07-09 11:33 ` Lionel Landwerlin
0 siblings, 1 reply; 29+ messages in thread
From: Chris Wilson @ 2019-07-09 10:07 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-07-09 10:32:08)
> +static int query_perf_config_data(struct drm_i915_private *i915,
> + struct drm_i915_query_item *query_item,
> + bool use_uuid)
> +{
> + struct drm_i915_query_perf_config __user *user_query_config_ptr =
> + u64_to_user_ptr(query_item->data_ptr);
> + struct drm_i915_perf_oa_config __user *user_config_ptr =
> + u64_to_user_ptr(query_item->data_ptr +
> + sizeof(struct drm_i915_query_perf_config));
> + struct drm_i915_perf_oa_config user_config;
> + struct i915_oa_config *oa_config = NULL;
> + u32 flags, total_size;
> + int ret;
> +
> + if (!i915->perf.initialized)
> + return -ENODEV;
> +
> + total_size = sizeof(struct drm_i915_query_perf_config) +
> + sizeof(struct drm_i915_perf_oa_config);
> +
> + if (query_item->length == 0)
> + return total_size;
> +
> + if (query_item->length < total_size) {
> + DRM_DEBUG("Invalid query config data item size=%u expected=%u\n",
> + query_item->length, total_size);
> + return -EINVAL;
> + }
> +
> + if (!access_ok(user_query_config_ptr, total_size))
> + return -EFAULT;
> +
> + if (__get_user(flags, &user_query_config_ptr->flags))
> + return -EFAULT;
> +
> + if (flags != 0)
> + return -EINVAL;
> +
> + ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
> + if (ret)
> + return ret;
> +
> + if (use_uuid) {
> + char uuid[UUID_STRING_LEN + 1] = { 0, };
> + struct i915_oa_config *tmp;
> + int id;
> +
> + BUILD_BUG_ON(sizeof(user_query_config_ptr->uuid) >= sizeof(uuid));
> +
> + if (__copy_from_user(uuid, user_query_config_ptr->uuid,
> + sizeof(user_query_config_ptr->uuid))) {
__copy_from_user() from inside a mutex brings back nightmares. I think
you are ok, but you are tarnishing this lock with mmap_sem, which is
huge and may bite in future. And it looks superfluous, no? You could do
the copy form user before taking the lock, and then once you have the
config pinned, you can drop the lock again.
-Chris
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^ permalink raw reply [flat|nested] 29+ messages in thread* Re: [PATCH v7 12/12] drm/i915: add support for perf configuration queries
2019-07-09 10:07 ` Chris Wilson
@ 2019-07-09 11:33 ` Lionel Landwerlin
0 siblings, 0 replies; 29+ messages in thread
From: Lionel Landwerlin @ 2019-07-09 11:33 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 09/07/2019 13:07, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2019-07-09 10:32:08)
>> +static int query_perf_config_data(struct drm_i915_private *i915,
>> + struct drm_i915_query_item *query_item,
>> + bool use_uuid)
>> +{
>> + struct drm_i915_query_perf_config __user *user_query_config_ptr =
>> + u64_to_user_ptr(query_item->data_ptr);
>> + struct drm_i915_perf_oa_config __user *user_config_ptr =
>> + u64_to_user_ptr(query_item->data_ptr +
>> + sizeof(struct drm_i915_query_perf_config));
>> + struct drm_i915_perf_oa_config user_config;
>> + struct i915_oa_config *oa_config = NULL;
>> + u32 flags, total_size;
>> + int ret;
>> +
>> + if (!i915->perf.initialized)
>> + return -ENODEV;
>> +
>> + total_size = sizeof(struct drm_i915_query_perf_config) +
>> + sizeof(struct drm_i915_perf_oa_config);
>> +
>> + if (query_item->length == 0)
>> + return total_size;
>> +
>> + if (query_item->length < total_size) {
>> + DRM_DEBUG("Invalid query config data item size=%u expected=%u\n",
>> + query_item->length, total_size);
>> + return -EINVAL;
>> + }
>> +
>> + if (!access_ok(user_query_config_ptr, total_size))
>> + return -EFAULT;
>> +
>> + if (__get_user(flags, &user_query_config_ptr->flags))
>> + return -EFAULT;
>> +
>> + if (flags != 0)
>> + return -EINVAL;
>> +
>> + ret = mutex_lock_interruptible(&i915->perf.metrics_lock);
>> + if (ret)
>> + return ret;
>> +
>> + if (use_uuid) {
>> + char uuid[UUID_STRING_LEN + 1] = { 0, };
>> + struct i915_oa_config *tmp;
>> + int id;
>> +
>> + BUILD_BUG_ON(sizeof(user_query_config_ptr->uuid) >= sizeof(uuid));
>> +
>> + if (__copy_from_user(uuid, user_query_config_ptr->uuid,
>> + sizeof(user_query_config_ptr->uuid))) {
> __copy_from_user() from inside a mutex brings back nightmares. I think
> you are ok, but you are tarnishing this lock with mmap_sem, which is
> huge and may bite in future. And it looks superfluous, no? You could do
> the copy form user before taking the lock, and then once you have the
> config pinned, you can drop the lock again.
> -Chris
>
Sounds good, updating.
-Lionel
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^ permalink raw reply [flat|nested] 29+ messages in thread