* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-01-18 23:58 ` Stefan Agner
0 siblings, 0 replies; 20+ messages in thread
From: Stefan Agner @ 2018-01-18 23:58 UTC (permalink / raw)
To: linux-arm-kernel
Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
Use PLL1 sys clock for all operating points higher than 528MHz.
Note: For higher operating points VDD_SOC_IN needs to be 125mV
higher than the ARM set-point (see datasheet). Specifically, the
i.MX6UL/ULL EVK boards have an external DC regulator which needs
adjustment. The regulator adjustment is not covered with this
change.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 628fe899cb48..840f6386c780 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
*/
clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
clk_set_parent(pll1_sw_clk, pll1_sys_clk);
- if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
- clk_set_parent(secondary_sel_clk, pll2_bus_clk);
- else
- clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
- clk_set_parent(step_clk, secondary_sel_clk);
- clk_set_parent(pll1_sw_clk, step_clk);
+ if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
+ if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
+ clk_set_parent(secondary_sel_clk, pll2_bus_clk);
+ else
+ clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
+ clk_set_parent(step_clk, secondary_sel_clk);
+ clk_set_parent(pll1_sw_clk, step_clk);
+ }
} else {
clk_set_parent(step_clk, pll2_pfd2_396m_clk);
clk_set_parent(pll1_sw_clk, step_clk);
--
2.15.1
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-01-18 23:58 ` Stefan Agner
@ 2018-02-09 11:52 ` Rafael J. Wysocki
-1 siblings, 0 replies; 20+ messages in thread
From: Rafael J. Wysocki @ 2018-02-09 11:52 UTC (permalink / raw)
To: Stefan Agner
Cc: viresh.kumar, fabio.estevam, octavian.purdila, shawnguo,
max.oss.09, marcel.ziswiler, linux-pm, linux-arm-kernel,
linux-kernel
On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
This makes sense to me, but I need someone with the requisite platform
knowledge to review it.
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
>
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-09 11:52 ` Rafael J. Wysocki
0 siblings, 0 replies; 20+ messages in thread
From: Rafael J. Wysocki @ 2018-02-09 11:52 UTC (permalink / raw)
To: linux-arm-kernel
On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
This makes sense to me, but I need someone with the requisite platform
knowledge to review it.
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-02-09 11:52 ` Rafael J. Wysocki
@ 2018-02-09 12:05 ` Stefan Agner
-1 siblings, 0 replies; 20+ messages in thread
From: Stefan Agner @ 2018-02-09 12:05 UTC (permalink / raw)
To: fabio.estevam, leonard.crestez
Cc: Rafael J. Wysocki, viresh.kumar, shawnguo, octavian.purdila,
max.oss.09, marcel.ziswiler, linux-pm, linux-arm-kernel,
linux-kernel
On 09.02.2018 12:52, Rafael J. Wysocki wrote:
> On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> This makes sense to me, but I need someone with the requisite platform
> knowledge to review it.
>
Fabio, Leonard, maybe one of you could have a look at it?
It is similar to what ("cpufreq: imx: Add support for 700MHz setpoint in
cpufreq") in downstream is doing, it avoids changing pll twice though.
And, as mentioned in the commit log, the dc_reg part is missing. This is
because it is not required on our Colibri iMX6ULL since it uses a higher
(not switchable) VDD_SOC_IN voltage by default.
--
Stefan
>> ---
>> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>> */
>> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> - else
>> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> - clk_set_parent(step_clk, secondary_sel_clk);
>> - clk_set_parent(pll1_sw_clk, step_clk);
>> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> + else
>> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> + clk_set_parent(step_clk, secondary_sel_clk);
>> + clk_set_parent(pll1_sw_clk, step_clk);
>> + }
>> } else {
>> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> clk_set_parent(pll1_sw_clk, step_clk);
>>
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-09 12:05 ` Stefan Agner
0 siblings, 0 replies; 20+ messages in thread
From: Stefan Agner @ 2018-02-09 12:05 UTC (permalink / raw)
To: linux-arm-kernel
On 09.02.2018 12:52, Rafael J. Wysocki wrote:
> On Friday, January 19, 2018 12:58:36 AM CET Stefan Agner wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> This makes sense to me, but I need someone with the requisite platform
> knowledge to review it.
>
Fabio, Leonard, maybe one of you could have a look at it?
It is similar to what ("cpufreq: imx: Add support for 700MHz setpoint in
cpufreq") in downstream is doing, it avoids changing pll twice though.
And, as mentioned in the commit log, the dc_reg part is missing. This is
because it is not required on our Colibri iMX6ULL since it uses a higher
(not switchable) VDD_SOC_IN voltage by default.
--
Stefan
>> ---
>> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>> */
>> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> - else
>> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> - clk_set_parent(step_clk, secondary_sel_clk);
>> - clk_set_parent(pll1_sw_clk, step_clk);
>> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> + else
>> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> + clk_set_parent(step_clk, secondary_sel_clk);
>> + clk_set_parent(pll1_sw_clk, step_clk);
>> + }
>> } else {
>> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> clk_set_parent(pll1_sw_clk, step_clk);
>>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-01-18 23:58 ` Stefan Agner
@ 2018-02-10 16:25 ` Fabio Estevam
-1 siblings, 0 replies; 20+ messages in thread
From: Fabio Estevam @ 2018-02-10 16:25 UTC (permalink / raw)
To: Stefan Agner, Yongcai Huang
Cc: rjw, viresh kumar, linux-pm, Marcel Ziswiler, max.oss.09,
linux-kernel, Octavian Purdila, Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
NXP Linux Team
Hi Anson,
On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
Could you please help reviewing this patch?
Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-10 16:25 ` Fabio Estevam
0 siblings, 0 replies; 20+ messages in thread
From: Fabio Estevam @ 2018-02-10 16:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi Anson,
On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
Could you please help reviewing this patch?
Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-02-10 16:25 ` Fabio Estevam
@ 2018-02-11 1:42 ` Anson Huang
-1 siblings, 0 replies; 20+ messages in thread
From: Anson Huang @ 2018-02-11 1:42 UTC (permalink / raw)
To: Fabio Estevam, Stefan Agner
Cc: rjw, viresh kumar, linux-pm, Marcel Ziswiler, max.oss.09,
linux-kernel, Octavian Purdila, Fabio Estevam, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
dl-linux-imx
Anson Huang
Best Regards!
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam@gmail.com]
> Sent: Sunday, February 11, 2018 12:26 AM
> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
> Cc: rjw@rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> linux-pm@vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
> max.oss.09@gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
>
> Hi Anson,
>
> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >
> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
> > EVK boards have an external DC regulator which needs adjustment. The
> > regulator adjustment is not covered with this change.
> >
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > ---
> > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> > 1 file changed, 8 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> > 100644
> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> > */
> > clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> > clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> > - else
> > - clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > - clk_set_parent(step_clk, secondary_sel_clk);
> > - clk_set_parent(pll1_sw_clk, step_clk);
> > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> > + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > + clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> > + else
> > + clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > + clk_set_parent(step_clk, secondary_sel_clk);
> > + clk_set_parent(pll1_sw_clk, step_clk);
> > + }
For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see where sets ARM PLL rate?
Anson.
> > } else {
> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> > clk_set_parent(pll1_sw_clk, step_clk);
>
> Could you please help reviewing this patch?
>
> Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-11 1:42 ` Anson Huang
0 siblings, 0 replies; 20+ messages in thread
From: Anson Huang @ 2018-02-11 1:42 UTC (permalink / raw)
To: linux-arm-kernel
Anson Huang
Best Regards!
> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Sunday, February 11, 2018 12:26 AM
> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
> Cc: rjw at rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> linux-pm at vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
> max.oss.09 at gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
>
> Hi Anson,
>
> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >
> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
> > EVK boards have an external DC regulator which needs adjustment. The
> > regulator adjustment is not covered with this change.
> >
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > ---
> > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> > 1 file changed, 8 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> > 100644
> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
> *policy, unsigned int index)
> > */
> > clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> > clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> > - else
> > - clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > - clk_set_parent(step_clk, secondary_sel_clk);
> > - clk_set_parent(pll1_sw_clk, step_clk);
> > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> > + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> > + clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> > + else
> > + clk_set_parent(secondary_sel_clk,
> pll2_pfd2_396m_clk);
> > + clk_set_parent(step_clk, secondary_sel_clk);
> > + clk_set_parent(pll1_sw_clk, step_clk);
> > + }
For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see where sets ARM PLL rate?
Anson.
> > } else {
> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> > clk_set_parent(pll1_sw_clk, step_clk);
>
> Could you please help reviewing this patch?
>
> Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-02-11 1:42 ` Anson Huang
@ 2018-02-11 16:17 ` Stefan Agner
-1 siblings, 0 replies; 20+ messages in thread
From: Stefan Agner @ 2018-02-11 16:17 UTC (permalink / raw)
To: Anson Huang
Cc: Fabio Estevam, rjw, viresh kumar, linux-pm, Marcel Ziswiler,
max.oss.09, linux-kernel, Octavian Purdila, Fabio Estevam,
Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
dl-linux-imx
On 11.02.2018 02:42, Anson Huang wrote:
> Anson Huang
> Best Regards!
>
>
>> -----Original Message-----
>> From: Fabio Estevam [mailto:festevam@gmail.com]
>> Sent: Sunday, February 11, 2018 12:26 AM
>> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
>> Cc: rjw@rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
>> linux-pm@vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
>> max.oss.09@gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
>> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
>> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
>> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
>> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
>> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
>> i.MX6UL/ULL
>>
>> Hi Anson,
>>
>> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
>> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> > Use PLL1 sys clock for all operating points higher than 528MHz.
>> >
>> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
>> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
>> > EVK boards have an external DC regulator which needs adjustment. The
>> > regulator adjustment is not covered with this change.
>> >
>> > Signed-off-by: Stefan Agner <stefan@agner.ch>
>> > ---
>> > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> > 1 file changed, 8 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
>> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
>> > 100644
>> > --- a/drivers/cpufreq/imx6q-cpufreq.c
>> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
>> *policy, unsigned int index)
>> > */
>> > clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> > clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> > - else
>> > - clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > - clk_set_parent(step_clk, secondary_sel_clk);
>> > - clk_set_parent(pll1_sw_clk, step_clk);
>> > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> > + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > + clk_set_parent(secondary_sel_clk,
>> pll2_bus_clk);
>> > + else
>> > + clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > + clk_set_parent(step_clk, secondary_sel_clk);
>> > + clk_set_parent(pll1_sw_clk, step_clk);
>> > + }
>
> For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> where sets ARM PLL rate?
This is done unconditionally after the if statement:
if (of_machine_is_compatible("fsl,imx6ul") ||
of_machine_is_compatible("fsl,imx6ull")) {
/*
* When changing pll1_sw_clk's parent to pll1_sys_clk,
* CPU may run at higher than 528MHz, this will lead to
* the system unstable if the voltage is lower than the
* voltage of 528MHz, so lower the CPU frequency to one
* half before changing CPU frequency.
*/
clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
clk_set_parent(pll1_sw_clk, pll1_sys_clk);
if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
clk_set_parent(secondary_sel_clk, pll2_bus_clk);
else
clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
clk_set_parent(step_clk, secondary_sel_clk);
clk_set_parent(pll1_sw_clk, step_clk);
}
} else {
clk_set_parent(step_clk, pll2_pfd2_396m_clk);
clk_set_parent(pll1_sw_clk, step_clk);
if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
clk_set_rate(pll1_sys_clk, new_freq * 1000);
clk_set_parent(pll1_sw_clk, pll1_sys_clk);
} else {
/* pll1_sys needs to be enabled for divider rate change to work. */
pll1_sys_temp_enabled = true;
clk_prepare_enable(pll1_sys_clk);
}
}
/* Ensure the arm clock divider is what we expect */
ret = clk_set_rate(arm_clk, new_freq * 1000);
--
Stefan
>
> Anson.
>
>> > } else {
>> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> > clk_set_parent(pll1_sw_clk, step_clk);
>>
>> Could you please help reviewing this patch?
>>
>> Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-11 16:17 ` Stefan Agner
0 siblings, 0 replies; 20+ messages in thread
From: Stefan Agner @ 2018-02-11 16:17 UTC (permalink / raw)
To: linux-arm-kernel
On 11.02.2018 02:42, Anson Huang wrote:
> Anson Huang
> Best Regards!
>
>
>> -----Original Message-----
>> From: Fabio Estevam [mailto:festevam at gmail.com]
>> Sent: Sunday, February 11, 2018 12:26 AM
>> To: Stefan Agner <stefan@agner.ch>; Anson Huang <anson.huang@nxp.com>
>> Cc: rjw at rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
>> linux-pm at vger.kernel.org; Marcel Ziswiler <marcel.ziswiler@toradex.com>;
>> max.oss.09 at gmail.com; linux-kernel <linux-kernel@vger.kernel.org>; Octavian
>> Purdila <octavian.purdila@nxp.com>; Fabio Estevam
>> <fabio.estevam@nxp.com>; Shawn Guo <shawnguo@kernel.org>; moderated
>> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
>> <linux-arm-kernel@lists.infradead.org>; dl-linux-imx <linux-imx@nxp.com>
>> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
>> i.MX6UL/ULL
>>
>> Hi Anson,
>>
>> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
>> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> > Use PLL1 sys clock for all operating points higher than 528MHz.
>> >
>> > Note: For higher operating points VDD_SOC_IN needs to be 125mV higher
>> > than the ARM set-point (see datasheet). Specifically, the i.MX6UL/ULL
>> > EVK boards have an external DC regulator which needs adjustment. The
>> > regulator adjustment is not covered with this change.
>> >
>> > Signed-off-by: Stefan Agner <stefan@agner.ch>
>> > ---
>> > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> > 1 file changed, 8 insertions(+), 6 deletions(-)
>> >
>> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
>> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
>> > 100644
>> > --- a/drivers/cpufreq/imx6q-cpufreq.c
>> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy
>> *policy, unsigned int index)
>> > */
>> > clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> > clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> > - else
>> > - clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > - clk_set_parent(step_clk, secondary_sel_clk);
>> > - clk_set_parent(pll1_sw_clk, step_clk);
>> > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> > + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> > + clk_set_parent(secondary_sel_clk,
>> pll2_bus_clk);
>> > + else
>> > + clk_set_parent(secondary_sel_clk,
>> pll2_pfd2_396m_clk);
>> > + clk_set_parent(step_clk, secondary_sel_clk);
>> > + clk_set_parent(pll1_sw_clk, step_clk);
>> > + }
>
> For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> where sets ARM PLL rate?
This is done unconditionally after the if statement:
if (of_machine_is_compatible("fsl,imx6ul") ||
of_machine_is_compatible("fsl,imx6ull")) {
/*
* When changing pll1_sw_clk's parent to pll1_sys_clk,
* CPU may run at higher than 528MHz, this will lead to
* the system unstable if the voltage is lower than the
* voltage of 528MHz, so lower the CPU frequency to one
* half before changing CPU frequency.
*/
clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
clk_set_parent(pll1_sw_clk, pll1_sys_clk);
if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
clk_set_parent(secondary_sel_clk, pll2_bus_clk);
else
clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
clk_set_parent(step_clk, secondary_sel_clk);
clk_set_parent(pll1_sw_clk, step_clk);
}
} else {
clk_set_parent(step_clk, pll2_pfd2_396m_clk);
clk_set_parent(pll1_sw_clk, step_clk);
if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
clk_set_rate(pll1_sys_clk, new_freq * 1000);
clk_set_parent(pll1_sw_clk, pll1_sys_clk);
} else {
/* pll1_sys needs to be enabled for divider rate change to work. */
pll1_sys_temp_enabled = true;
clk_prepare_enable(pll1_sys_clk);
}
}
/* Ensure the arm clock divider is what we expect */
ret = clk_set_rate(arm_clk, new_freq * 1000);
--
Stefan
>
> Anson.
>
>> > } else {
>> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> > clk_set_parent(pll1_sw_clk, step_clk);
>>
>> Could you please help reviewing this patch?
>>
>> Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread* RE: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-02-11 16:17 ` Stefan Agner
@ 2018-02-12 7:24 ` Anson Huang
-1 siblings, 0 replies; 20+ messages in thread
From: Anson Huang @ 2018-02-12 7:24 UTC (permalink / raw)
To: Stefan Agner
Cc: Fabio Estevam, rjw, viresh kumar, linux-pm, Marcel Ziswiler,
max.oss.09, linux-kernel, Octavian Purdila, Fabio Estevam,
Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
dl-linux-imx
Anson Huang
Best Regards!
> -----Original Message-----
> From: Stefan Agner [mailto:stefan@agner.ch]
> Sent: Monday, February 12, 2018 12:18 AM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>; rjw@rjwysocki.net; viresh kumar
> <viresh.kumar@linaro.org>; linux-pm@vger.kernel.org; Marcel Ziswiler
> <marcel.ziswiler@toradex.com>; max.oss.09@gmail.com; linux-kernel
> <linux-kernel@vger.kernel.org>; Octavian Purdila <octavian.purdila@nxp.com>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
>
> On 11.02.2018 02:42, Anson Huang wrote:
> > Anson Huang
> > Best Regards!
> >
> >
> >> -----Original Message-----
> >> From: Fabio Estevam [mailto:festevam@gmail.com]
> >> Sent: Sunday, February 11, 2018 12:26 AM
> >> To: Stefan Agner <stefan@agner.ch>; Anson Huang
> <anson.huang@nxp.com>
> >> Cc: rjw@rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> >> linux-pm@vger.kernel.org; Marcel Ziswiler
> >> <marcel.ziswiler@toradex.com>; max.oss.09@gmail.com; linux-kernel
> >> <linux-kernel@vger.kernel.org>; Octavian Purdila
> >> <octavian.purdila@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> >> Shawn Guo <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX /
> >> MXC ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>;
> >> dl-linux-imx <linux-imx@nxp.com>
> >> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> >> i.MX6UL/ULL
> >>
> >> Hi Anson,
> >>
> >> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> >> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> >> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >> >
> >> > Note: For higher operating points VDD_SOC_IN needs to be 125mV
> >> > higher than the ARM set-point (see datasheet). Specifically, the
> >> > i.MX6UL/ULL EVK boards have an external DC regulator which needs
> >> > adjustment. The regulator adjustment is not covered with this change.
> >> >
> >> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> >> > ---
> >> > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> >> > 1 file changed, 8 insertions(+), 6 deletions(-)
> >> >
> >> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> >> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> >> > 100644
> >> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> >> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> >> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct
> >> > cpufreq_policy
> >> *policy, unsigned int index)
> >> > */
> >> > clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> >> > clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> >> > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> >> > - clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> >> > - else
> >> > - clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > - clk_set_parent(step_clk, secondary_sel_clk);
> >> > - clk_set_parent(pll1_sw_clk, step_clk);
> >> > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> >> > + if (freq_hz >
> clk_get_rate(pll2_pfd2_396m_clk))
> >> > + clk_set_parent(secondary_sel_clk,
> >> pll2_bus_clk);
> >> > + else
> >> > + clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > + clk_set_parent(step_clk, secondary_sel_clk);
> >> > + clk_set_parent(pll1_sw_clk, step_clk);
> >> > + }
> >
> > For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> > where sets ARM PLL rate?
>
> This is done unconditionally after the if statement:
>
> if (of_machine_is_compatible("fsl,imx6ul") ||
> of_machine_is_compatible("fsl,imx6ull")) {
> /*
> * When changing pll1_sw_clk's parent to pll1_sys_clk,
> * CPU may run at higher than 528MHz, this will lead to
> * the system unstable if the voltage is lower than the
> * voltage of 528MHz, so lower the CPU frequency to one
> * half before changing CPU frequency.
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> else
> clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> clk_set_parent(step_clk, secondary_sel_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
> clk_set_rate(pll1_sys_clk, new_freq * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> } else {
> /* pll1_sys needs to be enabled for divider rate change to work.
> */
> pll1_sys_temp_enabled = true;
> clk_prepare_enable(pll1_sys_clk);
> }
> }
>
> /* Ensure the arm clock divider is what we expect */
> ret = clk_set_rate(arm_clk, new_freq * 1000);
>
>
> --
> Stefan
Thanks, I see the CLK_SET_RATE_PARENT flag is set for arm clk.
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Anson.
>
>
>
> >
> > Anson.
> >
> >> > } else {
> >> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> >> > clk_set_parent(pll1_sw_clk, step_clk);
> >>
> >> Could you please help reviewing this patch?
> >>
> >> Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-12 7:24 ` Anson Huang
0 siblings, 0 replies; 20+ messages in thread
From: Anson Huang @ 2018-02-12 7:24 UTC (permalink / raw)
To: linux-arm-kernel
Anson Huang
Best Regards!
> -----Original Message-----
> From: Stefan Agner [mailto:stefan at agner.ch]
> Sent: Monday, February 12, 2018 12:18 AM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: Fabio Estevam <festevam@gmail.com>; rjw at rjwysocki.net; viresh kumar
> <viresh.kumar@linaro.org>; linux-pm at vger.kernel.org; Marcel Ziswiler
> <marcel.ziswiler@toradex.com>; max.oss.09 at gmail.com; linux-kernel
> <linux-kernel@vger.kernel.org>; Octavian Purdila <octavian.purdila@nxp.com>;
> Fabio Estevam <fabio.estevam@nxp.com>; Shawn Guo
> <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX / MXC ARM
> ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; dl-linux-imx
> <linux-imx@nxp.com>
> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> i.MX6UL/ULL
>
> On 11.02.2018 02:42, Anson Huang wrote:
> > Anson Huang
> > Best Regards!
> >
> >
> >> -----Original Message-----
> >> From: Fabio Estevam [mailto:festevam at gmail.com]
> >> Sent: Sunday, February 11, 2018 12:26 AM
> >> To: Stefan Agner <stefan@agner.ch>; Anson Huang
> <anson.huang@nxp.com>
> >> Cc: rjw at rjwysocki.net; viresh kumar <viresh.kumar@linaro.org>;
> >> linux-pm at vger.kernel.org; Marcel Ziswiler
> >> <marcel.ziswiler@toradex.com>; max.oss.09 at gmail.com; linux-kernel
> >> <linux-kernel@vger.kernel.org>; Octavian Purdila
> >> <octavian.purdila@nxp.com>; Fabio Estevam <fabio.estevam@nxp.com>;
> >> Shawn Guo <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX /
> >> MXC ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>;
> >> dl-linux-imx <linux-imx@nxp.com>
> >> Subject: Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for
> >> i.MX6UL/ULL
> >>
> >> Hi Anson,
> >>
> >> On Thu, Jan 18, 2018 at 9:58 PM, Stefan Agner <stefan@agner.ch> wrote:
> >> > Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> >> > Use PLL1 sys clock for all operating points higher than 528MHz.
> >> >
> >> > Note: For higher operating points VDD_SOC_IN needs to be 125mV
> >> > higher than the ARM set-point (see datasheet). Specifically, the
> >> > i.MX6UL/ULL EVK boards have an external DC regulator which needs
> >> > adjustment. The regulator adjustment is not covered with this change.
> >> >
> >> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> >> > ---
> >> > drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> >> > 1 file changed, 8 insertions(+), 6 deletions(-)
> >> >
> >> > diff --git a/drivers/cpufreq/imx6q-cpufreq.c
> >> > b/drivers/cpufreq/imx6q-cpufreq.c index 628fe899cb48..840f6386c780
> >> > 100644
> >> > --- a/drivers/cpufreq/imx6q-cpufreq.c
> >> > +++ b/drivers/cpufreq/imx6q-cpufreq.c
> >> > @@ -114,12 +114,14 @@ static int imx6q_set_target(struct
> >> > cpufreq_policy
> >> *policy, unsigned int index)
> >> > */
> >> > clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> >> > clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> >> > - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> >> > - clk_set_parent(secondary_sel_clk,
> pll2_bus_clk);
> >> > - else
> >> > - clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > - clk_set_parent(step_clk, secondary_sel_clk);
> >> > - clk_set_parent(pll1_sw_clk, step_clk);
> >> > + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> >> > + if (freq_hz >
> clk_get_rate(pll2_pfd2_396m_clk))
> >> > + clk_set_parent(secondary_sel_clk,
> >> pll2_bus_clk);
> >> > + else
> >> > + clk_set_parent(secondary_sel_clk,
> >> pll2_pfd2_396m_clk);
> >> > + clk_set_parent(step_clk, secondary_sel_clk);
> >> > + clk_set_parent(pll1_sw_clk, step_clk);
> >> > + }
> >
> > For cpufreq > 528MHz, ARM PLL needs to be set_rate, I did NOT see
> > where sets ARM PLL rate?
>
> This is done unconditionally after the if statement:
>
> if (of_machine_is_compatible("fsl,imx6ul") ||
> of_machine_is_compatible("fsl,imx6ull")) {
> /*
> * When changing pll1_sw_clk's parent to pll1_sys_clk,
> * CPU may run at higher than 528MHz, this will lead to
> * the system unstable if the voltage is lower than the
> * voltage of 528MHz, so lower the CPU frequency to one
> * half before changing CPU frequency.
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> else
> clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> clk_set_parent(step_clk, secondary_sel_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk)) {
> clk_set_rate(pll1_sys_clk, new_freq * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> } else {
> /* pll1_sys needs to be enabled for divider rate change to work.
> */
> pll1_sys_temp_enabled = true;
> clk_prepare_enable(pll1_sys_clk);
> }
> }
>
> /* Ensure the arm clock divider is what we expect */
> ret = clk_set_rate(arm_clk, new_freq * 1000);
>
>
> --
> Stefan
Thanks, I see the CLK_SET_RATE_PARENT flag is set for arm clk.
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Anson.
>
>
>
> >
> > Anson.
> >
> >> > } else {
> >> > clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> >> > clk_set_parent(pll1_sw_clk, step_clk);
> >>
> >> Could you please help reviewing this patch?
> >>
> >> Thanks
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-01-18 23:58 ` Stefan Agner
@ 2018-02-12 8:53 ` Viresh Kumar
-1 siblings, 0 replies; 20+ messages in thread
From: Viresh Kumar @ 2018-02-12 8:53 UTC (permalink / raw)
To: Stefan Agner
Cc: rjw, fabio.estevam, octavian.purdila, shawnguo, max.oss.09,
marcel.ziswiler, linux-pm, linux-arm-kernel, linux-kernel
On 19-01-18, 00:58, Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-12 8:53 ` Viresh Kumar
0 siblings, 0 replies; 20+ messages in thread
From: Viresh Kumar @ 2018-02-12 8:53 UTC (permalink / raw)
To: linux-arm-kernel
On 19-01-18, 00:58, Stefan Agner wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-01-18 23:58 ` Stefan Agner
@ 2018-02-12 10:18 ` Rafael J. Wysocki
-1 siblings, 0 replies; 20+ messages in thread
From: Rafael J. Wysocki @ 2018-02-12 10:18 UTC (permalink / raw)
To: Stefan Agner
Cc: Rafael J. Wysocki, Viresh Kumar, Fabio Estevam, Octavian Purdila,
Shawn Guo, max.oss.09, marcel.ziswiler, Linux PM,
linux-arm-kernel, Linux Kernel Mailing List
On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Can you please rebase this on top of 4.16-rc1? It doesn't apply for me as is.
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> --
> 2.15.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-12 10:18 ` Rafael J. Wysocki
0 siblings, 0 replies; 20+ messages in thread
From: Rafael J. Wysocki @ 2018-02-12 10:18 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
> Use PLL1 sys clock for all operating points higher than 528MHz.
>
> Note: For higher operating points VDD_SOC_IN needs to be 125mV
> higher than the ARM set-point (see datasheet). Specifically, the
> i.MX6UL/ULL EVK boards have an external DC regulator which needs
> adjustment. The regulator adjustment is not covered with this
> change.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Can you please rebase this on top of 4.16-rc1? It doesn't apply for me as is.
> ---
> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
> index 628fe899cb48..840f6386c780 100644
> --- a/drivers/cpufreq/imx6q-cpufreq.c
> +++ b/drivers/cpufreq/imx6q-cpufreq.c
> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
> */
> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> - else
> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> - clk_set_parent(step_clk, secondary_sel_clk);
> - clk_set_parent(pll1_sw_clk, step_clk);
> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
> + else
> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
> + clk_set_parent(step_clk, secondary_sel_clk);
> + clk_set_parent(pll1_sw_clk, step_clk);
> + }
> } else {
> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
> clk_set_parent(pll1_sw_clk, step_clk);
> --
> 2.15.1
>
^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
2018-02-12 10:18 ` Rafael J. Wysocki
@ 2018-02-12 12:01 ` Stefan Agner
-1 siblings, 0 replies; 20+ messages in thread
From: Stefan Agner @ 2018-02-12 12:01 UTC (permalink / raw)
To: Rafael J. Wysocki, anson.huang
Cc: Rafael J. Wysocki, Viresh Kumar, Fabio Estevam, Octavian Purdila,
Shawn Guo, max.oss.09, marcel.ziswiler, Linux PM,
linux-arm-kernel, Linux Kernel Mailing List, rjwysocki
On 12.02.2018 11:18, Rafael J. Wysocki wrote:
> On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Can you please rebase this on top of 4.16-rc1? It doesn't apply for me as is.
>
Oh I see, Anson actually already submitted a patch which makes higher
CPU rates working.
My solution is slightly different in that it avoids unnecessary parent
changes...
I will rework this patch to apply this simplification to the current
state of the driver.
--
Stefan
>> ---
>> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>> */
>> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> - else
>> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> - clk_set_parent(step_clk, secondary_sel_clk);
>> - clk_set_parent(pll1_sw_clk, step_clk);
>> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> + else
>> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> + clk_set_parent(step_clk, secondary_sel_clk);
>> + clk_set_parent(pll1_sw_clk, step_clk);
>> + }
>> } else {
>> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> clk_set_parent(pll1_sw_clk, step_clk);
>> --
>> 2.15.1
>>
^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH] cpufreq: imx6q: support frequencies >528MHz for i.MX6UL/ULL
@ 2018-02-12 12:01 ` Stefan Agner
0 siblings, 0 replies; 20+ messages in thread
From: Stefan Agner @ 2018-02-12 12:01 UTC (permalink / raw)
To: linux-arm-kernel
On 12.02.2018 11:18, Rafael J. Wysocki wrote:
> On Fri, Jan 19, 2018 at 12:58 AM, Stefan Agner <stefan@agner.ch> wrote:
>> Depending on SKU i.MX6UL/i.MX6ULL support frequencies up to 900MHz.
>> Use PLL1 sys clock for all operating points higher than 528MHz.
>>
>> Note: For higher operating points VDD_SOC_IN needs to be 125mV
>> higher than the ARM set-point (see datasheet). Specifically, the
>> i.MX6UL/ULL EVK boards have an external DC regulator which needs
>> adjustment. The regulator adjustment is not covered with this
>> change.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> Can you please rebase this on top of 4.16-rc1? It doesn't apply for me as is.
>
Oh I see, Anson actually already submitted a patch which makes higher
CPU rates working.
My solution is slightly different in that it avoids unnecessary parent
changes...
I will rework this patch to apply this simplification to the current
state of the driver.
--
Stefan
>> ---
>> drivers/cpufreq/imx6q-cpufreq.c | 14 ++++++++------
>> 1 file changed, 8 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
>> index 628fe899cb48..840f6386c780 100644
>> --- a/drivers/cpufreq/imx6q-cpufreq.c
>> +++ b/drivers/cpufreq/imx6q-cpufreq.c
>> @@ -114,12 +114,14 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
>> */
>> clk_set_rate(arm_clk, (old_freq >> 1) * 1000);
>> clk_set_parent(pll1_sw_clk, pll1_sys_clk);
>> - if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> - clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> - else
>> - clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> - clk_set_parent(step_clk, secondary_sel_clk);
>> - clk_set_parent(pll1_sw_clk, step_clk);
>> + if (freq_hz <= clk_get_rate(pll2_bus_clk)) {
>> + if (freq_hz > clk_get_rate(pll2_pfd2_396m_clk))
>> + clk_set_parent(secondary_sel_clk, pll2_bus_clk);
>> + else
>> + clk_set_parent(secondary_sel_clk, pll2_pfd2_396m_clk);
>> + clk_set_parent(step_clk, secondary_sel_clk);
>> + clk_set_parent(pll1_sw_clk, step_clk);
>> + }
>> } else {
>> clk_set_parent(step_clk, pll2_pfd2_396m_clk);
>> clk_set_parent(pll1_sw_clk, step_clk);
>> --
>> 2.15.1
>>
^ permalink raw reply [flat|nested] 20+ messages in thread