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From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
	peter.maydell@linaro.org
Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
	wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com,
	palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org
Subject: Re: [RFC PATCH 6/8] riscv: Add configure script
Date: Wed, 20 May 2020 09:45:55 +0800	[thread overview]
Message-ID: <6aa1a054-4ce9-2794-7a52-236f4a38df2d@c-sky.com> (raw)
In-Reply-To: <a434ed23-5102-b39b-8fff-0f60e493e488@linaro.org>


On 2020/5/12 2:06, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +++ b/configure
>> @@ -58,6 +58,8 @@ guess_arch() {
>>           ARCH="m68k"
>>       elif check_define __powerpc64__ ; then
>>           ARCH="ppc64"
>> +    elif check_define __riscv ; then
>> +        ARCH="riscv64"
>>       else
>>           echo "This cpu is not supported by risu. Try -h. " >&2
>>           exit 1
> Why "riscv64" and not "riscv"?
>
> You can't really say more without checking __riscv_xlen.
Thanks for point it out. I will add support for RV32 next patch set.

Zhiwei
>
> r~



WARNING: multiple messages have this Message-ID (diff)
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: Richard Henderson <richard.henderson@linaro.org>,
	peter.maydell@linaro.org
Cc: alistair23@gmail.com, palmer@dabbelt.com,
	wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com,
	qemu-devel@nongnu.org, alex.bennee@linaro.org,
	qemu-riscv@nongnu.org
Subject: Re: [RFC PATCH 6/8] riscv: Add configure script
Date: Wed, 20 May 2020 09:45:55 +0800	[thread overview]
Message-ID: <6aa1a054-4ce9-2794-7a52-236f4a38df2d@c-sky.com> (raw)
In-Reply-To: <a434ed23-5102-b39b-8fff-0f60e493e488@linaro.org>


On 2020/5/12 2:06, Richard Henderson wrote:
> On 4/30/20 12:21 AM, LIU Zhiwei wrote:
>> +++ b/configure
>> @@ -58,6 +58,8 @@ guess_arch() {
>>           ARCH="m68k"
>>       elif check_define __powerpc64__ ; then
>>           ARCH="ppc64"
>> +    elif check_define __riscv ; then
>> +        ARCH="riscv64"
>>       else
>>           echo "This cpu is not supported by risu. Try -h. " >&2
>>           exit 1
> Why "riscv64" and not "riscv"?
>
> You can't really say more without checking __riscv_xlen.
Thanks for point it out. I will add support for RV32 next patch set.

Zhiwei
>
> r~



  reply	other threads:[~2020-05-20  1:46 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30  7:21 [RFC PATCH 0/8] RISCV risu porting LIU Zhiwei
2020-04-30  7:21 ` LIU Zhiwei
2020-04-30  7:21 ` [RFC PATCH 1/8] riscv: Add RV64I instructions description LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 16:39   ` Richard Henderson
2020-05-11 16:39     ` Richard Henderson
2020-05-20  2:41     ` LIU Zhiwei
2020-05-20  2:41       ` LIU Zhiwei
2020-05-20  5:39       ` Richard Henderson
2020-05-20  5:39         ` Richard Henderson
2020-04-30  7:21 ` [RFC PATCH 2/8] riscv: Generate payload scripts LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 17:40   ` Richard Henderson
2020-05-11 17:40     ` Richard Henderson
2020-05-20  2:37     ` LIU Zhiwei
2020-05-20  2:37       ` LIU Zhiwei
2020-05-20  5:41       ` Richard Henderson
2020-05-20  5:41         ` Richard Henderson
2020-05-20  9:06         ` LIU Zhiwei
2020-05-20  9:06           ` LIU Zhiwei
2020-04-30  7:21 ` [RFC PATCH 3/8] riscv: Define riscv struct reginfo LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 17:42   ` Richard Henderson
2020-05-11 17:42     ` Richard Henderson
2020-04-30  7:21 ` [RFC PATCH 4/8] riscv: Implement payload load interfaces LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 18:03   ` Richard Henderson
2020-05-11 18:03     ` Richard Henderson
2020-05-11 18:07     ` Richard Henderson
2020-05-11 18:07       ` Richard Henderson
2020-04-30  7:21 ` [RFC PATCH 5/8] riscv: Add standard test case LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 18:04   ` Richard Henderson
2020-05-11 18:04     ` Richard Henderson
2020-04-30  7:21 ` [RFC PATCH 6/8] riscv: Add configure script LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 18:06   ` Richard Henderson
2020-05-11 18:06     ` Richard Henderson
2020-05-20  1:45     ` LIU Zhiwei [this message]
2020-05-20  1:45       ` LIU Zhiwei
2020-05-20  2:28       ` LIU Zhiwei
2020-05-20  2:28         ` LIU Zhiwei
2020-04-30  7:21 ` [RFC PATCH 7/8] riscv: Add RV64M instructions description LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 18:12   ` Richard Henderson
2020-05-11 18:12     ` Richard Henderson
2020-04-30  7:21 ` [RFC PATCH 8/8] riscv: Add RV64F " LIU Zhiwei
2020-04-30  7:21   ` LIU Zhiwei
2020-05-11 18:11   ` Richard Henderson
2020-05-11 18:11     ` Richard Henderson
2020-05-19 12:27     ` LIU Zhiwei
2020-05-19 12:27       ` LIU Zhiwei
2020-05-11 16:30 ` [RFC PATCH 0/8] RISCV risu porting Richard Henderson
2020-05-11 16:30   ` Richard Henderson
2020-05-19  9:44   ` LIU Zhiwei
2020-05-19  9:44     ` LIU Zhiwei

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