From: Auger Eric <eric.auger@redhat.com> To: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>, Jacob Pan <jacob.jun.pan@linux.intel.com>, "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>, LKML <linux-kernel@vger.kernel.org>, Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org>, Alex Williamson <alex.williamson@redhat.com> Cc: Yi Liu <yi.l.liu@intel.com>, "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, Christoph Hellwig <hch@infradead.org>, Lu Baolu <baolu.lu@linux.intel.com>, Andriy Shevchenko <andriy.shevchenko@linux.intel.com> Subject: Re: [PATCH v3 02/16] iommu: Introduce cache_invalidate API Date: Mon, 13 May 2019 18:50:52 +0200 [thread overview] Message-ID: <7807afe9-efab-9f48-4ca0-2332a7a54950@redhat.com> (raw) In-Reply-To: <44d5ba37-a9e9-cc7a-2a3a-d32b840afa29@arm.com> Hi Jean-Philippe, On 5/13/19 1:20 PM, Jean-Philippe Brucker wrote: > Hi Eric, > > On 13/05/2019 10:14, Auger Eric wrote: >> I noticed my qemu integration was currently incorrectly using PASID >> invalidation for ASID based invalidation (SMMUV3 Stage1 CMD_TLBI_NH_ASID >> invalidation command). So I think we also need ARCHID invalidation. >> Sorry for the late notice. >>> >>> +/* defines the granularity of the invalidation */ >>> +enum iommu_inv_granularity { >>> + IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */ >> IOMMU_INV_GRANU_ARCHID, /* archid-selective invalidation */ >>> + IOMMU_INV_GRANU_PASID, /* pasid-selective invalidation */ > > In terms of granularity, these values have the same meaning: invalidate > the whole address space of a context. Then you can communicate two > things using the same struct: > * If ATS is enables an Arm host needs to invalidate all ATC entries > using PASID. > * If BTM isn't used by the guest, the host needs to invalidate all TLB > entries using ARCHID. > > Rather than introducing a new granule here, could we just add an archid > field to the struct associated with IOMMU_INV_GRANU_PASID? Something like... > >>> + IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */ >>> + IOMMU_INVAL_GRANU_NR, /* number of invalidation granularities */ >>> +}; >>> + >>> +/** >>> + * Address Selective Invalidation Structure >>> + * >>> + * @flags indicates the granularity of the address-selective invalidation >>> + * - if PASID bit is set, @pasid field is populated and the invalidation >>> + * relates to cache entries tagged with this PASID and matching the >>> + * address range. >>> + * - if ARCHID bit is set, @archid is populated and the invalidation relates >>> + * to cache entries tagged with this architecture specific id and matching >>> + * the address range. >>> + * - Both PASID and ARCHID can be set as they may tag different caches. >>> + * - if neither PASID or ARCHID is set, global addr invalidation applies >>> + * - LEAF flag indicates whether only the leaf PTE caching needs to be >>> + * invalidated and other paging structure caches can be preserved. >>> + * @pasid: process address space id >>> + * @archid: architecture-specific id >>> + * @addr: first stage/level input address >>> + * @granule_size: page/block size of the mapping in bytes >>> + * @nb_granules: number of contiguous granules to be invalidated >>> + */ >>> +struct iommu_inv_addr_info { >>> +#define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0) >>> +#define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1) >>> +#define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2) >>> + __u32 flags; >>> + __u32 archid; >>> + __u64 pasid; >>> + __u64 addr; >>> + __u64 granule_size; >>> + __u64 nb_granules; >>> +}; > > struct iommu_inv_pasid_info { > #define IOMMU_INV_PASID_FLAGS_PASID (1 << 0) > #define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1) > __u32 flags; > __u32 archid; > __u64 pasid; > }; I agree it does the job now. However it looks a bit strange to do a PASID based invalidation in my case - SMMUv3 nested stage - where I don't have any PASID involved. Couldn't we call it context based invalidation then? A context can be tagged by a PASID or/and an ARCHID. Domain invalidation would invalidate all the contexts belonging to that domain. Thanks Eric > >>> + >>> +/** >>> + * First level/stage invalidation information >>> + * @cache: bitfield that allows to select which caches to invalidate >>> + * @granularity: defines the lowest granularity used for the invalidation: >>> + * domain > pasid > addr >>> + * >>> + * Not all the combinations of cache/granularity make sense: >>> + * >>> + * type | DEV_IOTLB | IOTLB | PASID | >>> + * granularity | | | cache | >>> + * -------------+---------------+---------------+---------------+ >>> + * DOMAIN | N/A | Y | Y | >> * ARCHID | N/A | Y | N/A | >> >>> + * PASID | Y | Y | Y | >>> + * ADDR | Y | Y | N/A | >>> + * >>> + * Invalidations by %IOMMU_INV_GRANU_ADDR use field @addr_info. >> * Invalidations by %IOMMU_INV_GRANU_ARCHID use field @archid. >>> + * Invalidations by %IOMMU_INV_GRANU_PASID use field @pasid. >>> + * Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument. >>> + * >>> + * If multiple cache types are invalidated simultaneously, they all >>> + * must support the used granularity. >>> + */ >>> +struct iommu_cache_invalidate_info { >>> +#define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1 >>> + __u32 version; >>> +/* IOMMU paging structure cache */ >>> +#define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */ >>> +#define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */ >>> +#define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */ >>> +#define IOMMU_CACHE_TYPE_NR (3) >>> + __u8 cache; >>> + __u8 granularity; >>> + __u8 padding[2]; >>> + union { >>> + __u64 pasid; >> __u32 archid; > > struct iommu_inv_pasid_info pasid_info; > > Thanks, > Jean > >> >> Thanks >> >> Eric >>> + struct iommu_inv_addr_info addr_info; >>> + }; >>> +}; >>> + >>> + >>> #endif /* _UAPI_IOMMU_H */ >>> >
WARNING: multiple messages have this Message-ID (diff)
From: Auger Eric <eric.auger@redhat.com> To: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>, Jacob Pan <jacob.jun.pan@linux.intel.com>, "iommu@lists.linux-foundation.org" <iommu@lists.linux-foundation.org>, LKML <linux-kernel@vger.kernel.org>, Joerg Roedel <joro@8bytes.org>, David Woodhouse <dwmw2@infradead.org>, Alex Williamson <alex.williamson@redhat.com> Cc: "Tian, Kevin" <kevin.tian@intel.com>, Raj Ashok <ashok.raj@intel.com>, Andriy Shevchenko <andriy.shevchenko@linux.intel.com> Subject: Re: [PATCH v3 02/16] iommu: Introduce cache_invalidate API Date: Mon, 13 May 2019 18:50:52 +0200 [thread overview] Message-ID: <7807afe9-efab-9f48-4ca0-2332a7a54950@redhat.com> (raw) In-Reply-To: <44d5ba37-a9e9-cc7a-2a3a-d32b840afa29@arm.com> Hi Jean-Philippe, On 5/13/19 1:20 PM, Jean-Philippe Brucker wrote: > Hi Eric, > > On 13/05/2019 10:14, Auger Eric wrote: >> I noticed my qemu integration was currently incorrectly using PASID >> invalidation for ASID based invalidation (SMMUV3 Stage1 CMD_TLBI_NH_ASID >> invalidation command). So I think we also need ARCHID invalidation. >> Sorry for the late notice. >>> >>> +/* defines the granularity of the invalidation */ >>> +enum iommu_inv_granularity { >>> + IOMMU_INV_GRANU_DOMAIN, /* domain-selective invalidation */ >> IOMMU_INV_GRANU_ARCHID, /* archid-selective invalidation */ >>> + IOMMU_INV_GRANU_PASID, /* pasid-selective invalidation */ > > In terms of granularity, these values have the same meaning: invalidate > the whole address space of a context. Then you can communicate two > things using the same struct: > * If ATS is enables an Arm host needs to invalidate all ATC entries > using PASID. > * If BTM isn't used by the guest, the host needs to invalidate all TLB > entries using ARCHID. > > Rather than introducing a new granule here, could we just add an archid > field to the struct associated with IOMMU_INV_GRANU_PASID? Something like... > >>> + IOMMU_INV_GRANU_ADDR, /* page-selective invalidation */ >>> + IOMMU_INVAL_GRANU_NR, /* number of invalidation granularities */ >>> +}; >>> + >>> +/** >>> + * Address Selective Invalidation Structure >>> + * >>> + * @flags indicates the granularity of the address-selective invalidation >>> + * - if PASID bit is set, @pasid field is populated and the invalidation >>> + * relates to cache entries tagged with this PASID and matching the >>> + * address range. >>> + * - if ARCHID bit is set, @archid is populated and the invalidation relates >>> + * to cache entries tagged with this architecture specific id and matching >>> + * the address range. >>> + * - Both PASID and ARCHID can be set as they may tag different caches. >>> + * - if neither PASID or ARCHID is set, global addr invalidation applies >>> + * - LEAF flag indicates whether only the leaf PTE caching needs to be >>> + * invalidated and other paging structure caches can be preserved. >>> + * @pasid: process address space id >>> + * @archid: architecture-specific id >>> + * @addr: first stage/level input address >>> + * @granule_size: page/block size of the mapping in bytes >>> + * @nb_granules: number of contiguous granules to be invalidated >>> + */ >>> +struct iommu_inv_addr_info { >>> +#define IOMMU_INV_ADDR_FLAGS_PASID (1 << 0) >>> +#define IOMMU_INV_ADDR_FLAGS_ARCHID (1 << 1) >>> +#define IOMMU_INV_ADDR_FLAGS_LEAF (1 << 2) >>> + __u32 flags; >>> + __u32 archid; >>> + __u64 pasid; >>> + __u64 addr; >>> + __u64 granule_size; >>> + __u64 nb_granules; >>> +}; > > struct iommu_inv_pasid_info { > #define IOMMU_INV_PASID_FLAGS_PASID (1 << 0) > #define IOMMU_INV_PASID_FLAGS_ARCHID (1 << 1) > __u32 flags; > __u32 archid; > __u64 pasid; > }; I agree it does the job now. However it looks a bit strange to do a PASID based invalidation in my case - SMMUv3 nested stage - where I don't have any PASID involved. Couldn't we call it context based invalidation then? A context can be tagged by a PASID or/and an ARCHID. Domain invalidation would invalidate all the contexts belonging to that domain. Thanks Eric > >>> + >>> +/** >>> + * First level/stage invalidation information >>> + * @cache: bitfield that allows to select which caches to invalidate >>> + * @granularity: defines the lowest granularity used for the invalidation: >>> + * domain > pasid > addr >>> + * >>> + * Not all the combinations of cache/granularity make sense: >>> + * >>> + * type | DEV_IOTLB | IOTLB | PASID | >>> + * granularity | | | cache | >>> + * -------------+---------------+---------------+---------------+ >>> + * DOMAIN | N/A | Y | Y | >> * ARCHID | N/A | Y | N/A | >> >>> + * PASID | Y | Y | Y | >>> + * ADDR | Y | Y | N/A | >>> + * >>> + * Invalidations by %IOMMU_INV_GRANU_ADDR use field @addr_info. >> * Invalidations by %IOMMU_INV_GRANU_ARCHID use field @archid. >>> + * Invalidations by %IOMMU_INV_GRANU_PASID use field @pasid. >>> + * Invalidations by %IOMMU_INV_GRANU_DOMAIN don't take any argument. >>> + * >>> + * If multiple cache types are invalidated simultaneously, they all >>> + * must support the used granularity. >>> + */ >>> +struct iommu_cache_invalidate_info { >>> +#define IOMMU_CACHE_INVALIDATE_INFO_VERSION_1 1 >>> + __u32 version; >>> +/* IOMMU paging structure cache */ >>> +#define IOMMU_CACHE_INV_TYPE_IOTLB (1 << 0) /* IOMMU IOTLB */ >>> +#define IOMMU_CACHE_INV_TYPE_DEV_IOTLB (1 << 1) /* Device IOTLB */ >>> +#define IOMMU_CACHE_INV_TYPE_PASID (1 << 2) /* PASID cache */ >>> +#define IOMMU_CACHE_TYPE_NR (3) >>> + __u8 cache; >>> + __u8 granularity; >>> + __u8 padding[2]; >>> + union { >>> + __u64 pasid; >> __u32 archid; > > struct iommu_inv_pasid_info pasid_info; > > Thanks, > Jean > >> >> Thanks >> >> Eric >>> + struct iommu_inv_addr_info addr_info; >>> + }; >>> +}; >>> + >>> + >>> #endif /* _UAPI_IOMMU_H */ >>> > _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
next prev parent reply other threads:[~2019-05-13 16:51 UTC|newest] Thread overview: 104+ messages / expand[flat|nested] mbox.gz Atom feed top 2019-05-03 22:32 [PATCH v3 00/16] Shared virtual address IOMMU and VT-d support Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 01/16] iommu: Introduce attach/detach_pasid_table API Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 02/16] iommu: Introduce cache_invalidate API Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-13 9:14 ` Auger Eric 2019-05-13 9:14 ` Auger Eric 2019-05-13 11:20 ` Jean-Philippe Brucker 2019-05-13 11:20 ` Jean-Philippe Brucker 2019-05-13 16:50 ` Auger Eric [this message] 2019-05-13 16:50 ` Auger Eric 2019-05-13 17:09 ` Jean-Philippe Brucker 2019-05-13 17:09 ` Jean-Philippe Brucker 2019-05-13 22:16 ` Jacob Pan 2019-05-13 22:16 ` Jacob Pan 2019-05-14 7:36 ` Auger Eric 2019-05-14 7:36 ` Auger Eric 2019-05-14 10:41 ` Jean-Philippe Brucker 2019-05-14 10:41 ` Jean-Philippe Brucker 2019-05-14 17:44 ` Jacob Pan 2019-05-14 17:44 ` Jacob Pan 2019-05-14 17:57 ` Jacob Pan 2019-05-14 17:57 ` Jacob Pan 2019-05-15 11:03 ` Jean-Philippe Brucker 2019-05-15 11:03 ` Jean-Philippe Brucker 2019-05-15 14:47 ` Tian, Kevin 2019-05-15 14:47 ` Tian, Kevin 2019-05-15 15:25 ` Jean-Philippe Brucker 2019-05-15 15:25 ` Jean-Philippe Brucker 2019-05-14 7:46 ` Auger Eric 2019-05-14 7:46 ` Auger Eric 2019-05-14 10:42 ` Jean-Philippe Brucker 2019-05-14 10:42 ` Jean-Philippe Brucker 2019-05-14 11:02 ` Auger Eric 2019-05-14 11:02 ` Auger Eric 2019-05-14 17:55 ` Jacob Pan 2019-05-14 17:55 ` Jacob Pan 2019-05-15 15:52 ` Jean-Philippe Brucker 2019-05-15 15:52 ` Jean-Philippe Brucker 2019-05-15 16:25 ` Jacob Pan 2019-05-15 16:25 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 03/16] iommu: Add I/O ASID allocator Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-21 8:21 ` Auger Eric 2019-05-21 8:21 ` Auger Eric 2019-05-21 17:03 ` Jacob Pan 2019-05-21 17:03 ` Jacob Pan 2019-05-22 12:19 ` Jean-Philippe Brucker 2019-05-22 12:19 ` Jean-Philippe Brucker 2019-05-21 9:41 ` Auger Eric 2019-05-21 9:41 ` Auger Eric 2019-05-21 17:05 ` Jacob Pan 2019-05-21 17:05 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 04/16] ioasid: Add custom IOASID allocator Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-21 9:55 ` Auger Eric 2019-05-21 9:55 ` Auger Eric 2019-05-22 19:42 ` Jacob Pan 2019-05-22 19:42 ` Jacob Pan 2019-05-23 7:14 ` Auger Eric 2019-05-23 7:14 ` Auger Eric 2019-05-23 15:40 ` Jacob Pan 2019-05-23 15:40 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 05/16] iommu/vt-d: Enlightened PASID allocation Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 06/16] iommu/vt-d: Add custom allocator for IOASID Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 07/16] iommu/vtd: Optimize tlb invalidation for vIOMMU Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 08/16] iommu/vt-d: Replace Intel specific PASID allocator with IOASID Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 09/16] iommu: Introduce guest PASID bind function Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-16 14:14 ` Jean-Philippe Brucker 2019-05-16 14:14 ` Jean-Philippe Brucker 2019-05-16 16:14 ` Jacob Pan 2019-05-16 16:14 ` Jacob Pan 2019-05-20 19:22 ` Jacob Pan 2019-05-20 19:22 ` Jacob Pan 2019-05-21 16:09 ` Jean-Philippe Brucker 2019-05-21 16:09 ` Jean-Philippe Brucker 2019-05-21 22:50 ` Jacob Pan 2019-05-21 22:50 ` Jacob Pan 2019-05-22 15:05 ` Jean-Philippe Brucker 2019-05-22 15:05 ` Jean-Philippe Brucker 2019-05-22 17:15 ` Jacob Pan 2019-05-22 17:15 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 10/16] iommu/vt-d: Move domain helper to header Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 11/16] iommu/vt-d: Avoid duplicated code for PASID setup Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 12/16] iommu/vt-d: Add nested translation helper function Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 13/16] iommu/vt-d: Clean up for SVM device list Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 14/16] iommu/vt-d: Add bind guest PASID support Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 15/16] iommu/vt-d: Support flushing more translation cache types Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-03 22:32 ` [PATCH v3 16/16] iommu/vt-d: Add svm/sva invalidate function Jacob Pan 2019-05-03 22:32 ` Jacob Pan 2019-05-15 16:31 ` [PATCH v3 00/16] Shared virtual address IOMMU and VT-d support Jacob Pan 2019-05-15 16:31 ` Jacob Pan
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