* [PATCH] serial: tegra: Map the iir register to default defines
@ 2017-03-29 18:48 Olliver Schinagl
2017-03-30 10:17 ` Laxman Dewangan
2017-03-30 13:42 ` Jon Hunter
0 siblings, 2 replies; 13+ messages in thread
From: Olliver Schinagl @ 2017-03-29 18:48 UTC (permalink / raw)
To: Laxman Dewangan, Greg Kroah-Hartman, Jiri Slaby, Stephen Warren,
Thierry Reding, Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel, Olliver Schinagl
The tegra serial IP seems to be following the common layout and the
interrupt ID's match up nicely. Replace the magic values to match the
common serial_reg defines, with the addition of the Tegra unique End of
Data interrupt.
Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
---
Note I do not own any tegra hardware and just noticed it while working on my
somewhat related previous patch,
"serial: Do not treat the IIR register as a bitfield"
As such, this patch can only be applied after the aforementioned patch or the
iir variable will not have its mask applied yet.
drivers/tty/serial/serial-tegra.c | 19 ++++++++++---------
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c
index 4a084161d1d2..f765999dcbfe 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -83,6 +83,8 @@
#define TEGRA_TX_PIO 1
#define TEGRA_TX_DMA 2
+#define TEGRA_UART_IIR_EOD 0x8
+
/**
* tegra_uart_chip_data: SOC specific data.
*
@@ -707,20 +709,20 @@ static irqreturn_t tegra_uart_isr(int irq, void *data)
return IRQ_HANDLED;
}
- switch ((iir >> 1) & 0x7) {
- case 0: /* Modem signal change interrupt */
+ switch (iir) {
+ case UART_IIR_MSI: /* Modem signal change interrupt */
tegra_uart_handle_modem_signal_change(u);
break;
- case 1: /* Transmit interrupt only triggered when using PIO */
+ case UART_IIR_THRI: /* Transmit interrupt only triggered when using PIO */
tup->ier_shadow &= ~UART_IER_THRI;
tegra_uart_write(tup, tup->ier_shadow, UART_IER);
tegra_uart_handle_tx_pio(tup);
break;
- case 4: /* End of data */
- case 6: /* Rx timeout */
- case 2: /* Receive */
+ case TEGRA_UART_IIR_EOD: /* End of data */
+ case UART_IIR_RX_TIMEOUT: /* Rx timeout */
+ case UART_IIR_RDI: /* Receive */
if (!is_rx_int) {
is_rx_int = true;
/* Disable Rx interrupts */
@@ -734,13 +736,12 @@ static irqreturn_t tegra_uart_isr(int irq, void *data)
}
break;
- case 3: /* Receive error */
+ case UART_IIR_RLSI: /* Receive error */
tegra_uart_decode_rx_error(tup,
tegra_uart_read(tup, UART_LSR));
break;
- case 5: /* break nothing to handle */
- case 7: /* break nothing to handle */
+ default:
break;
}
}
--
2.11.0
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH] serial: tegra: Map the iir register to default defines
2017-03-29 18:48 [PATCH] serial: tegra: Map the iir register to default defines Olliver Schinagl
@ 2017-03-30 10:17 ` Laxman Dewangan
2017-03-30 13:42 ` Jon Hunter
1 sibling, 0 replies; 13+ messages in thread
From: Laxman Dewangan @ 2017-03-30 10:17 UTC (permalink / raw)
To: Olliver Schinagl, Greg Kroah-Hartman, Jiri Slaby, Stephen Warren,
Thierry Reding, Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel, Shardar Mohammed
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End of
> Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> ---
Adding Shardar for verifications.
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] serial: tegra: Map the iir register to default defines
@ 2017-03-30 10:17 ` Laxman Dewangan
0 siblings, 0 replies; 13+ messages in thread
From: Laxman Dewangan @ 2017-03-30 10:17 UTC (permalink / raw)
To: Olliver Schinagl, Greg Kroah-Hartman, Jiri Slaby, Stephen Warren,
Thierry Reding, Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel, Shardar Mohammed
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End of
> Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> ---
Adding Shardar for verifications.
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
[parent not found: <58DCDB54.5040005-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>]
* RE: [PATCH] serial: tegra: Map the iir register to default defines
2017-03-30 10:17 ` Laxman Dewangan
@ 2017-03-31 10:07 ` Shardar Mohammed
-1 siblings, 0 replies; 13+ messages in thread
From: Shardar Mohammed @ 2017-03-31 10:07 UTC (permalink / raw)
To: Laxman Dewangan, Olliver Schinagl, Greg Kroah-Hartman,
Jiri Slaby, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: linux-serial-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Verification failed on Tegra.
Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled.
while (1) {
iir = tegra_uart_read(tup, UART_IIR);
+iir &= UART_IIR_MASK;
Thanks,
Shardar
-----Original Message-----
From: Laxman Dewangan
Sent: Thursday, March 30, 2017 3:48 PM
To: Olliver Schinagl <oliver-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org>; Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>; Jiri Slaby <jslaby-IBi9RG/b67k@public.gmane.org>; Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>; Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>; Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Shardar Mohammed <smohammed-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End
> of Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org>
> ---
Adding Shardar for verifications.
Acked-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
^ permalink raw reply [flat|nested] 13+ messages in thread
* RE: [PATCH] serial: tegra: Map the iir register to default defines
@ 2017-03-31 10:07 ` Shardar Mohammed
0 siblings, 0 replies; 13+ messages in thread
From: Shardar Mohammed @ 2017-03-31 10:07 UTC (permalink / raw)
To: Laxman Dewangan, Olliver Schinagl, Greg Kroah-Hartman,
Jiri Slaby, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel
Verification failed on Tegra.
Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled.
while (1) {
iir = tegra_uart_read(tup, UART_IIR);
+iir &= UART_IIR_MASK;
Thanks,
Shardar
-----Original Message-----
From: Laxman Dewangan
Sent: Thursday, March 30, 2017 3:48 PM
To: Olliver Schinagl <oliver@schinagl.nl>; Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Jiri Slaby <jslaby@suse.com>; Stephen Warren <swarren@wwwdotorg.org>; Thierry Reding <thierry.reding@gmail.com>; Alexandre Courbot <gnurou@gmail.com>
Cc: linux-serial@vger.kernel.org; linux-tegra@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed <smohammed@nvidia.com>
Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines
On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End
> of Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> ---
Adding Shardar for verifications.
Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] serial: tegra: Map the iir register to default defines
2017-03-31 10:07 ` Shardar Mohammed
(?)
@ 2017-03-31 10:28 ` Jon Hunter
[not found] ` <c904007d-af59-c1fa-d11f-a69c4609ff84-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
-1 siblings, 1 reply; 13+ messages in thread
From: Jon Hunter @ 2017-03-31 10:28 UTC (permalink / raw)
To: Shardar Mohammed, Laxman Dewangan, Olliver Schinagl,
Greg Kroah-Hartman, Jiri Slaby, Stephen Warren, Thierry Reding,
Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel
On 31/03/17 11:07, Shardar Mohammed wrote:
> Verification failed on Tegra.
> Fix here is, IIR should be masked with UART_IIR_MASK after reading the IIR register as on Tegra bit-6 is used for internal usage to know if FIFO mode is enabled.
> while (1) {
> iir = tegra_uart_read(tup, UART_IIR);
> +iir &= UART_IIR_MASK;
Per Olliver's original email did you pick up the other patch [0] before
applying this because that does apply the mask. I mentioned to Olliver
that this should really be a series, so it is clear that this patch is
dependent upon the other.
> -----Original Message-----
> From: Laxman Dewangan
> Sent: Thursday, March 30, 2017 3:48 PM
> To: Olliver Schinagl <oliver@schinagl.nl>; Greg Kroah-Hartman <gregkh@linuxfoundation.org>; Jiri Slaby <jslaby@suse.com>; Stephen Warren <swarren@wwwdotorg.org>; Thierry Reding <thierry.reding@gmail.com>; Alexandre Courbot <gnurou@gmail.com>
> Cc: linux-serial@vger.kernel.org; linux-tegra@vger.kernel.org; linux-kernel@vger.kernel.org; Shardar Mohammed <smohammed@nvidia.com>
> Subject: Re: [PATCH] serial: tegra: Map the iir register to default defines
>
>
> On Thursday 30 March 2017 12:18 AM, Olliver Schinagl wrote:
>> The tegra serial IP seems to be following the common layout and the
>> interrupt ID's match up nicely. Replace the magic values to match the
>> common serial_reg defines, with the addition of the Tegra unique End
>> of Data interrupt.
>>
>> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
>> ---
>
> Adding Shardar for verifications.
>
> Acked-by: Laxman Dewangan <ldewangan@nvidia.com>
Furthermore does this ACK imply that you have reviewed the other patch
this one is dependent upon?
Cheers
Jon
[0] http://marc.info/?l=linux-serial&m=149081309627392&w=2
--
nvpublic
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] serial: tegra: Map the iir register to default defines
2017-03-29 18:48 [PATCH] serial: tegra: Map the iir register to default defines Olliver Schinagl
@ 2017-03-30 13:42 ` Jon Hunter
2017-03-30 13:42 ` Jon Hunter
1 sibling, 0 replies; 13+ messages in thread
From: Jon Hunter @ 2017-03-30 13:42 UTC (permalink / raw)
To: Olliver Schinagl, Laxman Dewangan, Greg Kroah-Hartman,
Jiri Slaby, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel
On 29/03/17 19:48, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End of
> Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> ---
> Note I do not own any tegra hardware and just noticed it while working on my
> somewhat related previous patch,
> "serial: Do not treat the IIR register as a bitfield"
>
> As such, this patch can only be applied after the aforementioned patch or the
> iir variable will not have its mask applied yet.
Nit-pick. If this is the case, then this should really be part of a
patch series so it is obvious to everyone that this should only be
applied after the other patch.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] serial: tegra: Map the iir register to default defines
@ 2017-03-30 13:42 ` Jon Hunter
0 siblings, 0 replies; 13+ messages in thread
From: Jon Hunter @ 2017-03-30 13:42 UTC (permalink / raw)
To: Olliver Schinagl, Laxman Dewangan, Greg Kroah-Hartman,
Jiri Slaby, Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel
On 29/03/17 19:48, Olliver Schinagl wrote:
> The tegra serial IP seems to be following the common layout and the
> interrupt ID's match up nicely. Replace the magic values to match the
> common serial_reg defines, with the addition of the Tegra unique End of
> Data interrupt.
>
> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> ---
> Note I do not own any tegra hardware and just noticed it while working on my
> somewhat related previous patch,
> "serial: Do not treat the IIR register as a bitfield"
>
> As such, this patch can only be applied after the aforementioned patch or the
> iir variable will not have its mask applied yet.
Nit-pick. If this is the case, then this should really be part of a
patch series so it is obvious to everyone that this should only be
applied after the other patch.
Cheers
Jon
--
nvpublic
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] serial: tegra: Map the iir register to default defines
2017-03-30 13:42 ` Jon Hunter
(?)
@ 2017-03-30 15:37 ` Olliver Schinagl
2017-03-31 13:21 ` Greg Kroah-Hartman
-1 siblings, 1 reply; 13+ messages in thread
From: Olliver Schinagl @ 2017-03-30 15:37 UTC (permalink / raw)
To: Jon Hunter, Laxman Dewangan, Greg Kroah-Hartman, Jiri Slaby,
Stephen Warren, Thierry Reding, Alexandre Courbot
Cc: linux-serial, linux-tegra, linux-kernel
Hey Jon,
On March 30, 2017 3:42:19 PM CEST, Jon Hunter <jonathanh@nvidia.com> wrote:
>
>On 29/03/17 19:48, Olliver Schinagl wrote:
>> The tegra serial IP seems to be following the common layout and the
>> interrupt ID's match up nicely. Replace the magic values to match the
>> common serial_reg defines, with the addition of the Tegra unique End
>of
>> Data interrupt.
>>
>> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
>> ---
>> Note I do not own any tegra hardware and just noticed it while
>working on my
>> somewhat related previous patch,
>> "serial: Do not treat the IIR register as a bitfield"
>>
>> As such, this patch can only be applied after the aforementioned
>patch or the
>> iir variable will not have its mask applied yet.
>
>Nit-pick. If this is the case, then this should really be part of a
>patch series so it is obvious to everyone that this should only be
>applied after the other patch.
Yes, and it was, but I did not want to have the really big list of names in this much smaller group.
>
>Cheers
>Jon
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH] serial: tegra: Map the iir register to default defines
2017-03-30 15:37 ` Olliver Schinagl
@ 2017-03-31 13:21 ` Greg Kroah-Hartman
0 siblings, 0 replies; 13+ messages in thread
From: Greg Kroah-Hartman @ 2017-03-31 13:21 UTC (permalink / raw)
To: Olliver Schinagl
Cc: Jon Hunter, Laxman Dewangan, Jiri Slaby, Stephen Warren,
Thierry Reding, Alexandre Courbot, linux-serial, linux-tegra,
linux-kernel
On Thu, Mar 30, 2017 at 05:37:41PM +0200, Olliver Schinagl wrote:
> Hey Jon,
>
> On March 30, 2017 3:42:19 PM CEST, Jon Hunter <jonathanh@nvidia.com> wrote:
> >
> >On 29/03/17 19:48, Olliver Schinagl wrote:
> >> The tegra serial IP seems to be following the common layout and the
> >> interrupt ID's match up nicely. Replace the magic values to match the
> >> common serial_reg defines, with the addition of the Tegra unique End
> >of
> >> Data interrupt.
> >>
> >> Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
> >> ---
> >> Note I do not own any tegra hardware and just noticed it while
> >working on my
> >> somewhat related previous patch,
> >> "serial: Do not treat the IIR register as a bitfield"
> >>
> >> As such, this patch can only be applied after the aforementioned
> >patch or the
> >> iir variable will not have its mask applied yet.
> >
> >Nit-pick. If this is the case, then this should really be part of a
> >patch series so it is obvious to everyone that this should only be
> >applied after the other patch.
> Yes, and it was, but I did not want to have the really big list of names in this much smaller group.
Ok, this is a mess, don't send me patches that need to be applied in a
specific order, yet are not obviously linked together in a single
series.
How do you expect a maintainer to handle this type of stuff? You need
to make it _OBVIOUS_ as to what I need to do here, otherwise I will get
it wrong.
I'm going to drop all of your patches from my queue and wait for a
resend with the correct order, and ones that work properly, you can do
better than this :)
thanks,
greg k-h
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2017-03-31 13:21 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-03-29 18:48 [PATCH] serial: tegra: Map the iir register to default defines Olliver Schinagl
2017-03-30 10:17 ` Laxman Dewangan
2017-03-30 10:17 ` Laxman Dewangan
[not found] ` <58DCDB54.5040005-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-03-31 10:07 ` Shardar Mohammed
2017-03-31 10:07 ` Shardar Mohammed
2017-03-31 10:28 ` Jon Hunter
[not found] ` <c904007d-af59-c1fa-d11f-a69c4609ff84-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2017-03-31 10:42 ` Shardar Mohammed
2017-03-31 10:42 ` Shardar Mohammed
2017-03-31 11:32 ` Olliver Schinagl
2017-03-30 13:42 ` Jon Hunter
2017-03-30 13:42 ` Jon Hunter
2017-03-30 15:37 ` Olliver Schinagl
2017-03-31 13:21 ` Greg Kroah-Hartman
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