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From: Zenghui Yu <yuzenghui@huawei.com>
To: Marc Zyngier <maz@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
	<kvmarm@lists.cs.columbia.edu>, <kvm@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	"Robert Richter" <rrichter@marvell.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	"Eric Auger" <eric.auger@redhat.com>,
	James Morse <james.morse@arm.com>,
	"Julien Thierry" <julien.thierry.kdev@gmail.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>
Subject: Re: [PATCH v4 16/20] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts
Date: Mon, 2 Mar 2020 10:40:30 +0800	[thread overview]
Message-ID: <865e3cc6-19e3-a1ec-84a6-8c15ad738345@huawei.com> (raw)
In-Reply-To: <7aa668a5920b8deb8c2ee2fec3ef69b3@kernel.org>

Hi Marc,

On 2020/2/29 3:16, Marc Zyngier wrote:
> Hi Zenghui,
> 
> On 2020-02-20 03:55, Zenghui Yu wrote:
>> Hi Marc,
>>
>> On 2020/2/14 22:57, Marc Zyngier wrote:
>>> In order to let a guest buy in the new, active-less SGIs, we
>>> need to be able to switch between the two modes.
>>>
>>> Handle this by stopping all guest activity, transfer the state
>>> from one mode to the other, and resume the guest.
>>>
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>
>> [...]
>>
>>> diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
>>> index 1bc09b523486..2c9fc13e2c59 100644
>>> --- a/virt/kvm/arm/vgic/vgic-v3.c
>>> +++ b/virt/kvm/arm/vgic/vgic-v3.c
>>> @@ -540,6 +540,8 @@ int vgic_v3_map_resources(struct kvm *kvm)
>>>           goto out;
>>>       }
>>>   +    if (kvm_vgic_global_state.has_gicv4_1)
>>> +        vgic_v4_configure_vsgis(kvm);
>>>       dist->ready = true;
>>>     out:
>>
>> Is there any reason to invoke vgic_v4_configure_vsgis() here?
>> This is called on the first VCPU run, through kvm_vgic_map_resources().
>> Shouldn't the vSGI configuration only driven by a GICD_CTLR.nASSGIreq
>> writing (from guest, or from userspace maybe)?
> 
> What I'm trying to catch here is the guest that has been restored with
> nASSGIreq set. At the moment, we don't do anything on the userspace
> side, because the vmm could decide to write that particular bit
> multiple times, and switching between the two modes is expensive (not
> to mention that all the vcpus may not have been created yet).
> 
> Moving it to the first run makes all these pitfalls go away (we have the
> final nASSSGIreq value, and all the vcpus are accounted for).

So what will happen on restoration is (roughly):

  - for GICR_ISPENR0: We will restore the pending status of vSGIs into
    software pending_latch, just like what we've done for normal SGIs.
  - for GICD_CTLR.nASSGIreq: We will only record the written value.
    (Note to myself: No invocation of configure_vsgis() in uaccess_write
     callback, I previously mixed it up with the guest write callback.)
  - Finally, you choose the first vcpu run as the appropriate point to
    potentially flush the pending status to HW according to the final
    nASSGIreq value.

> 
> Does this make sense to you?

Yeah, it sounds like a good idea! And please ignore what I've replied to
patch #15, I obviously missed your intention at that time, sorry...

But can we move this hunk to some places more appropriate, for example,
put it together with the GICD_CTLR's uaccess_write change? It might make
things a bit clearer for other reviewers. :-)


Thanks,
Zenghui


WARNING: multiple messages have this Message-ID (diff)
From: Zenghui Yu <yuzenghui@huawei.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	kvm@vger.kernel.org, linux-kernel@vger.kernel.org,
	Robert Richter <rrichter@marvell.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 16/20] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts
Date: Mon, 2 Mar 2020 10:40:30 +0800	[thread overview]
Message-ID: <865e3cc6-19e3-a1ec-84a6-8c15ad738345@huawei.com> (raw)
In-Reply-To: <7aa668a5920b8deb8c2ee2fec3ef69b3@kernel.org>

Hi Marc,

On 2020/2/29 3:16, Marc Zyngier wrote:
> Hi Zenghui,
> 
> On 2020-02-20 03:55, Zenghui Yu wrote:
>> Hi Marc,
>>
>> On 2020/2/14 22:57, Marc Zyngier wrote:
>>> In order to let a guest buy in the new, active-less SGIs, we
>>> need to be able to switch between the two modes.
>>>
>>> Handle this by stopping all guest activity, transfer the state
>>> from one mode to the other, and resume the guest.
>>>
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>
>> [...]
>>
>>> diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
>>> index 1bc09b523486..2c9fc13e2c59 100644
>>> --- a/virt/kvm/arm/vgic/vgic-v3.c
>>> +++ b/virt/kvm/arm/vgic/vgic-v3.c
>>> @@ -540,6 +540,8 @@ int vgic_v3_map_resources(struct kvm *kvm)
>>>           goto out;
>>>       }
>>>   +    if (kvm_vgic_global_state.has_gicv4_1)
>>> +        vgic_v4_configure_vsgis(kvm);
>>>       dist->ready = true;
>>>     out:
>>
>> Is there any reason to invoke vgic_v4_configure_vsgis() here?
>> This is called on the first VCPU run, through kvm_vgic_map_resources().
>> Shouldn't the vSGI configuration only driven by a GICD_CTLR.nASSGIreq
>> writing (from guest, or from userspace maybe)?
> 
> What I'm trying to catch here is the guest that has been restored with
> nASSGIreq set. At the moment, we don't do anything on the userspace
> side, because the vmm could decide to write that particular bit
> multiple times, and switching between the two modes is expensive (not
> to mention that all the vcpus may not have been created yet).
> 
> Moving it to the first run makes all these pitfalls go away (we have the
> final nASSSGIreq value, and all the vcpus are accounted for).

So what will happen on restoration is (roughly):

  - for GICR_ISPENR0: We will restore the pending status of vSGIs into
    software pending_latch, just like what we've done for normal SGIs.
  - for GICD_CTLR.nASSGIreq: We will only record the written value.
    (Note to myself: No invocation of configure_vsgis() in uaccess_write
     callback, I previously mixed it up with the guest write callback.)
  - Finally, you choose the first vcpu run as the appropriate point to
    potentially flush the pending status to HW according to the final
    nASSGIreq value.

> 
> Does this make sense to you?

Yeah, it sounds like a good idea! And please ignore what I've replied to
patch #15, I obviously missed your intention at that time, sorry...

But can we move this hunk to some places more appropriate, for example,
put it together with the GICD_CTLR's uaccess_write change? It might make
things a bit clearer for other reviewers. :-)


Thanks,
Zenghui

_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm

WARNING: multiple messages have this Message-ID (diff)
From: Zenghui Yu <yuzenghui@huawei.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Jason Cooper <jason@lakedaemon.net>,
	kvm@vger.kernel.org, Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-kernel@vger.kernel.org, Eric Auger <eric.auger@redhat.com>,
	Robert Richter <rrichter@marvell.com>,
	James Morse <james.morse@arm.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	kvmarm@lists.cs.columbia.edu,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 16/20] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts
Date: Mon, 2 Mar 2020 10:40:30 +0800	[thread overview]
Message-ID: <865e3cc6-19e3-a1ec-84a6-8c15ad738345@huawei.com> (raw)
In-Reply-To: <7aa668a5920b8deb8c2ee2fec3ef69b3@kernel.org>

Hi Marc,

On 2020/2/29 3:16, Marc Zyngier wrote:
> Hi Zenghui,
> 
> On 2020-02-20 03:55, Zenghui Yu wrote:
>> Hi Marc,
>>
>> On 2020/2/14 22:57, Marc Zyngier wrote:
>>> In order to let a guest buy in the new, active-less SGIs, we
>>> need to be able to switch between the two modes.
>>>
>>> Handle this by stopping all guest activity, transfer the state
>>> from one mode to the other, and resume the guest.
>>>
>>> Signed-off-by: Marc Zyngier <maz@kernel.org>
>>
>> [...]
>>
>>> diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
>>> index 1bc09b523486..2c9fc13e2c59 100644
>>> --- a/virt/kvm/arm/vgic/vgic-v3.c
>>> +++ b/virt/kvm/arm/vgic/vgic-v3.c
>>> @@ -540,6 +540,8 @@ int vgic_v3_map_resources(struct kvm *kvm)
>>>           goto out;
>>>       }
>>>   +    if (kvm_vgic_global_state.has_gicv4_1)
>>> +        vgic_v4_configure_vsgis(kvm);
>>>       dist->ready = true;
>>>     out:
>>
>> Is there any reason to invoke vgic_v4_configure_vsgis() here?
>> This is called on the first VCPU run, through kvm_vgic_map_resources().
>> Shouldn't the vSGI configuration only driven by a GICD_CTLR.nASSGIreq
>> writing (from guest, or from userspace maybe)?
> 
> What I'm trying to catch here is the guest that has been restored with
> nASSGIreq set. At the moment, we don't do anything on the userspace
> side, because the vmm could decide to write that particular bit
> multiple times, and switching between the two modes is expensive (not
> to mention that all the vcpus may not have been created yet).
> 
> Moving it to the first run makes all these pitfalls go away (we have the
> final nASSSGIreq value, and all the vcpus are accounted for).

So what will happen on restoration is (roughly):

  - for GICR_ISPENR0: We will restore the pending status of vSGIs into
    software pending_latch, just like what we've done for normal SGIs.
  - for GICD_CTLR.nASSGIreq: We will only record the written value.
    (Note to myself: No invocation of configure_vsgis() in uaccess_write
     callback, I previously mixed it up with the guest write callback.)
  - Finally, you choose the first vcpu run as the appropriate point to
    potentially flush the pending status to HW according to the final
    nASSGIreq value.

> 
> Does this make sense to you?

Yeah, it sounds like a good idea! And please ignore what I've replied to
patch #15, I obviously missed your intention at that time, sorry...

But can we move this hunk to some places more appropriate, for example,
put it together with the GICD_CTLR's uaccess_write change? It might make
things a bit clearer for other reviewers. :-)


Thanks,
Zenghui


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2020-03-02  2:40 UTC|newest]

Thread overview: 142+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-14 14:57 [PATCH v4 00/20] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier
2020-02-14 14:57 ` Marc Zyngier
2020-02-14 14:57 ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 01/20] irqchip/gic-v4.1: Skip absent CPUs while iterating over redistributors Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-17  9:11   ` Zenghui Yu
2020-02-17  9:11     ` Zenghui Yu
2020-02-17  9:11     ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 02/20] irqchip/gic-v3: Use SGIs without active state if offered Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-17  9:18   ` Zenghui Yu
2020-02-17  9:18     ` Zenghui Yu
2020-02-17  9:18     ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 03/20] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-17  9:09   ` Zenghui Yu
2020-02-17  9:09     ` Zenghui Yu
2020-02-17  9:09     ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 04/20] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-20  3:17   ` Zenghui Yu
2020-02-20  3:17     ` Zenghui Yu
2020-02-20  3:17     ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 05/20] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-20  3:21   ` Zenghui Yu
2020-02-20  3:21     ` Zenghui Yu
2020-02-20  3:21     ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 06/20] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-18  7:25   ` Zenghui Yu
2020-02-18  7:25     ` Zenghui Yu
2020-02-18  7:25     ` Zenghui Yu
2020-02-18  9:46     ` Marc Zyngier
2020-02-18  9:46       ` Marc Zyngier
2020-02-18  9:46       ` Marc Zyngier
2020-02-20  3:25       ` Zenghui Yu
2020-02-20  3:25         ` Zenghui Yu
2020-02-20  3:25         ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 07/20] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-20  3:32   ` Zenghui Yu
2020-02-20  3:32     ` Zenghui Yu
2020-02-20  3:32     ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 08/20] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-18  7:00   ` Zenghui Yu
2020-02-18  7:00     ` Zenghui Yu
2020-02-18  7:00     ` Zenghui Yu
2020-02-18  9:27     ` Marc Zyngier
2020-02-18  9:27       ` Marc Zyngier
2020-02-18  9:27       ` Marc Zyngier
2020-02-18 15:31       ` Marc Zyngier
2020-02-18 15:31         ` Marc Zyngier
2020-02-18 15:31         ` Marc Zyngier
2020-02-19 11:50         ` Zenghui Yu
2020-02-19 11:50           ` Zenghui Yu
2020-02-19 11:50           ` Zenghui Yu
2020-02-19 15:18           ` Zenghui Yu
2020-02-19 15:18             ` Zenghui Yu
2020-02-19 15:18             ` Zenghui Yu
2020-02-20  3:11         ` Zenghui Yu
2020-02-20  3:11           ` Zenghui Yu
2020-02-20  3:11           ` Zenghui Yu
2020-02-28 19:37           ` Marc Zyngier
2020-02-28 19:37             ` Marc Zyngier
2020-02-28 19:37             ` Marc Zyngier
2020-03-01 19:00             ` Marc Zyngier
2020-03-01 19:00               ` Marc Zyngier
2020-03-01 19:00               ` Marc Zyngier
2020-03-02  8:18               ` Zenghui Yu
2020-03-02  8:18                 ` Zenghui Yu
2020-03-02  8:18                 ` Zenghui Yu
2020-03-02 12:09                 ` Marc Zyngier
2020-03-02 12:09                   ` Marc Zyngier
2020-03-02 12:09                   ` Marc Zyngier
2020-03-02 14:21                   ` Bill Barrow
2020-02-14 14:57 ` [PATCH v4 09/20] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-20  3:37   ` Zenghui Yu
2020-02-20  3:37     ` Zenghui Yu
2020-02-20  3:37     ` Zenghui Yu
2020-02-28 19:00     ` Marc Zyngier
2020-02-28 19:00       ` Marc Zyngier
2020-02-28 19:00       ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 10/20] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 11/20] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 12/20] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 13/20] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 14/20] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 15/20] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-18  8:46   ` Zenghui Yu
2020-02-18  8:46     ` Zenghui Yu
2020-02-18  8:46     ` Zenghui Yu
2020-02-18  9:41     ` Marc Zyngier
2020-02-18  9:41       ` Marc Zyngier
2020-02-18  9:41       ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 16/20] KVM: arm64: GICv4.1: Allow SGIs to switch between HW and SW interrupts Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-20  3:55   ` Zenghui Yu
2020-02-20  3:55     ` Zenghui Yu
2020-02-20  3:55     ` Zenghui Yu
2020-02-28 19:16     ` Marc Zyngier
2020-02-28 19:16       ` Marc Zyngier
2020-02-28 19:16       ` Marc Zyngier
2020-03-02  2:40       ` Zenghui Yu [this message]
2020-03-02  2:40         ` Zenghui Yu
2020-03-02  2:40         ` Zenghui Yu
2020-02-14 14:57 ` [PATCH v4 17/20] KVM: arm64: GICv4.1: Plumb SGI implementation selection in the distributor Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 18/20] KVM: arm64: GICv4.1: Reload VLPI configuration on distributor enable/disable Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 19/20] KVM: arm64: GICv4.1: Allow non-trapping WFI when using HW SGIs Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57 ` [PATCH v4 20/20] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier
2020-02-14 14:57   ` Marc Zyngier

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