From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Date: Wed, 16 Dec 2020 10:22:29 -0800 [thread overview] Message-ID: <86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1608142916.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> --- target/riscv/cpu.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,12 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Date: Wed, 16 Dec 2020 10:22:29 -0800 [thread overview] Message-ID: <86e5ccd9eae2f5d8c2257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1608142916.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> --- target/riscv/cpu.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c0a326c843..9c064f3094 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -44,6 +44,12 @@ #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#if defined(TARGET_RISCV32) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 +#elif defined(TARGET_RISCV64) +# define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 +#endif + #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) -- 2.29.2
next prev parent reply other threads:[~2020-12-16 18:26 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-16 18:22 [PATCH v4 00/16] RISC-V: Start to remove xlen preprocess Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` Alistair Francis [this message] 2020-12-16 18:22 ` [PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis 2020-12-16 18:22 ` [PATCH v4 03/16] riscv: spike: Remove target macro conditionals Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 04/16] riscv: virt: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 05/16] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 06/16] hw/riscv: virt: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 07/16] hw/riscv: spike: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 08/16] hw/riscv: sifive_u: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-17 6:33 ` Bin Meng 2020-12-17 6:33 ` Bin Meng 2020-12-16 18:22 ` [PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 11/16] target/riscv: Specify the XLEN for CPUs Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-17 6:45 ` Bin Meng 2020-12-17 6:45 ` Bin Meng 2020-12-16 18:22 ` [PATCH v4 13/16] target/riscv: cpu_helper: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-17 6:36 ` Bin Meng 2020-12-17 6:36 ` Bin Meng 2020-12-16 18:23 ` [PATCH v4 14/16] target/riscv: csr: " Alistair Francis 2020-12-16 18:23 ` Alistair Francis 2020-12-17 6:37 ` Bin Meng 2020-12-17 6:37 ` Bin Meng 2020-12-16 18:23 ` [PATCH v4 15/16] target/riscv: cpu: Set XLEN independently from target Alistair Francis 2020-12-16 18:23 ` Alistair Francis 2020-12-16 18:23 ` [PATCH v4 16/16] hw/riscv: Use the CPU to determine if 32-bit Alistair Francis 2020-12-16 18:23 ` Alistair Francis 2020-12-16 18:51 ` Richard Henderson 2020-12-16 18:51 ` Richard Henderson 2020-12-17 6:44 ` Bin Meng 2020-12-17 6:44 ` Bin Meng 2020-12-17 13:58 ` Richard Henderson 2020-12-17 13:58 ` Richard Henderson 2020-12-17 17:25 ` Palmer Dabbelt 2020-12-17 17:25 ` Palmer Dabbelt 2020-12-17 17:42 ` Alistair Francis 2020-12-17 17:42 ` Alistair Francis
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