From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v4 14/16] target/riscv: csr: Remove compile time XLEN checks
Date: Thu, 17 Dec 2020 14:37:24 +0800 [thread overview]
Message-ID: <CAEUhbmVe+R3EPqQ-Ni0YB_1uuUd+U0xFGwbovYOmoVn19codsg@mail.gmail.com> (raw)
In-Reply-To: <7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com>
On Thu, Dec 17, 2020 at 2:23 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> ---
> target/riscv/cpu_bits.h | 4 +-
> target/riscv/csr.c | 176 +++++++++++++++++++++-------------------
> 2 files changed, 92 insertions(+), 88 deletions(-)
>
Tested-by: Bin Meng <bin.meng@windriver.com>
WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair.francis@wdc.com>
Cc: "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
"open list:RISC-V" <qemu-riscv@nongnu.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair23@gmail.com>
Subject: Re: [PATCH v4 14/16] target/riscv: csr: Remove compile time XLEN checks
Date: Thu, 17 Dec 2020 14:37:24 +0800 [thread overview]
Message-ID: <CAEUhbmVe+R3EPqQ-Ni0YB_1uuUd+U0xFGwbovYOmoVn19codsg@mail.gmail.com> (raw)
In-Reply-To: <7371180970b7db310d3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com>
On Thu, Dec 17, 2020 at 2:23 AM Alistair Francis
<alistair.francis@wdc.com> wrote:
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
> ---
> target/riscv/cpu_bits.h | 4 +-
> target/riscv/csr.c | 176 +++++++++++++++++++++-------------------
> 2 files changed, 92 insertions(+), 88 deletions(-)
>
Tested-by: Bin Meng <bin.meng@windriver.com>
next prev parent reply other threads:[~2020-12-17 6:39 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-16 18:22 [PATCH v4 00/16] RISC-V: Start to remove xlen preprocess Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 03/16] riscv: spike: Remove target macro conditionals Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 04/16] riscv: virt: " Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 05/16] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 06/16] hw/riscv: virt: " Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 07/16] hw/riscv: spike: " Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 08/16] hw/riscv: sifive_u: " Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-17 6:33 ` Bin Meng
2020-12-17 6:33 ` Bin Meng
2020-12-16 18:22 ` [PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 11/16] target/riscv: Specify the XLEN for CPUs Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-16 18:22 ` [PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-17 6:45 ` Bin Meng
2020-12-17 6:45 ` Bin Meng
2020-12-16 18:22 ` [PATCH v4 13/16] target/riscv: cpu_helper: " Alistair Francis
2020-12-16 18:22 ` Alistair Francis
2020-12-17 6:36 ` Bin Meng
2020-12-17 6:36 ` Bin Meng
2020-12-16 18:23 ` [PATCH v4 14/16] target/riscv: csr: " Alistair Francis
2020-12-16 18:23 ` Alistair Francis
2020-12-17 6:37 ` Bin Meng [this message]
2020-12-17 6:37 ` Bin Meng
2020-12-16 18:23 ` [PATCH v4 15/16] target/riscv: cpu: Set XLEN independently from target Alistair Francis
2020-12-16 18:23 ` Alistair Francis
2020-12-16 18:23 ` [PATCH v4 16/16] hw/riscv: Use the CPU to determine if 32-bit Alistair Francis
2020-12-16 18:23 ` Alistair Francis
2020-12-16 18:51 ` Richard Henderson
2020-12-16 18:51 ` Richard Henderson
2020-12-17 6:44 ` Bin Meng
2020-12-17 6:44 ` Bin Meng
2020-12-17 13:58 ` Richard Henderson
2020-12-17 13:58 ` Richard Henderson
2020-12-17 17:25 ` Palmer Dabbelt
2020-12-17 17:25 ` Palmer Dabbelt
2020-12-17 17:42 ` Alistair Francis
2020-12-17 17:42 ` Alistair Francis
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