From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: alistair.francis@wdc.com, bmeng.cn@gmail.com, palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v4 06/16] hw/riscv: virt: Remove compile time XLEN checks Date: Wed, 16 Dec 2020 10:22:40 -0800 [thread overview] Message-ID: <d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1608142916.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> --- hw/riscv/virt.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f8c5509f13..915e9ae216 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -43,12 +43,6 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -177,7 +171,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, } static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; int i, cpu, socket; @@ -242,11 +236,11 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(fdt, cpu_name); -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); + } name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); g_free(name); @@ -608,7 +602,8 @@ static void virt_machine_init(MachineState *machine) main_mem); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32_bit(machine)); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", @@ -616,8 +611,15 @@ static void virt_machine_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - start_addr, NULL); + if (riscv_is_32_bit(machine)) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.bin", + start_addr, NULL); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.bin", + start_addr, NULL); + } if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(machine, -- 2.29.2
WARNING: multiple messages have this Message-ID (diff)
From: Alistair Francis <alistair.francis@wdc.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, palmer@dabbelt.com, alistair.francis@wdc.com, alistair23@gmail.com Subject: [PATCH v4 06/16] hw/riscv: virt: Remove compile time XLEN checks Date: Wed, 16 Dec 2020 10:22:40 -0800 [thread overview] Message-ID: <d7ca1aca672515e6a4aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com> (raw) In-Reply-To: <cover.1608142916.git.alistair.francis@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> --- hw/riscv/virt.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f8c5509f13..915e9ae216 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -43,12 +43,6 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" -#if defined(TARGET_RISCV32) -# define BIOS_FILENAME "opensbi-riscv32-generic-fw_dynamic.bin" -#else -# define BIOS_FILENAME "opensbi-riscv64-generic-fw_dynamic.bin" -#endif - static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -177,7 +171,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, } static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, - uint64_t mem_size, const char *cmdline) + uint64_t mem_size, const char *cmdline, bool is_32_bit) { void *fdt; int i, cpu, socket; @@ -242,11 +236,11 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(fdt, cpu_name); -#if defined(TARGET_RISCV32) - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); -#else - qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); -#endif + if (is_32_bit) { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv32"); + } else { + qemu_fdt_setprop_string(fdt, cpu_name, "mmu-type", "riscv,sv48"); + } name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(fdt, cpu_name, "riscv,isa", name); g_free(name); @@ -608,7 +602,8 @@ static void virt_machine_init(MachineState *machine) main_mem); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32_bit(machine)); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", @@ -616,8 +611,15 @@ static void virt_machine_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); - firmware_end_addr = riscv_find_and_load_firmware(machine, BIOS_FILENAME, - start_addr, NULL); + if (riscv_is_32_bit(machine)) { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv32-generic-fw_dynamic.bin", + start_addr, NULL); + } else { + firmware_end_addr = riscv_find_and_load_firmware(machine, + "opensbi-riscv64-generic-fw_dynamic.bin", + start_addr, NULL); + } if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(machine, -- 2.29.2
next prev parent reply other threads:[~2020-12-16 18:33 UTC|newest] Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-12-16 18:22 [PATCH v4 00/16] RISC-V: Start to remove xlen preprocess Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 01/16] hw/riscv: Expand the is 32-bit check to support more CPUs Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 02/16] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 03/16] riscv: spike: Remove target macro conditionals Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 04/16] riscv: virt: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 05/16] hw/riscv: boot: Remove compile time XLEN checks Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` Alistair Francis [this message] 2020-12-16 18:22 ` [PATCH v4 06/16] hw/riscv: virt: " Alistair Francis 2020-12-16 18:22 ` [PATCH v4 07/16] hw/riscv: spike: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 08/16] hw/riscv: sifive_u: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-17 6:33 ` Bin Meng 2020-12-17 6:33 ` Bin Meng 2020-12-16 18:22 ` [PATCH v4 09/16] target/riscv: fpu_helper: Match function defs in HELPER macros Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 10/16] target/riscv: Add a riscv_cpu_is_32bit() helper function Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 11/16] target/riscv: Specify the XLEN for CPUs Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-16 18:22 ` [PATCH v4 12/16] target/riscv: cpu: Remove compile time XLEN checks Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-17 6:45 ` Bin Meng 2020-12-17 6:45 ` Bin Meng 2020-12-16 18:22 ` [PATCH v4 13/16] target/riscv: cpu_helper: " Alistair Francis 2020-12-16 18:22 ` Alistair Francis 2020-12-17 6:36 ` Bin Meng 2020-12-17 6:36 ` Bin Meng 2020-12-16 18:23 ` [PATCH v4 14/16] target/riscv: csr: " Alistair Francis 2020-12-16 18:23 ` Alistair Francis 2020-12-17 6:37 ` Bin Meng 2020-12-17 6:37 ` Bin Meng 2020-12-16 18:23 ` [PATCH v4 15/16] target/riscv: cpu: Set XLEN independently from target Alistair Francis 2020-12-16 18:23 ` Alistair Francis 2020-12-16 18:23 ` [PATCH v4 16/16] hw/riscv: Use the CPU to determine if 32-bit Alistair Francis 2020-12-16 18:23 ` Alistair Francis 2020-12-16 18:51 ` Richard Henderson 2020-12-16 18:51 ` Richard Henderson 2020-12-17 6:44 ` Bin Meng 2020-12-17 6:44 ` Bin Meng 2020-12-17 13:58 ` Richard Henderson 2020-12-17 13:58 ` Richard Henderson 2020-12-17 17:25 ` Palmer Dabbelt 2020-12-17 17:25 ` Palmer Dabbelt 2020-12-17 17:42 ` Alistair Francis 2020-12-17 17:42 ` Alistair Francis
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