* [PATCH v2] gdb: riscv: Add target description
@ 2020-12-30 8:25 Sylvain Pelissier
2020-12-30 8:32 ` Bin Meng
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Sylvain Pelissier @ 2020-12-30 8:25 UTC (permalink / raw)
To: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, open list:RISC-V, Sagar Karandikar,
Bastian Koppelmann, Bin Meng
[-- Attachment #1: Type: text/plain, Size: 1262 bytes --]
Target description is not currently implemented in RISC-V architecture.
Thus GDB won't set it properly when attached. The patch implements the
target description response.
Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
---
target/riscv/cpu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 254cd83f8b..ed4971978b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_END_OF_LIST(),
};
+static gchar *riscv_gdb_arch_name(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (riscv_cpu_is_32bit(env)) {
+ return g_strdup("riscv:rv32");
+ } else {
+ return g_strdup("riscv:rv64");
+ }
+}
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
/* For now, mark unmigratable: */
cc->vmsd = &vmstate_riscv_cpu;
#endif
+ cc->gdb_arch_name = riscv_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_initialize = riscv_translate_init;
cc->tlb_fill = riscv_cpu_tlb_fill;
--
2.25.1
[-- Attachment #2: Type: text/html, Size: 1550 bytes --]
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v2] gdb: riscv: Add target description
2020-12-30 8:25 [PATCH v2] gdb: riscv: Add target description Sylvain Pelissier
@ 2020-12-30 8:32 ` Bin Meng
2021-01-05 20:33 ` Alistair Francis
2021-01-05 21:03 ` Alistair Francis
2 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2020-12-30 8:32 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Wed, Dec 30, 2020 at 4:25 PM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] gdb: riscv: Add target description
@ 2020-12-30 8:32 ` Bin Meng
0 siblings, 0 replies; 11+ messages in thread
From: Bin Meng @ 2020-12-30 8:32 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, open list:RISC-V, Sagar Karandikar,
Bastian Koppelmann
On Wed, Dec 30, 2020 at 4:25 PM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] gdb: riscv: Add target description
2020-12-30 8:25 [PATCH v2] gdb: riscv: Add target description Sylvain Pelissier
@ 2021-01-05 20:33 ` Alistair Francis
2021-01-05 20:33 ` Alistair Francis
2021-01-05 21:03 ` Alistair Francis
2 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-01-05 20:33 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (riscv_cpu_is_32bit(env)) {
> + return g_strdup("riscv:rv32");
> + } else {
> + return g_strdup("riscv:rv64");
> + }
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> /* For now, mark unmigratable: */
> cc->vmsd = &vmstate_riscv_cpu;
> #endif
> + cc->gdb_arch_name = riscv_gdb_arch_name;
> #ifdef CONFIG_TCG
> cc->tcg_initialize = riscv_translate_init;
> cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2] gdb: riscv: Add target description
@ 2021-01-05 20:33 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-01-05 20:33 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, open list:RISC-V, Sagar Karandikar,
Bastian Koppelmann, Bin Meng
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (riscv_cpu_is_32bit(env)) {
> + return g_strdup("riscv:rv32");
> + } else {
> + return g_strdup("riscv:rv64");
> + }
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> /* For now, mark unmigratable: */
> cc->vmsd = &vmstate_riscv_cpu;
> #endif
> + cc->gdb_arch_name = riscv_gdb_arch_name;
> #ifdef CONFIG_TCG
> cc->tcg_initialize = riscv_translate_init;
> cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2] gdb: riscv: Add target description
2020-12-30 8:25 [PATCH v2] gdb: riscv: Add target description Sylvain Pelissier
@ 2021-01-05 21:03 ` Alistair Francis
2021-01-05 20:33 ` Alistair Francis
2021-01-05 21:03 ` Alistair Francis
2 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-01-05 21:03 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Bin Meng
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Hello,
This patch fails to apply. How did you send the email?
Alistair
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (riscv_cpu_is_32bit(env)) {
> + return g_strdup("riscv:rv32");
> + } else {
> + return g_strdup("riscv:rv64");
> + }
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> /* For now, mark unmigratable: */
> cc->vmsd = &vmstate_riscv_cpu;
> #endif
> + cc->gdb_arch_name = riscv_gdb_arch_name;
> #ifdef CONFIG_TCG
> cc->tcg_initialize = riscv_translate_init;
> cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2] gdb: riscv: Add target description
@ 2021-01-05 21:03 ` Alistair Francis
0 siblings, 0 replies; 11+ messages in thread
From: Alistair Francis @ 2021-01-05 21:03 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, open list:RISC-V, Sagar Karandikar,
Bastian Koppelmann, Bin Meng
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
<sylvain.pelissier@gmail.com> wrote:
>
> Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response.
>
> Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
Hello,
This patch fails to apply. How did you send the email?
Alistair
> ---
> target/riscv/cpu.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 254cd83f8b..ed4971978b 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_END_OF_LIST(),
> };
>
> +static gchar *riscv_gdb_arch_name(CPUState *cs)
> +{
> + RISCVCPU *cpu = RISCV_CPU(cs);
> + CPURISCVState *env = &cpu->env;
> +
> + if (riscv_cpu_is_32bit(env)) {
> + return g_strdup("riscv:rv32");
> + } else {
> + return g_strdup("riscv:rv64");
> + }
> +}
> +
> static void riscv_cpu_class_init(ObjectClass *c, void *data)
> {
> RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
> /* For now, mark unmigratable: */
> cc->vmsd = &vmstate_riscv_cpu;
> #endif
> + cc->gdb_arch_name = riscv_gdb_arch_name;
> #ifdef CONFIG_TCG
> cc->tcg_initialize = riscv_translate_init;
> cc->tlb_fill = riscv_cpu_tlb_fill;
> --
> 2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2] gdb: riscv: Add target description
2021-01-05 21:03 ` Alistair Francis
@ 2021-01-06 10:48 ` Sylvain Pelissier
-1 siblings, 0 replies; 11+ messages in thread
From: Sylvain Pelissier @ 2021-01-06 10:48 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt, Bin Meng
[-- Attachment #1: Type: text/plain, Size: 1838 bytes --]
Hello,
I may have made an error by copy pasting the comment into the file. I sent
a new v3 with git send-email. I hope it is fine now.
Regards
Sylvain
On Tue, 5 Jan 2021 at 22:03, Alistair Francis <alistair23@gmail.com> wrote:
> On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
> <sylvain.pelissier@gmail.com> wrote:
> >
> > Target description is not currently implemented in RISC-V architecture.
> Thus GDB won't set it properly when attached. The patch implements the
> target description response.
> >
> > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
>
> Hello,
>
> This patch fails to apply. How did you send the email?
>
> Alistair
>
> > ---
> > target/riscv/cpu.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 254cd83f8b..ed4971978b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > +static gchar *riscv_gdb_arch_name(CPUState *cs)
> > +{
> > + RISCVCPU *cpu = RISCV_CPU(cs);
> > + CPURISCVState *env = &cpu->env;
> > +
> > + if (riscv_cpu_is_32bit(env)) {
> > + return g_strdup("riscv:rv32");
> > + } else {
> > + return g_strdup("riscv:rv64");
> > + }
> > +}
> > +
> > static void riscv_cpu_class_init(ObjectClass *c, void *data)
> > {
> > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c,
> void *data)
> > /* For now, mark unmigratable: */
> > cc->vmsd = &vmstate_riscv_cpu;
> > #endif
> > + cc->gdb_arch_name = riscv_gdb_arch_name;
> > #ifdef CONFIG_TCG
> > cc->tcg_initialize = riscv_translate_init;
> > cc->tlb_fill = riscv_cpu_tlb_fill;
> > --
> > 2.25.1
>
[-- Attachment #2: Type: text/html, Size: 2679 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2] gdb: riscv: Add target description
@ 2021-01-06 10:48 ` Sylvain Pelissier
0 siblings, 0 replies; 11+ messages in thread
From: Sylvain Pelissier @ 2021-01-06 10:48 UTC (permalink / raw)
To: Alistair Francis
Cc: qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, open list:RISC-V, Sagar Karandikar,
Bastian Koppelmann, Bin Meng
[-- Attachment #1: Type: text/plain, Size: 1838 bytes --]
Hello,
I may have made an error by copy pasting the comment into the file. I sent
a new v3 with git send-email. I hope it is fine now.
Regards
Sylvain
On Tue, 5 Jan 2021 at 22:03, Alistair Francis <alistair23@gmail.com> wrote:
> On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
> <sylvain.pelissier@gmail.com> wrote:
> >
> > Target description is not currently implemented in RISC-V architecture.
> Thus GDB won't set it properly when attached. The patch implements the
> target description response.
> >
> > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
>
> Hello,
>
> This patch fails to apply. How did you send the email?
>
> Alistair
>
> > ---
> > target/riscv/cpu.c | 13 +++++++++++++
> > 1 file changed, 13 insertions(+)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 254cd83f8b..ed4971978b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
> > DEFINE_PROP_END_OF_LIST(),
> > };
> >
> > +static gchar *riscv_gdb_arch_name(CPUState *cs)
> > +{
> > + RISCVCPU *cpu = RISCV_CPU(cs);
> > + CPURISCVState *env = &cpu->env;
> > +
> > + if (riscv_cpu_is_32bit(env)) {
> > + return g_strdup("riscv:rv32");
> > + } else {
> > + return g_strdup("riscv:rv64");
> > + }
> > +}
> > +
> > static void riscv_cpu_class_init(ObjectClass *c, void *data)
> > {
> > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
> > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c,
> void *data)
> > /* For now, mark unmigratable: */
> > cc->vmsd = &vmstate_riscv_cpu;
> > #endif
> > + cc->gdb_arch_name = riscv_gdb_arch_name;
> > #ifdef CONFIG_TCG
> > cc->tcg_initialize = riscv_translate_init;
> > cc->tlb_fill = riscv_cpu_tlb_fill;
> > --
> > 2.25.1
>
[-- Attachment #2: Type: text/html, Size: 2679 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2] gdb: riscv: Add target description
2021-01-06 10:48 ` Sylvain Pelissier
@ 2021-01-06 11:35 ` Alex Bennée
-1 siblings, 0 replies; 11+ messages in thread
From: Alex Bennée @ 2021-01-06 11:35 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel, Alistair Francis, Alistair Francis, Bin Meng,
Palmer Dabbelt
Sylvain Pelissier <sylvain.pelissier@gmail.com> writes:
> Hello,
>
> I may have made an error by copy pasting the comment into the file. I sent
> a new v3 with git send-email. I hope it is fine now.
Your v3 doesn't include the review tags you got for v2 which makes it
look un-reviewed. See:
https://wiki.qemu.org/Contribute/SubmitAPatch#Proper_use_of_Reviewed-by:_tags_can_aid_review
You can either apply them manually by copy and paste when you reword the
commit message or use a tool to apply the old version and collect tags
from the mailing list archive.
> Regards
>
> Sylvain
>
> On Tue, 5 Jan 2021 at 22:03, Alistair Francis <alistair23@gmail.com> wrote:
>
>> On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
>> <sylvain.pelissier@gmail.com> wrote:
>> >
>> > Target description is not currently implemented in RISC-V architecture.
>> Thus GDB won't set it properly when attached. The patch implements the
>> target description response.
>> >
>> > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
>>
>> Hello,
>>
>> This patch fails to apply. How did you send the email?
>>
>> Alistair
>>
>> > ---
>> > target/riscv/cpu.c | 13 +++++++++++++
>> > 1 file changed, 13 insertions(+)
>> >
>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> > index 254cd83f8b..ed4971978b 100644
>> > --- a/target/riscv/cpu.c
>> > +++ b/target/riscv/cpu.c
>> > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
>> > DEFINE_PROP_END_OF_LIST(),
>> > };
>> >
>> > +static gchar *riscv_gdb_arch_name(CPUState *cs)
>> > +{
>> > + RISCVCPU *cpu = RISCV_CPU(cs);
>> > + CPURISCVState *env = &cpu->env;
>> > +
>> > + if (riscv_cpu_is_32bit(env)) {
>> > + return g_strdup("riscv:rv32");
>> > + } else {
>> > + return g_strdup("riscv:rv64");
>> > + }
>> > +}
>> > +
>> > static void riscv_cpu_class_init(ObjectClass *c, void *data)
>> > {
>> > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
>> > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c,
>> void *data)
>> > /* For now, mark unmigratable: */
>> > cc->vmsd = &vmstate_riscv_cpu;
>> > #endif
>> > + cc->gdb_arch_name = riscv_gdb_arch_name;
>> > #ifdef CONFIG_TCG
>> > cc->tcg_initialize = riscv_translate_init;
>> > cc->tlb_fill = riscv_cpu_tlb_fill;
>> > --
>> > 2.25.1
>>
--
Alex Bennée
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v2] gdb: riscv: Add target description
@ 2021-01-06 11:35 ` Alex Bennée
0 siblings, 0 replies; 11+ messages in thread
From: Alex Bennée @ 2021-01-06 11:35 UTC (permalink / raw)
To: Sylvain Pelissier
Cc: Alistair Francis, open list:RISC-V, Sagar Karandikar,
Bastian Koppelmann, Alistair Francis, Palmer Dabbelt, Bin Meng,
qemu-devel
Sylvain Pelissier <sylvain.pelissier@gmail.com> writes:
> Hello,
>
> I may have made an error by copy pasting the comment into the file. I sent
> a new v3 with git send-email. I hope it is fine now.
Your v3 doesn't include the review tags you got for v2 which makes it
look un-reviewed. See:
https://wiki.qemu.org/Contribute/SubmitAPatch#Proper_use_of_Reviewed-by:_tags_can_aid_review
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> Regards
>
> Sylvain
>
> On Tue, 5 Jan 2021 at 22:03, Alistair Francis <alistair23@gmail.com> wrote:
>
>> On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier
>> <sylvain.pelissier@gmail.com> wrote:
>> >
>> > Target description is not currently implemented in RISC-V architecture.
>> Thus GDB won't set it properly when attached. The patch implements the
>> target description response.
>> >
>> > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com>
>>
>> Hello,
>>
>> This patch fails to apply. How did you send the email?
>>
>> Alistair
>>
>> > ---
>> > target/riscv/cpu.c | 13 +++++++++++++
>> > 1 file changed, 13 insertions(+)
>> >
>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> > index 254cd83f8b..ed4971978b 100644
>> > --- a/target/riscv/cpu.c
>> > +++ b/target/riscv/cpu.c
>> > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = {
>> > DEFINE_PROP_END_OF_LIST(),
>> > };
>> >
>> > +static gchar *riscv_gdb_arch_name(CPUState *cs)
>> > +{
>> > + RISCVCPU *cpu = RISCV_CPU(cs);
>> > + CPURISCVState *env = &cpu->env;
>> > +
>> > + if (riscv_cpu_is_32bit(env)) {
>> > + return g_strdup("riscv:rv32");
>> > + } else {
>> > + return g_strdup("riscv:rv64");
>> > + }
>> > +}
>> > +
>> > static void riscv_cpu_class_init(ObjectClass *c, void *data)
>> > {
>> > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
>> > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c,
>> void *data)
>> > /* For now, mark unmigratable: */
>> > cc->vmsd = &vmstate_riscv_cpu;
>> > #endif
>> > + cc->gdb_arch_name = riscv_gdb_arch_name;
>> > #ifdef CONFIG_TCG
>> > cc->tcg_initialize = riscv_translate_init;
>> > cc->tlb_fill = riscv_cpu_tlb_fill;
>> > --
>> > 2.25.1
>>
--
Alex Bennée
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-01-06 11:41 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-12-30 8:25 [PATCH v2] gdb: riscv: Add target description Sylvain Pelissier
2020-12-30 8:32 ` Bin Meng
2020-12-30 8:32 ` Bin Meng
2021-01-05 20:33 ` Alistair Francis
2021-01-05 20:33 ` Alistair Francis
2021-01-05 21:03 ` Alistair Francis
2021-01-05 21:03 ` Alistair Francis
2021-01-06 10:48 ` Sylvain Pelissier
2021-01-06 10:48 ` Sylvain Pelissier
2021-01-06 11:35 ` Alex Bennée
2021-01-06 11:35 ` Alex Bennée
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